Memory devices, modules, and systems having a variety of physical sizes, memory formats and operating capabilities

Abstract

An apparatus is provided that includes a plurality of memory devices and a buffer device that permits use of memory devices having a variety of physical sizes and memory formats in an industry standard memory module format. The buffer device includes memory interface circuitry and at least one first-in-first-out (FIFO) or multiplexer circuit. The apparatus further includes a parallel bus connecting the buffer device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels each coupling the at least one FIFO or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 782,276, filed December 19, 2018, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to memory devices, modules, and systems, and more specifically, to memory devices, modules, and systems having different physical dimensions, memory formats, and operating capabilities. Background Technology

[0004] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming different states of memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), and synchronous dynamic RAM (SDRAM). Memory devices can be volatile or non-volatile. Improvements to memory devices typically include increasing memory cell density, increasing read / write speeds or further reducing operation latency, increasing reliability, improving data retention, reducing power consumption, or reducing manufacturing costs. Attached Figure Description

[0005] Figure 1 This is a simplified block diagram illustrating an embodiment of a memory device according to the present invention.

[0006] Figure 2 This is a simplified block diagram illustrating an embodiment of a memory system according to the present invention.

[0007] Figure 3 This is a simplified block diagram illustrating an embodiment of a memory device according to the present invention.

[0008] Figure 4 This is a flowchart illustrating a method for operating a device according to an embodiment of the present invention. Detailed Implementation

[0009] High data reliability, high-speed memory access, and reduced chip size are desirable characteristics of semiconductor memories. Semiconductor memories are often provided in memory modules corresponding to industry standards, such as dual in-line memory modules (DIMMs). Industry standards often require specific module dimensions (e.g., maximum height and thickness) and specific connector layouts. These constraints can pose challenges to providing high-density, hybrid media, and other high-performance memory modules because the total space available for the memory device is severely limited.

[0010] Therefore, several embodiments of the present invention relate to memory devices, memory systems, and memory modules that implement dynamic density. In this regard, the memory module may include a buffer between the module connector and the memory device, the buffer allowing the use of memory devices with various physical sizes (e.g., chip-scale packages) and memory formats (e.g., volatile and non-volatile) in industry-standard formats. The buffer may be configured to support memory devices with fewer onboard features (e.g., “dumb” memory arrays, where logic functions are offloaded to the buffer). The buffer may be further configured to support atomic in-memory operations, in-memory processing, and so on. The buffer can perform these functions and thus physically replace other module components, such as registered clock drivers (RCDs) and buffers (e.g., LRDIMM buffers).

[0011] Figure 1 This is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present invention. The memory device 100 may include a memory cell array, such as a memory array 150. The memory array 150 may include a plurality of memory banks (e.g., in...). Figure 1 The memory bank in the example (0 to 15) may contain multiple word lines (WL), multiple bit lines (BL), and multiple memory cells arranged at the intersections of the word lines and bit lines. The selection of word lines WL may be performed by row decoder 140, and the selection of bit lines BL may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may in turn be coupled to at least one corresponding primary I / O line pair (MIOT / B) via a transmission gate (TG), which may act as a switch.

[0012] The memory device 100 may employ a plurality of external terminals including command terminals and address terminals coupled to a command bus and an address bus to receive command signal CMD and address signal ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS, VDDQ, and VSSQ, and an on-die termination terminal ODT.

[0013] Address signals and memory address signals can be supplied externally to the command and address terminals. The address signals and memory address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 140, and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the memory address signal (BADD) and supply it to both the row decoder 140 and the column decoder 145.

[0014] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied from the memory controller to command and address terminals. The command signals can represent various memory commands from the memory controller (e.g., access commands, which may include read and write commands). The select signal CS can be used to select the memory device 100 to respond to commands and addresses provided to the command and address terminals. When the CS signal is provided to the memory device 100, commands and addresses can be decoded, and memory operations can be performed. The command signal CMD can be provided as an internal command signal ICMD to the command decoder 115 via command / address input circuitry 105. The command decoder 115 may include circuitry for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. The internal command signals may also include output and input activation commands, such as the timing command CMDCK.

[0015] When a read command is issued and the read command is promptly supplied to the row and column addresses, read data can be read from the memory cells specified by these row and column addresses in the memory array 150. The read command can be received by a command decoder 115, which can provide internal commands to the input / output circuitry 160, enabling read data to be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 155 and the input / output circuitry 160 according to the RDQS clock signal. The read data can be programmable in the memory device 100, for example, programmed in the mode register (…). Figure 1 The read delay information RL (not shown in the diagram) defines the time at which read data is provided. The read delay information RL can be defined in terms of the clock cycles of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal when the associated read data is provided after the read command is received by the memory device 100.

[0016] When a write command is issued and the command is supplied to the row and column addresses in a timely manner, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by the command decoder 115, which can provide internal commands to the input / output circuit 160, so that the write data can be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data can be written to the memory cell specified by the row and column addresses. Write data can be supplied to the data terminals at a time defined by the write delay WL information. The write delay WL information is programmable in the memory device 100, for example, programmed in the mode register ( Figure 1 (Not shown in the text). The write latency WL information can be defined in terms of the clock cycles of the CK clock signal. For example, the write latency WL can be the number of clock cycles of the CK signal when the associated write data is received after the write command is received by the memory device 100.

[0017] Power supply potentials VDD and VSS can be supplied to the power supply terminals. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the line decoder 140, the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0018] A power supply potential VDDQ can also be supplied to the power supply terminals. The power supply potential VDDQ, together with the power supply potential VSS, can be supplied to the input / output circuit 160. In an embodiment of the invention, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of the invention, the power supply potential VDDQ can be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ can be used for the input / output circuit 160 so that power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0019] An on-die termination signal ODT can be supplied to the on-die termination terminal. The on-die termination signal ODT can be supplied to the input / output circuit 160 to indicate that the memory device 100 enters an on-die termination mode (e.g., providing one of a predetermined number of impedance levels at one or more other terminals of the memory device 100).

[0020] External clock signals and complementary external clock signals can be supplied to the clock terminal and data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. CK and CKF signals are complementary, and WCK and WCKF signals are also complementary. Complementary clock signals can simultaneously have relative clock levels and transitions between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0021] The clock input circuit 120 includes an input buffer that can receive external clock signals. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive CK and CKF signals as well as WCK and WCKF signals. The clock input circuit 120 can receive external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command / address input circuit 105. For example, the internal clock circuit 130 may include a clock path that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1(Not shown in the image). The internal clock circuit 130 can further provide input / output (I / O) clock signals. The I / O clock signals can be supplied to the input / output circuit 160 and can be used as timing signals to determine the output timing for reading data and the input timing for writing data. Multiple clock frequencies can be provided for the I / O clock signals, allowing data to be output from and input to the memory device 100 at different data rates. Higher clock frequencies may be desirable when high memory speed is desired. Lower clock frequencies may be desirable when lower power consumption is desired. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0022] Memory devices (e.g.) Figure 1 The memory device 100 described herein may be provided in a memory module in which multiple memory devices are integrated into a package (e.g., mounted on a printed circuit board) using standard edge connectors (e.g., DIMM edge connectors) and standard host-side interfaces. For example, Figure 2 This is a simplified block diagram illustrating a memory system 200 according to an embodiment of the present invention. The memory system 200 includes a host device 210 operatively coupled to a memory module 220 (e.g., a dual in-line memory module (DIMM)). The memory module 220 may include a buffer device 230 operatively connected to a plurality of memory devices 250 via a bus 240. According to one aspect of this disclosure, the buffer device 230 may provide a standards-compliant host-side interface to the host 210 while allowing connection via the bus 240 of memory devices having various formats, physical sizes (e.g., densities), and functionalities.

[0023] According to one example, the memory device 250 of memory module 220 may include one or more chip-scale packaged memory devices that consume less substrate surface area on the printed circuit board of memory module 220 compared to other packaging methods, and can be connected to an independent data channel via one of several different bus schemes (e.g., multiplexing and / or first-in-first-out (FIFO)) for communication with memory device 250. Furthermore, buffer device 230 may include logic configured to perform various functions in memory device 250, including in-memory processing (PIM), atomic operations, etc. Buffer device 230 may further include logic for 'unloading' from memory device 250, which allows the use of 'non-smart' memory arrays (e.g., those without error correction codes (ECC) of standard DRAM modules).

[0024] According to one aspect of this disclosure, buffer device 230 is configured to manage all memory devices 250 (e.g., optimize traffic to reduce latency and power consumption) and provides enhanced host-side interface via extended memory functionality (e.g., in-memory operations and in-memory processing, such as atomic operations). By means of analog processing, buffer device 230 can act as a “black box” memory controller with a separate interface to the host. The black box approach allows the use of any one or more memory technologies (e.g., a mixture of various volatile and non-volatile memories).

[0025] For example, in one embodiment of the present invention, buffer device 230 may be configured to manage refresh cycles based on the needs of one or more of the memory devices 250 (e.g., in the absence of a refresh command from host 210, even for DDR5 implementations where host 210 would normally issue it). In another embodiment, buffer device 230 may be configured to predict the location of the next memory access (e.g., using snooping commands, memory access history, and other predictive intelligence methods) to optimize the refresh location, pre-adjust the array, or perform other optimizations based on the prediction.

[0026] According to one aspect of the invention, the buffer device 230 may include circuitry configured to optimize the power consumption of the memory device 250 (e.g., by shutting down the memory device in different ways, changing the operating voltage of the memory device, changing the clock rate of the memory device, etc.). Furthermore, the buffer device may be configured to manage the physical media of the memory device (e.g., mapping out faulty bits, columns, segments, etc., and transferring their contents to known good areas, which is transparent to the host).

[0027] According to another aspect of the invention, buffer device 230 can be used to replace conventional memory I / O drivers, terminal circuit systems, DLLs, ECC / CRC encoding / decoding circuit systems, and command decoding logic from each of the memory devices 250 (e.g., allowing these and other logic circuits originally present in a conventional DRAM die to be omitted from the memory device 250). In another embodiment of this disclosure, buffer device 230 can be configured to be level-shifted, such that in embodiments where the memory device 250 is a packaged DRAM die, DRAM I / O voltage and / or power can be reduced.

[0028] In another embodiment of this disclosure, buffering device 230 may be configured to support channels running in parallel with memory device 250 to facilitate lower latency. Therefore, in some embodiments, data transmitted via the data bus may be nondeterministic. According to another aspect, the signaling between buffering device 230 and memory device 250 may be more advanced than non-return-to-zero (NRZ) or other binary logic to achieve higher internal bandwidth (e.g., in some embodiments, as high as or even higher than external bandwidth).

[0029] Given the aforementioned capabilities of buffer 230, memory device 250 can be provided in various formats and capacities, offering a variety of functionalities, some included and some omitted. For example, a hierarchical memory can be provided behind buffer 230, where latency corresponds to address locations, and host device 210 can thus be configured to prioritize "hot" data (e.g., data expected to be read back faster after being written or read back more frequently than other data) at lower latency addresses. In this regard, hot address locations can also be configured to have a priority over any other data request (e.g., requests for access to hot locations can be reordered to the front of the request queue, and / or provided as an interrupt to any other access in the process).

[0030] Furthermore, the aforementioned capabilities can be further utilized by employing addressing schemes corresponding to memory arrays with different bus widths or page sizes (e.g., address 0x0 = 16 bits wide, 0x5 = 32 bits wide, 0xA = 64 bits wide, etc.) to save power and improve efficiency. In conventional systems with channels that only support 128-bit packets, the system must access the entire 128-bit bandwidth when requesting 64 data bits. In embodiments of this disclosure, different arrays or segments of arrays may be configured with different bus widths and page sizes (e.g., in a method not entirely dissimilar to the burst chop in DDR, which truncates data but does not provide the ability of the present invention to change the timing or power used to access data).

[0031] Although the memory module has been described and explained Figure 2 While the memory systems described herein may utilize other memory packages or systems (e.g., surface mount packages, flip chip packages, ball grid array packages, etc.) in other embodiments of the invention, furthermore, although the foregoing embodiments have been described with reference to industry-standard connectors, interfaces, and protocols, in other embodiments, memory systems, modules, and devices employing buffering devices may be provided in proprietary or custom formats.

[0032] Figure 3 This is a simplified block diagram illustrating an embodiment of a memory device according to the present invention. (See reference...) Figure 3As can be seen, memory device 300 may include buffer device 330 and multiple memory devices, such as memory devices 351 and 352. According to one embodiment of this disclosure, the multiple memory devices may include memory devices with different memory devices. For example, in such embodiments, memory device 351 may be a non-volatile memory device (e.g., NAND, PCM, NOR, MRAM, FeRAM, etc.), and the memory device may be a volatile memory device (e.g., DRAM, SRAM, etc.). The buffer device 330 may include various circuitry configured to allow communication between a connected host device (not described) and various memory devices 351 and 352. These circuitry include a channel interface (e.g., for command / address and data communication with the connected host device using a standard memory protocol such as DDR5), a memory interface (e.g., for command / address communication between the buffer device 330 and the memory devices via a command / address bus 341, and for performing logical functions therein, such as ECC, in-memory processing, and / or atomic operations), and FIFO circuitry and / or one or more multiplexers (e.g., for data communication between the buffer device 330 and the memory devices via a data bus 342).

[0033] According to one aspect of this disclosure, command / address bus 341 may include multiple independent control lines, each operably coupling a memory interface to a corresponding subset of multiple memory devices (e.g., illustrated as rows). Similarly, data bus 342 may include multiple independent data channels, each operably coupling a FIFO and / or multiplexer to a corresponding subset of multiple memory devices (e.g., illustrated as columns). See reference... Figure 3 As can be seen, a subset (e.g., column) of memory devices connected to each independent data channel may contain more than one type of memory device (e.g., one non-volatile memory device 351 and two volatile memory devices 352), while a subset (e.g., row) of memory devices connected to each independent control line contains a single type of memory device (e.g., all non-volatile memory devices 351 or all two volatile memory devices 352).

[0034] Figure 4 This is a flowchart illustrating a method of operating a device according to an embodiment of the present invention. The method includes receiving a plurality of signals at a buffer of the device, the plurality of signals including command / address signals and data signals (block 410). According to one aspect of this disclosure, the receiving feature of block 410 may be implemented using a buffer 330, as described above. Figure 3The method is described in more detail below. The method further includes using a memory interface circuitry of a buffer device to direct command / address signals to a first subset of a plurality of memory devices of the device via multiple independent control lines (block 420). According to one aspect of this disclosure, the directing feature of block 420 can be implemented using the memory interface circuitry of buffer device 330, as described above. Figure 3 The method is described in more detail below. It further comprises guiding data signals to a second subset of multiple memory devices (block 430) via multiple independent data channels using at least one first-in-first-out (FIFO) circuit or multiplexer circuit of the buffer device. According to one aspect of this disclosure, the guiding feature of block 430 may be implemented using the FIFO circuit and / or multiplexer circuit of the buffer device 330, as described above. Figure 3 A more detailed explanation follows.

[0035] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the methods described can be combined.

[0036] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that the signal may represent a signal bus, wherein the bus may have multiple bit widths.

[0037] The devices discussed herein, including memory devices, can be formed on semiconductor substrates or dies such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0038] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations.

[0039] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0040] As will be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the invention. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are within the scope of the invention.

Claims

1. An apparatus comprising: Multiple memory devices; A buffer device comprising: Memory interface circuitry, and At least one first-in-first-out (FIFO) circuit or multiplexer circuit; as well as A parallel bus operably connects the buffer device to the plurality of memory devices, the parallel bus comprising: Multiple independent control lines, each of which operatively couples the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and Multiple independent data channels, each of which operably couples the at least one FIFO circuit or multiplexer circuit to a corresponding subset of multiple second subsets of the multiple memory devices, wherein each subset of the multiple first subsets intersects with each subset of the multiple second subsets.

2. The device of claim 1, wherein each of the first subset of the plurality of memory devices comprises a memory device of a single memory type.

3. The device of claim 1, wherein each of the second subset of the plurality of memory devices comprises a memory device having a different memory type.

4. The device according to claim 3, wherein the different memory types include one or more of NAND, NOR, phase change memory PCM, magnetoresistive memory MRAM, DRAM, SRAM and ferroelectric memory.

5. The device of claim 1, wherein the buffer device includes a channel interface configured to communicate with a connected host device using the DDR5 protocol.

6. The device of claim 1, wherein the memory interface circuitry is configured to perform in-memory processing functions in one or more of the plurality of memory devices.

7. The device of claim 1, wherein the memory interface circuitry is configured to perform atomic memory functions in one or more of the plurality of memory devices.

8. The device of claim 1, wherein the plurality of memory devices comprises chip-scale packaged memory devices.

9. The device of claim 1, wherein the plurality of memory devices comprises one or more memory devices without an error correction code (ECC) circuit system, and further wherein the memory interface circuit system is configured to perform error correction in the one or more memory devices.

10. The device of claim 1, wherein the buffer is configured to map the physical addresses of the plurality of memory devices to logical addresses.

11. The device of claim 1, wherein the buffer is configured to remap the physical addresses of the plurality of memory devices in response to the detection of a bad bit in one or more of the plurality of memory devices.

12. A method comprising: The device receives multiple signals at its buffer, including command / address signals and data signals. The memory interface circuitry of the buffer device directs the command / address signal to a first subset of a first subset of a plurality of memory devices of the device via a plurality of independent control lines. as well as The data signal is directed via multiple independent data channels to a second subset of multiple second subsets of the multiple memory devices using at least one first-in-first-out FIFO circuit or multiplexer circuit of the buffer device, wherein each subset of the multiple first subsets intersects with each subset of the multiple second subsets.

13. The method of claim 12, wherein the first subset of the plurality of memory devices comprises a memory device of a single memory type.

14. The method of claim 12, wherein the second subset of the plurality of memory devices comprises memory devices having different memory types.

15. The method of claim 14, wherein the different memory types include one or more of NAND, NOR, phase-change memory (PCM), magnetoresistive memory (MRAM), DRAM, SRAM, and ferroelectric memory.

16. The method of claim 12, wherein the plurality of signals are transmitted from the connected host device using the DDR5 protocol.

17. The method of claim 12, further comprising using the memory interface circuitry to perform in-memory processing functions of one or more of the plurality of memory devices.

18. The method of claim 12, further comprising using the memory interface circuitry system to perform atomic memory functions of one or more of the plurality of memory devices.

19. The method of claim 13, wherein the plurality of memory devices comprises chip-scale packaged memory devices.

20. The method of claim 13, wherein the plurality of memory devices comprises one or more memory devices without an error correction code (ECC) circuit system, and further comprises performing an error correction function in the one or more memory devices using the memory interface circuit system.

21. The method of claim 12, further comprising using the buffer device to map the physical addresses of the plurality of memory devices to logical addresses.

22. The method of claim 12, further comprising remapping the physical addresses of the plurality of memory devices with the buffer in response to detecting a bad bit in one or more of the plurality of memory devices.

23. An apparatus comprising: Multiple memory devices are arranged in the first channel and the second channel; A first buffer device and a second buffer device, respectively corresponding to the first channel and the second channel, each buffer device comprising: Memory interface circuitry, and At least one first-in-first-out (FIFO) circuit or multiplexer circuit; and A parallel bus that operably connects the first buffer device and the second buffer device to memory devices of the first channel and the second channel, respectively, the parallel bus comprising: Multiple independent control lines, each of which operably couples the memory interface circuitry of one of the first and second buffer devices to a corresponding subset of a plurality of first subsets of the plurality of memory devices, and Multiple independent data channels, each of which operably couples at least one FIFO circuit or multiplexer circuit of one of the first buffer device and the second buffer device to a corresponding subset of multiple second subsets of the multiple memory devices, wherein each subset of the multiple first subsets intersects with each subset of the multiple second subsets.

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