Gate driver circuit and method of driving transistor

Abstract

A gate driver circuit and a method for driving a transistor are disclosed. A gate driver circuit includes a gate driver and a sensing circuit. The gate driver is configured to generate an on-current to drive a transistor during a plurality of on-switching events, wherein a voltage across the transistor changes from a first value to a second value at a slope during the plurality of on-switching events, wherein the slope is an active type or a passive type depending on the magnitude of the on-current. The sensing circuit determines whether the slope during a first on-switching event is an active type or a passive type, and if the slope is an active type, adjusts the magnitude of the on-current during a second on-switching event following the first on-switching event, and if the slope is a passive type, keeps the magnitude of the on-current unchanged during the second on-switching event.

Description

Technical Field

[0001] The present disclosure relates generally to driving techniques in gate drivers, and more particularly to regulating the rate of change of voltage of a transistor driven by a gate driver. Background Art

[0002] The new generation of insulated gate bipolar transistor (IGBT) and metal oxide semiconductor field effect transistor (MOSFET) power switches (superjunction and wide bandgap power switches) are characterized by the gate-drain capacitance (C GD ), which follows the drain-source voltage V DS The range is extremely nonlinear. Especially in superjunction technology, the gate-drain capacitance C GD This capacitance is the root of switching speed transients due to large changes in voltage.

[0003] In hard switching applications, when V DS When the power switch is high, the power switch is turned on, or in other words, when the high voltage V DS With high current I DS Hard switching occurs when there is overlap between the currents I and V. This overlap causes energy loss, which can be reduced by increasing the di / dt and dV / dt (i.e., the current I DS The slope and voltage V DS Therefore, there may be a very steep V called dV / dt. DS Voltage transients.

[0004] In standard planar technology, fast dV / dt transients are present, but they are blocked by the C GD In fact, the gate driver output current Io+ used to boost (i.e., charge) the gate voltage of the power transistor during the turn-on transient flows entirely into C during the dV / dt period. GD , and the gate voltage appears flat, forming a "Miller plateau". If the speed of dV / dt is doubled, the capacitance C GD Its apparent value is doubled, and the system self-regulates.

[0005] For this reason, when using power switching devices, the output switches at very high dV / dt (when V DS voltage is high) and ends with a long, slow tail of the last few volts (when C GD becomes larger) ends. Figure 1 On the left the dV / dt behavior in the power switch is shown and on the right a schematic representation of the IGBT 1 is shown. In particular, Figure 1 The left side shows the VDS (i.e., dV / dt) and I DS During the turn-on switching event, V GS With C GD As V GS Equal to the threshold voltage Vth, the current I DS It just starts to flow. Figure 1 Also shown on the right is a schematic diagram of the power transistor 1, showing the parasitic capacitance C GD , drain-source voltage V DS , drain-source current I DS , and the gate-source voltage V GS .

[0006] As shown in the figure on the left, V is called dV / dt DS The voltage transient is initially very steep and fast, then changes to end with a long, slow tail within the last few volts. This dynamic behavior is typical of transistor devices, especially in superjunction devices, and both fast dV / dt transients and slow dV / dt transients are undesirable for a number of reasons.

[0007] First, the transistor switching characteristics are reflected on the motor phases, so that these power devices cannot be properly accepted by motor manufacturers due to the hard stress reflected on the motor phases. In particular, the fast dV / dt stresses the motor, especially the insulation material between the motor windings. Therefore, the fast dV / dt transients may damage or even destroy the insulation material between the motor windings.

[0008] Second, from an electromagnetic interference (EMI) and electromagnetic compatibility (EMC) standpoint, the steep dV / dt values ​​can create problems in qualifying the final system.

[0009] Third, low or small dV / dt values ​​worsen switching losses because the losses continue as long as the dV / dt tail is greater than zero.

[0010] In summary, when using transistor switches, it is difficult to find the correct single value of Io+ current to turn on the power transistor because the switching speed appears too fast (i.e., fast dV / dt) or too slow (i.e., slow dV / dt tail) at different times of the same switching event. In addition, as a parasitic capacitor, C GD Not controlled in production. This can lead to large batch differences in limit values.

[0011] In view of the above, a detection and driving strategy may be needed to reduce such transients at dV / dt values ​​suitable for motor driving and at the same time limit the switching losses in the power inverter. Summary of the invention

[0012] An embodiment provides a gate driver circuit including a gate driver and a sensing circuit. The gate driver is configured to generate an on-current to drive a transistor during a plurality of on-switching events, wherein a voltage across the transistor changes from a first value to a second value at a slope during the plurality of on-switching events, wherein the slope is an active type or a passive type, and wherein the slope of the active type depends on the magnitude of the on-current. The sensing circuit is configured to determine whether the slope during a first on-switching event is an active type or a passive type, and if the slope is an active type, then adjust the magnitude of the on-current during a second on-switching event following the first on-switching event, and if the slope is a passive type, then keep the magnitude of the on-current unchanged during the second on-switching event.

[0013] An embodiment provides a gate driver circuit including a gate driver and a sensing circuit. The gate driver is configured to generate an on-current to drive a transistor during a plurality of on-switching events, wherein each of the plurality of on-switching events includes a first time interval and a second time interval following the first time interval. During the plurality of on-switching events, the voltage across the transistor changes from a first value to a second value at an initial slope during the first time interval and at a second slope during the second time interval, wherein the initial slope is greater than the second slope. The initial slope starts during or after the dead time, wherein the initial slope depends on the magnitude of the on-current at the start of or after the dead time, and wherein the second slope depends on the magnitude of the on-current. The sensing circuit is configured to detect the expiration of a first time interval of a first on-switching event in the plurality of on-switching events, and in response to the detected expiration of the first time interval, the on-current is increased to a maximum value within at least a portion of the second time interval of the first on-switching event.

[0014] An embodiment provides a method for driving a transistor. The method includes generating an on-current during a plurality of on-switching events to drive the transistor, wherein a voltage across the transistor changes from a first value to a second value at a slope during the plurality of on-switching events, wherein the slope is an active type or a passive type, and wherein the slope of the active type depends on the magnitude of the on-current; determining whether the slope during a first on-switching event is an active type or a passive type; and if the slope is an active type, adjusting the magnitude of the on-current during a second on-switching event following the first on-switching event, and if the slope is a passive type, keeping the magnitude of the on-current unchanged during the second on-switching event.

[0015] An embodiment provides a method for driving a transistor. The method includes generating an on-current to drive the transistor during a plurality of on-switching events, wherein each of the plurality of on-switching events includes a first time interval and a second time interval following the first time interval, wherein during the plurality of on-switching events, a voltage across the transistor changes from a first value to a second value at an initial slope during the first time interval and at a second slope during the second time interval, wherein the initial slope is greater than the second slope, wherein the initial slope starts during or after a dead time, wherein the initial slope depends on the magnitude of the on-current at the start of or after the dead time, and wherein the second slope depends on the magnitude of the on-current; detecting expiration of a first time interval of a first on-switching event in the plurality of on-switching events; and increasing the on-current to a maximum value within at least a portion of the second time interval of the first on-switching event in response to the detected expiration of the first time interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Embodiments are described herein with reference to the accompanying drawings.

[0017] Figure 1 The left side of FIG. 1 shows a voltage circuit diagram of the dV / dt behavior in a power switch, and Figure 1 The right side of is a schematic representation of a power switch according to one or more embodiments;

[0018] Figure 2 is a schematic block diagram of a power inverter system according to one or more embodiments;

[0019] Figure 3 is a schematic block diagram of a dV / dt sensing and regulation circuit according to one or more embodiments;

[0020] FIG. 4A to FIG. 4C Schematic diagram showing different options for integrating HV capacitors on a gate driver IC according to one or more embodiments;

[0021] Figure 5 is a schematic block diagram of a dV / dt sensing and regulation circuit according to one or more embodiments;

[0022] Fig. 6A is a schematic block diagram of a dV / dt sensing and regulation circuit according to one or more embodiments;

[0023] Figure 6B is a schematic block diagram of a dV / dt sensing and regulation circuit according to one or more embodiments;

[0024] Figure 6Cis a schematic block diagram of a dV / dt sensing and regulation circuit according to one or more embodiments;

[0025] Fig.6D is a schematic block diagram of a dV / dt sensing and regulation circuit according to one or more embodiments;

[0026] Figure 7 is a schematic diagram of a dV / dt sensing circuit according to one or more embodiments;

[0027] Figure 8 An example of a register of a dV / dt regulator storing a plurality of bits b0-b9 plus an optional overflow bit, wherein b0 is the LSB and b9 or the overflow bit is the most significant bit (MSB) according to one or more embodiments is shown;

[0028] Fig. 9 A schematic diagram illustrating inverter branches across multiple transitions during different switching events according to one or more embodiments;

[0029] Fig.10 shows two signal graphs showing negative fully passive, partially passive, and active signals on the left and positive fully passive, partially passive, and active signals on the right according to one or more embodiments;

[0030] Fig.11 is a schematic diagram of another dV / dt sensing circuit according to one or more embodiments; and

[0031] Fig.12 is a signal diagram illustrating an output response of a signal Beta of a third comparator based on a voltage at a sense node according to one or more embodiments. DETAILED DESCRIPTION

[0032] Below, the details are set forth to provide a more thorough explanation of the exemplary embodiments. However, it will be apparent to those skilled in the art that these embodiments may be practiced without these specific details. In other examples, well-known structures and devices are shown in block diagram form or in schematic diagrams rather than in detail to avoid obscuring the embodiments. In addition, unless otherwise specifically noted, the features of the different embodiments described below may be combined with each other.

[0033] In addition, in the following description, identical or similar reference numerals are used to represent identical or similar elements or elements having identical or similar functions. Since identical or functionally equivalent elements are given the same reference numerals in the drawings, repeated descriptions of elements having the same reference numerals may be omitted. Therefore, descriptions provided for elements having the same or similar reference numerals are interchangeable.

[0034] In this regard, directional terms such as "top," "bottom," "below," "front," "rear," "back," "leading edge," "trailing," "above," and the like may be used with reference to the orientation of the drawings being described. Because portions of the embodiments may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and not for limitation. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. Therefore, the following detailed description should not be construed as limiting.

[0035] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intervening element. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0036] In the embodiments described herein or shown in the accompanying drawings, any direct electrical connection or coupling, i.e., any connection or coupling without additional intervening elements, may also be achieved by an indirect connection or coupling, i.e., a connection or coupling with one or more additional intervening elements, and vice versa, as long as the general purpose of the connection or coupling is essentially maintained, for example, for transmitting a certain signal or transmitting certain information. Features from different embodiments may be combined to form additional embodiments. For example, unless otherwise indicated, variations or modifications described with respect to one of the embodiments may also be applied to other embodiments.

[0037] The term "substantially" may be used herein to account for small manufacturing tolerances (eg, within 5%) that are considered acceptable in the industry without departing from aspects of the embodiments described herein.

[0038] A sensor may refer to a component that converts a physical quantity to be measured into an electrical signal such as a current signal or a voltage signal. The physical quantity may be, for example, a current or a voltage at a shunt resistor in a single shunt resistor system.

[0039] Signal processing circuits and / or signal conditioning circuits may receive one or more signals from one or more components and perform signal conditioning or signal processing on the one or more signals. Signal conditioning as used herein refers to manipulating a signal for further processing in a manner that the signal meets the requirements of the next level. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other process required to make the signal suitable for processing after conditioning.

[0040] Thus, the signal processing circuitry may include an analog-to-digital converter (ADC) that converts analog signals from one or more sensor elements into digital signals. The signal processing circuitry may also include a digital signal processor (DSP) that performs some processing on the digital signals.

[0041] Modern devices in automotive, consumer and industrial applications rely on power semiconductor devices for many functions such as converting electrical energy and driving motors or electric machines. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes, to name a few, have been used in a variety of applications including, but not limited to, switches in power supplies and power converters.

[0042] A power semiconductor device typically comprises a semiconductor structure configured to conduct a load current along a load current path between two load terminal structures or load electrodes (e.g., source / emitter and drain / collector) of the device. In addition, the load current path can be controlled by means of a control electrode, sometimes referred to as a gate electrode. For example, upon receiving a corresponding control signal from, for example, a driver unit, the control electrode can set the power semiconductor device to one of a conducting state or a blocking state. The control signal can be a voltage signal or a current signal having a controlled value.

[0043] A power transistor, also called a power switch or transistor switch, is a power semiconductor device that can be used to drive a load current. For example, an IGBT is turned on or off by activating and deactivating its gate terminal. Applying a positive input voltage signal between the gate and emitter will keep the device in its "on" state, while making the input gate signal zero or slightly negative will turn the device "off". There is a turn-on process and a turn-off process for turning a power transistor on and off a power transistor.

[0044] During the turn-on process, a gate driver integrated circuit (IC) can be used to provide (supply) a gate current (i.e., a turn-on current) to the gate of the power transistor in order to charge the gate to a sufficient voltage to turn on the device. In particular, current Io+ is a gate driver output current used to raise (i.e., charge) the gate of the power transistor during the turn-on transient. Therefore, current Io+ is used to turn on the power transistor.

[0045] In contrast, during the turn-off process, the gate driver IC is used to draw (sink) a gate current (i.e., a turn-off current) from the gate of the power transistor in order to discharge the gate sufficiently to turn off the device. Current Io- is the gate driver output current used to discharge the gate of the power transistor during the turn-off transient. Therefore, current Io- is used to turn off the power transistor.

[0046] According to the pulse width modulation (PWM) scheme, a voltage pulse can be output from the gate driver IC as a control signal. Therefore, the control signal can switch between an on voltage level and an off voltage level during the PWM period for controlling the power transistor. This in turn charges and discharges the gate voltage to turn on and off the power transistor, respectively.

[0047] In particular, the gate of the power transistor is a capacitive load, and the on-current (i.e., gate supply current) and the off-current (i.e., gate sink current) are specified as the initial current when the switching event is initiated. During the off-event, after a certain small amount of time (small compared to the PWM period), the gate current decreases and reaches a zero value when the gate reaches 0V. During the on-event, after a certain small amount of time (small compared to the PWM period), the gate current decreases and reaches a zero value when the gate reaches 15V.

[0048] The transistor may include an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET) (e.g., Si MOSFET or SiC MOSFET). Although IGBT may be used as an example in the following embodiments, it should be understood that MOSFET may replace IGBT, and vice versa. In this context, in any of the examples described herein, when MOSFET is used to replace IGBT, the drain of MOSFET may replace the collector of IGBT, the source of MOSFET may replace the emitter of IGBT, and the drain-source voltage V DS Can replace the collector-emitter voltage V of IGBT CE Therefore, any IGBT module can be replaced by a MOSFET module, and conversely any MOSFET module can be replaced by an IGBT module.

[0049] For example, in a power MOSFET, the gate is insulated by a thin silicon oxide. Therefore, the power MOSFET has capacitance between the gate-drain terminal, the gate-source terminal, and the drain-source terminal.

[0050] Ciss is the input capacitance and is the capacitance obtained by summing the gate-source capacitance Cgs and the gate-drain capacitance Cgd (Ciss = Cgd + Cgs); from the input point of view, Ciss is the capacitance of the MOSFET as a whole. This capacitance must be driven (charged) in order for the MOSFET to operate, so it is an important parameter when studying the drivability or input loss of the input device. Qg is the amount of charge required to drive (charge) Ciss.

[0051] Coss is the output capacitance obtained by adding the drain-source capacitance Cds and the gate-drain capacitance Cgd (Coss=Cds+Cgd), and is the total capacitance on the output side. If Coss is large, current due to Coss flows at the output even when the gate is turned off.

[0052] Crss is the gate-drain capacitance Cgd itself (Crss=Cgd), and is called feedback capacitance or reverse transfer capacitance. This parameter greatly affects the switching speed. Qgd is the amount of charge required to drive (charge) Crss.

[0053] These capacitances show a dependency on the drain voltage VDS. For example, the drain-source voltage VDS affects the value of Cds, and the drain-gate voltage VDG affects the value of Cgd.

[0054] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in an embodiment, the power semiconductor device can be configured to carry a load current to be supplied to a load and / or a load current provided by a power supply, respectively. For example, the semiconductor device can include one or more power semiconductor units, such as a monolithically integrated diode unit and / or a monolithically integrated transistor unit. Such a diode unit and / or such a transistor unit can be integrated in a power semiconductor module.

[0055] Power semiconductor devices comprising transistors suitably connected to form a half-bridge are commonly used in the field of power electronics. For example, a half-bridge can be used to drive an electric motor or a switched-mode power supply.

[0056] For example, a multiphase inverter is configured to provide multiphase power by supplying power to multiple phase loads (e.g., a three-phase motor). For example, three-phase power involves three symmetrical sine waves that are 120 electrical degrees out of phase with each other. In a symmetrical three-phase power system, three conductors each carry an alternating current (AC) with the same frequency and voltage amplitude relative to a common reference, but with a phase difference of one-third of a cycle. Due to the phase difference, the voltage on any conductor reaches its peak at one-third of a cycle after one of the other conductors and one-third of a cycle before the remaining conductors. This phase delay provides constant power transmission to a balanced linear load. This also makes it possible to generate a rotating magnetic field in the motor.

[0057] In a three-phase system feeding a balanced and linear load, the sum of the instantaneous currents in the three conductors is zero. In other words, the current in each conductor is equal in magnitude to the sum of the currents in the other two conductors, but of opposite sign. The return path for the current in any phase conductor is through the other two phase conductors. The instantaneous currents produce a current space vector.

[0058] The three-phase inverter includes three inverter branches, each inverter branch is used for each phase in the three phases, and each inverter branch is connected to a direct current (DC) voltage source in parallel with each other. Each inverter branch includes, for example, a pair of power transistors arranged in a half-bridge configuration to convert DC to AC. In other words, each inverter branch includes two complementary transistors (i.e., a high-side transistor and a low-side transistor) connected in series, and the two complementary transistors are turned on and off complementarily to each other to drive the phase load.

[0059] Turning on both the high-side transistor and the low-side transistor at the same time will result in a short circuit of the power supply through the bridge. This situation is called "bridge breakdown" and will most likely destroy the bridge. In order to avoid bridge breakdown, "dead time" can be added to the control scheme. With this additional time, one switch will always be turned off first, and the other switch will be turned on after the dead time expires. Therefore, the two switches are temporarily turned off during the dead time to ensure that the two switches are not turned on at the same time. Providing dead time can avoid bridge breakdown on the one hand, but on the other hand it also has adverse effects that will be described below.

[0060] As mentioned above, refer to Figure 1 , known as dV / dt V DS The voltage transient is initially very steep and rapid, then, when C GD As it gets larger, it changes to have a small slope, ending with a long, slow tail over the last few volts. This dynamic behavior is typical of transistor devices, and fast dV / dt transients and slow dV / dt transients are undesirable.

[0061] The fast dV / dt transient may be referred to as the first dV / dt transient or the initial dV / dt transient of a turn-on switching event, and the slow dV / dt transient may be referred to as the second dV / dt transient or the subsequent dV / dt transient of a turn-on switching event, wherein the slope of the fast dV / dt transient is much steeper than the slope of the slow dV / dt transient, and the duration of the fast dV / dt transient is much shorter than the duration of the slow dV / dt transient. As an example, the voltage slope dV / dt during the initial fast portion may have a slope of 50 volts per nanosecond, while the voltage slope dV / dt during the slow tail portion may be 50 volts per microsecond, which is 1000 times slower than the fast dV / dt portion. The change in slope may be detected by the sensing circuit described herein to detect the end of the initial fast portion and the beginning of the slow tail portion.

[0062] Therefore, according to one or more embodiments provided herein, the value of the on-current Io+ for the high-side power transistor can be adjusted via a high voltage (HV) gate driver (also referred to as a high-side gate driver). Similarly, the on-current Io+ for the low-side power transistor can be adjusted via a low voltage (LV) gate driver (also referred to as a low-side gate driver). The current Io+ can be set and / or adjusted during the on-switching event that occurs to cut off the slow tail portion of dV / dt, and can be set and / or adjusted at the next on-switching event to adjust the fast (steep) portion of dV / dt.

[0063] Figure 2 2 is a schematic block diagram of a power inverter system 200 according to one or more embodiments. The power inverter system 200 includes a single-phase motor drive stage 10 (ie, an inverter branch) and a gate driver 20 electrically coupled to the single-phase motor drive stage 10.

[0064] The single-phase motor drive stage 10 includes a low-side transistor 11 and a high-side transistor 12 controlled to provide a load current ILOAD to a motor (not shown). Both the transistor 11 and the transistor 12 can be super junction devices, and can be MOSFET (SJ-MOSFET) or IGBT (SJIBGT), but are not limited to super junction devices.

[0065] The gate driver 20 is a monolithic high voltage (HV) gate driver, which includes a low voltage (LV) gate driver 21 for driving the low-side transistor switch 11 and a HV gate driver 22 for driving the high-side transistor switch 12. The gate drivers 21 and 22 both perform gate drive of their respective power transistors 11 and 12 based on PWM signals LIN and HIN received from a microcontroller unit (MCU). The PWM signal is a control signal received from the MCU at the PWM logic unit 35 of the gate driver 20. The PWM logic unit 35 receives the LIN and HIN signals from the MCU and ensures that the minimum dead time is achieved to prevent bridge breakdown. Finally, the corresponding PWM signal is passed to the corresponding low-side gate driver 21 and the high-side gate driver 22, wherein the PWM signal HIN to the high-side gate driver 22 passes through the HV level shifter 25. After this, the low-side gate driver 21 and the high-side gate driver 22 perform dV / dt regulation and gate drive.

[0066] The gate drivers 21 and 22 include separate pre-driver circuits 26 and 27 and buffers 33 and 34, respectively. The pre-driver circuits 26 and 27 are configured to receive a PWM signal and control the on / off state of a corresponding first current source, such as a supply FET, for generating a current Io+ based on the PWM signal. In addition, the pre-driver circuits 26 and 27 are configured to receive a PWM signal and control the on / off state of a corresponding second current source, such as an absorption FET, for generating a current Io- based on the PWM signal. Respective current sources are provided in the buffers 33 and 34. Therefore, the buffers 33 and 34 may each include a pair of complementary FETs for generating an on current Io+ and an off current Io- for the corresponding power transistors 11 and 12.

[0067] Each of the pre-driver circuits 26 and 27 may also include a dV / dt regulator configured to control the magnitude of the on current Io+ and the off current Io- via the current sources in the control buffers 33 and 34. In other words, each dV / dt regulator commands the corresponding buffer 33 or 34 to use a specific current capability.

[0068] Therefore, the LV gate driver 21 and the HV gate driver 22 each include a pre-driver circuit, a first current source and a second current source, wherein the pre-driver circuit includes a dV / dt regulator for controlling the amplitude of the on current Io+ and the off current Io- provided to / from the power transistor.

[0069] The LV gate driver 21 is arranged in the low voltage domain, while the HV gate driver is arranged in the high voltage domain. In fact, the gate driver 20 also includes a termination region (not shown) isolating the high voltage domain from the low voltage domain, which can be referred to as an isolation termination region. Therefore, the termination region provides a high voltage isolation barrier between the two voltage domains.

[0070] The gate driver 20 may be configured to receive a PWM control signal from the MCU and to turn on or off the corresponding transistors 11 and 12 according to the received PWM control signal. For example, during the turn-on process of the corresponding transistor 11 or 12, the gate driver 20 may be used to provide (supply) a gate current to the gate of the corresponding transistor 11 / 12 so as to charge the gate. Conversely, during the turn-off process, the gate driver 20 may be used to draw (absorb) a gate current from the gate of the transistor 11 / 12 so as to discharge the gate.

[0071] Therefore, the MCU is electrically coupled to the gate driver 20 for transmitting information and control signals therebetween, and the gate driver 20 is electrically coupled to the inverter branch 10 for driving the power transistors of the inverter branch 10 .

[0072] The three regions of HV domain, LV domain and termination region are constructed as a whole in a single integrated circuit. The technology used to manufacture gate driver 20 is capable of constructing all three regions on a single silicon die and constructing a single IC gate driver. Between the HV domain and the LV domain is the termination region, whose main purpose is to electrically isolate the HV domain and the LV domain. The termination region in this particular technology (as well as in other high voltage technologies) includes a large diode that is usually used as a bootstrap diode 23 to charge the bootstrap capacitor 24. The level shifter 25 is used to convert (i.e., level shift) the control signal, thereby transmitting the control information from the low voltage / power domain to the high voltage / power domain.

[0073] In addition, Vb refers to the high-side floating supply voltage; Vs refers to the high-side floating ground voltage; Vcc refers to the supply voltage fixed by the low-side logic; Vss refers to the low-side ground voltage; HO refers to the high-side floating output voltage; LO refers to the low-side output voltage; DC+ refers to the DC link positive; DC- refers to the DC link negative; and HIN and LIN refer to the logic input voltage (i.e., control signal) received from the MCU. In some cases, for example, when a current-separated die is used, Vtypei and Vtype can be used to indicate two current-separated voltages or potentials of similar voltage types. For example, Vcci and Vcc related to the Vcc type can be used, but Vcci and Vcc are two current-separated voltages. Similarly, GNDi and GND can be used in this case.

[0074] Typically, Vb = Vcc-Vs-Vd, where Vd is the voltage drop across the bootstrap diode 23. When Vcc = 15V, Vs = 0V and the bootstrap diode 23 is forward biased and has a forward bias voltage drop of Vd = 0.5V, then Vb = 15V-0V-0.5V = 14.5V. That is, during normal operation, Vb is about 15V higher than Vs due to the supply of the bootstrap capacitor 24 to the high side. The positive power rail DC+ is typically in the range of 200-1200V, but is not limited thereto. Above this, when the low-side switch 11 is turned on (and the switch 12 is turned off), Vs is equal to DC- (e.g., Vss or 0V). DC- is a negative power rail and can be shorted to Vss, as shown, but not required. In this case, Vb is close to 15V, and the bootstrap capacitor 24 is charged by Vcc through the bootstrap diode 23. Otherwise, when high-side switch 12 is on (and switch 11 is off), Vs equals DC+, in which case Vb is 15V higher than DC+, and bootstrap capacitor 24 discharges slowly, ie bootstrap diode 23 is reverse biased and non-conducting.

[0075] The aforementioned voltages are set so that the high-side voltage domain operates in a voltage or power domain higher than the voltage or power domain of the low-side voltage domain. For example, when DC+ is 1200V, the low-side (external) supply voltage Vcc can be set to 15V, and the high-side supply voltage Vb can operate at a maximum voltage of 1215V.

[0076] The MCU coupled to the LV gate driver 21 is electrically coupled to the LV domain of the gate driver 20. Therefore, the MCU is configured to generate PWM control signals for controlling the transistors 11 and 12, and transmit the control signals to the gate driver 20 in the LV domain. For example, the gate driver 20 is configured to receive instructions from the MCU to drive the motor phases (i.e., inverter branches) connected to the voltage Vs using PWM control signals. These PWM control signals are received by the gate driver 20 in the LV domain (i.e., at the input pins HIN and LIN) and are passed to the corresponding HV gate driver 22 and LV gate driver 21 via appropriate logic (e.g., PWM logic 35, and level shifter 25 for the high side). The LV gate driver 21 and the HV gate driver 22 are configured to receive the PWM control signals and drive the corresponding power transistors 11 and 12 via the output terminals HO and LO of the gate driver 20.

[0077] Figure 3 is a schematic block diagram of a dV / dt sensing and regulation circuit 300 according to one or more embodiments. The dV / dt sensing and regulation circuit 300 includes a monolithic gate driver IC 301 having two separate voltage islands. The dV / dt sensing and regulation circuit 300 and Figure 2The power inverter system 200 shown in FIG. 1 is similar to that shown in FIG. 2 , but further includes an HV capacitor 30 connected between the low-side gate driver 21 and the high-side gate driver 22 for sensing and regulating the switching dV / dt for both the low-side switch 11 and the high-side switch 12. For example, the HV capacitor 30 may be connected to the low-side gate driver 21 and the high-side gate driver 22, such as Figure 7 As shown. The HV capacitor 30 in this example is capable of handling 200-1200V, but is not necessarily limited thereto. In this arrangement, one or more HV capacitors 30 may be used. Also shown are freewheeling diodes D1 and D2 coupled to their respective power transistors 11 and 12.

[0078] In addition, the LV gate driver 21 and the HV gate driver 22 each include a corresponding dV / dt regulator 31 or 32, which in this example is integrated with a corresponding pre-driver circuit. Both dV / dt regulators 31 and 32 sense and adjust the switch dV / dt in a similar manner by using the HV capacitor 30. In particular, the dV / dt regulators 31 and 32 use the HV capacitor 30 to measure the slope of dV / dt in an analog manner. The measured slope can then be used to adjust the dV / dt. The LV gate driver 21 and the HV gate driver 22 also each include a buffer 33 or 34, as described above.

[0079] The dV / dt sensing and regulating circuit 300 also includes a DC link power supply 40 (VDC), a low-side gate driver power supply 41 (VL), a high-side gate driver power supply 42 (VH), a decoupling capacitor 24L (e.g., a bootstrap capacitor) coupled in parallel to the low-side gate driver power supply 41, a decoupling capacitor 24H (e.g., a bootstrap capacitor) coupled in parallel to the high-side gate driver power supply 42, and a resistor R providing a path for current flow. The voltage VH is equal to Vb-Vs, and the voltage VL is equal to Vcc-Vss (i.e., Vcc-GND).

[0080] The gate driver IC 301 includes a logic unit 35, which includes circuits for processing signals received from the microcontroller via pins HIN and LIN, and also forwards PWM control signals from the MCU to dV / dt regulators 31 and 32. Therefore, ultimately, the corresponding PWM control signals are passed to the corresponding low-side gate driver 21 and high-side gate driver 22. Among them, the signal to the high-side gate driver is passed through the HV level shifter 25. After this, dV / dt regulation and gate driving are performed based on the PWM control signal. The logic unit 35 also ensures that the minimum dead time is achieved to prevent bridge breakdown.

[0081] The HV capacitor 30 is substantially linear such that its voltage is proportional to the charge stored therein and may be rated for at least 200 V. The HV capacitor 30 may be placed across two voltage domains, possibly external to or integrated on the gate driver IC 301, to measure the voltage slope (dV / dt) in active hard switching applications and thus regulate the next active switching event by adjusting the Io+ current according to the measured voltage slope dV / dt. For an active hard switching event, the voltage V DS or V CE The slope of (ie, dV / dt) occurs after the power switch 11 or 12 has taken over the load current.

[0082] Both dV / dt regulators 31 and 32 can use HV capacitor 30 to measure the slope of dV / dt, which includes the slope of the "fast" portion of dV / dt and the slope of the "tail" portion of dV / dt. The dV / dt regulators 31 and 32 can use the measured slope to adjust the next active switching event by adjusting the Io+ current according to the measured voltage slope dV / dt. In addition, the dV / dt regulators 31 and 32 can use the measured slope to detect the situation where dV / dt transitions from the fast portion to the tail portion. That is, the dV / dt regulators 31 and 32 can detect when the interval of the fast dV / dt expires and when the interval of the tail dV / dt begins.

[0083] After the time interval of the fast dV / dt expires (i.e., after the slope has been measured), the dV / dt regulators 31 and 32 can automatically enable the current Io+ to increase to its maximum value (Io+max) to cut off the long second tail effect of the dV / dt. Here, "cut off" means maximizing the dV / dt after the fast dV / dt period, thereby reducing or completely eliminating the duration of the tail effect. By maximizing the dV / dt, the voltage VDS develops faster toward DC+ or DC-, whichever is applicable. In this case, the gate drivers 21 and 22 are configured to provide the full maximum current Io+ to the gate of its corresponding transistor 11 or 12 in order to reduce the duration of the tail effect.

[0084] The advantage of this solution is that every type of dV / dt can be detected (ie fully passive, partially passive or active) and only active dV / dt can be selected for adjusting the voltage slope dV / dt.

[0085] The dV / dt regulators 31 and 32 may be configured to target a specific slope for the fast dV / dt and maintain the slope of the fast dV / dt at the target slope or within a target range by adjusting the Io+ current according to the measured voltage slope dV / dt to regulate the next active switching event.

[0086] For example, the target dV / dt may be of the order of 5 V / ns, which is a good compromise between electromagnetic noise and power dissipation in the power switches 11 and 12. In this example, the HV capacitor 30 may have a capacitance of 0.1 pF, which gives a current of 500 μA at a target slope of 5 V / ns, which is easily detected and measured.

[0087] For the HV capacitor 30, an external high voltage capacitor can be used, or the capacitor 30 can be integrated on the gate driver IC. Several solutions to build such HV capacitor on chip can be used.

[0088] One possibility is to use bond wires from pads in the HV side / domain to floating pads in the LV side / domain, both pads on the same IC, and use the pad metal-poly capacitance of the IC as the HV capacitor 30. Bond wires can be used because metal layers are usually not allowed to pass through the termination region.

[0089] Another possibility is to use metal-to-metal capacitors, where two different metal layers are used. There is a physical relationship between the oxide thickness and the applied voltage that can be withstood. For example, for a 600V application, the minimum thickness of the oxide layer may be 4μm.

[0090] Another possibility is to use n+ silicon instead of polysilicon as the second electrode.

[0091] In general, any pair of conductive layers may be used with one or more dielectric layers therebetween for capacitor 30. This allows some freedom in finding the dielectric thickness required for the rated voltage.

[0092] Another possibility to enable modular expansion to higher voltages is to use two or more capacitors in series.

[0093] FIG. 4A to FIG. 4C Schematic showing additional options for integrating HV capacitors on gate driver ICs.

[0094] For example, Figure 4AA metal layer 401 on the LV side of the gate driver IC and a floating metal pad 402 on the LV side are shown, wherein the metal pad 402 is coupled to a bonding wire 403, and the bonding wire 403 is coupled to a metal pad (not shown) on the HV side of the gate driver IC. A polysilicon layer 404 on the LV side is also provided. The metal polysilicon capacitor Clv and the pad metal polysilicon capacitor Chv can be connected in series as the HV capacitor 30.

[0095] Figure 4B A metal pad 502 on the LV side and a metal pad 505 on the HV side are shown coupled together by a bonding wire 503. The LV side and the HV side also include corresponding polysilicon layers 504 and 506. The LV side and the HV side of the gate driver IC are separated by a HV termination region 507, which isolates the HV side from the LV side. The pad metal polysilicon capacitor Clv and the pad metal polysilicon capacitor Chv can be connected in series as an HV capacitor 30. In this implementation, the two metal pads 502 and 505 and their bonding wires 503 remain floating, so their exact voltage is unknown when the entire gate driver IC 20 is connected to 0v. Even so, the voltage between the floating part and the chip should be in the range of several volts.

[0096] Figure 4C A plan view of a gate driver IC 20 according to one or more embodiments is shown. In particular, a HV domain 408, a LV domain 409, and an HV termination region 407 are shown, wherein the HV termination region 407 separates the two voltage domains 408 and 409. In addition, two metal concentric rings 410 and 411 (or c-shapes) are disposed in the HV termination region 407 above the HV well boundary, wherein one metal ring 410 is connected to the LV voltage domain 409 and the other metal ring 411 is connected to the HV domain 408. The portion of the metal ring 410 coupled to the LV domain 409 serves as a low voltage metal electrode of the capacitor 30, while the portion of the metal ring 411 coupled to the HV domain 408 serves as a high voltage metal electrode of the capacitor 30.

[0097] The accuracy of the dV / dt measurement is affected by the exact value of this capacitor. Even so, the accuracy using the described dV / dt adjustment is + / -40%, while the accuracy of the system without dV / dt adjustment is + / -66% to + / -300%. Therefore, the accuracy of the entire system can be improved using the dV / dt adjustment technique described in this article. If using Figure 7 If multiple capacitors or sensing circuits with resistors or comparator levels are used, fine tuning can be performed by changing the capacitance, resistor or comparator reference values ​​to further improve accuracy.

[0098] Figure 5is a schematic block diagram of a dV / dt sensing and regulation circuit 500 according to one or more embodiments. The dV / dt sensing and regulation circuit 500 includes a monolithic gate driver IC 501 having two separate voltage islands. The gate driver IC 501 is similar to Figure 3 301, but uses dual HV capacitors 30a and 30b instead of a single HV capacitor 30. Therefore, dV / dt regulators 31 and 32 each use their respective HV capacitors 30a or 30b to measure the voltage slope dV / dt of their respective power transistors 11 or 12, and update their respective register values ​​based on the measurement. The corresponding dV / dt regulator reads the register value to determine the current level of current Io+, and controls the two current sources to achieve the determined current level of current Io+.

[0099] HV capacitors 30a and 30b are integrated as shown to measure the voltage slope dV / dt. HV capacitor 30a is coupled to voltage Vs (i.e., floating ground voltage of the high-side region) and the input node of low-side dV / dt regulator 31 (e.g., coupled to Figure 7 and Fig.10 The voltage Vs pin of the gate driver IC 501 is coupled to the collector of the low-side switch 11 and the emitter of the high-side switch 12. The HV capacitor 30b is coupled to the ground Vss / GND (i.e., the ground voltage of the low-side region) and the input node of the high-side dV / dt regulator 32 (e.g., Figure 7 and 10 HVsense node described further in .

[0100] Alternatively, as described below, a single HV capacitor 30 may be used, such as Figure 3 and Figure 7 Therefore, in Figure 5 In the illustrated embodiment, a single HV capacitor may be coupled to both input nodes of the dV / dt regulators 31 and 32 .

[0101] Fig. 6A is a schematic block diagram of a dV / dt sensing and regulation circuit 600-1 according to one or more embodiments. The dV / dt sensing and regulation circuit 600-1 includes a multi-die gate driver with three separate voltage islands. In this case, galvanic isolation between ICs is used to galvanically isolate the dies. The gate driver includes the previously described Figure 2 , Figure 3 and Figure 5. The three separate voltage islands include logic IC 61, low voltage IC 62, and high voltage IC 63. Logic IC 61 provides information from logic unit 35 to IC 62 and IC 63 via transformers represented by TX and RX. Alternatively, the information can be transmitted through capacitors or another signal transmission method. The galvanic isolation barrier 64 is represented by the dotted lines between the different voltage islands.

[0102] The dV / dt regulators 31 and 32 use HV capacitors 30a and 30b integrated as shown to measure the voltage slope dV / dt. Specifically, the HV capacitor 30a is integrated on the low voltage IC 62 (i.e., the low side gate driver), and the HV capacitor 30b is integrated on the high voltage IC 63 (i.e., the high side gate driver). The HV capacitor 30a is coupled to the voltage Vs (i.e., the floating ground voltage of the high side region) and the input node of the low side dV / dt regulator 31 (e.g., coupled to Figure 7 and Fig.10 The voltage Vs pin of the high voltage IC 63 is coupled to the collector of the low side switch 11 and the emitter of the high side switch 12. The HV capacitor 30b is coupled to the ground Vss / GND (i.e., the ground voltage of the low side region) and the input node of the high side dV / dt regulator 32 (e.g., coupled to Figure 7 and Fig.10 HVsense node described further in .

[0103] Fig. 6A Further shown is a dVCE11 / dt sensing path 43 (i.e., dV / dt sensing of low-side transistor 11). The derivative of the VCE voltage of power transistor 11 will be sensed by dV / dt regulator 31. The VCE voltage of power transistor 11 is labeled VCE11. VH is the voltage of the power supply of high voltage IC 63, with decoupling capacitor 24H in parallel. VL is the power supply voltage of low voltage IC 62, with decoupling capacitor 24L in parallel. The power applied to the half-bridge formed by power transistors 11 and 12 comes from voltage source 40 having voltage VDC. At Figure 7 and Fig.10 dV / dt regulators 31 and 32 and capacitors 30 (30a and 30b) are described in FIG.

[0104] The sense path 43 from the emitter of the power transistor 11 to the collector of the power transistor 11 is as follows: The sense path 43 starts at the emitter of the power transistor 11 (DC- or Vss) and passes through VL or the decoupling capacitor 24L to Vcc. The sense path 43 continues from Vcc through the resistor 72 of the dV / dt regulator 31 to the LVsense node (see Figure 7 and Fig.10), and continues through capacitor 30a to reach Vs, which is equivalent to the collector of power transistor 11.

[0105] If Kirchhoff's voltage law is considered, it is as follows: VCE11 = VL - VR72 + VC30a, where VR72 is the voltage across resistor 72 and VC30a is the voltage across capacitor 30a. If this formula is differentiated, and it is assumed that the derivative of VL is 0 (i.e., the derivative of the DC voltage is 0) and the derivative of VR72 is much lower than the derivative of VCE11, then: dVCE11 / dt = dVC30a / dt. Then, the current flowing through capacitor 30a is iC30a = C30a*dVCE11 / dt, and the voltage drop across resistor 72 is VR72 = R72*iC30a = R72*C30a*VCE11 / dt.

[0106] Figure 6B is a schematic block diagram of a dV / dt sensing and regulating circuit 600-1 according to one or more embodiments. Specifically, Figure 6B Equivalent to Fig. 6A ,Apart from Figure 6B The dVCE12 / dt sense path 44 (ie, dV / dt sensing of the high-side transistor 12 ) is shown outside.

[0107] The derivative of the VCE voltage of the power transistor 12 will be sensed by the dV / dt regulator 32. The VCE voltage of the power transistor 12 is labeled VCE12. The sense path 44 from the emitter of the power transistor 12 to the collector of the power transistor 12 is as follows: the sense path 44 starts at the emitter (Vs) of the power transistor 12 and then passes through VH or the decoupling capacitor 24H to Vb. The sense path 44 continues through the resistor 82 of the dV / dt regulator 32 to the HVsense node (see Figure 7 and Fig.10 ), and continues through capacitor 30b to Vss. The sensing path 44 continues through the DC link power supply VDC to DC+, which is equivalent to the collector of power transistor 12.

[0108] If Kirchhoff's voltage law is considered, it is as follows: VCE12 = VH - VR82 - VC30b + VDC, where VR82 is the voltage across resistor 82, and VC30b is the voltage across HV capacitor 30b. If this formula is differentiated, and it is assumed that the derivatives of VH and VDC are 0 (i.e., the derivative of the DC voltage is 0), and the derivative of VR82 is much lower than the derivative of VCE12, then: dVCE12 / dt = -dVC30b / dt. Then, the current flowing through capacitor 30a is iC30b = C30b*(-dVCE12 / dt), and the voltage drop across resistor 82 is VR82 = R82*iC30b = R72*C30b*(-dVCE12 / dt).

[0109] Figure 6C is a schematic block diagram of a dV / dt sensing and regulation circuit 600-2 according to one or more embodiments. The dV / dt sensing and regulation circuit 600-2 includes a multi-die gate driver with three separate voltage islands. In this case, galvanic isolation between ICs is used. The gate driver includes the previously described Figure 2 , Figure 3 , Figure 5 , Fig. 6A and Figure 6B . The three separate voltage islands include logic IC 61, low voltage IC 62, and high voltage IC 63. Logic IC 61 provides information from logic unit 35 to IC 62 and IC 63 via transformers represented by TX and RX. Alternatively, the information can be transmitted through capacitors or another signal transmission method. The galvanic isolation barrier 64 is represented by the dotted lines between the different voltage islands.

[0110] The dV / dt regulators 31 and 32 use HV capacitors 30a and 30b integrated as shown to measure the voltage slope dV / dt. Specifically, the HV capacitor 30a is integrated on the low voltage IC 62, and the HV capacitor 30b is integrated on the high voltage IC 63. The HV capacitors 30a and 30b are coupled together so that the HV capacitor 30a is coupled to the HV capacitor 30b and the input node of the low-side dV / dt regulator 31 (e.g., coupled to Figure 7 and Fig.10 ). HV capacitor 30 b is coupled to HV capacitor 30 a and an input node of high-side dV / dt regulator 32 (e.g., coupled to Figure 7 and Fig.10 HVsense node described further in .

[0111] Therefore, the features of dV / dt sensing and control can be fully integrated without adding any additional pins. A monolithic solution with two separate voltage islands can be used. Alternatively, in a multi-die solution, galvanic isolation between the chips with three separate voltage islands can be used. In both cases, no additional voltage islands need to be added due to dV / dt sensing.

[0112] Figure 6C Also shown is a dVCE11 / dt sensing path 45 (i.e., dV / dt sensing of low-side transistor 11). The derivative of the VCE voltage of power transistor 11 will be sensed by dV / dt regulator 31. As previously described, the VCE voltage of power transistor 11 is labeled VCE11, and Figure 7 and Fig.10 dV / dt regulators 31 and 32 and capacitors 30 (30a and 30b) are described in FIG.

[0113] The sense path 45 from the emitter of the power transistor 11 to the collector of the power transistor 11 is as follows: the sense path 43 starts at the emitter of the power transistor 11 (DC- or Vss) and then goes through VL or decoupling capacitor 24L to Vcc. The sense path 45 continues from Vcc through resistor 72 of the dV / dt regulator 31 to the LVsense node (see Figure 7 and Fig.10 ) and continues through capacitors 30a and 30b to the HVsense node (see Figure 7 and Fig.10 ). Starting from the HVsense node, the sense path 45 continues through the resistor 82 to Vb and then through VH or the decoupling capacitor 24H to Vs, which is equivalent to the collector of the power transistor 11.

[0114] If Kirchhoff's voltage law is considered, it is as follows: VCE11 = VL - VR72 + VC30 - VR82 - VH. If this formula is differentiated, and it is assumed that the derivatives of VH and VL are 0 (i.e., the derivative of the DC voltage is 0), and the derivatives of VR72 and VR82 are much lower than the derivative of VCE11, then: dVCE11 / dt = dVC30 / dt. Then, the current flowing through capacitors 30a and 30b is iC30 = C30*dVCE11 / dt, and the voltage drop across resistor 72 is VR72 = R72*iC30 = R72*C30*dVCE11 / dt.

[0115] Fig.6D is a schematic block diagram of a dV / dt sensing and regulating circuit 600-2 according to one or more embodiments. Specifically, Fig.6D Equivalent to Figure 6C ,Apart from Fig.6D The dVCE12 / dt sense path 46 (ie, dV / dt sensing of the high-side transistor 12 ) is shown outside.

[0116] The derivative of the VCE voltage of the power transistor 12 will be sensed by the dV / dt regulator 32. The VCE voltage of the power transistor 12 is labeled VCE12. The sense path 46 from the emitter of the power transistor 12 to the collector of the power transistor 12 is as follows: the sense path 46 starts at the emitter (Vs) of the power transistor 12 and then passes through VH or the decoupling capacitor 24H to Vb. The sense path 44 continues through the resistor 82 of the dV / dt regulator 32 to the HVsense node (see Figure 7 and Fig.10 ) and continues through capacitors 30b and 30a to the LVsense node (see Figure 7 and Fig.10 ). From the LVsense node, the sense path 46 continues through resistor 72 to Vcc and then through VL or decoupling capacitor 24L to Vss. The sense path 46 continues through the DC link power supply VDC to DC+, which is equivalent to the collector of the power transistor 12.

[0117] If Kirchhoff's voltage law is considered, it is as follows: VCE12 = VH - VR82 - VC30 - VR72 - VL + VDC. If this formula is differentiated, assuming that the derivatives of VH, VL and VDC are 0 (i.e., the derivative of the DC voltage is 0), and that the derivatives of VR72 and VR82 are much lower than the derivative of VCE12, then: dVCE12 / dt = -dVC30 / dt. Then, the current flowing through capacitors 30a and 30b is iC30 = C30*(-dVCE12 / dt), and the voltage drop across resistor 82 is VR82 = R82*iC30 = R72*C30*(-dVCE12 / dt).

[0118] Therefore, any voltage source in the chain that senses the derivative of the VCE voltage of the driven power transistor with a capacitor can be considered as a short circuit, taking into account the sensing paths 43-46 and due to the fact that the derivative of the DC voltage source is zero. It is also possible to design the corresponding power supply to have a low impedance at a given frequency that the derivative of the VCE voltage will contain.

[0119] As will be described in further detail, one or more HV capacitors can be used to sense (e.g., sampled by an ADC or directly using a linear circuit) the dV / dt of the driven switch to regulate the dV / dt of the driven switch. The HV capacitor is indirectly connected between the driver and the collector / drain of the driven switch, where indirectly means by using one or more decoupling capacitors in the power circuit of the driven switch.

[0120] Figure 7 is a schematic diagram of a dV / dt sensing circuit 700 according to one or more embodiments. In particular, the dV / dt sensing circuit 700 includes a HV capacitor 30 electrically coupled between a dV / dt regulator 31 and a dV / dt regulator 32 .

[0121] The dV / dt regulator 31 includes a Zener diode 71 and a sense resistor 72 coupled in parallel between a local voltage source Vcc and a LVsense node. The LVsense node is also electrically coupled to the HV capacitor 30 and to the respective inputs of two comparators 73 and 74. The two comparators have different threshold levels (i.e., reference voltages) provided at one of the inputs of the comparator (e.g., the V+ input). For example, the first comparator 73 receives a first reference voltage equal to Vcc-Δ1, and the second comparator 74 receives a second reference voltage equal to Vcc-Δ2, where Δ1 is less than Δ2, and Δ1 and Δ2 are configurable.

[0122] LVsense is an analog node, so it senses the slope in an analog manner. In other words, since the linearity of the HV capacitor 30 and the sensitivity of the node are configurable (e.g., according to the selection of the HV capacitor 30 and the sensing resistor R), LVsense linearly senses the slope dV / dt. For example, the value of the sensing resistor R can be selected so that the voltage at the LVsense node is equal to Vcc-1V when the dV / dt slope is 1000V / microsecond. The sensing resistor R can be a variable resistor that can be adjusted based on the desired sensitivity. Therefore, the voltage at the LVsense node represents the slope dV / dt of the VDS of the power transistor 11 and is proportional to it.

[0123] The following example shows how the voltage at the LVsense node reacts to the slope of a dV / dt. In the absence of a dV / dt (i.e., the V DS In a steady state), LVsense is equal to Vcc. For the active fast portion of the dV / dt with a slope of 5000V / microsecond, LVsense can be equal to Vcc-5V. For the passive fast portion of the dV / dt with a slope of 1500V / microsecond, LVsense can be equal to Vcc-1.5V. For the tail portion of the dV / dt with a slope of 5V / microsecond, LVsense can be equal to Vcc-0.005V. Therefore, the voltage at the LVsense node represents the magnitude of the slope dV / dt of VDS of the power transistor 11.

[0124] When the voltage at the LVsense node is less than the first reference voltage Vcc–Δ1, the output of the first comparator 73 is “good” valid (e.g., “1”), otherwise it is “0”. When the voltage at the LVsense node is less than the second reference voltage Vcc-Δ2, the output of the second comparator 74 is “fast” valid (e.g., “1”), otherwise it is “0”. The outputs of the comparators 73 and 74 are then provided to a processing circuit that applies the output values ​​to a set of rules. The processing circuit then determines a result based on the set of rules. The result can be output from the processing circuit to the logic of the LV gate driver 21 in the form of instructions to adjust the on-current Io+ provided to the power transistor 11.

[0125] The dV / dt regulator 32 includes a Zener diode 81 and a sense resistor 82 coupled in parallel between a local voltage source Vb and an HVsense node. The HVsense node is also electrically coupled to the HV capacitor 30 and to the respective inputs of two comparators 83 and 84. The two comparators have different threshold levels (i.e., reference voltages) provided at one of the inputs of the comparator (e.g., the V+ input). For example, the first comparator 83 receives a first reference voltage equal to Vb-Δ1, and the second comparator 84 receives a second reference voltage equal to Vb-Δ2, where Δ1 is less than Δ2, and Δ1 and Δ2 are configurable.

[0126] Similar to LVsense, HVsense is an analog node, so it senses the slope in an analog manner. In other words, since the linearity of the HV capacitor 30 and the sensitivity of the node are configurable (for example, according to the selection of the HV capacitor 30 and the sensing resistor R), HVsense linearly senses the slope dV / dt. For example, the value of the sensing resistor R can be selected so that the voltage at the HVsense node is equal to Vb-1V when the dV / dt slope is 1000V / microsecond. The sensing resistor R can be a variable resistor that can be adjusted based on the desired sensitivity. Therefore, the voltage at the HVsense node represents the slope dV / dt of the VDS of the power transistor 12 and is proportional to it.

[0127] The following examples illustrate how the voltage at the HVsense node reacts to the slope of the dV / dt. In the absence of dV / dt (i.e., the VDS of the power switch is in a steady state), HVsense is equal to Vb. For the active fast portion of the dV / dt with a slope of 5000V / microsecond, HVsense can be equal to Vb–5V. For the passive fast portion of the dV / dt with a slope of 1500V / microsecond, HVsense can be equal to Vb–1.5V. For the tail portion of the dV / dt with a slope of 5V / microsecond, HVsense can be equal to Vb–0.005V. Therefore, the voltage at the HVsense node represents the magnitude of the slope dV / dt of the VDS of the power transistor 12.

[0128] When the voltage at the HVsense node is less than the first reference voltage Vb–Δ1, the output of the first comparator 83 is “good” valid (e.g., “1”), otherwise it is “0”. When the voltage at the HVsense node is less than the second reference voltage Vb-Δ2, the output of the second comparator 84 is “fast” valid (e.g., “1”), otherwise it is “0”. The outputs of comparators 83 and 84 are then provided to a processing circuit that applies the output values ​​to a set of rules. The processing circuit then determines a result based on the set of rules. The result can be output from the processing circuit to the logic of the HV gate driver 22 in the form of instructions to adjust the on-current Io+ provided to the power transistor 12.

[0129] Therefore, the HV capacitor 30 is connected to two local power supplies (Vcc on the low voltage side and Vb on the high voltage side) through resistors 72 / 82 and protection Zener diodes 71 / 81. The HV side dV / dt regulator 32 is responsible for determining the positive dV / dt level that occurs when the high side switch 12 driven by the HV gate driver 22 is turned on. The LV side dV / dt regulator 31 is responsible for determining the negative active dV / dt level that occurs when the low side switch 11 driven by the LV gate driver 21 is turned on.

[0130] During a positive dV / dt event, the HVsense node is pulled down compared to the static voltage, i.e., Vb. Otherwise, the HVsense node is equal to the static voltage. Similarly, during a negative dV / dt event, the LVsense node is pulled down compared to the static voltage, i.e., Vcc. Otherwise, the LVsense node is equal to the static voltage. The HV capacitance of capacitor 30 and the resistor values ​​of resistors 72 and 82 can both be used to adjust the sensitivity of the corresponding dV / dt regulators 31 and 32. Fine tuning can also be used if necessary.

[0131] As described above, two comparators are placed on each side (i.e., LV side and HV side) to sense the levels reached by the HVsense node and the LVsense node with two different threshold levels, where Δ1 < Δ2. In this way, the logic signal "good" will be valid at a slower (i.e., less steep) dV / dt relative to a "fast" (i.e., steeper) dV / dt. In other words, the voltage range between Δ1 and Δ2 defines the range where Figure 1 The target range of the slope dV / dt expected for the fast dV / dt portion is shown. The fast dV / dt portion is defined by a measurement interval during which it is enabled (and expected) to measure the slope of the fast dV / dt portion.

[0132] Therefore, in a dV / dt event, there may be three valid combinations of two logic signals output by a pair of comparators (ie, comparator pair 73 and 74, or comparator pair 83 and 84).

[0133] The first valid combination includes when both comparator outputs are valid. That is, when both the "good" and "fast" logic signals are valid. In this case, the fast dV / dt is faster than the target range, which indicates that Figure 1 The slope of the fast dV / dt portion in is too steep.

[0134] The second valid combination includes when the output of comparator 73 is valid and the output of comparator 74 is not valid or when the output of comparator 83 is valid and the output of comparator 84 is not valid. That is, when the "good" logic signal is valid and the "fast" logic signal is not valid. In this case, the fast dV / dt is within the target range, which indicates that Figure 1 The slope of the fast dV / dt portion is appropriate.

[0135] The third valid combination includes when both comparator outputs are not valid. That is, when neither the "good" nor the "fast" logic signals are valid. In this case, the fast dV / dt is slower than the target range, which indicates that Figure 1 The slope of the fast dV / dt portion in is too small. This could also mean that VDS is in steady state and there is no slope dV / dt.

[0136] Since the pulse width sensed at the LVsense (HVsense) node is equal to the duration of the negative (positive) active dV / dt, which is approximately 100ns (e.g., at DC+ equal to 600V and target dV / dt of 5V / ns In the example of ), the comparator input signals from each sensing node will last long enough so that each comparator will not be very fast. In addition, the height of the pulse sensed at the node LVsense or HVsense is set by the freely selectable values ​​of capacitor 30 and resistor 72 / 82. Therefore, by selecting appropriate resistances for resistors 72 / 82, the input signals at nodes LVsense and HVsense can be within the unit voltage range. Comparators 73, 74, 83 and 84 can be made very simple. For example, a simple CMOS inverter with different switching thresholds can be used as a comparator. The CMOS inverter has the advantage of not dissipating static power, and since the static input is equal to the supply voltage, this is an advantage in a bootstrap power supply system where the static power consumption in the HV region should be low.

[0137] Alternatively, other types of comparators or devices that perform the comparison may be used, including but not limited to an ADC sampler that samples the value of the sense node and a microprocessor that compares the sample to two threshold levels.Linear circuits can also be used to measure dV / dt transients.

[0138] In summary, after a valid active switching measurement, there may be three situations: dV / dt is faster than the target range, dV / dt is within the target range, or dV / dt is slower than the target range. In order to converge to the correct current Io+ required for the application (taking into account variable conditions such as temperature, supply voltage, etc.), the measurement results are digitally integrated in a digital register using an algorithm or rule set in the three measurement situations, for example. In the first case (i.e., dV / dt is faster than the target range), the register value is reduced by 1 least significant bit (LSB). In the second case (i.e., dV / dt is within the target range), the register value is maintained or remains unchanged. In the third case (i.e., dV / dt is slower than the target range), the register value is increased by 1 LSB.

[0139] Figure 8 An example of a register 80 of a dV / dt regulator is shown, which stores a plurality of bits b0-b9 plus an optional overflow bit, wherein b0 is the LSB and b9 or the overflow bit is the most significant bit (MSB). In addition, the register 80 can be divided into multiple sections, including a buffer portion, a valid portion, and an overflow bit.

[0140] Each dV / dt regulator has a corresponding register 80 that indicates the magnitude of the Io+ current based on a binary coded value stored therein. Alternatively, it will be appreciated that a thermometer encoding may be used. The logic of the corresponding HV gate driver or LV gate driver implements the Io+ current based on the register value. The register 80 has n bits in the "valid portion," the bits of which select and indicate a binary-weighted Io+ current component. That is, the binary-weighted Io+ current component adds an amplitude component to the default Io+ component. The default Io+ component exists in all cases as a low-level current that cannot be turned off. Otherwise, if there is no Io+ current, there will be no turn-on switching event, dV / dt cannot be measured, and the system will be blocked.

[0141] Therefore, if bits b4-b9 are all zero, the Io+ current programmed by the dV / dt regulator is set to the default level Io+. If bit b4 stores 1, a current value ΔI is added to the default level Io+. If bit b5 stores 1, a current value 2ΔI is added to the default level Io+. If bit b6 stores 1, a current value 4ΔI is added to the default level Io+. If bit b7 stores 1, a current value 8ΔI is added to the default level Io+. If bit b8 stores 1, a current value 16ΔI is added to the default level Io+. If bit b9 stores 1, a current value 32ΔI is added to the default level Io+. The values ​​stored in bits b4-b9 are adjusted based on the output of the comparator pair (73 and 74 or 83 and 84) and the algorithm applied.

[0142] Register 80 may also have m "buffer" least significant bits which have no direct effect on the Io+ value but which may be used to stabilize the Io+ level, for example to avoid a ping-pong effect.

[0143] Finally, register 80 may also have an overflow bit for fault condition detection. For example, the overflow bit may be used when the maximum Io+ current is insufficient. This may occur when all n bits (i.e., bits b4-b9) are 1 and the dV / dt regulator still detects a third condition (i.e., dV / dt is slower than the target range). Since all n bits are "full", the register value cannot be increased further. Instead, a 1 is stored in the overflow bit to indicate to the system that the current Io+ of the LV gate driver or HV gate driver cannot be increased further enough to bring the dV / dt within the target range.

[0144] The dV / dt regulator is configured to adjust the Io+ current based on the register value of the next active switching event. In other words, during the current or first active switching event, the dV / dt regulator measures the fast dV / dt transient and updates or maintains the register value based on the output of the comparator. On the next active switching event following the first active switching event, the dV / dt regulator reads the register value stored in register 80 and controls the magnitude of the Io+ current for the fast dV / dt period of the next active switching event based on the register value. At the same time, the dV / dt regulator again measures the fast dV / dt transient during the next active switching event, and the process repeats.

[0145] Furthermore, after the period of fast dV / dt expires (e.g., the period may have a duration of 500ns-1us, but is not limited thereto), the dV / dt regulator is configured to increase the Io+ current to its maximum value in order to cut off the long second tail of the dV / dt. The maximum value may be an "uncontrolled" level at which the current source (e.g., supply FET) generating the Io+ current is fully turned on.

[0146] The conditions that determine the correct value for the Io+ current are those that change slowly over time or not at all (eg, switch characteristics, temperature, load current, power supply, etc.) so the system can achieve the target range and track the required changes.

[0147] To avoid gating erroneous measurement results into register 80, the dV / dt measurement may be verified before gating the result into the register.

[0148] The first level of verification is that the measurement is valid only within a short time window (~500ns-1us) after the corresponding power device gate starts to rise (or after LIN / HIN turn-on commutation). This should avoid most erroneous measurements caused by large DC bus noise caused by another inverter branch switch, for example.

[0149] Fig. 9 A schematic diagram of an inverter branch across multiple transitions during different switching events according to one or more embodiments is shown. In normal operation, the two power switching devices 11 and 12 of the inverter branch are turned on and off one after another. Since the power switching devices are not ideal, the number of turn-on times and the number of turn-off times are not strictly the same. Turning on both devices at the same time will cause bridge breakdown. In order to avoid this, a dead time is added to the control scheme of the two power transistors 11 and 12. With this additional time, one switch will always be turned off first, and the other switch will be turned on after the dead time expires. Providing a dead time can avoid bridge breakdown on the one hand, but it also has adverse effects on the other hand.

[0150] The load current can be positive (i.e., flowing from the half-bridge to the motor) or negative (i.e., flowing from the motor to the half-bridge). In both cases, there are three possible settings for the switches of the inverter branches: the high-side switch is off and the low-side switch is off; the high-side switch is on and the low-side switch is off; or the high-side switch is off and the low-side switch is on.

[0151] First, assume that the load current is positive, the high-side switch 12 switches from on to off, and the low-side switch 11 switches from off to on, as shown in Fig. 9 As shown in the upper part of , or the high-side switch 12 switches from off to on, and the low-side switch 11 switches from on to off, as Fig. 9 During the effective dead time, both devices are off and the freewheeling diode D2 of the low-side switch 11 conducts the output current to the motor.

[0152] There are three different types of negative dV / dt: completely passive, partially passive, and active. Similarly, there are three different types of positive dV / dt: completely passive, partially passive, and active. Fig.10 Two signal graphs are shown showing negative fully passive, partial passive, and active signals on the left and positive fully passive, partial passive, and active signals on the right, according to one or more embodiments.

[0153] For active negative dV / dt, Vs remains at the high voltage of the DC link (i.e., DC+) throughout the dead time, and then drops to the low voltage of the DC link (i.e., DC-) after the dead time. Therefore, for active negative dV / dt, the Vs slope is outside the dead time. On the other hand, in a fully passive negative dV / dt, the Vs slope is completely within the dead time before the low-side switch 11 is turned on. For a partially passive negative dV / dt, the Vs slope is partially within the dead time and partially outside the dead time. In addition, when a partial passive dV / dt occurs, the output of the comparator of the dV / dt regulator may be unreliable in the valid window because the pulse on the HVsense node or the LVsense node has a small duration. For example, the duration may be so short that the comparator does not trip at all, and the two comparators are unable to distinguish this situation from the situation where the dV / dt is slower than the target range.

[0154] In this case, the negative active dV / dt is driven by turning on the low-side switch 11 , while the partial passive dV / dt and the fully passive dV / dt are driven by turning off the high-side switch 12 .

[0155] In other cases where the load current is negative, the low-side switch 11 switches from on to off, and the high-side switch 12 switches from off to on. Here, the freewheeling diode D1 conducts the load current during the dead time. There are three different types of positive dV / dt: fully passive, partially passive, and active.

[0156] For active positive dV / dt, Vs remains at the low voltage of the DC link (i.e., DC-) throughout the dead time and then rises to the high voltage of the DC link (i.e., DC+) after the dead time. Therefore, for active positive dV / dt, the Vs slope is outside the dead time. On the other hand, in a fully passive positive dV / dt, the Vs slope is within the dead time before the high-side switch 12 is turned on. For a partially passive positive dV / dt, the Vs slope is partially within the dead time and partially outside the dead time. In addition, when a partially passive dV / dt occurs, the output of the comparator of the dV / dt regulator may not be reliable in the valid window because the pulse on the HVsense node or the LVsense node has a small duration. For example, the duration may be so short that the comparator does not trip at all, and the two comparators are unable to distinguish this situation from the situation where the dV / dt is slower than the target range.

[0157] In this case, the positive active dV / dt is driven by turning on the high-side switch 12 , while the partial passive dV / dt and the full passive dV / dt are driven by turning off the low-side switch 11 .

[0158] The power switch is sized to easily conduct currents above the maximum load current. Therefore, the dV / dt slope is steeper when switching is performed actively. Vice versa, during fully passive switching, dV / dt is slower (no EMI issues), but energy is not dissipated in the power switch because both are turned off. In a partially passive switch, there is a first passive portion of the switching event, followed by a second active portion. In the first passive portion, dV / dt behaves as during fully passive switching (i.e., slower and no power dissipation in the switch). In the second active portion, dV / dt behaves as during active switching. For the second active portion, the current Io+ can be set based on measurements made during the previous active switching event. However, dV / dt is not measured during the second active portion of the partially passive switch because erroneous measurements due to short pulse durations may occur. Therefore, dV / dt measurements during the second active portion may be unreliable.

[0159] The dV / dt regulators 31 and 32 are configured to determine the type of negative dV / dt and positive dV / dt, and only regulate active dV / dt while ignoring passive dV / dt. Specifically, the dV / dt regulator can verify that the dV / dt is active before enabling its register 80 to be updated. In order to achieve this determination of the type of dV / dt, a third comparator is introduced in each dV / dt regulator 31 and 32.

[0160] Fig.111 is a schematic diagram of a dV / dt sensing circuit 1000 according to one or more embodiments. In particular, the dV / dt sensing circuit 1000 is similar to the dV / dt regulators 31 and 32 except that additional third comparators 75 and 85 are added to the dV / dt regulators 31 and 32. Figure 7 The dV / dt sensing circuit 700 shown is similar. Comparators 75 and 85 are used to verify that the dV / dt being measured is an active dV / dt.

[0161] As described above, the sense nodes LVsense and HVsense detect the extent of the slope dV / dt. Similar to other comparators, the third comparator 75, 85 reacts according to the voltage at the sense node relative to its threshold voltage. The constant Δ3 is significantly lower than the other constants Δ1 and Δ2 (i.e., Δ3<<Δ1, Δ2), so that the threshold level (i.e., the reference voltage) at the input of the third comparator 75 or 85 is higher than the other threshold levels. In this way, the logic output of the third comparator is valid on any "fast" dV / dt (including active dV / dt and passive dV / dt). However, due to the decrease in slope during the slow tail portion of dV / dt, the third comparator is not valid on the slow tail portion of dV / dt. That is, at the moment when dV / dt changes from the "fast" portion to the "tail" portion, the voltage at the sense node reacts so that the voltage is greater than the threshold level of the third comparator 75, 85. This causes the output of the third comparator 75 , 85 to switch (eg, from 1 to 0), indicating that the “fast” portion of the dV / dt has expired and the “tail” portion of the dV / dt has begun.

[0162] Fig.12 is a signal diagram showing the output response of the signal Beta of the third comparator 75 based on the voltage at the LVsense node according to one or more embodiments. The voltage at the LVsense node represents the slope of dV / dt. The third comparator 85 operates similarly based on the voltage at the HVsense node. Therefore, the third comparator 75, 85 with an accurately selected threshold can distinguish between two families of slopes: (1) active slope and passive slope on one side, and (2) tail slope or steady state on the other side.

[0163] For example, the tail portion may be 100 times or even 1000 times slower than any type of fast dV / dt portion. By way of example only, in the tail portion, the dV / dt may be in the 1-5V / microsecond range and be fundamentally different from and orders of magnitude lower than the fast portion, where during the fast portion, the passive dV / dt may be 500-3000V / microsecond and the active dV / dt may be 4500-5500V / microsecond. Thus, the third comparator may detect the slow tail portion, for example, by switching the output of the third comparator from high (e.g., “1”) to low (e.g., “0”) in response to an order of magnitude reduction in the voltage slope relative to any type of fast dV / dt. The order of magnitude may be 100 or greater.

[0164] For example, the third comparator 75 receives a third reference voltage equal to Vcc-Δ3, where Δ3 is configurable. When the voltage at the LVsense node is less than the third reference voltage Vcc-Δ3, the output "Beta" of the third comparator 75 is valid (e.g., "1"), otherwise it is "0". Since the third reference voltage is relatively close to Vcc, a drop from Vcc greater than Δ3 can be detected, indicating that the slope of the fast dV / dt has begun. The output "Beta" of the third comparator 75 is provided to the processing circuit, which applies the output together with the output "fast" and the output "good" to an algorithm or rule set. The processing circuit then determines a result based on the algorithm, where the result can be used to update or maintain the register 80. The result can be output from the processing circuit to the logic of the LV gate driver 21 in the form of an instruction to adjust the on-current Io+ provided to the power transistor 11.

[0165] Similarly, the third comparator 85 receives a third reference voltage equal to Vb-Δ3, where Δ3 is configurable. When the voltage at the HVsense node is less than the third reference voltage Vb-Δ3, the output "Beta" of the third comparator 85 is valid (e.g., "1"), otherwise it is "0". Since the third reference voltage is relatively close to Vb, a drop from Vb greater than Δ3 can be detected, indicating that the slope of the fast dV / dt has begun. The output "Beta" of the third comparator 85 is provided to a processing circuit that applies the output together with the output "fast" and the output "good" to an algorithm or rule set. The processing circuit then determines a result based on the algorithm, where the result can be used to update or maintain the register 80. The result can be output from the processing circuit to the logic of the HV gate driver 22 in the form of an instruction to adjust the on-current Io+ provided to the power transistor 12.

[0166] The algorithm of each gate driver 21 and 22 (ie each dV / dt regulator) can now distinguish between four different measurement situations.

[0167] In the first case, the "Good", "Fast" and "Beta" signals are all active. As a result, it is determined that the dV / dt is faster than the target range, and the register value of register 80 is decreased by 1 least significant bit (LSB).

[0168] In the second case, both the "Good" and "Beta" signals are valid, but the "Fast" signal is not valid. As a result, it is determined that the dV / dt is within the target range, and the register value of register 80 is maintained or remains unchanged.

[0169] In the third case, neither the "Good" nor the "Fast" signal is valid, but the "Beta" signal is valid. As a result, it is determined that the dV / dt is slower than the target range, and the register value of register 80 is increased by 1 LSB.

[0170] Finally, in the fourth case, none of the "Good", "Fast" and "Beta" signals are active. Thus, prior to the on command to the power transistor, no signal is active in the measurement window, or the "Beta" signal is active. In this case, dV / dt is passive, and the value of register 80 is maintained or remains unchanged (i.e., the dV / dt regulator does not take any action).

[0171] In addition, if the "Beta" signal is valid before the validation window (i.e., if the "Beta" signal is valid during the dead time), this means that a full or partial passive dV / dt event has occurred. In this case, when the "Beta" signal is valid during any portion of the dead time, the processing circuit of the dV / dt regulator is configured to ignore any data from the comparator for a predetermined duration, and data should not be gated into the register 80. Therefore, in the case where the "Beta" signal is valid during the dead time before the active switching event, any new data is ignored by the processing circuit (e.g., not gated into the register 80). In other words, the processing circuit of each dV / dt regulator 31 and 32 is configured to track the dead time and distinguish active dV / dt events from passive dV / dt events based on whether the "Beta" signal is valid during any portion of the dead time or only after the dead time expires. Thus, this effectively enables the dV / dt regulators 31 and 32 to ignore passive or partially passive dV / dt and only allow data to be gated into the register 80 during active switching events.

[0172] As described above, the high sensitivity dV / dt sensing signal "Beta" can be used to detect the end of the fast portion of the dV / dt and the beginning of the tail portion of the dV / dt. Upon detecting such a change in the signal "Beta", the processing circuitry of the dV / dt regulator 31 or 32 can indicate to the gate driver that an active or passive switching event has expired. In response, the gate driver can fully turn on its corresponding power transistor 11 or 12 so that the current Io+ is at a maximum value for a second duration including a second interval of the dV / dt. More specifically, the current remains at its maximum value starting from the end of the fast portion of the dV / dt, through the tail portion of the dV / dt, until the next switching event. This maximized current reduces Figure 1 The typical slow dV / dt tail of a power device is shown, because the dV / dt in the tail has a very low dV / dt. Therefore, this correction of the slow tail dV / dt is performed in real time, as opposed to the correction of the fast dV / dt which is corrected in the next active switching event.

[0173] Another advantage can exist in regulating fast dV / dt with precisely selected Io+ current and fully turning on the power switch using all available current after the fast dV / dt expires. This technique can help keep the power switch itself fully turned on even when noise is coupled to its gate.

[0174] In view of the above, a dV / dt sensing circuit having a dV / dt regulator for each power transistor is configured to autonomously and dynamically regulate dV / dt using one or more linear HV capacitors. Each dV / dt regulator uses one or more HV capacitors to sense the voltage slope dV / dt of the driven power transistor to regulate the dV / dt of the same driven power transistor. The capacitors can be integrated on the gate driver chip, and the capacitors are used to detect the type (active, passive or partially passive) and speed (fast dV / dt or slow tail) of the voltage slope dV / dt, and regulate accordingly: in the next active switching event, adjust the Io+ current, and in the same switching event, cut off the slow tail.

[0175] Using one or more HV capacitors for sensing (sampling by ADC or directly using linear circuits), the voltage slope dV / dt of the driven power transistor can be measured to adjust the dV / dt of the driven power transistor. The HV capacitor can be indirectly connected between the gate driver and the collector / drain of the driven power transistor. Indirect is defined as one or more decoupling capacitors in the system using the driven power transistor. This configuration gives the advantage that in a half-bridge or bridge branch, this omits one additional high voltage pin in the driver package that needs to be isolated from all other pins.

[0176] Additionally, one or more capacitors connected between the low-side gate driver and the high-side gate driver may be used to sense and regulate the switching dV / dt of both the low-side switch and the high-side switch, independent of the regulation method as described herein, and regardless of whether an ADC with multiple samples and digital cycle-to-cycle regulation or linear circuit regulation is used.

[0177] Typically, it is the collector-emitter voltage or drain-source voltage of the two switches that should be regulated. Preferably, the feedback capacitor is connected from the collector or drain of the driven switch to the sense input of the gate driver (which is referenced to the emitter or source of the driven switch). However, in a half-bridge configuration (such as a Buck or Boost configuration), if it is desired to save capacitors, a single HV capacitor 30 can be used, such as Figure 3 , Figure 7 and Fig.10 This can be done because, from a small signal point of view, the emitter or source of the low-side switch is the same as the collector or drain of the high-side switch.

[0178] Additionally, if it is preferred to use an integrated capacitor / capacitors (either in the gate driver package in a system-in-package or on one or more gate driver dies in a system-on-silicon), one more high voltage pin may be added to the package, which would require creepage distances to other nodes / pins if two separate capacitors were used to sense the collector / drain directly. For a half-bridge driver, the different voltage clusters are: input control signals and low-side gate driver supply and output, high-side gate driver supply and output, and finally dV / dt sensing on the collector / drain of the high-side switch. Since only two signal clusters require creepage distances, two separate sides of the package, a dual small outline (DSO) type package, can be used and the distance is almost free. For the third node, a lot of package space is used.

[0179] So the bottom line here is that if the described configuration is used, the features of dv / dt sensing and control can be fully integrated without adding any additional pins. For example, a monolithic solution with two separate voltage islands or a multi-die solution with galvanic isolation between the chips and three separate voltage islands can be used. What both examples have in common is that since the dv / dt sensing is fully integrated, no additional voltage islands need to be added.

[0180] Although various embodiments have been described, it will be apparent to those of ordinary skill in the art that more embodiments and implementations are possible within the scope of the present disclosure. Therefore, the present invention is not limited except in accordance with the appended claims and their equivalents. With respect to the various functions performed by the above-mentioned components or structures (assemblies, devices, circuits, systems, etc.), unless otherwise indicated, the terms used to describe these components (including references to "devices") are intended to correspond to any component or structure that performs the specified functions of the described components (i.e., functionally equivalent), even if the structure is not structurally equivalent to the disclosed structure that performs the functions in the exemplary embodiments of the present invention shown herein.

[0181] In addition, the attached claims are hereby incorporated into the detailed description, where each claim can be independently presented as a separate example embodiment. Although each claim can be independently presented as a separate example embodiment, it should be noted that although a dependent claim may refer to a specific combination with one or more other claims in a claim, other example embodiments may also include a combination of a dependent claim with the subject matter of each other dependent claim or independent claim. Unless it is stated that a specific combination is not intended, such a combination is proposed herein. In addition, it is intended to include the features of a claim to any other independent claim, even if the claim is not directly subordinate to the independent claim.

[0182] It should also be noted that the methods disclosed in the specification or claims may be implemented by a device having means for performing each of the individual actions of these methods.

[0183] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in the specification or claims should not be interpreted as being in a specific order. Therefore, unless these actions or functions are not interchangeable for technical reasons, the disclosure of multiple actions or functions does not limit these actions or functions to a specific order. In addition, in some embodiments, a single action may include or may be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included and are part of the disclosure of the single action.

[0184] Depending on certain implementation requirements, the embodiments provided herein can be implemented in hardware or software. This implementation can be performed using a digital storage medium in which an electronically readable control signal is stored, such as a floppy disk, DVD, Blu-ray, CD, RAM, ROM, PROM, EPROM, EEPROM or flash memory, which cooperates (or can cooperate) with a programmable computer system to perform the corresponding method. Therefore, the digital storage medium can be computer readable.

[0185] Instructions may be executed by one or more processors, such as one or more central processing units (CPUs), digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, as used herein, the term "processor" refers to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules. Similarly, the technology may be fully implemented in one or more circuits or logic elements.

[0186] Thus, the techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented in one or more processors including one or more microprocessors, DSPs, ASICs, or any other equivalent integrated or discrete logic circuits, as well as any combination of such components.

[0187] The control unit including the hardware may also perform one or more of the techniques described in the present disclosure. Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure. The software may be stored on a non-transitory computer-readable medium such that the non-transitory computer-readable medium includes a program code or program algorithm stored thereon that causes the computer program to perform the steps of the method when executed.

[0188] Although various exemplary embodiments have been disclosed, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention, which changes and modifications will achieve some of the advantages of the concepts disclosed herein. It will be apparent to those skilled in the art that other components performing the same functions may be appropriately replaced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be mentioned that even in features not explicitly mentioned, features explained with reference to a particular drawing may be combined with features of other drawings. Such modifications to the general inventive concept are intended to be covered by the appended claims and their legal equivalents.

Claims

1. A gate driver circuit, comprising: a gate driver configured to: generate an on-current to drive a transistor during a plurality of on-switching events, wherein a voltage across the transistor changes from a first value to a second value at a slope during the plurality of on-switching events, wherein the slope is an active type or a passive type, and wherein the active type slope depends on a magnitude of the on-current; and a sensing circuit configured to: determine whether the slope during a first conduction switching event is the active type or the passive type, and if the slope is the active type, adjust the magnitude of the conduction current during a second conduction switching event subsequent to the first conduction switching event, and if the slope is the passive type, keep the magnitude of the conduction current unchanged during the second conduction switching event, Wherein, if the slope occurs at least partially within a dead time of a switching cycle including the first turn-on switching event, the slope is of the passive type, and wherein, if the slope occurs completely after the dead time of the switching cycle, the slope is of the active type.

2. The gate driver circuit according to claim 1, wherein: The sensing circuit is also configured to measure the slope of the voltage during the first conduction switching event, compare the measured slope with a target slope range to generate a comparison result, and adjust the amplitude of the conduction current during the second conduction switching event based on the comparison result so that the slope of the voltage during the second conduction switching event is within the target slope range.

3. The gate driver circuit according to claim 2, wherein: Based on the comparison result, the sensing circuit is further configured to: If the measured slope is above the target slope range, reducing the magnitude of the on-current within the second on-switching event; If the measured slope is within the target slope range, keeping the magnitude of the conduction current constant during the second conduction switching event; as well as If the measured slope is below the target slope range, the magnitude of the on-current is increased within the second on-switching event.

4. The gate driver circuit according to claim 1, further comprising: a high-side region operating in a first voltage domain; a low-side region operating in a second voltage domain lower than the first voltage domain; as well as a capacitor coupled to the high-side region and to the low-side region, The sensing circuit is coupled to the capacitor to detect and measure the slope.

5. The gate driver circuit according to claim 4, wherein: The gate driver and the sensing circuit are disposed in the high-side region, and the transistor is a high-side power transistor.

6. The gate driver circuit according to claim 5, wherein: The capacitor is coupled to an input node of the sensing circuit and to a ground voltage of the low-side region.

7. The gate driver circuit according to claim 5, further comprising: another gate driver disposed in the low-side region and configured to drive a low-side power transistor complementary to the high-side power transistor; another sensing circuit disposed in the low-side region and configured to sense a voltage across the low-side power transistor, the voltage across the low-side power transistor having another slope that changes during conduction of the low-side power transistor, The capacitor is coupled to an input node of the sensing circuit and to an input node of the other sensing circuit.

8. The gate driver circuit according to claim 4, wherein: The gate driver and the sensing circuit are disposed in the low-side region, and the transistor is a low-side power transistor.

9. The gate driver circuit according to claim 8, wherein: The capacitor is coupled to an input node of the sensing circuit and a floating ground voltage of the high-side region.

10. The gate driver circuit according to claim 8, further comprising: another gate driver disposed in the high-side region and configured to drive a high-side power transistor complementary to the low-side power transistor; another sensing circuit disposed in the high-side region and configured to sense a voltage across the high-side power transistor, the voltage across the high-side power transistor having another slope that changes during conduction of the high-side power transistor, The capacitor is coupled to an input node of the sensing circuit and to an input node of the other sensing circuit.

11. The gate driver circuit according to claim 1, wherein: Each of the plurality of conducting switching events comprises a first time interval and a second time interval following the first time interval, The slope includes an initial slope during the first time interval and a second slope during the second time interval, wherein the initial slope is greater than the second slope, and The sensing circuit is also configured to determine whether an initial slope during the first turn-on switching event is of the active type or the passive type, and if the initial slope during the first turn-on switching event is of the active type, adjust the amplitude of the turn-on current during the second turn-on switching event, and if the initial slope during the first turn-on switching event is of the passive type, maintain the amplitude of the turn-on current unchanged during the second turn-on switching event.

12. The gate driver circuit according to claim 11, wherein: The sensing circuit is also configured to measure an initial slope of the voltage during the first on-switching event, compare the measured initial slope with a target slope range to generate a comparison result, and adjust the magnitude of the on-current during the second on-switching event based on the comparison result.

13. The gate driver circuit according to claim 11, wherein: The sensing circuit is further configured to detect expiration of a first time interval of the first conductive switching event and to increase the conductive current to a maximum value for at least a portion of a second time interval of the first conductive switching event.

14. The gate driver circuit according to claim 1, wherein: The second conductive switching event is a next conductive switching event subsequent to the first conductive switching event.

15. The gate driver circuit according to claim 1, wherein: The plurality of turn-on switching events are active hard switching events during which the slope of the voltage occurs after the transistor has taken over load current.

16. A gate driver circuit comprising: a gate driver configured to generate an on-current to drive a transistor during a plurality of on-switching events, wherein each of the plurality of on-switching events comprises a first time interval and a second time interval subsequent to the first time interval, wherein, during the plurality of conduction switching events, the voltage across the transistor changes from a first value to a second value with an initial slope during the first time interval and with a second slope during the second time interval, wherein the initial slope is greater than the second slope, wherein the initial slope begins during or after a dead time, wherein the initial slope depends on the magnitude of the on-current at the beginning of or after the dead time, and wherein the second slope depends on the magnitude of the on-current; and a sensing circuit configured to detect expiration of a first time interval of a first conductive switching event of the plurality of conductive switching events, and in response to the detected expiration of the first time interval, increase the conductive current to a maximum value within at least a portion of a second time interval of the first conductive switching event, wherein the sensing circuit is further configured to: determine whether an initial slope during the first conduction switching event is of an active type or a passive type, and if the initial slope is of the active type, adjust the magnitude of the conduction current during a second conduction switching event following the first conduction switching event, and if the initial slope is of the passive type, keep the magnitude of the conduction current unchanged during the second conduction switching event, and Wherein, if the slope occurs at least partially within a dead time of a switching cycle including the first turn-on switching event, the slope is of the passive type, and wherein if the slope occurs completely after the dead time of the switching cycle, the slope is of the active type.

17. The gate driver circuit of claim 16, wherein: Under the condition that the initial slope is of the active type: The sensing circuit is also configured to measure an initial slope during the first turn-on switching event, compare the measured initial slope with a target slope range to generate a comparison result, and adjust the amplitude of the turn-on current during the second turn-on switching event based on the comparison result so that the initial slope of the voltage during the second turn-on switching event is within the target slope range.

18. The gate driver circuit according to claim 17, wherein: Based on the comparison result, the sensing circuit is further configured to: If the measured initial slope is above the target slope range, reducing the magnitude of the on-current within the second on-switching event; If the measured initial slope is within the target slope range, keeping the magnitude of the on-current constant during the second on-switching event; as well as If the measured initial slope is below the target slope range, the magnitude of the on-current is increased within the second on-switching event.

19. A method of driving a transistor, comprising: generating an on-current to drive the transistor during a plurality of on-switching events, wherein a voltage across the transistor changes from a first value to a second value with a slope during the plurality of on-switching events, wherein the slope is an active type or a passive type, and wherein the active type slope depends on a magnitude of the on-current; and determining whether the slope during a first conductive switching event is the active type or the passive type; and if the slope is of the active type, adjusting the magnitude of the on-current during a second on-switching event subsequent to the first on-switching event, and if the slope is of the passive type, maintaining the magnitude of the on-current unchanged during the second on-switching event, Wherein, if the slope occurs at least partially within a dead time of a switching cycle including the first turn-on switching event, the slope is of the passive type, and wherein, if the slope occurs completely after the dead time of the switching cycle, the slope is of the active type.

20. A method of driving a transistor, comprising: generating an on-current to drive the transistor during a plurality of on-switching events, wherein each of the plurality of on-switching events comprises a first time interval and a second time interval subsequent to the first time interval, wherein, during the plurality of conduction switching events, the voltage across the transistor changes from a first value to a second value with an initial slope during the first time interval and with a second slope during the second time interval, wherein the initial slope is greater than the second slope, wherein the initial slope begins during or after a dead time, wherein the initial slope depends on the magnitude of the on-current at the beginning of or after the dead time, and wherein the second slope depends on the magnitude of the on-current; detecting expiration of a first time interval of a first conductive switching event of the plurality of conductive switching events; and increasing the on-current to a maximum value during at least a portion of a second time interval of the first on-switching event in response to the detected expiration of the first time interval, wherein the method further comprises determining whether the slope during a first conduction switching event is of an active type or a passive type; and if the slope is of the active type, adjusting the magnitude of the conduction current during a second conduction switching event following the first conduction switching event, and if the slope is of the passive type, maintaining the magnitude of the conduction current unchanged during the second conduction switching event, and Wherein, if the slope occurs at least partially within a dead time of a switching cycle including the first turn-on switching event, the slope is of the passive type, and wherein, if the slope occurs completely after the dead time of the switching cycle, the slope is of the active type.

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