Display device

Abstract

According to one aspect of the present invention, a display device is provided. The display device includes: a plurality of pixels respectively coupled to scan lines and data lines intersecting the scan lines, wherein at least some of the plurality of pixels include a driving transistor and a switching transistor, the driving transistor including: a substrate; a first insulating layer disposed on the substrate; a first active layer disposed on the first insulating layer; a first gate electrode disposed on the first active layer; and a first source electrode and a first drain electrode electrically connected to the first active layer, the first drain electrode being spaced apart from the first source electrode by a first distance, and the switching transistor including: a second gate electrode disposed between the substrate and the first insulating layer; a second active layer disposed on the same layer as the first active layer; and a second source electrode and a second drain electrode electrically connected to the second active layer, the second drain electrode being spaced apart from the second source electrode by a second distance different from the first distance.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0025157, filed on March 5, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention relate generally to a display device, and more particularly, to a display device including a pixel transistor having a narrow width and / or a scan driver, and a method of manufacturing the display device. Background Art

[0003] As the information society develops, the demand for display devices for displaying images in various forms is increasing. Consequently, various display devices such as liquid crystal displays (LCDs), plasma display panels (PDPs), and light-emitting displays are being utilized. Light-emitting displays include organic light-emitting displays (OLEDs) that use organic light-emitting diodes (OLEDs) as light-emitting elements and micro-LED displays (MLEDs) that use micro-LEDs as light-emitting elements.

[0004] This flat panel display device includes a display panel, a gate driver circuit, a data driver circuit, and a timing controller. The display panel includes data lines, gate lines, and pixels formed at the intersections of the data and gate lines. Using thin-film transistors as switching elements, each pixel receives a data voltage from the data line when a gate signal is supplied to the gate line. Each pixel emits light of a predetermined brightness based on the data voltage.

[0005] Recently, flat panel display devices capable of displaying images at ultra-high definition (UHD) have been released, and flat panel display devices capable of displaying images at 8K UHD are being developed. UHD refers to a resolution of 3840×2160, and 8K UHD refers to a resolution of 7680×4320.

[0006] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] Applicants have discovered that, in the case of high-resolution flat panel display devices as discussed above, as the number of pixels increases, the area used for the scan driver circuit and thin film transistor in each pixel may be too large to fit in the display device.

[0008] Display devices constructed according to the principles of the invention and exemplary embodiments, and methods for manufacturing the same according to the principles of the invention, can reduce the width of at least one transistor in a scan driver circuit and the width of a switching transistor in each pixel without complicating manufacturing, for example, without increasing the number of masks typically used in the manufacturing process of the display device. For example, some embodiments of the display device according to the invention can ensure process economy by maintaining the number of masks, achieve a narrow bezel by reducing the overall width of the scan driver circuit, and achieve a high-resolution display device by reducing the area of ​​the switching transistor in each pixel.

[0009] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0010] According to one aspect of the invention, a display device includes a plurality of pixels respectively coupled to scan lines and data lines intersecting the scan lines, wherein at least some of the plurality of pixels include a driving transistor and a switching transistor, the driving transistor including: a substrate; a first insulating layer disposed on the substrate; a first active layer disposed on the first insulating layer; a first gate electrode disposed on the first active layer; and a first source electrode and a first drain electrode electrically connected to the first active layer, the first drain electrode being separated from the first source electrode by a first distance, and the switching transistor including: a second gate electrode disposed between the substrate and the first insulating layer; a second active layer disposed on the same layer as the first active layer; and a second source electrode and a second drain electrode electrically connected to the second active layer, the second drain electrode being separated from the second source electrode by a second distance different from the first distance.

[0011] The first active layer and the second active layer may include indium gallium zinc oxide or indium tin zinc oxide.

[0012] The first active layer may include a first source region, a first drain region, and a first channel region disposed therebetween, and the second active layer may include a second source region, a second drain region, and a second channel region disposed therebetween.

[0013] A length of the first active layer in the first direction may be greater than a length of the second active layer in the first direction.

[0014] The first active layer and the second active layer may directly contact the first insulating layer.

[0015] The driving transistor may include a top gate structure having a first metal layer disposed between the substrate and the first insulating layer, and the first metal layer and the second gate electrode include the same material.

[0016] The driving transistor may further include a second insulating layer disposed on the first gate electrode. The first source electrode may be connected to the first source region of the first active layer via a first contact hole passing through the second insulating layer, and the first drain electrode may be connected to the first drain region of the first active layer via a second contact hole passing through the second insulating layer.

[0017] The first source electrode may contact the first metal layer through a fifth contact hole passing through the first insulating layer and the second insulating layer.

[0018] The driving transistor may further include a first gate insulating layer disposed between the first gate electrode and the first active layer, and the first gate electrode contacts the first metal layer through a sixth contact hole passing through the first insulating layer and the first gate insulating layer.

[0019] The second insulating layer does not overlap with the second active layer of the switching transistor.

[0020] The switching transistor may include a bottom-gate structure in which the second source electrode may be in contact with the second source region of the second active layer and the second drain electrode may be in contact with the second drain region of the second active layer. A first distance in the first direction between the first source electrode and the first drain electrode may be greater than a second distance in the first direction between the second source electrode and the second drain electrode.

[0021] The second insulating layer may further include a third contact hole and a fourth contact hole at least partially overlapping the second active layer of the switching transistor and passing through the second insulating layer. The second source electrode may be connected to the second source region of the second active layer through the third contact hole, and the second drain electrode may be connected to the second drain region of the second active layer through the fourth contact hole.

[0022] A first distance between the first source electrode and the first drain electrode in the first direction may be greater than a second distance between the second source electrode and the second drain electrode in the first direction.

[0023] The display device may further include a scan driver circuit to output a scan signal to the scan line, wherein the scan driver circuit may include a pull-up transistor to output a gate-on voltage when a pull-up node is charged with a gate-on voltage. The pull-up transistor may include a third gate electrode disposed between the substrate and the first insulating layer, and a third active layer disposed on the same layer as the first active layer.

[0024] The third active layer may include indium gallium zinc oxide or indium tin zinc oxide.

[0025] The driving transistor may further include a second insulating layer disposed on the first gate electrode, and the second insulating layer may not overlap the third active layer of the pull-up transistor.

[0026] According to another aspect of the invention, a method for manufacturing a display device includes the following steps: forming a first metal layer and a second gate electrode on a substrate; forming a first insulating layer on the first metal layer and the second gate electrode; forming a first active layer and a second active layer made of an oxide semiconductor material on the first insulating layer; forming a first gate insulating layer and a first gate electrode on the first active layer; forming a second insulating layer including a first contact hole and a second contact hole on the first gate electrode; and forming a first source electrode and a first drain electrode on the second insulating layer, and forming a second source electrode and a second drain electrode on the second active layer, and the distance between the first source electrode and the first drain electrode is different from the distance between the second source electrode and the second drain electrode.

[0027] The first active layer and the second active layer may be made of indium gallium zinc oxide or indium tin zinc oxide.

[0028] The forming of the second insulating layer may include depositing an inorganic layer on the entire surface of the first insulating layer and etching the inorganic layer to expose the second active layer.

[0029] The second active layer may include a second source region, a second drain region, and a second channel region disposed between the second source region and the second drain region. The step of forming the second insulating layer may include the following steps: depositing an inorganic layer on the entire surface of the first insulating layer; and forming a third contact hole exposing the second source region of the second active layer and a fourth contact hole exposing the second drain region of the second active layer by etching the inorganic layer.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0032] Figure 1 is a perspective view of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0033] Figure 2 yes Figure 1 A plan view of the interior of a display device schematically illustrates some of its internal components.

[0034] Figure 3 yes Figure 2 is an equivalent circuit diagram of a representative pixel of the display device shown in .

[0035] Figure 4 yes Figure 2A circuit diagram of an exemplary embodiment of a scan driver circuit is shown in FIG.

[0036] Figure 5 yes Figure 3 1 is a plan view of an exemplary embodiment of a driving transistor of a pixel shown in FIG.

[0037] Figure 6 It is along Figure 5 A cross-sectional view taken along line II'.

[0038] Figure 7 yes Figure 3 A plan view of an exemplary embodiment of a switching transistor of a pixel shown in FIG.

[0039] Figure 8 It is along Figure 7 A cross-sectional view taken along line II-II'.

[0040] Figure 9 is a graph of the drive current and gate voltage of a bottom-gate transistor.

[0041] Figure 10 is a graph of the drive current and gate voltage of a top-gate transistor.

[0042] Figure 11 yes Figure 3 1 is a plan view of another exemplary embodiment of a switching transistor of a pixel shown in FIG.

[0043] Figure 12 It is along Figure 11 A cross-sectional view taken along line II-II'.

[0044] Figure 13 yes Figure 3 1 is a plan view of another exemplary embodiment of a driving transistor of a pixel shown in FIG.

[0045] Figure 14 It is along Figure 13 A cross-sectional view taken along line II'.

[0046] Figure 15 yes Figure 3 1 is a plan view of yet another exemplary embodiment of a driving transistor of a pixel shown in .

[0047] Figure 16 It is along Figure 15 A cross-sectional view taken along line III-III'.

[0048] Figure 17 is a flowchart illustrating an exemplary embodiment of a method of manufacturing a display device according to principles of the invention.

[0049] Figures 18 to 24 It shows Figure 17 sectional views of steps in a method of manufacturing a display device.

[0050] Figure 25 is a flow chart illustrating another exemplary embodiment of a method of manufacturing a display device according to principles of the invention.

[0051] Figure 26 and Figure 27 It shows Figure 25 sectional views of certain steps in a method for manufacturing a display device. DETAILED DESCRIPTION

[0052] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of devices or methods that employ one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making the various exemplary embodiments unnecessarily obscure. In addition, the various exemplary embodiments may be different, but need not be exclusive. For example, without departing from the inventive concept, the specific shape, configuration, and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0053] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features of varying details of some of the ways in which the inventive concept may be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0054] The use of cross hatching and / or shading is generally provided in the accompanying drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or express any preference or demand for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements can be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described order. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0055] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bound to" another element or layer, the element or layer may be directly on, directly connected to or directly bound to the other element or layer, or there may be intermediate elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bound to" another element or layer, there are no intermediate elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis and the z-axis), but may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0056] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be named a second element without departing from the teachings of the disclosure.

[0057] For descriptive purposes, spatially relative terms such as "under," "beneath," "under," "down," "over," "up," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "under" or "beneath" other elements or features would then be positioned "over" the other elements or features. Thus, the exemplary term "under" can include both above and below orientations. Furthermore, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), with the spatially relative descriptors used herein interpreted accordingly.

[0058] The terms used herein are for the purpose of describing specific embodiments, and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular "one", "one (kind / person)" and "the (described)" are also intended to include plural forms. In addition, when using the terms "comprise" and / or "include" and variations thereof in this manual, the description indicates the presence of stated features, integral bodies, steps, operations, elements, components and / or their groups, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially (substantially)", "approximately (about)" and other similar terms are used as approximate terms and are not used as degree terms, so as to explain the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0059] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the figures due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device and, as such, are not necessarily intended to be limiting.

[0060] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0061] Hereinafter, specific exemplary embodiments will be described with reference to the accompanying drawings.

[0062] Figure 1 is a perspective view of an exemplary embodiment of a display device 10 constructed according to the principles of the invention. Figure 2 yes Figure 1 The interior of the display device 10 schematically illustrates a plan view of some of its internal components. Figure 3 yes Figure 2 1 is an equivalent circuit diagram of a representative pixel of the display device 10 shown in FIG.

[0063] Throughout the specification, the terms "on...", "top", and "upper surface" refer to the upward direction (i.e., the Z-axis direction) from the display panel 100, and the terms "under...", "bottom", and "lower surface" refer to the downward direction (i.e., the direction opposite to the Z-axis direction) from the display panel 100. In addition, "left", "right", "upper", and "lower surface" refer to directions when the display panel 100 is viewed in a plane. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the direction of the X-axis, "upper" refers to the Y-axis direction, and "lower" refers to the direction opposite to the Y-axis direction.

[0064] Reference Figure 1 and Figure 2 , the display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen in portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs)) and various products (such as televisions, notebook computers, monitors, billboards, and the Internet of Things (IoT)). The display device 10 can be any one of an organic light-emitting display, a liquid crystal display, a plasma display, a field emission display, an electrophoretic display, an electrowetting display, a quantum dot light-emitting display, a micro light-emitting diode (LED) display, and any other display known in the art. Hereinafter, an organic light-emitting display will be described as an example of the display device 10, but exemplary embodiments are not limited to organic light-emitting displays.

[0065] The display device 10 according to an exemplary embodiment includes a display panel 100 , a display driver circuit 200 , and a circuit board 300 .

[0066] The display panel 100 can be formed in a rectangular plane having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). Each corner where the short side extending in the first direction (X-axis direction) intersects the long side extending in the second direction (Y-axis direction) can be rounded with a predetermined curvature or can be a right angle. The planar shape of the display panel 100 is not limited to a rectangular shape, but can also be another polygonal shape, a circular shape or an elliptical shape. The display panel 100 can be formed to be flat. However, the display panel 100 is not limited to this example and can also include a curved portion formed at the left and right ends of the display panel 100 and having a constant curvature or a varying curvature. In addition, the display panel 100 can be formed to be flexible so that the display panel 100 can be bent, folded or curled.

[0067] The display panel 100 may include a display area DA in which a plurality of pixels P are formed to display an image, and a non-display area NDA disposed around the display area DA. When the display panel 100 includes a curved portion, the display area DA may also include the curved portion. In this case, an image may also be displayed on the curved portion of the display panel 100.

[0068] In the display area DA, not only pixels P are provided but also scan lines SL, data lines DL, and power lines connected to the pixels P may be provided. The scan lines SL may be formed to extend in a first direction (X-axis direction) and be substantially parallel to each other in a second direction (Y-axis direction) intersecting the first direction, and the data lines DL may be formed to extend in a second direction (Y-axis direction) and be substantially parallel to each other in the first direction (X-axis direction). Each of the pixels P may be connected to at least one of the scan lines SL and one of the data lines DL.

[0069] Reference Figure 2 and Figure 3 Each pixel P may include a driving transistor DT, at least one switching transistor ST, a light-emitting element EL, and a capacitor Cst. Since the switching transistor ST is turned on by a scan signal received from a scan line SL, the data voltage of the data line DL may be applied to the gate electrode of the driving transistor DT. The driving transistor DT may supply a driving current to the light-emitting element EL based on the data voltage applied to the gate electrode, thereby causing the light-emitting element EL to emit light. The driving transistor DT and the at least one switching transistor ST may be thin-film transistors. The light-emitting element EL may emit light based on the driving current of the driving transistor DT. The light-emitting element EL may be an organic light-emitting diode including a first electrode, an organic light-emitting layer, and a second electrode. The capacitor Cst may maintain a constant data voltage applied to the gate electrode of the driving transistor DT.

[0070] Reference Figure 1 and Figure 2 , the non-display area NDA can be defined as an area extending from the outside of the display area DA to the edge of the display panel 100. In the non-display area NDA, a scan driver circuit SDC for sending a scan signal to the scan line SL and a data voltage distribution circuit DMUX connected between the data line DL and the routing line RL can be provided. In addition, a pad (also called a "soldering pad" or "pad") DP electrically connected to the display driver circuit 200 and the circuit board 300 can be provided in the non-display area NDA. In this case, the display driver circuit 200 and the pad DP can be provided on the edge of the display panel 100.

[0071] The scan driver circuit SDC can be connected to the display driver circuit 200 through at least one scan control line SCL. The scan driver circuit SDC can receive a scan control signal from the display driver circuit 200 through at least one scan control line SCL. The scan driver circuit SDC can generate a scan signal according to the scan control signal and sequentially output the scan signal to the scan lines SL. Although the scan driver circuit SDC is Figure 2 The scan driver circuit SDC is formed in the non-display area NDA on one side (e.g., the left side) of the display area DA, but exemplary embodiments are not limited to this case. For example, the scan driver circuit SDC may also be formed in the non-display area NDA on both sides (e.g., the left and right sides) of the display area DA.

[0072] The data voltage distribution circuit DMUX may be connected between the routing line RL and the data lines DL. A ratio of the number of routing lines RL connected to the data voltage distribution circuit DMUX to the number of data lines DL connected to the data voltage distribution circuit DMUX may be 1:q, where q is an integer equal to or greater than 2. The data voltage distribution circuit DMUX may distribute a data voltage applied to one routing line RL to a plurality of data lines DL.

[0073] The display driver circuit 200 is connected to the pad DP and receives digital video data and timing signals. The display driver circuit 200 converts the digital video data into analog positive / negative polarity data voltages and supplies the analog positive / negative polarity data voltages to the data lines DL via the routing lines RL and the data voltage distribution circuit DMUX. In addition, the display driver circuit 200 generates a scan control signal for controlling the scan driver circuit SDC and supplies the scan control signal to the scan driver circuit SDC via the scan control line SCL. The scan signal from the scan driver circuit SDC selects a pixel P to be supplied with a data voltage and supplies the data voltage to the selected pixel P. In addition, the display driver circuit 200 can supply a power supply voltage to the power supply line.

[0074] The display driver circuit 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 in the pad region using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. However, exemplary embodiments are not limited to this, and the display driver circuit 200 may also be mounted on the circuit board 300.

[0075] The pad DP can be electrically connected to the display driver circuit 200. The circuit board 300 can be attached to the pad DP using an anisotropic conductive film. Therefore, the guide lines of the circuit board 300 can be electrically connected to the pad DP. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0076] The pixel P may include Figure 3 The driving transistor DT, at least one switching transistor ST, the light emitting element EL and the capacitor Cst are shown in FIG.

[0077] The switching transistor ST is turned on by a scan signal received from the kth scan line SLk (where k is a positive integer). Therefore, the data voltage of the jth data line DLj (where j is a positive integer) can be applied to the gate electrode of the driving transistor DT. The switching transistor ST may have a gate electrode connected to the kth scan line SLk, a source electrode connected to the gate electrode of the driving transistor DT, and a drain electrode connected to the jth data line DLj.

[0078] The driving transistor DT can supply a driving current to the light emitting element EL according to a data voltage applied to its gate electrode, thereby causing the light emitting element EL to emit light. The driving transistor DT may have a gate electrode connected to the source electrode of the switching transistor ST, a source electrode connected to the first electrode of the light emitting element EL, and a drain electrode connected to a first power supply line VDDL to which a first power supply voltage is applied.

[0079] The driving transistor DT and at least one switching transistor ST may be thin film transistors. Figure 3 In the embodiment, the driving transistor DT and the at least one switching transistor ST are formed as N-type semiconductor transistors having N-type semiconductor characteristics, but the exemplary embodiment is not limited to this case. That is, the driving transistor DT and the at least one switching transistor ST may also be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0080] The light-emitting element EL can emit light according to the driving current of the driving transistor DT. The light-emitting element EL can be an organic light-emitting diode including a first electrode, an organic light-emitting layer, and a second electrode. The first electrode of the light-emitting element EL can be connected to the source electrode of the driving transistor DT, and the second electrode can be connected to a second power supply line VSSL to which a second power supply voltage lower than the first power supply voltage is applied.

[0081] The capacitor Cst may be connected between the gate electrode and the drain electrode of the driving transistor DT. Therefore, the capacitor Cst may maintain a data voltage applied to the gate electrode of the driving transistor DT constant.

[0082] Figure 4 yes Figure 2 A circuit diagram of an exemplary embodiment of a scan driver circuit SDC is shown in FIG.

[0083] The scan driver circuit SDC may include a plurality of stages STA connected in a slave manner, and Figure 4An exemplary embodiment of a single stage STA is shown. The stage STA may sequentially output scan signals to the scan lines SL.

[0084] Reference Figure 4 Each of the stages STA includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU that is turned on when the pull-up node NQ has a gate-on voltage, a pull-down transistor TD that is turned on when the pull-down node NQB has a gate-on voltage, and a node controller NC for controlling charging and discharging of the pull-up node NQ and the pull-down node NQB.

[0085] The node controller NC can be connected to a start terminal ST to which a start signal or an output signal of a previous stage is input, a reset terminal RT to which an output signal of a next stage is input, a gate-on voltage terminal VGHT to which a gate-on voltage is applied, and a gate-off voltage terminal VGLT to which a gate-off voltage is applied. The node controller NC controls the charging and discharging of the pull-up node NQ and the pull-down node NQB according to the start signal input to the start terminal ST or the output signal of the previous stage. In order to stably control the output of the stage STA, when the pull-up node NQ has a gate-on voltage, the node controller NC controls the pull-down node NQB to have a gate-off voltage, and when the pull-down node NQB has a gate-on voltage, the node controller NC controls the pull-up node NQ to have a gate-off voltage. To this end, the node controller NC may include a plurality of transistors.

[0086] When the stage STA is pulled up (i.e., when the pull-up node NQ has a gate-on voltage and outputs the clock signal input to the clock terminal CT to the output terminal OT), the pull-up transistor TU is turned on. When the stage STA is pulled down (e.g., when the pull-down node NQB has a gate-on voltage and outputs the gate-off voltage of the gate-off voltage terminal VGLT to the output terminal OT), the pull-down transistor TD is turned on.

[0087] The pull-up transistor TU, the pull-down transistor TD of the stage STA, and the transistor of the node controller NC may be formed as a thin film transistor. Figure 4 The pull-up transistor TU, the pull-down transistor TD of the stage STA, and the transistor of the node controller NC are formed as N-type semiconductor transistors having N-type semiconductor characteristics, but the exemplary embodiment is not limited to this case. That is, the pull-up transistor TU, the pull-down transistor TD of the stage STA, and the transistor of the node controller NC may also be formed as P-type semiconductor transistors having P-type semiconductor characteristics.

[0088] Figure 5 yes Figure 3 FIG. 1 is a plan view of an exemplary embodiment of a driving transistor DT of a pixel P shown in FIG.

[0089] Figure 6 It is along Figure 5 A cross-sectional view taken along line II'. Figure 7 yes Figure 3 FIG. 1 is a plan view of an exemplary embodiment of a switching transistor ST of a pixel P shown in FIG. Figure 8 It is along Figure 7 A cross-sectional view taken along line II-II'.

[0090] exist Figure 5 and Figure 6 In the exemplary embodiment shown in FIG, the driving transistor DT of the pixel P has a top gate structure in which a gate electrode is formed on top of an active layer. Figure 7 and Figure 8 In the exemplary embodiment shown in , the switching transistor ST has a bottom gate structure in which a gate electrode is formed under an active layer. Specifically, for example, the driving transistor DT may be formed in a coplanar structure, and the switching transistor ST may be formed in a back channel etched structure.

[0091] Reference Figures 5 to 8 , as in Figure 5 and Figure 6 The driving transistor DT shown in FIG includes a first gate electrode 111, a first active layer 131, a first source electrode 141, a first drain electrode 151 and a first metal layer 161. Figure 7 and Figure 8 The switching transistor ST shown in FIG. 1 includes a second gate electrode 112 , a second active layer 132 , a second source electrode 142 , and a second drain electrode 152 .

[0092] The driving transistor DT and the switching transistor ST are formed on a first substrate 101. The first substrate 101 may be made of plastic or glass.

[0093] Figure 6 The first metal layer 161 and Figure 8 The second gate electrode 112 shown in may be formed on the first substrate 101 .

[0094] The first metal layer 161 may be a layer for blocking light from the first substrate 101 from entering the first active layer 131 .

[0095] The first metal layer 161 and / or the second gate electrode 112 can be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials.

[0096] The first metal layer 161 and the second gate electrode 112 may be formed integrally with each other and may be formed of the same material.

[0097] The length of the first metal layer 161 in the third direction DR3 may be greater than the length of the second gate electrode 112 in the third direction DR3. The length of the first metal layer 161 in the third direction DR3 may be smaller than the length of the first active layer 131 in the third direction DR3. In addition, the length of the first metal layer 161 in the third direction DR3 may be greater than the length of the first gate electrode 111 in the third direction DR3.

[0098] The first insulating layer 102 may be provided on the first metal layer 161. The first insulating layer 102 may be a layer for protecting the driving transistor DT and the switching transistor ST of the pixel P from moisture introduced through the first substrate 101. The first insulating layer 102 may be composed of a plurality of inorganic layers stacked alternately. For example, the first insulating layer 102 may be a layer in which silicon oxide (SiO x ) layer, silicon nitride (SiN x A multilayer in which one or more inorganic layers selected from ) layers and SiON layers are alternately stacked.

[0099] Figure 6 The first active layer 131 and Figure 8 The second active layer 132 shown in FIG may be formed on the first insulating layer 102. The first active layer 131 and the second active layer 132 may be in direct contact with the first insulating layer 102. That is, one surface of the first insulating layer 102 may be in direct contact with the first insulating layer 102. Figure 6 The first metal layer 161 and Figure 8 The second gate electrode 112 is in direct contact with the first insulating layer 102, and the other surface of the first insulating layer 102 can be in direct contact with the second gate electrode 112. Figure 6 The first active layer 131 and Figure 8 The second active layer 132 is in direct contact with the substrate.

[0100] The first active layer 131 may include a source region 131a, a drain region 131b, and a channel region 131c. The second active layer 132 may include a source region 132a, a drain region 132b, and a channel region 132c. The channel region 131c may be disposed between the source region 131a and the drain region 131b, and the channel region 132c may be disposed between the source region 132a and the drain region 132b.

[0101] The first active layer 131 and the second active layer 132 may be oxide semiconductors. The first active layer 131 and the second active layer 132 may be made of indium gallium zinc oxide or indium tin zinc oxide.

[0102] A length of the first active layer 131 in the third direction DR3 may be greater than a length of the second active layer 132 in the third direction DR3.

[0103] like Figure 6As shown in , the first active layer 131 may overlap the first gate electrode 111, with the first gate insulating layer 120 interposed between the first active layer 131 and the first gate electrode 111. Figure 8 , the second active layer 132 may overlap the second gate electrode 112, with the first insulating layer 102 interposed therebetween. Specifically, the channel region 131 c of the first active layer 131 may overlap the first gate electrode 111, and the second channel region 132 c of the second active layer 132 may overlap the second gate electrode 112.

[0104] Reference Figure 6 The first gate insulating layer 120 is provided on the first active layer 131. The first gate insulating layer 120 may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers). In addition, refer to Figure 8 , the second source electrode 142 and the second drain electrode 152 may be disposed on the second active layer 132, and the first protection layer 170 may be formed on the second source electrode 142 and the second drain electrode 152, so that the first gate insulating layer 120 may not be disposed on the second active layer 132. That is, the second active layer 132 does not overlap with the first gate insulating layer 120 and does not contact the first gate insulating layer 120.

[0105] Reference Figure 6 , the first gate electrode 111 is provided on the first gate insulating layer 120. The first gate electrode 111 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials.

[0106] Despite Figure 6 In the embodiment, the first gate insulating layer 120 is disposed only between the first gate electrode 111 and the first active layer 131 , but the exemplary embodiment is not limited to this case. That is, the first gate insulating layer 120 may also be formed on the upper surface and the side surface of the first active layer 131 .

[0107] Figure 9 is a graph of the drive current and gate voltage of a bottom-gate transistor. Figure 10 is a graph of the drive current and gate voltage of a top-gate transistor.

[0108] Figure 9 and Figure 10 is a graph showing the results of positive bias stress. Figure 9 and Figure 10 , and Figure 9When the driving transistor DT is formed as a bottom-gate transistor, the driving transistor DT is as shown in FIG. Figure 10 As shown in , when formed into a top-gate structure (ie, when formed into a top-gate transistor), excellent reliability is exhibited against positive bias stress. Therefore, the reliability of the driving transistor DT can be ensured.

[0109] Refer again Figure 6 The second insulating layer 160 is provided on the first gate electrode 111. The second insulating layer 160 may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers).

[0110] The second insulating layer 160 may be in direct contact with the upper and side surfaces of the first gate electrode 111 and the side surfaces of the first gate insulating layer 120 .

[0111] In addition, the second insulating layer 160 may overlap with the first active layer 131 and directly contact the first active layer 131. In addition, the second insulating layer 160 is not provided on the second active layer 132. That is, the second insulating layer 160 does not overlap with the second active layer 132 and does not contact the second active layer 132.

[0112] A first contact hole CT1 passing through the second insulating layer 160 to expose a portion of the upper surface of the first active layer 131 and a second contact hole CT2 passing through the second insulating layer 160 to expose another portion of the upper surface of the first active layer 131 may be formed in the second insulating layer 160. That is, the first contact hole CT1 may expose the first source region 131a of the first active layer 131, and the second contact hole CT2 may expose the first drain region 131b of the first active layer 131.

[0113] like Figure 6 As shown in FIG, the first source electrode 141 and the first drain electrode 151 of the driving transistor DT may be disposed on the second insulating layer 160. Figure 8 As shown in , the second source electrode 142 and the second drain electrode 152 of the switching transistor ST may be disposed on the second active layer 132 .

[0114] Reference Figure 6 The first source electrode 141 contacts the first source region 131a formed on one side of the first active layer 131 through the first contact hole CT1. The first drain electrode 151 contacts the first drain region 131b formed on the other side of the first active layer 131 through the second contact hole CT2.

[0115] Reference Figure 8The second source electrode 142 may contact the second source region 132 a formed on one side of the second active layer 132 . The second drain electrode 152 may contact the second drain region 132 b formed on the other side of the second active layer 132 .

[0116] Each of the first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152 may be a single layer or a multilayer made of any one or more of zinc indium oxide (ZIO), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. For example, each of the first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152 may be a stacked structure of ZIO-Cu-ZIO.

[0117] exist Figure 5 and Figure 6 The first distance d1 between the first source electrode 141 and the first drain electrode 151 in the third direction DR3 shown in FIG may be greater than that in FIG. Figure 7 and Figure 8 The second distance d2 between the second source electrode 142 and the second drain electrode 152 in the third direction DR3 shown in FIG is large.

[0118] That is, Figure 8 As shown in FIG, since in the switching transistor ST, the second source electrode 142 and the second drain electrode 152 can directly contact the second active layer 132 without any layer interposed therebetween, the second distance d2 between the second source electrode 142 and the second drain electrode 152 in the third direction DR3 can be reduced to less than Figure 6 The first distance d1 between the first source electrode 141 and the first drain electrode 151 in the third direction DR3 is small. Therefore, the area of ​​the switching transistor ST in the pixel P can be reduced, thereby increasing the number of pixels in a given area and easily realizing a high-resolution display device.

[0119] The first protective layer 170 is formed on the first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152. The first protective layer 170 may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers).

[0120] The first planarization layer 180 may be formed on the first protective layer 170 to planarize steps caused by thin film transistors such as the driving transistor DT and the switching transistor ST. The first planarization layer 180 may be made of an organic layer such as acryl resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0121] like Figure 6 As shown in FIG, a pixel defining layer 195 and a light emitting element EL including a first electrode 191 , an organic light emitting layer 192 , and a second electrode 193 may be formed on the first planarization layer 180 .

[0122] Reference Figure 6 and Figure 8 , the first electrode 191 may be formed on the first planarization layer 180. The first electrode 191 may be connected to the first source electrode 141 of the driving transistor DT through a contact hole passing through the first protection layer 170 and the first planarization layer 180.

[0123] The pixel defining layer 195 may be formed on the first planarization layer 180 and may cover edges of the first electrode 191 to define the pixels P. That is, the pixel defining layer 195 serves as a pixel defining layer for defining the pixels P. Here, each of the pixels P includes a region in which the first electrode 191, the organic light emitting layer 192, and the second electrode 193 are sequentially stacked such that holes from the first electrode 191 and electrons from the second electrode 193 are combined together in the organic light emitting layer 192 to emit light.

[0124] The organic light-emitting layer 192 may be disposed on the first electrode 191 and the pixel defining layer 195. The organic light-emitting layer 192 may include a hole transport layer, a light-emitting layer, and an electron transport layer. Furthermore, the organic light-emitting layer 192 may be formed as a series structure of two or more stacks, in which case a charge generation layer may be formed between the stacks.

[0125] The second electrode 193 may be formed on the organic light emitting layer 192. The second electrode 193 may be a common layer common to all pixels.

[0126] The light-emitting element EL may be a top emission type that emits light toward the second substrate (i.e., in an upward direction). In this case, the first electrode 191 may be made of a metal material with high reflectivity (such as a stack of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stack of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, or a stack of an APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu). In addition, the second electrode 193 may be made of a transparent conductive material (TCO) capable of transmitting light, such as ITO or indium zinc oxide (IZO), or a semi-transmissive conductive material such as an alloy of magnesium (Mg), silver (Ag), or magnesium (Mg) and silver (Ag). When the second electrode 193 is made of a semi-transmissive conductive material, the light emission efficiency can be increased by the microcavity.

[0127] Encapsulation layer 196 may be formed on second electrode 193 to prevent the introduction of oxygen or moisture. Encapsulation layer 196 may include at least one inorganic layer. The inorganic layer may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. In addition, encapsulation layer 196 may include at least one organic layer to prevent particles from penetrating encapsulation layer 196 and entering organic light-emitting layer 192 and second electrode 193. The organic layer may be made of epoxy resin, acrylate, or polyurethane acrylate.

[0128] according to Figures 5 to 8 In the exemplary embodiment, the driving transistor DT has a top gate structure and the switching transistor ST has a bottom gate structure. Therefore, it is possible to ensure the reliability of the display device 10 while reducing the area of ​​the switching transistor ST, thereby realizing a high-resolution display device.

[0129] Furthermore, the first active layer 131 of the driving transistor DT and the second active layer 132 of the switching transistor ST are disposed on the same layer, and the first active layer 131 and the second active layer 132 can be formed simultaneously through the same mask process step. Therefore, the number of masks can be reduced during the manufacturing process of the display device, thereby ensuring process economy.

[0130] The pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC may each include a third gate electrode, a third active layer, a third source electrode, and a third drain electrode. Each of the pull-up transistor TU, the pull-down transistor TD, and the transistor of the node controller NC of the scan driver circuit SDC may have the same Figure 7 and Figure 8The bottom gate structure of the switching transistor ST shown in FIG is substantially the same as the bottom gate structure. In this case, the third gate electrode, the third active layer, the third source electrode and the third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD and the transistor of the node controller NC of the scan driver circuit SDC are the same as those in the above reference. Figure 7 and Figure 8 The second gate electrode 112 , the second active layer 132 , the second source electrode 142 , and the second drain electrode 152 of the switching transistor ST are described as being substantially the same, and thus detailed descriptions thereof are omitted to avoid redundancy.

[0131] Since the transistors of the scan driver circuit SDC are formed to have the same bottom gate structure as that of the switching transistor ST, as explained above, the distance between the second source electrode 142 and the second drain electrode 152 of each of the transistors can be reduced. Therefore, even when a high-resolution display device is implemented, an increase in the width of the scan driver circuit SDC can be prevented.

[0132] Hereinafter, other exemplary embodiments will be described. In the following exemplary embodiments, the same elements as those described above will be denoted by the same reference numerals, and redundant descriptions thereof will be omitted or briefly given to avoid redundancy.

[0133] Figure 11 yes Figure 3 FIG. 1 is a plan view of another exemplary embodiment of a switching transistor ST of a pixel P shown in FIG. Figure 12 It is along Figure 11 A cross-sectional view taken along line II-II'.

[0134] Figure 11 and Figure 12 An exemplary embodiment of Figure 7 and Figure 8 The exemplary embodiment of FIG. 1 is different in that the switch transistor ST_1 is formed with an etch stopper structure.

[0135] Reference Figure 11 and Figure 12 In the switching transistor ST_1, the second insulating layer 160′ is disposed on the second active layer 132. That is, the second insulating layer 160′ may overlap with and directly contact the second active layer 132. The second insulating layer 160′ overlapping the second channel region 132c of the second active layer 132 may be an etch stopper layer.

[0136] A third contact hole CT3 passing through the second insulating layer 160' to expose a portion of the upper surface of the second active layer 132 and a fourth contact hole CT4 passing through the second insulating layer 160' to expose another portion of the upper surface of the second active layer 132 may be formed in the second insulating layer 160'. That is, the third contact hole CT3 may expose the second source region 132a of the second active layer 132, and the fourth contact hole CT4 may expose the second drain region 132b of the second active layer 132.

[0137] The second source electrode 142' and the second drain electrode 152' of the switching transistor ST_1 may be disposed on the second insulating layer 160'. The second source electrode 142' contacts the second source region 132a formed on one side of the second active layer 132 through a third contact hole CT3. The second drain electrode 152' contacts the second drain region 132b formed on the other side of the second active layer 132 through a fourth contact hole CT4.

[0138] Therefore, if Figure 6 The first distance d1 between the first source electrode 141 and the first drain electrode 151 of the driving transistor DT in the third direction DR3 may be greater than Figure 11 and Figure 12 The third distance d3 between the second source electrode 142′ and the second drain electrode 152′ of the switching transistor ST_1 shown in the third direction DR3 is large. That is, because the switching transistor ST_1 according to the illustrated exemplary embodiment has a bottom-gate structure, the third distance d3 between the second source electrode 142′ and the second drain electrode 152′ in the third direction DR3 can be reduced. Therefore, the area of ​​the switching transistor ST_1 in the pixel P can be reduced, thereby increasing the number of pixels in a given area and easily realizing a high-resolution display device.

[0139] In addition, since the first active layer 131 of the driving transistor DT and the second active layer 132 of the switching transistor ST_1 are disposed on the same layer, the number of masks may be maintained as described above.

[0140] In addition, each of the pull-up transistor TU, the pull-down transistor TD of the scan driver circuit SDC, and the transistor of the node controller NC may have a Figure 11 and Figure 12 The etching stopper structure of the switching transistor ST_1 shown in FIG is substantially the same as the etching stopper structure. In this case, the third gate electrode, the third active layer, the third source electrode, and the third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD, and the transistor of the node controller NC of the scan driver circuit SDC are the same as those in the above reference. Figure 11 and Figure 12The second gate electrode 112 , the second active layer 132 , the second source electrode 142 ′, and the second drain electrode 152 ′ of the described switching transistor ST_1 are substantially the same, and thus detailed descriptions thereof are omitted to avoid redundancy.

[0141] Figure 13 yes Figure 3 FIG. 1 is a plan view of another exemplary embodiment of a driving transistor DT of a pixel P shown in FIG. Figure 14 It is along Figure 13 A cross-sectional view taken along line II'.

[0142] Figure 13 and Figure 14 An exemplary embodiment of Figure 5 and Figure 6 The exemplary embodiment of FIG. 1 is different in that the first source electrode 141 ′ of the driving transistor DT_1 is connected to the first metal layer 161 .

[0143] Reference Figure 13 and Figure 14 A fifth contact hole CT5 passing through the first insulating layer 102 and the second insulating layer 160 to expose the first metal layer 161 may be formed in the first insulating layer 102 and the second insulating layer 160 .

[0144] The first source electrode 141' can contact the first metal layer 161 through the fifth contact hole CT5. In this case, the first metal layer 161 and the first source electrode 141', which are disposed below the first active layer 131, have the same voltage. When the first metal layer 161 and the first source electrode 141' have the same potential, the first active layer 131 adjacent to the first metal layer 161 may not be activated compared to the first active layer 131 adjacent to the first gate electrode 111. In other words, the electron mobility in the channel region 131c of the first active layer 131 can be reduced. Therefore, even if the driving current per pixel decreases as the number of pixels increases in a high-resolution display device, a decrease in the driving voltage range of the driving transistor DT_1 can be prevented or reduced.

[0145] Figure 15 yes Figure 3 FIG. 1 is a plan view of yet another exemplary embodiment of a driving transistor DT of a pixel P shown in FIG. Figure 16 It is along Figure 15 A cross-sectional view taken along line III-III'.

[0146] Figure 15 and Figure 16 An exemplary embodiment of Figure 5 and Figure 6 The exemplary embodiment of FIG. 1 is different in that the first gate electrode 111 ′ of the driving transistor DT_2 is connected to the first metal layer 161 .

[0147] Reference Figure 15 and Figure 16 A sixth contact hole CT6 passing through the first insulating layer 102 and the first gate insulating layer 120 to expose the first metal layer 161 may be formed in the first insulating layer 102 and the first gate insulating layer 120 .

[0148] The first gate electrode 111 ′ may make contact with the first metal layer 161 through the sixth contact hole CT6 .

[0149] In this case, the first metal layer 161 and the first gate electrode 111' disposed under the first active layer 131 have the same voltage. That is, the first gate electrode 111' can serve as a top gate electrode, and the first metal layer 161 can serve as a bottom gate electrode. Therefore, since the driving transistor DT_2 can be driven in a dual-gate manner, it is possible to prevent or reduce leakage current from flowing through the channel region 131c of the first active layer 131 when the driving transistor DT_2 is turned off.

[0150] Next, a method of manufacturing a display device according to an exemplary embodiment will be described. Figures 1 to 8 The method of the display device 10 will be described as an example. Figures 1 to 8 Elements that are substantially the same as those of the present invention will be designated by the same reference numerals, and detailed descriptions thereof will be omitted to avoid redundancy.

[0151] Figure 17 is a flowchart illustrating an exemplary embodiment of a method of manufacturing a display device according to principles of the invention. Figures 18 to 24 It shows Figure 17 sectional views of steps of a method for manufacturing a display device. Figures 18 to 24 Each of the Figure 6 The cross section I-I' shown in Figure 8 The cross section II-II' is shown in FIG.

[0152] Reference Figure 17 According to an exemplary embodiment, a method for manufacturing a display device may include the following steps: forming a first metal layer and a second gate electrode on a first substrate (step S101); forming a first insulating layer on the first metal layer and the second gate electrode (step S102); forming a first active layer and a second active layer on the first insulating layer (step S103); forming a first gate insulating layer and a first gate electrode on the first active layer (step S104); forming a second insulating layer including a first contact hole and a second contact hole on the first gate electrode (step S105); forming a source electrode and a drain electrode on the second insulating layer and the second active layer (step S106); and forming a first protective layer, a first planarization layer, etc. on the source electrode and the drain electrode (step S107).

[0153] Reference Figure 17 and Figure 18 In the method of manufacturing a display device according to an exemplary embodiment, a first metal layer 161 and a second gate electrode 112 are formed on a first substrate 101 (step S101 ).

[0154] The first metal layer 161 may be a layer for blocking light from the first substrate 101 from entering the first active layer 131 .

[0155] The first metal layer 161 and the second gate electrode 112 may be formed integrally with each other and may be formed of the same material. For example, each of the first metal layer 161 and the second gate electrode 112 may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials.

[0156] The first metal layer 161 and the second gate electrode 112 may be formed by patterning a metal layer, which is formed on the entire surface of the first substrate 101 by sputtering, in an etching process using a photoresist pattern.

[0157] Next, refer to Figure 17 and Figure 19 , a first insulating layer 102 is formed on the first metal layer 161 and the second gate electrode 112 (step S102). The first insulating layer 102 is a layer for protecting the driving transistor DT and the switching transistor ST of each pixel P from the influence of moisture introduced through the first substrate 101. The first insulating layer 102 can be composed of a plurality of inorganic layers stacked alternately. For example, the first insulating layer 102 can be a layer composed of silicon oxide (SiO x ) layer, silicon nitride (SiN x The first insulating layer 102 may be formed by chemical vapor deposition.

[0158] Next, refer to Figure 17 and Figure 20 , a first active layer 131 and a second active layer 132 are formed on the first insulating layer 102 (step S103 ).

[0159] Specifically, the first active layer 131 and the second active layer 132 may be formed by forming an active layer on the entire surface of the first insulating layer 102 and then patterning the active layer.

[0160] The active layer may be an oxide semiconductor. For example, the active layer may be an oxide semiconductor containing tin (Sn). In this case, the active layer may be indium gallium zinc oxide or indium tin zinc oxide. The active layer may be formed by sputtering.

[0161] The first active layer 131 and the second active layer 132 may be formed by patterning the active layer in an etching process using a photoresist pattern. The active layer may be patterned by wet etching or dry etching. The photoresist may then be removed by a stripping process.

[0162] Since the first active layer 131 and the second active layer 132 are simultaneously formed by patterning the active layer, the number of masks can be maintained, thereby ensuring process economy.

[0163] Next, refer to Figure 17 and Figure 21 , a first gate insulating layer 120 and a first gate electrode 111 are formed on the first active layer 131 (step S104 ).

[0164] The first gate insulating layer 120 may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers). The first gate insulating layer 120 may be formed by chemical vapor deposition.

[0165] The first gate electrode 111 may be a single layer or multiple layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The first gate electrode 111 may be formed by patterning a gate metal layer in an etching process using a photoresist pattern, the gate metal layer being formed on the entire surface of the first gate insulating layer 120 by sputtering.

[0166] The first gate insulating layer 120 may be etched and patterned by using the first gate electrode 111 as a mask.

[0167] Next, refer to Figure 17 and Figure 22 A second insulating layer 160 including a first contact hole CT1 and a second contact hole CT2 is formed on the first gate electrode 111 (step S105 ).

[0168] The second insulating layer 160 may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers). The second insulating layer 160 may be formed by chemical vapor deposition.

[0169] A first contact hole CT1 passing through the second insulating layer 160 to expose a portion of the upper surface of the first active layer 131 and a second contact hole CT2 passing through the second insulating layer 160 to expose another portion of the upper surface of the first active layer 131 may be formed in the second insulating layer 160 .

[0170] The second insulating layer 160 may not be formed on the first substrate 101 of the switching transistor ST. That is, the first substrate 101 of the switching transistor ST does not overlap with the second insulating layer 160. Therefore, the second active layer 132 of the switching transistor ST does not overlap with the second insulating layer 160, and the upper surface and side surfaces of the second active layer 132 may be exposed to the outside.

[0171] Next, refer to Figure 17 and Figure 23 A first source electrode 141 , a second source electrode 142 , a first drain electrode 151 , and a second drain electrode 152 are formed on the second insulating layer 160 and the second active layer 132 (step S106 ).

[0172] Each of the first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The first source electrode 141, the second source electrode 142, the first drain electrode 151, and the second drain electrode 152 may be formed by patterning a source-drain metal layer in an etching process using a photoresist pattern, and the source-drain metal layer is formed on the entire surface of the second insulating layer 160 and the second active layer 132 by sputtering.

[0173] The first source electrode 141 may be formed to contact the first source region 131a formed on one side of the first active layer 131 through the first contact hole CT1. The first drain electrode 151 may be formed to contact the first drain region 131b formed on the other side of the first active layer 131 through the second contact hole CT2.

[0174] The second source electrode 142 may be formed to contact the second source region 132a formed on one side of the second active layer 132. The second drain electrode 152 may be formed to contact the second drain region 132b formed on the other side of the second active layer 132. The etchant used to pattern the source-drain metal layer to form the second source electrode 142 and the second drain electrode 152 of the switching transistor ST may be an etchant having selectivity for selectively etching the source-drain metal layer while minimizing the etching rate of the second active layer 132, which is an oxide semiconductor.

[0175] Next, refer to Figure 17and Figure 24 A first protective layer 170 , a first planarization layer 180 , and the like are formed on the first source electrode 141 , the second source electrode 142 , the first drain electrode 151 , and the second drain electrode 152 , thereby completing the display device (step S107 ).

[0176] The first protective layer 170 may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers). The first protective layer 170 may be formed by chemical vapor deposition.

[0177] A first planarization layer 180 may be formed on the first protective layer 170 to planarize steps caused by thin film transistors such as the driving transistor DT and the switching transistor ST. The first planarization layer 180 may be made of an organic layer such as acryl resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0178] As described above, the driving transistor DT has a top gate structure and the switching transistor ST has a bottom gate structure. Therefore, the reliability of the display device 10 can be ensured while reducing the area of ​​the switching transistor ST, thereby realizing a high-resolution display device.

[0179] Furthermore, since the first active layer 131 of the driving transistor DT and the second active layer 132 of the switching transistor ST are disposed on the same layer, the number of masks can be maintained, thereby ensuring process economy.

[0180] The third gate electrode, third active layer, third source electrode and third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD and the multiple transistors of the node controller NC of the scan driver circuit SDC can be formed to be substantially the same as the second gate electrode 112, the second active layer 132, the second source electrode 142 and the second drain electrode 152 of the switching transistor ST described above, and therefore a detailed description thereof is omitted to avoid redundancy.

[0181] For ease of description, the first switching transistor and the second switching transistor of the scan driver circuit SDC are respectively referred to as a pull-up transistor TU and a pull-down transistor TD of the scan driver circuit SDC.

[0182] Since the transistors of the scan driver circuit SDC are formed to have the same bottom gate structure as that of the switching transistor ST, even if a high-resolution display device is implemented, an increase in the width of the scan driver circuit SDC can be prevented.

[0183] A method of manufacturing a display device according to an exemplary embodiment will now be described. In the following exemplary embodiments, the same elements as those described above will be denoted by the same reference numerals, and redundant descriptions thereof will be omitted or briefly discussed to avoid redundancy.

[0184] Figure 25 is a flow chart illustrating another exemplary embodiment of a method of manufacturing a display device according to principles of the invention. Figure 26 and Figure 27 It shows Figure 25 sectional views of certain steps in a method for manufacturing a display device. Figure 26 and Figure 27 Each of the Figure 6 The cross section I-I' shown in Figure 12 The cross section II-II' is shown in FIG.

[0185] Figure 25 、 Figure 26 and Figure 27 Steps S205 and S206 of the exemplary embodiment are the same as Figure 17 、 Figure 22 and Figure 23 Steps S105 and S106 of the exemplary embodiment of FIG. 5 are different.

[0186] Figure 25 Steps S201 to S204 and S207 are the same as Figure 17 Steps S101 to S104 and S107 are substantially the same, and thus detailed descriptions thereof are omitted to avoid redundancy.

[0187] Reference Figure 25 and Figure 26 A second insulating layer 160 ′ including first to fourth contact holes CT1 to CT4 is formed on the first gate electrode 111 and the second active layer 132 (step S205 ).

[0188] The second insulating layer 160' may be an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer composed of these layers). The second insulating layer 160' may be formed by chemical vapor deposition.

[0189] A first contact hole CT1 passing through the second insulating layer 160 ′ to expose a portion of the upper surface of the first active layer 131 and a second contact hole CT2 passing through the second insulating layer 160 ′ to expose another portion of the upper surface of the first active layer 131 may be formed in the second insulating layer 160 ′.

[0190] In addition, a third contact hole CT3 and a fourth contact hole CT4 may be formed through the second insulating layer 160 ′ to expose a portion of the upper surface of the second active layer 132 and another portion of the upper surface of the second active layer 132 .

[0191] Next, refer to Figure 25 and Figure 27 A first source electrode 141 , a second source electrode 142 ′, a first drain electrode 151 , and a second drain electrode 152 ′ are formed on the second insulating layer 160 ′ (step S206 ).

[0192] Each of the first source electrode 141, the second source electrode 142', the first drain electrode 151, and the second drain electrode 152' can be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys of these materials. The first source electrode 141, the second source electrode 142', the first drain electrode 151, and the second drain electrode 152' can be formed by patterning a source-drain metal layer in an etching process using a photoresist pattern, and the source-drain metal layer is formed on the entire surface of the second insulating layer 160' by sputtering.

[0193] The first source electrode 141 may be formed to contact the first source region 131a formed on one side of the first active layer 131 through the first contact hole CT1. The first drain electrode 151 may be formed to contact the first drain region 131b formed on the other side of the first active layer 131 through the second contact hole CT2.

[0194] Furthermore, the second source electrode 142' may be formed to contact the second source region 132a formed on one side of the second active layer 132 through the third contact hole CT3. The second drain electrode 152' may be formed to contact the second drain region 132b formed on the other side of the second active layer 132 through the fourth contact hole CT4.

[0195] As described above, since the switching transistor ST_1 has an etch stopper structure, the second insulating layer 160' is formed on the second active layer 132 of the switching transistor ST_1. Therefore, the second active layer 132 can be prevented from being damaged when the second source electrode 142' and the second drain electrode 152' are formed by patterning the source / drain metal layer.

[0196] Since the switching transistor ST_1 has a bottom gate structure, the area of ​​the switching transistor ST_1 can be reduced. Therefore, as described above, a high-resolution display device having a greater number of pixels per given area can be realized.

[0197] The third gate electrode, third active layer, third source electrode and third drain electrode of each of the pull-up transistor TU, the pull-down transistor TD and the multiple transistors of the node controller NC of the scan driver circuit SDC can be formed to be substantially the same as the second gate electrode 112, the second active layer 132, the second source electrode 142' and the second drain electrode 152' of the switching transistor ST_1 according to the exemplary embodiment shown, and therefore a detailed description thereof is omitted to avoid redundancy.

[0198] According to exemplary embodiments, it is possible to ensure process economy by maintaining the number of masks, realize a narrow bezel by reducing the width of a scan driver circuit, and realize a high-resolution display device by reducing the area of ​​a switching transistor.

[0199] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the claims and various obvious modifications and equivalent arrangements that will be apparent to those skilled in the art.

Claims

1. A display device, comprising: A plurality of pixels are respectively coupled to a scan line and a data line intersecting the scan line, wherein at least some of the plurality of pixels include a driving transistor and a switching transistor, The driving transistor includes: a substrate; a first insulating layer disposed on the substrate; a first active layer disposed on the first insulating layer; a first gate electrode disposed on the first active layer; and a first source electrode and a first drain electrode electrically connected to the first active layer, the first drain electrode being spaced apart from the first source electrode by a first distance, and The switching transistor includes: a second gate electrode disposed between the substrate and the first insulating layer; a second active layer disposed on the same layer as the first active layer; and a second source electrode and a second drain electrode electrically connected to the second active layer, the second drain electrode being spaced apart from the second source electrode by a second distance different from the first distance. Wherein, the second gate electrode is arranged between the substrate and the second active layer.

2. The display device according to claim 1, wherein The first active layer and the second active layer include indium gallium zinc oxide or indium tin zinc oxide.

3. The display device according to claim 1, wherein A length of the first active layer in a first direction is greater than a length of the second active layer in the first direction.

4. The display device according to claim 1, wherein The first active layer and the second active layer are in direct contact with the first insulating layer, The display device further includes a first metal layer disposed between the substrate and the first insulating layer. wherein the first active layer is stacked with the first metal layer, and Wherein, the first metal layer and the second gate electrode directly contact the first insulating layer.

5. The display device according to claim 4, wherein The first metal layer and the second gate electrode include the same material. The display device according to claim 5 , wherein: The driving transistor further includes a second insulating layer disposed on the first gate electrode, and The first source electrode is connected to the first source region of the first active layer through a first contact hole passing through the second insulating layer, and the first drain electrode is connected to the first drain region of the first active layer through a second contact hole passing through the second insulating layer.

7. The display device according to claim 6, wherein: The first source electrode contacts the first metal layer through a fifth contact hole passing through the first insulating layer and the second insulating layer.

8. The display device according to claim 7, wherein: The driving transistor further includes a first gate insulating layer disposed between the first gate electrode and the first active layer, and the first gate electrode contacts the first metal layer through a sixth contact hole passing through the first insulating layer and the first gate insulating layer.

9. The display device according to claim 6, wherein: The second insulating layer does not overlap the second active layer of the switching transistor.

10. The display device according to claim 9, wherein The switching transistor includes a bottom gate structure in which the second source electrode contacts the second source region of the second active layer and the second drain electrode contacts the second drain region of the second active layer, and The first distance between the first source electrode and the first drain electrode in the first direction is greater than the second distance between the second source electrode and the second drain electrode in the first direction.

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