Integrated circuit chip and manufacturing method thereof, integrated circuit package and display device

Abstract

An integrated circuit (IC) chip includes a via contact plug extending in a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along the bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method for manufacturing an IC chip includes: forming an under-bump metal (UBM) layer inside and outside the through hole; and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer in the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0027635 filed on March 11, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present invention relates to an integrated circuit (IC) chip, a method for manufacturing an IC chip, and an IC package and a display device including the IC chip, and more specifically, to an IC chip including a contact structure configured to pass through a substrate, a method for manufacturing the IC chip, and an IC package and a display device including the IC chip. Background Art

[0004] In recent years, as portable electronic devices such as smartphones are required to be miniaturized and multifunctional, it is important to develop new structures and technologies to maintain a small form factor and high reliability without increasing the size of the electronic devices. Summary of the invention

[0005] The inventive concept provides an integrated circuit (IC) chip having a structure in which various ICs having different functions are three-dimensionally stacked to provide improved reliability, and an IC package and a display device including the IC chip.

[0006] The inventive concept also provides a method of manufacturing an IC chip by three-dimensionally stacking various ICs having different functions using a simplified process to provide improved reliability.

[0007] According to one aspect of the present invention, there is provided an IC chip, comprising: an IC portion, the IC portion comprising a substrate and a device layer formed on the substrate; a via contact plug extending in a vertical direction inside a through hole passing through the substrate and the device layer; a via contact liner surrounding the via contact plug inside the through hole; a connection pad liner integrally connected to the via contact liner, the connection pad liner extending in a lateral direction along the bottom surface of the substrate; a dummy bump structure located outside the through hole and integrally connected to the via contact plug; and a bump structure connected to the connection pad liner at a position separated from the via contact plug and the dummy bump structure.

[0008] According to another aspect of the inventive concept, an IC chip is provided, comprising: a first IC portion, comprising a first substrate and a first device layer formed on the first substrate; a second IC portion, comprising a second substrate and a second device layer formed on the second substrate, the second IC portion overlapping the first IC portion in a vertical direction; a via contact portion, comprising: a via contact plug extending in a vertical direction along a through hole passing through the second substrate and the second device layer; a connection pad liner connected to the via contact portion, the connection pad liner extending in a lateral direction along a bottom surface of the second substrate; a dummy bump structure protruding from one end of the via contact portion to the outside of the through hole; and a bump structure formed on the connection pad liner and located at a position spaced apart from the dummy bump structure in a lateral direction. The via contact plug, the dummy bump structure, and the bump structure comprise the same material as each other.

[0009] According to another aspect of the present invention, an IC chip is provided, comprising: a first IC part, comprising a first substrate and a first device layer formed on the first substrate; a second IC part, comprising a second substrate spaced apart from the first substrate, and a second device layer between the second substrate and the first device layer, wherein the first device layer is between the second substrate and the first substrate; a via contact plug extending in a vertical direction along a through hole passing through the second IC part; a via contact liner surrounding an outer side wall of the via contact plug inside the through hole; a connection pad liner integrally connected to the via contact liner, the connection pad liner extending in a lateral direction along a bottom surface of the second substrate; a dummy bump structure connected to the via contact plug; and a bump structure connected to the connection pad liner. The via contact plug, the dummy bump structure, and the bump structure include the same metal as each other.

[0010] According to another aspect of the inventive concept, there is provided an IC package, comprising: a support substrate; a plurality of conductive lines formed on the support substrate; and an IC chip mounted on the support substrate and configured to be electrically connected to the plurality of conductive lines. The IC chip is one of the IC chips according to aspects of the inventive concept.

[0011] According to another aspect of the inventive concept, there is provided a display device including: a display driver IC (DDI) chip including one of the IC chips according to aspects of the inventive concept; and a display panel configured to display image data through control of the DDI chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0013] Figure 1A is a plan view of a partial region of an integrated circuit (IC) chip according to an example embodiment, and Figure 1B is along Figure 1A An enlarged cross-sectional view taken along line X1-X1';

[0014] Figure 2 is a cross-sectional view of a partial region of an IC chip according to an example embodiment;

[0015] Figure 3 is a cross-sectional view of a partial region of an IC chip according to an example embodiment;

[0016] Figure 4 is a cross-sectional view of a partial region of an IC chip according to an example embodiment;

[0017] Figure 5 is a cross-sectional view of a partial region of an IC chip according to an example embodiment;

[0018] Figure 6 is a plan view of a partial region of an IC chip according to an example embodiment;

[0019] Figure 7 is a plan view of a partial region of an IC chip according to an example embodiment;

[0020] Figure 8 is a plan view of a partial region of an IC chip according to an example embodiment;

[0021] Fig. 9 is a plan view of a partial region of an IC chip according to an example embodiment;

[0022] Fig.10 is a plan view of a partial region of an IC chip according to an example embodiment;

[0023] Fig.11 is a schematic plan view of a stacked structure including a plurality of IC chips according to an example embodiment;

[0024] Fig.12 According to an example embodiment Fig.11 A plan view of the configuration of any one of the plurality of IC chips shown in FIG.

[0025] Fig.13A is a schematic plan view of an IC package according to an example embodiment, and Fig. 13B is along Fig.13A An enlarged cross-sectional view taken along line BB';

[0026] Fig.14 is a block diagram of a display device according to an example embodiment; and

[0027] FIG. 15A to FIG. 15J are cross-sectional views showing a process sequence of a method of manufacturing an IC chip according to example embodiments. DETAILED DESCRIPTION

[0028] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same reference elements, and repeated descriptions thereof will be omitted.

[0029] Figure 1A is a plan view of a partial region of an integrated circuit (IC) chip 100 according to an example embodiment, and Figure 1B is along Figure 1A An enlarged cross-sectional view taken along line X1-X1'.

[0030] As used herein, each of the various IC chips may include a package that may include one or more chips stacked on a package substrate.

[0031] Reference Figure 1A and Figure 1B , the IC chip 100 may include a first IC part ICP1 and a second IC part ICP2, which are bonded to each other to overlap each other in the vertical direction (Z direction). The first IC part ICP1 may include: a first substrate 110, and a first device layer DA1 formed on an active surface 110F of the first substrate 110. The second IC part ICP2 may include: a second substrate 120, and a second device layer DA2 formed on an active surface 120A of the second substrate 120. The first substrate 110 and the second substrate 120 may be positioned relative to each other, wherein the first device layer DA1 and the second device layer DA2 are between the first substrate 110 and the second substrate 120.

[0032] The first device layer DA1 and the second device layer DA2 may each include a plurality of different types of individual devices (e.g., individual devices 132 and 142). For example, the plurality of individual devices 132 and 142 included in the first device layer DA1 and the second device layer DA2 may include: a metal oxide semiconductor field effect transistor (MOSFET) including a plurality of transistors, a system large-scale integrated circuit (LSI), a micro-electromechanical system (MEMS), an active device, or a passive device.

[0033] A plurality of individual devices 132 included in the first device layer DA1 may be formed on the active surface 110F of the first substrate 110. At least some of the plurality of individual devices 132 may be configured to be electrically connected to a plurality of first active regions AC1 defined in the first substrate 110 through a plurality of first device isolation films 112. In the first IC portion ICP1, the closer each of the plurality of first device isolation films 112 is to the second IC portion ICP2, the greater the width of each of the plurality of first device isolation films 112 in a lateral direction (e.g., X direction) may become.

[0034] A plurality of individual devices 142 included in the second device layer DA2 may be formed on the active surface 120A of the second substrate 120. At least some of the plurality of individual devices 142 may be configured to be electrically connected to a plurality of second active regions AC2 defined in the second substrate 120 through a plurality of second device isolation films 122. In the second IC portion ICP2, the closer each of the plurality of second device isolation films 122 is to the first IC portion ICP1, the greater the width of each of the plurality of second device isolation films 122 in a lateral direction (e.g., X direction) may become.

[0035] In the first device layer DA1 and the second device layer DA2, a plurality of multilayer interconnect structures (e.g., 134 and 144) may be formed on a plurality of individual devices 132 and 142. The plurality of multilayer interconnect structures 134 and 144 may include a plurality of interconnect layers (e.g., 134A and 144A) and a plurality of contact plugs (e.g., 134B and 144B). The plurality of interconnect layers 134A and 144A and the plurality of contact plugs 134B and 144B may include a metal layer and a conductive barrier film configured to surround the surface of the metal layer. The metal layer may include: copper (Cu), tungsten (W), tantalum (Ta), titanium (Ti), cobalt (Co), manganese (Mn), aluminum (Al), or a combination thereof, and the conductive barrier film may include: tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), tungsten nitride (WN), or a combination thereof. In the plurality of multilayer interconnection structures 134 and 144, the number of interconnection layers 134A and 144A sequentially stacked in the vertical direction (Z direction) is not particularly limited, and various selections may be made. The plurality of single devices 132 and 142 and the plurality of multilayer interconnection structures 134 and 144 may be insulated from each other by interlayer insulating films 136 and 146. The interlayer insulating films 136 and 146 may include silicon oxide films, silicon nitride films, silicon oxynitride films, or combinations thereof.

[0036] In the first device layer DA1, the closer each of the plurality of interconnection layers 134A is to the second IC part ICP2, the larger the width of each of the plurality of interconnection layers 134A in the lateral direction (e.g., X direction) may become. In the second device layer DA2, the closer each of the plurality of interconnection layers 144A is to the first IC part ICP1, the larger the width of each of the plurality of interconnection layers 144A in the lateral direction (e.g., X direction) may become.

[0037] There may be a bonding structure BS between the first IC part ICP1 and the second IC part ICP2. The bonding structure BS may include: a silicon oxide film, a silicon nitride film, a silicon carbonitride film, a silicon carbide film, a polymer film or a combination thereof. The polymer film may include: polyimide, polyamide, polyacrylate, polyaromatic amide or a combination thereof. In some embodiments, the bonding structure BS may have a multilayer structure including a plurality of silicon carbonitride (SiCN) films (e.g., 152A, 152B, 156A, and 156B) and a plurality of tetraethyl orthosilicate (TEOS) films (e.g., 154A and 154B). In the bonding structure BS, the two SiCN films 156A and 156B in contact with each other may have a structure in which SiCN-SiCN are directly bonded to each other. The structure in which the SiCN films 156A and 156B are directly bonded to each other may be a combined structure obtained by performing a bonding process at the wafer-to-wafer level. The configuration of the bonding structure BS is not limited to Figure 1B The examples shown in the figure can be variously modified and varied. In some embodiments, the bonding structure BS can be omitted. In this case, the IC chip 100 can have a structure in which the first IC part ICP1 is bonded to the second IC part ICP2 by directly bonding the interlayer insulating film 136 to the interlayer insulating film 146.

[0038] The first IC part ICP1 and the second IC part ICP2 may perform different functions. In some embodiments, the first IC part ICP1 may include a logic device, and the second IC part ICP2 may include an analog device. In some embodiments, at least one of the first IC part ICP1 and the second IC part ICP2 may also include a memory device. For example, the first IC part ICP1 may include a logic device and a memory device, and the second IC part ICP2 may include an analog device. In some other embodiments, the first IC part ICP1 may include a logic device, and the second IC part ICP2 may include an analog device and a memory device. In some embodiments, the second IC part ICP2 may include a peripheral circuit such as an input / output device I / O.

[0039] In some embodiments, the logic device may include various types of logic units, which include multiple circuit elements such as transistors and registers. The logic unit may constitute, for example, AND, NAND, OR, NOR, XOR, XNOR, INV, ADD, BUF, DLY, FIL, MUX, OAI, AO, AOI, D flip-flop, reset flip-flop, master-slave flip-flop, or latch. For example, the logic device may include a logic circuit required for a display driver IC (DDI) for driving pixels included in a display such as a liquid crystal display (LCD) and a plasma display panel (PDP). The memory device may include a flash memory, a static random access memory (SRAM), a dynamic RAM (DRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a magnetic RAM (MRAM), or a combination thereof.

[0040] In some embodiments, the first IC part ICP1 may include a low voltage element including a low voltage transistor to which a relatively low operating voltage is applied, and the second IC part ICP2 may include a high voltage element including a high voltage transistor to which a relatively high operating voltage is applied. In some examples, the high voltage transistor may refer to a transistor having an operating voltage equal to or greater than 1V, and the low voltage transistor may refer to a transistor having an operating voltage less than 1V. In some examples, the high voltage transistor may refer to a transistor having an operating voltage equal to or greater than 3V, and the low voltage transistor may refer to a transistor having an operating voltage less than 3V. In some other embodiments, the first IC part ICP1 and the second IC part ICP2 may include devices configured to operate in different operating modes. For example, the first IC part ICP1 may include a device configured to operate in a low power mode compared to the device included in the second IC part ICP2. The second IC part ICP2 may include a device configured to operate in a high power mode compared to the device included in the first IC part ICP1.

[0041] The IC chip 100 may include: a via contact portion BVC and a dummy bump structure DBM, wherein the via contact portion BVC extends in a vertical direction (Z direction) along a through hole BVH, the through hole BVH being formed to pass through the first IC portion ICP1 and the bonding structure BS, and the dummy bump structure DBM protrudes from one end of the via contact portion BVC to the outside of the through hole BVH.

[0042] The through hole BVH may be formed to pass through the second substrate 120, the second device layer DA2, and the bonding structure BS from the backside (or bottom) surface 120B of the second substrate 120. In some embodiments, the through hole BVH may be formed to partially pass through the interlayer insulating film 136 of the first device layer DA1 included in the first IC portion ICP1. In some embodiments, the via contact portion BVC may be connected to at least one of the plurality of interconnect layers 134A included in the first device layer DA1. In some other embodiments, the via contact portion BVC may be connected to at least one of the plurality of interconnect layers 144A included in the second device layer DA2. Although Figure 1B An example is shown in which the via contact portion BVC is connected to the interconnection layer 134A of the first device layer DA1 and the interconnection layer 144A of the second device layer DA2, but the inventive concept is not limited thereto. For example, the via contact portion BVC may be configured to be connected only to the interconnection layer 134A of the first device layer DA1 or only to the interconnection layer 144A of the second device layer DA2.

[0043] The via contact portion BVC may include: a via contact plug VCP, which passes through the second substrate 120, the second device layer DA2 and the bonding structure BS through the through hole BVH and extends in the vertical direction (Z direction), and a via contact liner VCL surrounding the outer sidewall of the via contact plug VCP in the through hole BVH. The via contact liner VCL may contact the inner surface of the through hole BVH and fill the space between the inner surface of the through hole BVH and the via contact plug VCP.

[0044] The via contact plug VCP may include a first under-bump metallization (UBM) layer 166A and a first connection metal layer 168A, which contacts the first UBM layer 166A and fills the inside of the through hole BVH on the first UBM layer 166A. The first UBM layer 166A may include Ti, W, TiW, or a combination thereof. The first connection metal layer 168A may include gold (Au).

[0045] The via contact liner VCL may include W, Al, Ti, TiN or a combination thereof. The via contact liner VCL may include a first lower conductive layer 162A and a first upper conductive layer 164A, which may be sequentially stacked to conformally cover the inner surface of the through hole BVH. The first lower conductive layer 162A may contact the interconnect layer 134A of the first device layer DA1 and the interconnect layer 144A of the second device layer DA2. In some embodiments, the first lower conductive layer 162A may include a W film, and the first upper conductive layer 164A may include an Al film. In some embodiments, each of the first lower conductive layer 162A and the first upper conductive layer 164A may also include a conductive barrier film, which may include Ti, TiN or a combination thereof.

[0046] The bonding structure BS may surround the sidewall of the via contact portion BVC. The via contact portion BVC may pass through the bonding structure BS in a vertical direction (Z direction).

[0047] The connection pad liner CPL may extend along the back side 120B on the back side 120B of the second substrate 120 in a lateral direction (e.g., a direction parallel to the XY plane). The connection pad liner CPL may be connected to the via contact portion BVC. The connection pad liner CPL may be integrally connected to the via contact liner VCL included in the via contact portion BVC. The via contact liner VCL and the connection pad liner CPL may constitute a conductive liner that may extend continuously from the inside of the through hole BVH to the outside of the through hole BVH.

[0048] The connection pad liner CPL may include W, Al, Ti, TiN or a combination thereof. The connection pad liner CPL may include a second lower conductive layer 162B and a second upper conductive layer 164B, which are sequentially stacked on the back side 120B of the second substrate 120. The first lower conductive layer 162A of the via contact liner VCL may include the same material as the second lower conductive layer 162B of the connection pad liner CPL. The first upper conductive layer 164A of the via contact liner VCL may include the same material as the second upper conductive layer 164B of the connection pad liner CPL. The second lower conductive layer 162B may be integrally connected to the first lower conductive layer 162A. The second upper conductive layer 164B may be integrally connected to the first upper conductive layer 164A. The second lower conductive layer 162B may include a W film, and the second upper conductive layer 164B may include an Al film. In some embodiments, each of the second lower conductive layer 162B and the second upper conductive layer 164B may further include a conductive barrier film, which may include Ti, TiN, or a combination thereof.

[0049] When referring to an orientation, layout, position, shape, size, amount or other measurement, terms such as "same", "equal", "planar" or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, amount or other measurement, but are intended to include nearly the same orientation, layout, position, shape, size, amount or other measurement, such as within acceptable variations that may occur due to manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, items described as "substantially the same", "substantially equal" or "substantially planar" may be exactly the same, completely equal or completely planar, or may be the same, equal or planar within acceptable variations that may occur, such as due to manufacturing processes.

[0050] The dummy bump structure DBM may be located outside the through hole BVH and protrude from the back side 120B of the second substrate 120 to the outside of the second IC part ICP2. The dummy bump structure DBM may be integrally connected to the via contact plug VCP. The dummy bump structure DBM may include a second UBM layer 166B and a second connection metal layer 168B, which is located on the second UBM layer 166B and in contact with the second UBM layer 166B. The second UBM layer 166B may include Ti, W, TiW or a combination thereof. The second connection metal layer 168B may include Au. The first UBM layer 166A of the via contact plug VCP may include the same material as the second UBM layer 166B of the dummy bump structure DBM. The first connection metal layer 168A of the via contact plug VCP may include the same material as the second connection metal layer 168B of the dummy bump structure DBM.

[0051] The bump structure BM may be formed on the connection pad liner CPL. The bump structure BM may be in contact with the top surface of the connection pad liner CPL. The bump structure BM may be positioned separately from the back side 120B of the second substrate 120, wherein the connection pad liner CPL is between the bump structure BM and the back side 120B of the second substrate 120. The bump structure BM may be located at a position separated from the dummy bump structure DBM in a lateral direction (e.g., X direction). The minimum distance D1 between the bump structure BM and the dummy bump structure DBM in the lateral direction may be greater than 0.

[0052] The bump structure BM may include a third UBM layer 166C and a third connection metal layer 168C, which may be located on the third UBM layer 166C and in contact with the third UBM layer 166C. The third UBM layer 166C may include Ti, W, TiW or a combination thereof. The third connection metal layer 168C may include Au. The first UBM layer 166A of the via contact plug VCP, the second UBM layer 166B of the dummy bump structure DBM, and the third UBM layer 166C of the bump structure BM may include the same material. The first connection metal layer 168A of the via contact plug VCP, the second connection metal layer 168B of the dummy bump structure DBM, and the third connection metal layer 168C of the bump structure BM may include the same material.

[0053] In some embodiments, the first connection metal layer 168A of the via contact plug VCP, the second connection metal layer 168B of the dummy bump structure DBM, and the third connection metal layer 168C of the bump structure BM may include Au. For example, the first connection metal layer 168A may include an Au plug, the second connection metal layer 168B may include a dummy Au bump, the dummy Au bump is integrally connected to the Au plug, and the third connection metal layer 168C may include an Au bump, the Au bump is located at a position spaced apart from each of the Au plug and the dummy Au bump. In some other embodiments, in addition to gold (Au), the first connection metal layer 168A, the second connection metal layer 168B, and the third connection metal layer 168C may also include an additional metal. The additional metal may include nickel (Ni), copper (Cu), praseodymium (Pr), or a combination thereof.

[0054] Herein, the dummy bump structure DBM is a structure formed at the same level as the bump structure BM (for example, the level of the bottom surface of the dummy bump structure DBM is the same as the level of the bump structure BM) and adjacent to the bump structure BM. The dummy bump structure DBM is formed by the same conductive layer (for example, Fig.15I For example, the dummy bump structure DBM can be formed simultaneously with the bump structure BM using the same process of depositing and patterning the conductive layer of the bump structure BM. The dummy bump structure DBM in the IC chip 100 is not used to transmit signals to external devices (e.g., Fig.14 External terminals of the display panel 2300) shown in FIG.

[0055] exist Figure 1A , reference numeral “CX1” denotes a contact region between the interconnection layer 134A of the first device layer DA1 and the via contact portion BVC, and reference numeral “CX2” denotes a contact region between the connection pad liner layer CPL and the bump structure BM.

[0056] A groove G1 may be formed in the second substrate 120, and the groove G1 surrounds at least a portion of the via contact portion BVC at a position spaced apart from the via contact portion BVC. The groove G1 may include an annular space that may pass through the second substrate 120 and extend in the vertical direction (Z direction) at a position spaced apart from the via contact portion BVC in a lateral direction (e.g., a direction parallel to the XY plane).

[0057] The IC chip 100 may include an insulating film 170 that fills the groove G1 and covers the back side 120B of the second substrate 120. The insulating film 170 may include a through-insulating portion 170A that fills the groove G1 and an insulating liner portion 170B that covers the back side 120B of the second substrate 120. The through-insulating portion 170A may surround at least a portion of the via contact liner VCL at a position separated from the via contact portion BVC in a lateral direction (e.g., a direction parallel to the XY plane). The insulating liner portion 170B may be disposed between the back side 120B of the second substrate 120 and the connection pad liner CPL. The insulating film 170 may include an aluminum oxide film or a hafnium oxide film. In some embodiments, at least a portion of the through-insulating portion 170A may include an air gap. As used herein, the term "air" may refer to an atmosphere or other gas that may be present during the manufacturing process. The through-insulating portion 170A may pass through the second substrate 120 and extend in a vertical direction (Z direction), and has a ring-shaped planar structure. The via contact portion BVC may pass through the insulating liner portion 170B.

[0058] Figure 1A An example is shown in which each of the via contact portion BVC, the through-insulation portion 170A, the dummy bump structure DBM, and the bump structure BM has a rectangular planar shape, but the inventive concept is not limited thereto. For example, each of the via contact portion BVC, the through-insulation portion 170A, the dummy bump structure DBM, and the bump structure BM may have one of various planar shapes such as a circle, an ellipse, and a polygon.

[0059] The IC chip 100 may further include a passivation pattern 180 configured to cover the connection pad liner CPL on the back side 120B of the second substrate 120. The passivation pattern 180 may cover a partial area of ​​the connection pad liner CPL between the dummy bump structure DBM and the bump structure BM. The passivation pattern 180 may include an oxide film, a nitride film, or a combination thereof, but is not limited thereto.

[0060] The back surface 120B of the second substrate 120 , the top surface DBT of the dummy bump structure DBM, and the top surface BT of the bump structure BM may face the same direction.

[0061] In some embodiments, the top surface DBT of the dummy bump structure DBM may include a portion closer to the second substrate 120 than the top surface BT of the bump structure BM. The top surface DBT of the dummy bump structure DBM may have a concave shape, and the dummy bump structure DBM may include a portion having a smaller thickness in the vertical direction (Z direction) than the thickness of the bump structure BM in the vertical direction (Z direction).

[0062] In some embodiments, the dummy bump structure DBM and the bump structure BM may have different top profiles. For example, the difference ΔLV1 between the highest horizontal plane of the top surface DBT of the dummy bump structure DBM farthest from the back side 120B of the second substrate 120 and the lowest horizontal plane of the top surface DBT of the dummy bump structure DBM closest to the back side 120B of the second substrate 120 may be greater than the difference ΔLV2 between the highest horizontal plane of the top surface BT of the bump structure BM farthest from the back side 120B of the second substrate 120 and the lowest horizontal plane of the top surface BT of the bump structure BM closest to the back side 120B of the second substrate 120. The highest horizontal plane of the dummy bump structure DBM may be closer to the back side 120B of the second substrate 120 than the highest horizontal plane of the bump structure BM in the vertical direction (Z direction). For example, the distance between the highest horizontal plane of the dummy bump structure DBM and the back side 120B in the vertical direction may be smaller than the distance between the highest horizontal plane of the bump structure BM and the back side 120B in the vertical direction.

[0063] In the IC chip 100, the first connection metal layer 168A included in the via contact portion BVC and the third connection metal layer 168C included in the bump structure BM may include the same metal. The internal space of the via contact portion BVC surrounded by the via contact liner VCL may be filled with metal instead of an insulating material, so that the entire horizontal cross-sectional area of ​​the via contact portion BVC may be used as a conductive area. Therefore, the resistance of the via contact portion BVC may be significantly reduced, and the tolerance of the IC chip 100 to physical stress may be increased to improve the physical strength of the IC chip 100. For example, when each of the first connection metal layer 168A and the third connection metal layer 168C includes Au, since Au has a lower resistivity than another metal (e.g., aluminum (Al) and tungsten (W)), the resistance of the via contact portion BVC may be further reduced. Therefore, the resistance of the via contact portion BVC configured to electrically connect multiple interconnect layers 134A and 144A to the outside in the IC chip 100 may be reduced to improve the reliability of the IC chip 100.

[0064] Figure 2 is a cross-sectional view of a partial region of an IC chip 200 according to example embodiments.

[0065] Reference Figure 2 , the IC chip 200 may have Figure 1A and Figure 1B 2, except that, for example, IC chip 200 may include a dummy bump structure DBM2 and a bump structure BM2 having top surfaces DBT2 and BT2 at the same horizontal plane. In some examples, IC chip 200 may include a dummy bump structure DBM2 and a bump structure BM2 having top surfaces DBT2 and BT2 at the same vertical horizontal plane by using a chemical mechanical planarization (CMP) process. In this case, the top surfaces DBT2 and BT2 may be flat. Other detailed configurations of the dummy bump structure DBM2 and the bump structure BM2 may be the same as those of reference 1. Figure 1A and Figure 1B The configurations of the described dummy bump structure DBM and the bump structure BM are substantially the same.

[0066] Figure 3 is a cross-sectional view of a partial region of an IC chip 300 according to example embodiments.

[0067] Reference Figure 3 , the IC chip 300 may have Figure 1A and Figure 1B The IC chip 100 shown in FIG. 1 has a configuration substantially the same as that of the IC chip 100 shown in FIG. 1 , except that, for example, the IC chip 300 may include a via contact portion BVC3 and a dummy bump structure DBM3, wherein the via contact portion BVC3 extends in the vertical direction (Z direction) along a through hole BVH3 formed to pass through the first IC portion ICP1 and the bonding structure BS, and the dummy bump structure DBM3 is integrally connected to the via contact portion BVC3 and protrudes from one end of the via contact portion BVC3 to the outside of the through hole BVH3. The via contact portion BVC3 may not be connected to the interconnection layer 144A of the second device layer DA2 but only to the interconnection layer 134A of the first device layer DA1. The dummy bump structure DBM3 may have a top surface DBT3 having a concave shape, and at least a portion of the dummy bump structure DBM3 may have a portion having a thickness smaller than the thickness of the bump structure BM2 in the vertical direction (Z direction). The detailed configuration of the via contact portion BVC3 and the dummy bump structure DBM3 may be the same as that of the reference 1. Figure 1A and Figure 1B The configurations of the described via contact portion BVC and the dummy bump structure DBM are substantially the same.

[0068] Figure 4 is a cross-sectional view of a partial region of an IC chip 400 according to example embodiments.

[0069] Reference Figure 4 , IC chip 400 may have Figure 1A and Figure 1B 1, except that, for example, the IC chip 400 may include: an etch delay film 420 and a contact plug pad 422 formed near the active surface 120A of the second substrate 120 included in the second IC part ICP2, and a via contact portion BVC4 in contact with the contact plug pad 422. The etch delay film 420 and the contact plug pad 422 may be in contact with each other. The via contact portion BVC4 may include a portion that is in contact with the contact plug pad 422 through the etch delay film 420 and is self-aligned through the contact plug pad 422.

[0070] The etching delay film 420 may include an insulating material. For example, the etching delay film 420 may include a silicon oxide film, a silicon nitride film, or a combination thereof. The contact plug pad 422 may include a conductive material. In some embodiments, the contact plug pad 422 may include a metal, a metal silicide, a conductive metal nitride, or a combination thereof. The contact plug pad 422 may include a metal selected from W, Al, Cu, and Ti or doped polysilicon. In some embodiments, the contact plug pad 422 may include a material identical to at least a portion of a plurality of multilayer interconnect structures (e.g., 134 and 144).

[0071] The etch delay film 420 may be buried in the second substrate 120. The etch delay film 420 may be formed before the interlayer insulating film 146 is formed on the second substrate 120. After the etch delay film 420 buried in the second substrate 120 is formed and before the interlayer insulating film 146 is formed, a contact plug pad 422 may be formed on the etch delay film 420 in alignment with the etch delay film 420.

[0072] The closer the via contact portion BVC4 formed in the through hole BVH4 is to the dummy bump structure DBM, the larger the width of the via contact portion BVC4 in the lateral direction can become. The width of the via contact portion BVC4 can be discontinuously changed in the direction in which the via contact portion BVC4 extends from the dummy bump structure DBM to the first substrate 110. For example, at the position where the via contact portion BVC4 passes through the contact plug pad 422, the lateral width of the via contact portion BVC4 can be relatively sharply reduced. At the position where the via contact portion BVC4 passes through the interconnect layer 144A in contact with the via contact portion BVC4, the lateral width of the via contact portion BVC4 can be relatively sharply reduced. Towards the dummy bump structure DBM, the via contact portion BVC4 can have a larger lateral width. Therefore, when the first connection metal layer 168A is formed to fill the inside of the through hole BVH4, a good gap filling characteristic can be obtained.

[0073] In some embodiments, any one of the etching delay film 420 and the contact plug pad 422 may be omitted. In this case, the via contact portion BVC4 may be formed to be self-aligned through any one of the etching delay film 420 and the contact plug pad 422. At a position where the via contact portion BVC4 passes through any one of the etching delay film 420 and the contact plug pad 422 in a direction from the dummy bump structure DBM toward the first substrate 110, the lateral width of the via contact portion BVC4 may be relatively sharply reduced. The detailed configuration of the via contact portion BVC4 may be similar to that of the reference 1. Figure 1A and Figure 1B The detailed configuration of the via contact portion BVC described is basically the same.

[0074] Figure 5 is a cross-sectional view of a partial region of an IC chip 500 according to example embodiments.

[0075] Reference Figure 5 , IC chip 500 may have Figure 1A and Figure 1B The IC chip 100 shown in FIG. 1 has substantially the same configuration as that of the IC chip 100 shown in FIG. 1 , except that, for example, the IC chip 500 may include a via contact portion BVC5 extending in the vertical direction (Z direction) along a through hole BVH5 formed to pass through a portion of the second IC portion ICP2. The via contact portion BVC5 may not be connected to the interconnect layer 134A of the first device layer DA1 but may be connected to the interconnect layer 144A of the second device layer DA2. The via contact portion BVC5 may be located at a position spaced apart from the first IC portion ICP1 and the bonding structure BS in the vertical direction. The dummy bump structure DBM may be integrally connected to the via contact portion BVC5 and protrude from one end of the via contact portion BVC5 to the outside of the through hole BVH5. The detailed configuration of the via contact portion BVC5 may be the same as that of reference 1. Figure 1A and Figure 1B The detailed configuration of the via contact portion BVC described is basically the same.

[0076] Figure 6 is a plan view of a partial region of an IC chip 600 according to an example embodiment.

[0077] Reference Figure 6 , the IC chip 600 may have Figure 1A and Figure 1BThe IC chip 100 shown in FIG. 1 has a substantially same configuration as that of the IC chip 100, except that, for example, the IC chip 600 may include two via contact portions (e.g., BVC61 and BVC62) positioned adjacent to each other, and the two via contact portions BVC61 and BVC62 may be connected to one dummy bump structure DBM6. The two via contact portions BVC61 and BVC62 may be surrounded by one through insulating portion 670A having a ring shape. The detailed configuration of each of the via contact portions BVC61 and BVC62 may be the same as that of the reference 1. Figure 1A and Figure 1B The detailed configuration of the via contact portion BVC described in the foregoing is substantially the same. The detailed configuration of the dummy bump structure DBM6 and the through-insulation portion 670A may be respectively the same as that of the reference Figure 1A and Figure 1B The configurations of the described dummy bump structure DBM and the through-insulation portion 170A are substantially the same.

[0078] Figure 6 An example is shown in which each of the via contact portions BVC61 and BVC62, the dummy bump structure DBM6, and the through insulating portion 670A has a rectangular planar shape, but the inventive concept is not limited thereto. Each of the via contact portions BVC61 and BVC62, the dummy bump structure DBM6, and the through insulating portion 670A may have one of various planar shapes such as a circle, an ellipse, and a polygon. Although Figure 6 An example in which two via contact portions BVC61 and BVC62 are connected to one dummy bump structure DBM6 is shown, but the two via contact portions BVC61 and BVC62 may be respectively connected to additional dummy bump structures (not shown) separated from each other.

[0079] Figure 7 is a plan view of a partial region of an IC chip 700 according to an example embodiment.

[0080] Reference Figure 7 , IC chip 700 may have Figure 1A and Figure 1B , except that, for example, the IC chip 700 may include three via contact portions BVC71, BVC72, and BVC73 positioned adjacent to each other, and the three via contact portions BVC71, BVC72, and BVC73 may be connected to one dummy bump structure DBM7. The three via contact portions BVC71, BVC72, and BVC73 may be surrounded by one through insulating portion 770A having a ring shape. The detailed configuration of each of the via contact portions BVC71, BVC72, and BVC73 may be the same as that of the IC chip 100 shown in FIG. Figure 1A and Figure 1BThe detailed configuration of the via contact portion BVC described in the embodiment of the present invention is substantially the same as that of the via contact portion BVC described in the embodiment of the present invention. The detailed configuration of the dummy bump structure DBM7 and the through-insulation portion 770A can be respectively the same as that of the reference Figure 1A and Figure 1B The configurations of the described dummy bump structure DBM and the through-insulation portion 170A are substantially the same.

[0081] Each of the via contact portions BVC71, BVC72, and BVC73, the dummy bump structure DBM7, and the through insulating portion 770A is not limited to Figure 7 The planar shape shown in FIG. 1 may have various planar shapes. Figure 7 An example is shown in which three via contact portions BVC71, BVC72, and BVC73 are connected to one dummy bump structure DBM7, but some via contact portions selected from the three via contact portions BVC71, BVC72, and BVC73 may be connected to a dummy bump structure that is different from the dummy bump structure connected to other some via contact portions selected from the three via contact portions BVC71, BVC72, and BVC73. One or two via contact portions selected from the three via contact portions BVC71, BVC72, and BVC73 may be one or two dummy via contact portions that are not electrically connected to another external conductor.

[0082] Figure 8 is a plan view of a partial region of an IC chip 800 according to an example embodiment.

[0083] Reference Figure 8 , IC chip 800 may have Figure 1A and Figure 1B 8, except that, for example, the IC chip 800 may include a plurality of via contact portions BVC8 positioned adjacent to each other and arranged in a matrix. The plurality of via contact portions BVC8 may be connected to one dummy bump structure DBM8. The plurality of via contact portions BVC8 may be surrounded by one through insulating portion 870A having a ring shape. The detailed configuration of each of the plurality of via contact portions BVC8 may be the same as that of the reference Figure 1A and Figure 1B The detailed configuration of the via contact portion BVC described in the embodiment of the present invention is substantially the same as that of the via contact portion BVC described in the embodiment of the present invention. The detailed configuration of the dummy bump structure DBM8 and the through-insulation portion 870A may be the same as that of the via contact portion BVC described in the embodiment of the present invention. Figure 1A and Figure 1B The configurations of the dummy bump structures DBM and the through-insulation portions 170A described above are substantially the same. Each of the plurality of via contact portions BVC8, the dummy bump structures DBM8, and the through-insulation portions 870A is not limited to Figure 8Some of the via contact portions BVC8 selected from the plurality of via contact portions BVC8 may be dummy via contact portions that are not electrically connected to another external conductor.

[0084] Fig. 9 is a plan view of a partial region of an IC chip 900 according to an example embodiment.

[0085] Reference Fig. 9 , IC chip 900 may have Figure 8 800 shown in FIG. 1 , except that, for example, in IC chip 900, multiple via contact portions BVC8 can be respectively connected to different dummy bump structures among multiple dummy bump structures (e.g., DBM81, DBM82, DBM83, and DBM84). Multiple dummy bump structures DBM81, DBM82, DBM83, and DBM84 can be surrounded by a through insulating portion 870A having a ring shape. The detailed configuration of each of the multiple dummy bump structures DBM81, DBM82, DBM83, and DBM84 can be the same as that of reference 1. Figure 1A and Figure 1B The configuration of the described dummy bump structure DBM is the same.

[0086] Fig.10 is a plan view of a partial region of an IC chip 1000 according to an example embodiment.

[0087] Reference Fig.10 , IC chip 1000 may have Figure 1A and Figure 1B 1070B, except that, for example, in IC chip 1000, via contact portion BVC may be surrounded by a plurality of through-insulating portions (e.g., 1070A and 1070B) positioned separately from each other. In some embodiments, the plurality of through-insulating portions 1070A and 1070B may be configured to be connected to each other. The detailed configuration of each of the plurality of through-insulating portions 1070A and 1070B may be the same as that of reference 1000. Figure 1A and Figure 1B The detailed configuration of the through-insulation portion 170A described is the same.

[0088] Fig.11 is a plan view of a stack structure ST including a plurality of IC chips 1100 according to example embodiments.

[0089] Reference Fig.11The stacked structure ST may have a structure in which a first substrate 110 and a second substrate 120 are stacked in a vertical direction (Z direction). A plurality of first device layers DA1 may be formed on the first substrate 110, and a plurality of second device layers DA2 may be formed on the second substrate 120. The stacked structure ST may include a plurality of IC chips 1100. Fig.11 The plurality of IC chips 1100 included in the two full shots FS1 and FS2 are shown among the plurality of IC chips 1100 included in the stack structure ST. Fig.11 The plurality of IC chips 1100 shown in FIG. 1 may still be in a state before the plurality of IC chips 1100 are separated from each other and divided by a sawing process. Each of the plurality of IC chips 1100 may have a reference Figure 1A , Figure 1B as well as Figures 2 to 10 The structure of any one of the IC chips 100 , 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , and 1000 is described.

[0090] In the stack structure ST, the plurality of IC chips 1100 may be positioned apart from each other with scribe lines SL between the plurality of IC chips 1100. The full shots FS1 and FS2 may include the plurality of IC chips 1100. Each of the plurality of IC chips 1100 may constitute a DDI chip.

[0091] Fig.12 According to an example embodiment Fig.11 11 is a plan view of the configuration of any one of the plurality of IC chips 1100 shown in FIG.

[0092] Reference Fig.12 , the IC chip 1100 may include a circuit region 1120 and a peripheral region 1130 located around the circuit region 1120. For the sake of simplicity, although Fig.12 1100 is shown with a dotted line as a boundary between the circuit region 1120 and the peripheral region 1130, but the boundary between the circuit region 1120 and the peripheral region 1130 may not be physically distinguished. A plurality of driving circuit units 1122 and a plurality of interconnection patterns (not shown) may be located in the circuit region 1120. A plurality of connection portions CA may be formed in the peripheral region 1130. Each of the plurality of connection portions CA of the IC chip 1100 may include a plurality of connection portions CA from the reference Figure 1A , Figure 1B as well as Figures 2 to 10 Any one selected from the described bump structures BM and BM2. The plurality of connection portions CA may include a plurality of input electrode pads CA1 and a plurality of output electrode pads CA2.

[0093] Each of the plurality of driving circuit units 1122 may be electrically connected to any one of the plurality of connection portions CA through a plurality of interconnection patterns. The plurality of driving circuit units 1122 may generate a signal for driving the display panel (e.g., Fig.14 The plurality of driving circuit units 1122 may include a shift register, a data register, a row latch unit, a digital-to-analog converter (DAC), and an output buffer unit, but are not limited thereto. In some embodiments, similar to Figure 1A , Figure 1B as well as Figures 2 to 5 1 , the plurality of driving circuit units 1122 may include a first device layer DA1 formed on a first substrate 110 and a second device layer DA2 formed on a second substrate 120. The first device layer DA1 may include devices configured to operate in a lower power mode than devices included in the second device layer DA2.

[0094] The plurality of input electrode pads CA1 may constitute an input portion of the IC chip 1100 together with the input connection terminals, and the plurality of output electrode pads CA2 may constitute an output portion of the IC chip 1100 together with the output connection terminals. In some embodiments, each of the input connection terminals and the output connection terminals may include a reference Figure 1A , Figure 1B as well as Figures 2 to 10 Any of the described bump structures BM and BM2.

[0095] Fig.13A is a schematic plan view of an IC package 1200 according to an example embodiment, and Fig. 13B is along Fig.13A The enlarged cross-sectional view taken along the line BB' of FIG. Fig.13A The connecting portion CA along line BB' is not shown, but may be connected along line Fig. 13B The line BB' shown in FIG. 1 sets two connecting portions CA.

[0096] Reference Fig.13A and Fig. 13B , IC package 1200 may include reference Fig.12 The IC chip 1100 described above and the supporting substrate 1210 having a mounting surface on which the IC chip 1100 is mounted. The IC chip 1100 included in the IC package 1200 may be in a Fig.11The plurality of IC chips 1100 shown in FIG. 1 are in a state after being separated into individual chips through a sawing process.

[0097] In some embodiments, the IC chip 1100 may be a source driver chip (or source driver) configured to receive a signal voltage from an external device (e.g., an external printed circuit board (PCB)), generate an image signal, and output the image signal to a display panel (e.g., Fig.14 In some other embodiments, the IC chip 1100 may be a gate driver chip (or a gate driver) configured to generate a scan signal including an on / off signal of a transistor and output the scan signal to a gate line of the display panel.

[0098] In some embodiments, the support substrate 1210 may include a flexible film. For example, the support substrate 1210 may include polyimide, but is not limited thereto. The IC chip 1100 may be mounted on the mounting surface of the support substrate 1210 using a flip chip bonding method through a bump structure included in a plurality of connection portions CA. The bump structure included in the connection portion CA may be a bump structure formed from a reference numeral. Figure 1A , Figure 1B as well as Figures 2 to 10 Any one selected from the described bump structures BM and BM2.

[0099] A plurality of conductive lines 1230 may be formed on the support substrate 1210. The plurality of conductive lines 1230 may include a metal, such as copper (Cu). The plurality of conductive lines 1230 may include an input interconnection portion 1232 and an output interconnection portion 1234. The plurality of input electrode pads CA1 may be connected to the input interconnection electrode 1250 located on the support substrate 1210 through the input interconnection portion 1232. The plurality of output electrode pads CA2 may be connected to the output interconnection electrode 1260 located on the support substrate 1210 through the output interconnection portion 1234.

[0100] IC chip 1100 may include reference Figure 1A , Figure 1B as well as Figures 2 to 10 The structure of any one of the described IC chips 100, 200, 300, 400, 500, 600, 700, 800, 900, and 1000. Each of the bump structures BM and BM2 may be directly connected to any one of the plurality of conductive lines 1230. Each of the dummy bump structures DBM, DBM2, DBM3, DBM6, DBM7, DBM8, DBM81, DBM82, DBM83, and DBM84 may not be directly connected to any one of the plurality of conductive lines 1230.

[0101] A solder resist layer 1270 may be formed on the support substrate 1210. The solder resist layer 1270 may cover a portion of the plurality of conductive lines 1230. The solder resist layer 1270 may not cover portions of the input interconnection portion 1232 and the output interconnection portion 1234 connected to the connection portion CA. The solder resist layer 1270 may include insulating ink, a photosensitive solder resist, or a solder resist film.

[0102] The space between the IC chip 1100 and the support substrate 1210 may be filled with an underfill layer 1280. The underfill layer 1280 may include epoxy resin.

[0103] Portions of the plurality of connection portions CA and the plurality of conductive lines 1230 that may overlap with the IC chip 1100 in the vertical direction (Z direction) may be located below the IC chip 1100. Fig.13A In the plan view of FIG. 1 , portions of the plurality of connection portions CA and the plurality of conductive lines 1230 covered by the IC chip 1100 may not be visible from above.

[0104] Included in reference Fig.13A and Fig. 13B The IC chip 1100 in the IC package 1200 described in reference Figure 1A , Figure 1B as well as Figures 2 to 10 The similarities of the described IC chips 100, 200, 300, 400, 500, 600, 700, 800, 900 and 1000 can be that the first connection metal layer 168A included in the via contact parts BVC, BVC3, BVC4 and BVC5 and the third connection metal layer 168C included in the bump structure BM include the same metal. In addition, the internal space of the via contact parts BVC, BVC3, BVC4 and BVC5 surrounded by the via contact liner VCL can be filled with metal without insulating material, so that the entire horizontal cross-sectional area of ​​the via contact parts BVC, BVC3, BVC4 and BVC5 can be used as a conductive area. Therefore, the resistance of the via contact parts BVC, BVC3, BVC4 and BVC5 can be significantly reduced, and the tolerance of the IC chip 1100 to physical stress can be increased to improve the physical strength of the IC chip 1100. For example, when each of the first connection metal layer 168A and the third connection metal layer 168C includes Au having a relatively low resistivity, the resistance of the via contact portions BVC, BVC3, BVC4, and BVC5 can be further reduced. Therefore, the reliability of the IC package 1200 including the IC chip 1100 can be improved.

[0105] Fig.14 is a block diagram of a display apparatus 2000 according to an example embodiment.

[0106] Reference Fig.14 , the display device 2000 may include an application processor (AP) 2100 , a DDI chip 2200 , and a display panel 2300 .

[0107] The AP 2100 may control the overall operation of the display device 2000 and receive and output a data packet having display data in response to a clock signal ECLK. The data packet may include display data RGB Data, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a data enable signal DE.

[0108] The DDI chip 2200 may receive data packets from the AP 2100 and output a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable signal DE, and display data RGB Data. In some embodiments, the AP 2100 and the DDI chip 2200 may perform interface functions such as a mobile industry processor interface (MIPI), a mobile display digital interface (MDDI), and a compact display port (CDP). In some embodiments, a graphics memory (e.g., a graphics RAM (GRAM)) may be embedded in the DDI chip 2200 to enable a high-speed serial interface (HSSI) with the AP 2100. In some other embodiments, in order to enable HSSI with the AP 2100, the DDI chip 2200 may buffer data packets and output display data without using the GRAM. The DDI chip 2200 may include a reference Figure 1A , Figure 1B as well as Figures 2 to 10 At least one of the structures of the IC chips 100, 200, 300, 400, 500, 600, 700, 800, 900, and 1000 described above. In some examples, the DDI chip 2200 may be a reference Fig. 13B An IC package 1200 is described.

[0109] Through the control of the DDI chip 2200, the display panel 2300 can display the display data in frames. The display panel 2300 may include an organic light emitting display (OLED) panel, a liquid crystal display (LCD) panel, a plasma display panel (PDP), an electrophoretic display panel, or an electrowetting display panel. In some embodiments, the display panel 2300 may be connected to a touch screen (not shown) and configured to receive sensing data from the touch screen.

[0110] In the display device 2000 according to the present invention, the DDI chip 2200 and the reference Figure 1A , Figure 1B as well as Figures 2 to 10The similarity of the described IC chips 100, 200, 300, 400, 500, 600, 700, 800, 900 and 1000 can be that the first connection metal layer 168A included in the via contact parts BVC, BVC3, BVC4 and BVC5 and the third connection metal layer 168C included in the bump structure BM include the same metal. In addition, the internal space of the via contact parts BVC, BVC3, BVC4 and BVC5 can be filled with metal without insulating material. Therefore, the resistance of the via contact parts BVC, BVC3, BVC4 and BVC5 can be significantly reduced, and the tolerance of the IC chip 1100 to stress can be increased to improve the physical strength of the DDI chip 2200. For example, when each of the first connection metal layer 168A and the third connection metal layer 168C includes Au with relatively low resistivity, the resistance of the via contact parts BVC, BVC3, BVC4 and BVC5 can be further reduced. Therefore, the reliability of the display device 2000 including the DDI chip 2200 may be improved.

[0111] FIG. 15A to FIG. 15J is a cross-sectional view of a process sequence of a method for manufacturing an IC chip 100 according to an example embodiment. FIG. 15A to FIG. 15J Describing the manufacturing process according to the exemplary embodiment Figure 1A and Figure 1B The method of the IC chip 100 is shown in FIG. FIG. 15A to FIG. 15J In the drawings, the same reference numerals are used to denote Figure 1A and Figure 1B The same elements as those in and their repeated description will be omitted.

[0112] Reference Fig.15A , a first device layer DA1 may be formed on the active surface 110F of the first substrate 110 to form a first IC portion ICP1, and a first insulating structure BL1 may be formed on the first device layer DA1. The first insulating structure BL1 may include a stacked structure of a SiCN film 152A, a TEOS film 154A, and a SiCN film 156A, which are sequentially stacked on the first device layer DA1. A second device layer DA2 may be formed on the active surface 120A of the second substrate 120 to form a second IC portion ICP2, and a second insulating structure BL2 may be formed on the second device layer DA2. The second insulating structure BL2 may include a stacked structure of a SiCN film 152B, a TEOS film 154B, and a SiCN film 156B, which are sequentially stacked on the second device layer DA2.

[0113] Thereafter, the first IC part ICP1 may be aligned with the second IC part ICP2 in the vertical direction (Z direction) so that the first substrate 110 is positioned opposite to the second substrate 120 with the first device layer DA1 and the second device layer DA2 between the first substrate 110 and the second substrate 120. After the first IC part ICP1 is aligned with the second IC part ICP2 in the vertical direction, the first insulating structure BL1 may be positioned opposite to the second insulating structure BL2.

[0114] Reference Fig. 15B , the SiCN film 156A formed on the first IC part ICP1 can be brought into contact with the SiCN film 156B formed on the second IC part ICP2, and an annealing process can be performed so that the SiCN film 156A and the SiCN film 156B can be bonded to each other. Therefore, a SiCN-SiCN direct bonding structure in which the SiCN film 156A and the SiCN film 156B are bonded to each other can be obtained. The annealing process can be performed at a temperature selected from a temperature range of about 180° C. to about 450° C.

[0115] While the SiCN films 156A and 156B are bonded to each other, pressure may be applied to the first substrate 110 and the second substrate 120 to apply pressure to the SiCN films 156A and 156B. The plurality of SiCN films 152A, 152B, 156A, and 156B and the plurality of TEOS films 154A and 154B interposed between the first device layer DA1 and the second device layer DA2 may constitute a bonding structure BS.

[0116] Reference Fig. 15C , a first mask pattern M1 may be formed to cover the back side 120B of the second substrate 120. A first opening H1 having a ring-shaped planar structure may be formed in the first mask pattern M1. The first mask pattern M1 may include a photoresist pattern.

[0117] The second substrate 120 exposed through the first opening H1 may be anisotropically etched using the first mask pattern M1 as an etching mask, thereby forming a groove G1 exposing the interlayer insulating film 146. The groove G1 may have a ring-shaped planar structure.

[0118] Reference Fig.15D , can be obtained from Fig. 15C The first mask pattern M1 is removed from the combined structure of the substrate 120 and the insulating film 170 may be formed to fill the groove G1 and cover the back side 120B of the second substrate 120. The insulating film 170 may include: a through insulating portion 170A configured to fill the groove G1; and an insulating liner portion 170B configured to cover the back side 120B of the second substrate 120 outside the groove G1.

[0119] Reference Fig.15E ,exist Fig.15D In the combined structure of , a second mask pattern M2 having a second opening H2 may be formed on the insulating film 170. The insulating liner portion 170B exposed through the second opening H2, and the second substrate 120, the interlayer insulating film 146, and the bonding structure BS located below the insulating liner portion 170B may be etched using the second mask pattern M2 as an etching mask. Thereafter, a portion of the interlayer insulating film 136 may be etched to form a through hole BVH having a bottom surface exposing the interconnection layer 134A.

[0120] The second mask pattern M2 may include a photoresist pattern. The through hole BVH may be formed at a position separated from the through insulating portion 170A in a plane region defined by the through insulating portion 170A. The through hole BVH may be formed by an etching process such as dry etching. In some examples, the through hole BVH may be formed by one-time etching, so that the manufacturing process cost may be reduced.

[0121] Reference Fig.15F , can be obtained from Fig.15E The second mask pattern M2 is removed from the combined structure of , and a conductive layer 160 may be formed to cover the inner bottom surface and sidewalls of the via hole BVH and the top surface of the insulating liner portion 170B.

[0122] Conductive layer 160 may include: a lower conductive layer 162 that conformally covers an inner bottom surface and sidewalls of via BVH and a top surface of insulating liner portion 170B; and an upper conductive layer 164 that is located on lower conductive layer 162 to conformally cover lower conductive layer 162 .

[0123] Reference Figure 15G , you can Fig.15F The conductive layer 160 is patterned in the combined structure to form a via contact liner VCL and a connection pad liner CPL. The via contact liner VCL may include a portion of the conductive layer 160 that remains inside the through hole BVH. The connection pad liner CPL may include a portion of the conductive layer 160 that remains on the back side 120B of the second substrate 120. The via contact liner VCL may include a first lower conductive layer 162A and a first upper conductive layer 164A, which include a portion of the lower conductive layer 162 and a portion of the upper conductive layer 164, respectively. The connection pad liner CPL may include a second lower conductive layer 162B and a second upper conductive layer 164B, which include another portion of the lower conductive layer 162 and another portion of the upper conductive layer 164, respectively.

[0124] Thereafter, a passivation pattern 180 may be formed on the connection pad liner CPL. The passivation pattern 180 may have a first opening 180A communicating with the via hole BVH and a second opening 180B exposing a top surface of the connection pad liner CPL.

[0125] Reference Fig.15H , an under bump metallization (UBM) layer 166 may be formed to blanket cover Figure 15G The top surface of the combined structure of , and a third mask pattern M3 may be formed on the UBM layer 166. The third mask pattern M3 may include a plurality of openings that define a region where a plurality of bumps are to be formed. For example, the third mask pattern M3 may be formed on the UBM layer 166, and the third mask pattern M3 may not be formed in the region where the plurality of openings are located.

[0126] The UBM layer 166 may be formed to cover the via contact liner VCL inside the through hole BVH and to cover the connection pad liner CPL outside the through hole BVH. The UBM layer 166 may include Ti, W, TiW, or a combination thereof. The third mask pattern M3 may include a photoresist pattern.

[0127] Reference Fig.15I The UBM layer 166 exposed by the third mask pattern M3 may be used as a seed layer. Fig.15H The electroplating process is performed on the combined structure of. Therefore, the first connection metal layer 168A, the second connection metal layer 168B and the third connection metal layer 168C can be formed. The first connection metal layer 168A can cover the UBM layer 166 inside the through hole BVH. The second connection metal layer 168B can be integrally connected to the first connection metal layer 168A and protrude from the first connection metal layer 168A to the outside of the through hole BVH. The third connection metal layer 168C can cover the UBM layer 166 on the connection pad liner CPL. The first connection metal layer 168A, the second connection metal layer 168B and the third connection metal layer 168C can be formed simultaneously using an electroplating process performed in the same space.

[0128] During the formation of the first connection metal layer 168A, the second connection metal layer 168B, and the third connection metal layer 168C, the first connection metal layer 168A and the second connection metal layer 168B may include a portion formed using an electroplating process performed on the UBM layer 166 at a relatively low level located inside the through hole BVH. The third connection metal layer 168C may be formed using an electroplating process performed on the UBM layer 166 at a relatively high level located on the connection pad liner CPL outside the through hole BVH. For example, the top surface of the second connection metal layer 168B and the top surface of the third connection metal layer 168C may have different profiles. In some embodiments, the top surface of the second connection metal layer 168B and the top surface of the third connection metal layer 168C may be formed at a higher level than the top surface of the third mask pattern M3.

[0129] Reference Fig.15J , a stripping process can be used from Fig.15I The third mask pattern M3 is removed from the combined structure of the passivation pattern 180. In some examples, by using a lift-off process, when the third mask pattern M3 is removed, portions of the second connection metal layer 168B and the third connection metal layer 168C formed on the third mask pattern M3 may be removed simultaneously. The second connection metal layer 168B and the third connection metal layer 168C may be used as an etching mask to etch the portion of the UBM layer 166 exposed after the third mask pattern M3 is removed, thereby exposing the top surface of the passivation pattern 180 around the second connection metal layer 168B and the third connection metal layer 168C.

[0130] After the top surface of the passivation pattern 180 is exposed, the following items can be obtained from the remaining portion of the UBM layer 166 that is not removed: the first UBM layer 166A included in the via contact plug VCP, the second UBM layer 166B included in the dummy bump structure DBM, and the third UBM layer 166C included in the bump structure BM.

[0131] In the method for manufacturing the IC chip 100 according to the embodiment disclosed herein, the first connection metal layer 168A of the via contact portion BVC and the third connection metal layer 168C of the bump structure BM can be formed simultaneously. Therefore, in order to form the first connection metal layer 168A of the via contact portion BVC and the third connection metal layer 168C of the bump structure BM, a separate mask pattern may not be used except for the third mask pattern M3. Therefore, the manufacturing cost of the IC chip 100 can be reduced, and the process of manufacturing the IC chip 100 can be simplified.

[0132] Although referenced FIG. 15A to FIG. 15J Describes Figure 1A and Figure 1BHowever, various modifications and changes may be made without departing from the scope of the present invention, and those skilled in the art will understand that reference may be made to the method of manufacturing the IC chip 100. FIG. 15A to FIG. 15J manufacture Figures 2 to 10 The IC chips 200 , 300 , 400 , 500 , 600 , 700 , 800 , 900 , and 1000 shown in FIG. 1 or various IC chips having a structure similar thereto.

[0133] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit chip, include: an integrated circuit portion, the integrated circuit portion comprising a substrate and a device layer formed on the substrate; A via contact plug extending in a vertical direction inside a through hole passing through the substrate and the device layer; A via contact liner surrounding the via contact plug in the through hole; a connection pad liner integrally connected to the via contact liner, the connection pad liner extending in a lateral direction along the bottom surface of the substrate; a dummy bump structure, located outside the through hole and integrally connected to the via contact plug; as well as a bump structure connected to the connection pad liner at a position separated from the via contact plug and the dummy bump structure, Wherein, the via contact liner and the connection pad liner are conductive liner layers, and Wherein, the bump structure is electrically connected to the dummy bump structure through the connection pad liner.

2. The integrated circuit chip according to claim 1, in, The via contact plug, the dummy bump structure, and the bump structure include the same metal as each other.

3. The integrated circuit chip according to claim 1, in, Each of the via contact plug, the dummy bump structure and the bump structure includes an under bump metal (UBM) layer and a connection metal layer in contact with the UBM layer, and Wherein, the connecting metal layer includes gold Au.

4. The integrated circuit chip according to claim 1, in, The dummy bump structure and the bump structure have different top profiles, and Wherein, the top surface of the dummy bump structure is closer to the bottom surface of the substrate than the top surface of the bump structure.

5. The integrated circuit chip according to claim 1, further comprising: include: A through insulating portion surrounds at least a portion of the via contact liner at a position spaced apart from the via contact liner in the lateral direction, the through insulating portion passes through the substrate and extends longitudinally in the vertical direction.

6. A display device, include: A display driver integrated circuit DDI chip, comprising the integrated circuit chip according to claim 1; as well as The display panel is configured to display image data through the control of the DDI chip.

7. An integrated circuit chip, include: A first integrated circuit portion includes a first substrate and a first device layer formed on the first substrate; a second integrated circuit portion, comprising a second substrate and a second device layer formed on the second substrate, the second integrated circuit portion overlapping the first integrated circuit portion in a vertical direction; a via contact portion, comprising a via contact plug, the via contact plug extending in the vertical direction along a through hole passing through the second substrate and the second device layer; a connection pad liner electrically connected to the via contact portion, the connection pad liner extending in a lateral direction along a bottom surface of the second substrate; a dummy bump structure protruding from one end of the via contact portion toward the outside of the through hole; as well as a bump structure formed on the connection pad liner and electrically connected to the connection pad liner and located at a position spaced apart from the dummy bump structure in the lateral direction, wherein the via contact plug, the dummy bump structure and the bump structure comprise the same material as each other, and Wherein, the connection pad lining layer is a conductive layer.

8. The integrated circuit chip according to claim 7, in, The first substrate and the second substrate are spaced apart from each other, with the first device layer and the second device layer being between the first substrate and the second substrate.

9. The integrated circuit chip according to claim 7, in, The via contact portion further includes a via contact liner surrounding an outer sidewall of the via contact plug, wherein the via contact liner is integrally connected to the connection pad liner.

10. The integrated circuit chip according to claim 9, in, The via contact plug includes a gold plug and a first under bump metal (UBM) layer covering the sidewall and bottom surface of the gold plug, and The dummy bump structure includes a dummy gold bump integrally connected to the gold plug, and a second UBM layer integrally connected to the first UBM layer.

11. The integrated circuit chip according to claim 7, in, The top surface of the dummy bump structure, the top surface of the bump structure, and the bottom surface of the second substrate face the same direction, and Wherein, the top surface of the dummy bump structure is closer to the bottom surface of the second substrate than the top surface of the bump structure.

12. The integrated circuit chip according to claim 7, further comprising: include: a bonding structure between the first integrated circuit portion and the second integrated circuit portion, The bonding structure surrounds the sidewall of the via contact portion.

13. The integrated circuit chip according to claim 7, further comprising: include: A through insulating portion surrounds at least a portion of the via contact portion at a position spaced apart from the via contact portion in the lateral direction, the through insulating portion passes through the second substrate and extends longitudinally in the vertical direction.

14. The integrated circuit chip according to claim 7, in, At least one of the first device layer and the second device layer includes at least one interconnect layer configured to connect to the via contact portion.

15. The integrated circuit chip according to claim 7, in, The first integrated circuit portion includes a logic device, and Wherein, the second integrated circuit portion includes analog devices.

16. The integrated circuit chip according to claim 15, in, Any one of the first integrated circuit portion and the second integrated circuit portion further includes a memory device.

17. An integrated circuit chip, include: A first integrated circuit portion includes a first substrate and a first device layer formed on the first substrate; A second integrated circuit portion includes: a second substrate spaced apart from the first substrate, and a second device layer between the second substrate and the first device layer, wherein the first device layer is between the second substrate and the first substrate; a via contact plug extending in a vertical direction along a through hole passing through the second integrated circuit portion; A via contact liner, surrounding an outer sidewall of the via contact plug inside the through hole; a connection pad liner integrally connected to the via contact liner, the connection pad liner extending in a lateral direction along the bottom surface of the second substrate; a dummy bump structure connected to the via contact plug; and The bump structure is connected to the connection pad liner, The via contact plug, the dummy bump structure and the bump structure include the same metal.

18. The integrated circuit chip according to claim 17, in, The dummy bump structure has a concave top surface, and Wherein, a thickness of at least a portion of the dummy bump structure in the vertical direction is smaller than a thickness of the bump structure in the vertical direction.

19. The integrated circuit chip according to claim 17, further comprising: include: a bonding structure between the first device layer and the second device layer, Wherein, the via contact plug and the via contact liner pass through the bonding structure.

20. The integrated circuit chip according to claim 19, in, The first device layer includes a first device configured to operate in a lower power mode than a second device included in the second device layer operates.

21. An integrated circuit package, include: A supporting substrate; A plurality of conductive lines formed on the support substrate; as well as an integrated circuit chip mounted on the support substrate and configured to be electrically connected to the plurality of conductive lines, Wherein, the integrated circuit chip comprises: A first integrated circuit portion includes a first substrate and a first device layer formed on the first substrate; a second integrated circuit portion, comprising a second substrate and a second device layer formed on the second substrate, the second integrated circuit portion overlapping the first integrated circuit portion in a vertical direction; a via contact plug extending in the vertical direction inside a through hole passing through the second substrate and the second device layer; A via contact liner surrounding the via contact plug in the through hole; a connection pad liner integrally connected to the via contact liner, the connection pad liner extending in a lateral direction along the bottom surface of the second substrate; a dummy bump structure located outside the through hole and integrally connected to the via contact plug; and a bump structure connected to the connection pad liner at a position spaced apart from the via contact plug and the dummy bump structure, wherein the bump structure is directly connected to at least one of the plurality of conductive lines, and the dummy bump structure is not directly connected to any of the plurality of conductive lines, Wherein, the via contact liner and the connection pad liner are conductive liner layers, and Wherein, the bump structure is electrically connected to the dummy bump structure through the connection pad liner.

22. A method for manufacturing an integrated circuit chip, the method include: preparing an integrated circuit portion, the integrated circuit portion comprising a substrate and a device layer formed on an active surface of the substrate; forming a through hole from a bottom surface of the substrate, the bottom surface of the substrate being opposite to an active surface of the substrate, wherein the through hole passes through the substrate and the device layer; forming a via contact liner and a connection pad liner, wherein the via contact liner covers an inner wall of the through hole, and the connection pad liner is integrally connected to the via contact liner and extends in a lateral direction along a bottom surface of the substrate; forming an under bump metal (UBM) layer to cover the via contact liner inside the through hole and the connection pad liner outside the through hole; as well as forming a first connection metal layer, a second connection metal layer, and a third connection metal layer, wherein the first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer and protrudes to the outside of the through hole, and the third connection metal layer is spaced apart from the second connection metal layer in the lateral direction and covers the UBM layer on the connection pad liner, Wherein, the via contact liner and the connection pad liner are conductive liner layers, and Wherein, the third connection metal layer is electrically connected to the second connection metal layer through the connection pad liner.

23. The method according to claim 22, in, The first connection metal layer and the third connection metal layer are formed simultaneously.

24. The method according to claim 22, in, Each of the first connection metal layer, the second connection metal layer, and the third connection metal layer includes gold Au.

25. A method for manufacturing an integrated circuit chip, the method include: preparing a first integrated circuit portion, the first integrated circuit portion comprising a first substrate, and a first device layer formed on an active surface of the first substrate; preparing a second integrated circuit portion, the second integrated circuit portion comprising a second substrate, and a second device layer formed on an active surface of the second substrate; bonding the first integrated circuit portion and the second integrated circuit portion to each other so that the first substrate is positioned opposite the second substrate with the first device layer and the second device layer between the first substrate and the second substrate; forming a through hole from a bottom surface of the second substrate, the bottom surface being opposite to an active surface of the second substrate, wherein the through hole passes through the second substrate and the first device layer and exposes at least one first interconnect layer included in the first device layer; forming a via contact liner and a connection pad liner, wherein the via contact liner covers an inner wall of the through hole, and the connection pad liner is integrally connected to the via contact liner and extends in a lateral direction along a bottom surface of the second substrate; forming an under bump metal (UBM) layer to cover the via contact liner inside the through hole and the connection pad liner outside the through hole; as well as A first connection metal layer, a second connection metal layer and a third connection metal layer are formed, wherein the first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer and protrudes to the outside of the through hole, and the third connection metal layer is separated from the second connection metal layer and covers the UBM layer on the connection pad liner.

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