Apparatus and method for command queuing

Abstract

The present disclosure includes apparatuses and methods for command queuing. Several embodiments include receiving a queued command request from a host at a memory system; sending a command response from the memory system to the host, the command response indicating that the memory system is ready to receive a command in a command queue of the memory system; and receiving a command descriptor block of the command from the host at the memory system in response to sending the command response.

Description

[0001] Related information of divisional application

[0002] This application is a divisional application. The parent application of this divisional application is the patent application entitled "Command Queuing" with the application number 201580008744.0 and the filing date of February 12, 2015. TECHNICAL FIELD

[0003] The present disclosure relates generally to semiconductor memory and methods, and more specifically to command queuing. BACKGROUND

[0004] Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and can include random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered and can include NAND flash memory, NOR flash memory, phase-change random access memory (PCRAM), resistive random access memory (RRAM), spin-torque transfer random access memory (STT RAM), and magnetic random access memory (MRAM), among others.

[0005] Multiple memory devices can be combined together to form, for example, a memory system including multiple memory devices, such as a memory card as an embedded storage solution or as a solid state drive. A memory system, such as a memory card, can include non-volatile memory (e.g., NAND flash memory and / or NOR flash memory) and / or can include volatile memory (e.g., DRAM and / or SRAM), as well as various other types of non-volatile and volatile memory. Flash memory devices can include memory cells that store data in charge storage structures, such as floating gates, for example, and can be used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use single transistor memory cells that allow for high memory density, high reliability, and low power consumption.

[0006] Memory systems can be used as portable memory or embedded storage solutions for use with several hosts in a computing system and / or for replacing hard disk drives as the primary storage for a computing system because solid state drives can have advantages over hard disk drives in performance, size, weight, durability, operating temperature range, and power consumption. For example, memory systems can have superior performance when compared to disk drives because of their lack of moving parts, which can avoid seek time, latency, and other electromechanical delays associated with disk drives. Memory system manufacturers can use non-volatile memory to form memory systems that can not use an internal battery for power, thus allowing the drive to be more universal and compact.

[0007] Memory systems can include several memory devices, such as several memory chips. As will be appreciated by those skilled in the art, a memory chip can include several dies and / or logical units (LUNs), such as where a LUN can be one or more dies. Each die can include several memory arrays and peripheral circuitry thereon. Memory arrays can include several memory cells organized into several physical pages, and the physical pages can be organized into several blocks. Flash memory cell arrays can be programmed one page at a time and erased one block at a time. Operations performed on a memory system, such as read, write, and erase operations, can be limited by the amount of resources available in the memory system to manage operations by the memory devices in the memory system. SUMMARY

[0008] In one aspect, the disclosure relates to a method for command queuing, comprising: receiving a command at a memory system (104, 204) from a host (102), wherein the command comprises a command descriptor block (244); and in response to receiving the command descriptor block, placing the command described by the command descriptor block in a command queue (126) of the memory system.

[0009] In another aspect, the disclosure relates to an apparatus, comprising: a controller (125); and a memory device (130) coupled to the controller, wherein the apparatus is configured to: place a command in a command queue (126) in response to receiving the command comprising a command descriptor block (244); and execute the command in response to receiving a ready-to-transfer command (450).

[0010] In another aspect, the disclosure relates to a method for command queuing, comprising: receiving a first command at a memory system (104, 204) from a host (102), wherein the first command comprises a first command descriptor block; placing the first command in a command queue (126) of the memory system in response to receiving the first command descriptor block; executing the first command in response to receiving a ready-to-send command (450); receiving a second command at the memory system from the host, wherein the second command comprises a second command descriptor block; and placing the second command in the command queue of the memory system while executing the first command in response to receiving the second command descriptor block. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory system in accordance with a number of embodiments of the present disclosure.

[0012] Figure 2 FIG. illustrates an example of a method for command queuing in a memory system in accordance with a number of embodiments of the present disclosure.

[0013] Figure 3 FIG. illustrates an example of a command block descriptor in accordance with a number of embodiments of the present disclosure.

[0014] Figure 4A FIG. illustrates an example of a method for executing commands in a command queue in a memory system in accordance with a number of embodiments of the present disclosure.

[0015] Figure 5 FIG. illustrates an example of a data transfer request header included in a data transfer request in accordance with a number of embodiments of the present disclosure.

[0016] Figure 6 FIG. illustrates an example of a method for command queuing and command execution in a memory system in accordance with a number of embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host; sending a command response from the memory system to the host, the command response indicating that the memory system is ready to receive a command in a command queue of the memory system; and receiving a command descriptor block of the command at the memory system from the host in response to sending the command response.

[0018] Several embodiments of the present invention can incorporate command queuing and simultaneous command execution for commands controlled using the embedded multimedia card (e.MMC) protocol. New command classes can be introduced and added to the commands in the e.MMC protocol to allow for command queuing and simultaneous command execution when using the e.MMC protocol. Queued command request commands (e.g., CMD 43), prepare to transfer commands (e.g., CMD 44), task management function request commands (e.g., CMD 45), receive data commands (e.g., CMD 46), and send data commands (e.g., CMD 47) can be added as command classes to the e.MMC protocol. These commands can be incorporated into the e.MMC protocol to allow for command queuing and simultaneous command execution with minimal changes to the e.MMC state machine of a memory system or with only one state change added to the e.MMC state machine of a memory system.

[0019] As used herein, "several" something can mean one or more such things. For example, several memory units can mean one or more memory units. Also, as used herein, the designations "M" and "N" (especially with respect to element symbols in the figures) indicate that the particular feature so designated can be included with several embodiments of the present invention.

[0020] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures can be identified by the use of similar digits. For example, 104 can refer to element "04" in Figure 1 and 204 in Figure 2 may refer to similar elements.

[0021] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory system 104, in accordance with several embodiments of the present invention. As used herein, the memory system 104, controller 125, or memory devices 130-1,..., 130-N can also be considered individually as an "apparatus." The memory system 104 can be any of several memory systems (e.g., a memory card), and can include a host interface 106, a controller 125, and a plurality of memory devices 130-1,..., 130-N (e.g., solid state memory devices such as NAND flash devices) that provide a storage volume for the memory system 104. The memory system 104 can be communicatively coupled to a host 102 via the host interface 106 (e.g., a board or bus).

[0022] Examples of host 102 can include a laptop computer, a personal computer, a digital camera, a digital recording and playback device, a mobile telephone, a PDA, a memory card reader, and an interface hub, among other host systems. Memory system 104 can be part of a cloud storage networking infrastructure, for example, memory system 104 is coupled to host 102 via host interface 106, which can include a serial advanced technology attachment (SATA), a peripheral component interconnect express (PCIe), a universal serial bus (USB), Fibre Channel, or Ethernet connection, among other connectors and interfaces. In general, however, host interface 106 can provide an interface for communicating control, address, data, and other signals between memory system 104 and host 102, for example, on command and / or data buses.

[0023] Host 102 can include several processors (e.g., parallel processors, co-processors, etc.) communicatively coupled to a memory and bus control. The several processors can be several microprocessors or some other type of control circuitry (e.g., several application specific integrated circuits (ASICs), for example). Other components of computing system 100 can also have processors. The memory and bus control can have the memory and other components directly communicatively coupled thereto, for example, dynamic random access memory (DRAM), a graphical user interface and / or other user interface (e.g., a display monitor, a keyboard, a mouse, etc.).

[0024] Controller 125 can communicate with memory (e.g., memory devices 130-1 through 130-N) to control data read, write, and erase operations, among other operations. For example, controller 125 can include several components in the form of hardware and / or firmware (e.g., one or more integrated circuits / logic) and / or software for controlling access to memory and / or for facilitating data transfers between host 102 and memory.

[0025] In the example illustrated in Figure 1 Controller 125 includes command queue 126 and status registers 127. However, controller 125 can include various other components not illustrated so as not to obscure embodiments of the application. Also, although command queue 126 and status registers 127 are illustrated as residing on controller 125, in some embodiments, command queue 126 and status registers 127 can reside elsewhere in system 100 or on different components of the system, for example, as standalone components.

[0026] The command queue 126 can include a number of commands that have been received by the memory system 104 from the host 102 for execution. The command queue 126 can include information associated with the commands, which is included in a command descriptor block for each of the commands in the command queue 126. The status registers 127 can be registers that store status information for each of the commands in the command queue 126, such as, for example, task sleep, task enable, task complete, task error, and / or task abort. The command queue 126 and the status registers 127 can include volatile memory units, such as, for example, DRAM memory units, and / or non-volatile memory, such as, for example, flash, RRAM, MRAM, STTRAM, and / or PCRAM memory units, to store the information associated with the commands. Data received from the host during execution of the commands in the command queue 126 can have error correction code (ECC) operations performed on the data by an ECC module before being stored in the memory devices 130-1 through 130-N.

[0027] The memory system 104 includes a bus 120 to send / receive various signals and / or commands, such as data signals, control signals, and / or address signals, etc., between the memory devices 130-1, 130-N and the controller 125. Although the illustrated example includes a single bus 120, in some embodiments, the memory system 104 can include a number of buses, such as lanes, such as a number of separate data buses, control buses, and / or address buses. The bus 120 is shared by the plurality of memory devices 130-1, 130-N and can have various types of bus structures, including, but not limited to, bus structures related to the Open NAND Flash Interface (ONFI). Moreover, the bus 120 can include various types of bus structures, including, but not limited to, Compact Flash Interface, MultiMediaCard (MMC), Secure Digital (SD), Consumer Electronics Advanced Technology Attachment (CE-ATA), Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association bus (PCMCIA), Firewire (IEEE 1394), and Small Computer System Interface (SCSI). For example, the bus 120 can be a hardwired shared physical bus. Figure 1

[0028] Figure 1 The computing system 100 illustrated in FIG. 1 is one example of such a system; however, embodiments of the application are not limited to this Figure 1 configuration shown in FIG. 1. ​

[0029] As Figure 1 illustrated in the background, memory devices 130-1,..., 130-N can include a number of dies and / or chips that can contain a number of memory arrays 112-1, 112-2,..., 112-M that provide storage volumes for memory system 104. Memory arrays 112-1, 112-2,..., 112-M can contain peripheral circuitry thereon. In a number of embodiments, memory arrays 112-1, 112-2,..., 112-M can be the minimal components of memory system 104 capable of independently executing commands from host 102 and / or sending status to host 102 via host interface 106. For example, memory arrays 112-1, 112-2,..., 112-M can include flash memory arrays having a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture and can include memory arrays having RRAM, MRAM, STTRAM, and / or PCRAM memory cells.

[0030] Figure 1 Embodiments illustrated in the background can include additional circuitry, logic, and / or components not illustrated in order not to obscure embodiments of the present application. For example, memory devices 130-1,..., 130-N can include address circuitry to latch address signals provided over I / O circuitry at I / O connectors. The signals can be received and decoded by a row decoder and a column decoder to access memory system 104.

[0031] Figure 2 An example of a method for command queuing in a memory system is illustrated in accordance with a number of embodiments of the present application. In Figure 2In particular embodiments, a queued command request 240-1 (e.g., CMD 43) can be sent from the host 202 to the memory system 204. The queued command request 240-1 can indicate to the memory system 204 that the host 202 wants to send a command to the memory system 204 for the memory system 204 to add to a command queue in the memory system 204. The memory system 204 can send a command response 242-1 to the host in response to receiving the queued command request. The command response 242-1 can include a queue busy bit set to one (1) indicating that the memory system 204 is not ready to receive a command in the command queue, e.g., the command queue is full. When the host 202 receives the command response 242-1 with the queue busy bit set to (1), the host 202 does not send a command block descriptor back to the memory system 204. In several embodiments, the host 202 can send several queued command requests to the memory system 204 until the memory system 204 sends a command response back with the queue busy bit set to zero (0). For example, after a period of time, the host 202 can send another queued command request 240-P to the memory system 204 that includes the same information as the queued command request 240-1. If the command queue in the memory system 204 is ready to receive a command to be added to the command queue, the memory system 204 can send a command response 242-0 to the host 202 with the queue busy bit set to zero (0) indicating that the memory system 204 is ready to add a command to the command queue. The host 202 sends a command descriptor block 244 to the memory system 204 and the memory system 204 places the command described in the command descriptor block 244 in the command queue. The command descriptor block 244 includes information about the command that enables the host 202 and the memory system 204 to execute the command when they are ready to do so.

[0032] In several embodiments, the host 202 can send a task management function request command (e.g., CMD 45) to the memory system 204. The task management function request command can be used to check a status register (e.g., status register 127) in the memory system 204 to determine the status of the command queue (e.g., command queue 126) in the memory system 204. Figure 1 Figure 1 ​The task management function request command can be sent from the host 202 to the memory system 204 with an indication to abort the command queue, whereby each of the commands in the command queue is aborted by the memory system 204. In addition, a stop command (e.g., a CMD 12 and / or a high priority interrupt (HPI) command) can be sent from the host 202 to the memory system 204, which will cause the memory system 204 to abort the command queue.

[0033] In several embodiments, several commands can be added to the command queue when the host sends several queued command requests to the memory system and then sends several command descriptor blocks to the memory system in response to receiving several command responses indicating that the command queue is ready to receive commands. The several queued command requests can be received from the host on a command line, such that the queued command requests can be received by the memory system and responded to by the memory system when performing commands from the command queue on the data bus in the memory system.

[0034] Figure 3 An example of a command block descriptor 344 is illustrated in accordance with several embodiments of the present disclosure. In Figure 3In some embodiments, the command block descriptor 344 includes a number of fields that provide information associated with the command so that the command can be placed in the command queue and executed according to the information contained in the command block descriptor 344. For example, the command block descriptor can include 32 bytes and other numbers of bytes. In this example, the command block descriptor 344 can include 32 bytes, where byte 0 is associated with the command operation code 341, byte 1 is associated with the command priority information 343, byte 2 is reserved, byte 3 is associated with the command task tag 345, bytes 4 to 7 are associated with the command arguments 346, bytes 8 to 11 are associated with the command start address 348, bytes 12 to 13 are reserved, bytes 14 to 15 are associated with the command block count 349, and bytes 16 to 31 are reserved. By way of example, the command operation byte 341 can be set to a value of 01h corresponding to a read command. The command operation byte 341 can be set to a value of 02h corresponding to a write command. The command priority information 343 can indicate an order of execution priority in the command queue. The command priority information 343 byte can be set to a value of 00h, which corresponds to a simple priority in which the command is placed in the command queue without priority. The command priority information 343 byte can be set to a value of 01h, which corresponds to an ordered priority in which the command is placed in the command queue so that the command is executed in time order based on when the memory system receives the command. The command priority information 343 byte can be set to a value of 02h, which corresponds to a queue head priority in which the command is the next command to be executed. The command task tag 345 byte can correspond to a unique identifier used to distinguish the command from other commands in the command queue. The command task tag byte 345 can be set to a value ranging from 00h to FFh. The command arguments 346 (e.g., reliable write or forced program request), the command start address 348, and the command block count 349 can be set to values according to the e.MMC protocol.

[0035] In some embodiments, the command descriptor block can include any number of bytes, such as less than 32 bytes. For example, when some information such as command priority, command tag, task attributes, command arguments, and / or block count, among other information, is included in the queued command request, the command descriptor block can include less than 32 bytes.

[0036] Figure 4A FIG. D illustrates an example of a method for executing commands in a command queue in a memory system 404 according to some embodiments of the present disclosure. In Figure 4AIn one embodiment, once the host 402 has sent one or more commands to the command queue in the memory system 404, the host 402 can send a prepare transfer command 450 (e.g., CMD 44) to the memory system 404 when the host 402 is ready to transmit or receive data. The memory system 404 can send a data transfer request 452-0 to the host 402 in response to receiving the prepare transfer command 450. The data transfer request 452-0 can correspond to the command in the command queue that is ready for execution next. In several embodiments, if the memory system 404 is not ready to send or receive data, the data transfer request can provide a negative response and not request a data transfer. In several embodiments, the data transfer request can be delivered using command / response signals and not using the data bus. The data transfer request 452-0 can include a direction bit that indicates the direction of data transfer when executing the command. For example, a direction bit set to 1 indicates that the command is a write command where data is sent from the host to the memory system. The data transfer request 452-0 can include a command tag field to identify which command from the command queue is being executed and can also include a data offset field and a data size field to indicate which portions of data should be transferred. In Figure 4A In one embodiment, the data transfer request 452-0 sent in response to receiving the prepare transfer command includes a direction bit set to 0 indicating that the command is a read command where data is sent from the memory system to the host. The direction bit set to 0 in the data transfer request 452-0 allows the memory system 404 to maintain control of the bus and send the read data 454 requested in the command from the memory system 404 to the host 402. The memory system 404 remains in the send data state when the direction bit of the data transfer request is set to 0, therefore, in several embodiments, the data transfer request with the direction bit set to 0 does not cause a state change in the memory system 404. In several embodiments, the memory system can be configured such that when the memory system 404 sends a data transfer request with the direction bit set to 0, the memory system 404 remains in the send data state.

[0037] In Figure 4BOnce host 402 has sent one or more commands to the command queue in memory system 404, host 402 can send a readiness to transmit command 450 (e.g., CMD 44) to memory system 404 when host 402 is ready to transmit or receive data. Memory system 404 may send a data transfer request 452-1 to host 402 in response to receiving readiness to transmit command 450. Data transfer request 452-1 includes direction bits indicating the direction of data transfer during command execution. In some embodiments, if memory system 404 is not ready to transmit or receive data, the data transfer request may provide a negative response and not request data transfer. In some embodiments, the data transfer request may be delivered using command / response signals and not using a data bus. Figure 4B In the data transfer request 452-1 sent in response to receiving a readiness to transfer command, a direction bit set to 1 corresponding to a write command is included. The data transfer request 452-1 may include a command flag field to identify which command from the command queue is being executed, and may also include a data offset field and a data size field to indicate which portions of the data should be transferred. The direction bit set to 1 in the data transfer request 452-1 allows the host 402 to control the bus and send the requested write data 456 from the host 402 to the memory system 404. The memory system 404 transitions from a data transmission state to a data reception state when the direction bit of the data transfer request 452-1 is set to 1. In some embodiments, the state machine of the memory system may be configured such that when the memory system 404 sends a data transfer request with the direction bit set to 1, the memory system 404 changes from a data transmission state to a data reception state.

[0038] exist Figure 4C Once host 402 has sent one or more commands to the command queue in memory system 404, host 402 can send a readiness to transmit command 450 (e.g., CMD 44) to memory system 404 when host 402 is ready to transmit or receive data. Memory system 404 can respond to host 402 with a data transfer request 452-0 in response to receiving readiness to transmit command 450, the data transfer request 452-0 including direction bits indicating the direction of data transfer during command execution. In some embodiments, if memory system 404 is not ready to transmit or receive data, the data transfer request can provide a negative response and not request data transfer. In some embodiments, the data transfer request can be delivered using command / response signals and not using a data bus. Figure 4CIn one embodiment, the data transfer request 452-0 sent in response to receiving the prepare to transfer command 450 contains a direction bit set to 0 corresponding to a read command. The data transfer request 452-0 can contain a command tag field to identify which command from the command queue is being executed and can also contain a data offset field and a data size field to indicate which portions of data should be transferred. The host 402 sends a send data command 458 (e.g., CMD 47) to the memory system 404 in response to receiving the data transfer request 452-0 with the direction bit set to 0. The send data command 458 requests the memory system 404 to send data to the host 402, so the memory system 404 transitions from the transfer state to the send data state and the memory system 404 takes control of the bus and sends the read data 454 requested in the command from the memory system 404 to the host 402. When all the data has been transferred, the memory system 404 moves back from the send data state to the transfer state. In several embodiments, the state machine of the memory system can be configured such that the memory system 404 changes from the send data state to the transfer state after sending the transfer data request 452-0 and then changes from the transfer state to the send data state when the memory system 404 receives the send data command 458 from the host.

[0039] In Figure 4D In one embodiment, once the host 402 has sent one or more commands to the command queue in the memory system 404, the host 402 can send a prepare to transfer command 450 (e.g., CMD 44) to the memory system 404 when the host 402 is ready to transmit or receive data. The memory system 404 can send a data transfer request 452-1 to the host 402 in response to receiving the prepare to transfer command 450, the data transfer request 452-1 containing a direction bit to indicate the direction of data transfer during execution of the command. In several embodiments, if the memory system 404 is not ready to send or receive data, the data transfer request can provide a negative response and not request data transfer. In several embodiments, the data transfer request can be delivered using command / response signals and not using the data bus. In Figure 4DIn particular embodiments, the data transfer request 452-1 sent in response to receiving the prepare to transfer command 450 contains a direction bit set to one corresponding to a write command. The data transfer request 452-1 can contain a command tag field to identify which command from the command queue is being executed and can also contain a data offset field and a data size field to indicate which portions of data should be transferred. The host 402 sends a receive data command 460 (e.g., CMD 46) to the memory system 404 in response to receiving the data transfer request 452-1 with the direction bit set to one. The receive data command 460 indicates to the memory system 404 that the memory system 404 is to receive data from the host 402, so the memory system 404 transitions from the transfer state to a receive data state and the memory system 404 allows the host 402 to control the bus and sends the write data 456 requested in the command from the host 402 to the memory system 404. When all the data has been transferred, the memory system 404 moves from the receive data state back to the transfer state.

[0040] In several embodiments, the state machine of the memory system can be configured such that the memory system 404 changes from the send data state to the transfer state after sending the transfer data request and then changes from the transfer state to the receive data state when the memory system 404 receives the receive data command 460 from the host 402.

[0041] In several embodiments, when an error is raised during execution of a command, the command fails. The memory system can respond to additional queued command requests from the host with a command response having an error bit indicating that there was an error during execution of the command. The host can also query the memory system with a task management function request command to receive updates on the status of commands in the command queue.

[0042] Figure 5 An example of a data transfer request header 552 included in a data transfer request is illustrated in accordance with several embodiments of the present application. In Figure 5In some embodiments, the data transfer request header 552 includes several fields that provide information associated with the command so that the command can be identified by the host and executed by the host and memory device. For example, the data transfer request header can include 32 bits and other numbers of bits. The data transfer request header 552 includes 32 bytes, where bytes 0 to byte 1 are reserved, byte 2 is associated with the transfer direction 551, byte 3 is associated with the command task tag 545, bytes 4 to byte 11 are reserved, bytes 12 to byte 13 are associated with the data buffer offset 553, bytes 14 to byte 15 are associated with the command transfer length 555, and bytes 16 to byte 31 are reserved. The transfer direction 551 byte can be set to a value 00h corresponding to a read command. The transfer direction 551 byte can be set to a value Oh corresponding to a write command. The command task tag 545 byte can correspond to a unique identifier used to distinguish and identify the command from other commands to be executed in the command queue. The command task tag 545 byte can be set to a value ranging from 00h to FFh. The data buffer offset 553 can be an offset of the data transfer within the full data transfer of the task. The data transfer request header 552 can be composed of any number of bytes. For example, when the data transfer request is delivered using the command / response signal, the data transfer request can be composed of less than 32 bytes, even though the same fields as previously described are included.

[0043] Figure 6 FIG. 1 illustrates an example of a method for command queuing and command execution in a memory system, in accordance with some embodiments of the present disclosure. Figure 6 The method illustrated in FIG. 1 includes several commands being executed simultaneously, where commands and command responses are sent between the host and the memory system on the command line, while data associated with the commands is transferred between the memory system and the host on the data bus. Thus, in some embodiments, the data bus can be controlled by the host or the memory system based on the commands sent on the command line and the data bus can be used to transfer data between the host and the memory device while commands are sent on the command line. For example, a command can be added to the command queue via a command sent between the host and the memory system, while data associated with the command in the command queue is sent on the data bus between the host and the memory system.

[0044] In Figure 6 In some embodiments, a first queued command request 640-1 (e.g., CMD 43) associated with a first command 647-1 is sent from the host 602 to the memory system 604. The first command 647-1 is a 4KB read command. In response, the memory system 604 can send a command response (not shown) and the host 602 can send a command block descriptor for the first command (not shown), so that the first command 647-1 can be added to the command queue.

[0045] A second queued command request 640-2 (e.g., CMD 43) associated with a second command 647-2 is sent from the host 602 to the memory system 604. The second command 647-2 is a 16 KB write command. In response, the memory system 604 can send a command response (not shown) and the host 602 can send a command block descriptor (not shown) for the second command, so the second command 647-2 can be added to the command queue. The command queue now has two commands: the first command 647-1 ready for execution and the second command 647-2.

[0046] A prepare transfer command 650-1 (e.g., CMD 44) is sent from the host 602 to the memory system 604 on the command line 605. In Figure 6 In the interim, the memory system 604 is not ready to execute the command and sends a command response to the host 602 indicating this. After a period of time, the host 602 then sends the prepare transfer command 650-1 (e.g., CMD 44) again to the memory system 604. The memory system 604 responds to the prepare transfer command 650-1 with a data transfer request 652-1 identifying the command, a 4 KB read command 647-1, and a data transfer direction. The host 602 sends a send data command 658-1 (e.g., CMD 47) in response to receiving the data transfer request 652-1, causing the memory system 604 to take control of the data bus 606 and send the 4 KB of data 657-1 associated with the first command 647-1.

[0047] When the 4KB of data associated with the first command 647-1 is sent from the memory system 604 to the host 602 on the data bus 606, the ready-to-transfer command 650-2 (e.g., CMD 44) and a third queued command request 640-3 (e.g., CMD 43) associated with the third command 647-3 are sent from the host 602 to the memory system 604 on the command line 605. The third command 647-3 is added to the command queue when the memory system 604 sends a command response (not shown) for the third queued command request 640-3 and the host 602 can send a command block descriptor (not shown) for the third command so the third command 647-3 can be added to the command queue. The memory system 604 responds to the ready-to-transfer command 650-2 with a data transfer request 652-2 that identifies the second command 647-2, a 16KB write command, a direction of data transfer, and a portion of data to be transferred (e.g., a data offset and a data size). The host 602 sends a receive data command 660-2 (e.g., CMD 46) in response to receiving the data transfer request 652-2, causing the host 602 to take control of the data bus 606 and send 8KB of data 657-2 associated with the second command 647-2 to the memory system 604.

[0048] When the 8KB of data associated with the second command 647-2 is sent from the host 602 to the memory system 604 on the data bus 606, a ready-to-transfer command 650-3 (e.g., CMD 44) is sent from the host 602 to the memory system 604 on the command line 605. The memory system 604 responds to the ready-to-transfer command 650-3 by sending a data transfer request 652-3 on the command line 605 that identifies the third command 647-3, an 8KB read command, and a direction of data transfer. The priority indicated in the third command 647-3 is higher than the priority of the command 647-2, so the command 647-3 is executed next and execution of the second command 647-2 is paused while the third command is executed (e.g., where only 8KB of the 16KB associated with the second command 647-2 is sent from the host 602 to the memory system 604). The host 602 sends a send data command 658-3 (e.g., CMD 47) in response to receiving the data transfer request 652-3, causing the memory system 604 to take control of the data bus 606 and send 8KB of data 657-3 associated with the third command 647-3.

[0049] A fourth queued command request 640-4 (e.g., CMD 43) associated with a fourth command 647-4 is sent from the host 602 to the memory system 604. The fourth command 647-4 is an 8KB read command. In response, the memory system 604 can send a command response (not shown) and the host 602 can send a command block descriptor (not shown) for the fourth command, so the fourth command 647-4 can be added to the command queue. The command queue now has three commands: the second command 647-2 that has been partially executed, the third command 647-3 that is executing, and the fourth command 647-4 that is ready for execution.

[0050] As the 8KB data associated with the third command 647-3 is sent from the memory system 604 to the host 602 on the data bus 606, a prepare transfer command 650-2 (e.g., CMD 44) is again sent from the host 602 to the memory system 604 on the command line 605, so that execution of the second command 647-2 can resume. The memory system 604 responds to the prepare transfer command 650-2 with a data transfer request 652-2 that identifies the second command 647-2, the 16KB write command, the direction of data transfer, and the portion of data to be transferred (e.g., data offset and data size). The host 602 sends a receive data command 660-2 (e.g., CMD 46) in response to receiving the data transfer request 652-2, causing the host 602 to take control of the data bus 606 and send the 8KB data 657-2 associated with the second command 647-2 to the memory system 604 to complete execution of the second command 647-2.

[0051] As the 8KB data associated with the second command 647-2 is sent from the host 602 to the memory system 604 on the data bus 606, a prepare transfer command 650-4 (e.g., CMD 44) is sent from the host 602 to the memory system 604 on the command line 605. The memory system 604 responds to the prepare transfer command 650-4 with a data transfer request 652-4 that identifies the fourth command 647-4, the 8KB read command, and the direction of data transfer. The host 602 sends a send data command 658-4 (e.g., CMD 47) in response to receiving the data transfer request 652-4, causing the memory system 604 to take control of the data bus 606 and send the 8KB data 657-4 associated with the fourth command 647-4.

[0052] The host 602 sends prepare transfer commands 650-5 and 650-6 to the memory system 604, but the command queue is empty, so the memory system 604 sends a command response (not shown) to the host 602 indicating that the command queue is empty and / or the memory system 604 does not send a data transfer request in response to the commands 650-5 and 650-6.

[0053] While specific embodiments have been illustrated and described herein, it will be appreciated that various arrangements can be substituted for the specific embodiments shown and described without departing from the spirit and scope of the disclosure. This disclosure is intended to cover any and all adaptations or variations of various embodiments of the application. It is to be understood that the above description is intended to be illustrative and not restrictive. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of ordinary skill in the art upon reviewing the above description. The scope of the application includes other applications and uses of the above-described structures and methods. The scope of the application should be determined, therefore, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of patents and scientific articles herein are hereby incorporated by reference in their entirety.

[0054] In the foregoing Detailed Description, some features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the disclosed embodiments require more features than are explicitly recited in each claim. Rather, inventive subject matter can lie in fewer than all features of a single disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this Detailed Description, with each claim acting as a separate embodiment of the application.

Claims

1. A method for command queuing, comprising: receiving, at a memory device from a host, a first queued command request associated with a first command to be queued at the memory device; sending a first response to the first queued command request from the memory device to the host, wherein the first response indicates that the memory device is ready to add the first command to a command queue; receiving, at the memory device from the host, the first command in response to receiving the first response, wherein the first command comprises a command descriptor block; receiving, by the memory device from the host, a ready-to-transfer command to indicate that the host is ready to send or receive data requested in the first command; sending a data transfer request from the memory device to the host in response to the ready-to-transfer command; and transferring data to or reading data from the memory device in response to sending the data transfer request.

2. The method of claim 1, wherein the command descriptor block has priority information for the first command.

3. The method of claim 2, wherein the priority information includes a parameter indicating that the first command is to be placed in a command queue with an execution highest priority.

4. The method of claim 2, wherein the priority information includes a parameter indicating that the first command is to be placed in the command queue with an execution time sequence priority.

5. The method of claim 2, wherein the priority information includes a parameter indicating that the first command is to be placed in a command queue without an execution priority.

6. The method of claim 1, wherein the command descriptor block of the first command has a command operation code, priority information, a task tag, command arguments, a start address, and a block count.

7. The method of claim 1, wherein the method includes receiving the first command at the memory device when the memory device is in a transfer state.

8. The method of claim 1, wherein the method includes causing the memory device to change from a transfer state to a receive state in response to sending the data transfer request.

9. The method of claim 1, wherein the method includes command queuing using an embedded multimedia card (e.MMC) protocol.

10. An apparatus for command queuing, comprising: a controller; and a memory device coupled to the controller, wherein the apparatus is configured to: receive a first queued command request associated with a first command to be queued at the memory device; send a first response to the first queued command request from the memory device to a host, wherein the first response indicates that the memory device is ready to add the first command to a command queue; receive the first command in the command queue in response to sending the first response, wherein the first command comprises a command descriptor block; receive a ready-to-transfer command to indicate that the host is ready to send or receive data requested in the first command; send a data transfer request from the memory device to the host in response to the ready-to-transfer command; and transfer data to or read data from the memory device in response to sending the data transfer request. sending a data transfer request from the memory device to the host; and transmitting data to or reading data from the memory device in response to sending the data transfer request from the memory device to the host.

11. The apparatus of claim 10, wherein the apparatus is configured to receive a receive data command from the host at the controller in response to sending the data transfer request with the first direction bit indicating the data transfer to the memory device; transitioning from the transfer state to a receive data state; and receiving the data from the host at the device.

12. The device of claim 10, wherein device is configured to receive a send data command from the host at the controller in response to sending the data transfer request with the second direction bit indicating reading data from the memory device, transition from the transfer state to a send data state, and send the data from the memory device to the host.

13. The device of claim 10, wherein the device is configured to receive a task management function request command from the host and send a status of each of a number of commands in a command queue to the host.

14. The device of claim 10, wherein the device is configured to receive a task management function request command from the host and abort each of a number of commands in a command queue.

15. A method for command queuing, comprising: receiving, at a memory device from a host, a first queued command request associated with a first command to be queued at the memory device; sending a first response to the first queued command request from the memory device to the host, wherein the first response indicates that the memory device is ready to add the first command to a command queue; in response to receiving the first response, receiving, at the memory device from the host, the first command in the command queue, wherein the first command comprises a first command descriptor block; receiving, by the memory device from the host, a first ready-to-transfer command to indicate that the host is ready to send or receive data requested in the first command; sending a first data transfer request from the memory device to the host in response to the first ready-to-transfer command; transmitting data to or reading data from the memory device in response to sending the first data transfer request; receiving, at the memory device from the host, a second queued command request associated with a second command to be queued at the memory device; and sending a second response to the second queued command request from the memory device to the host, wherein the second response indicates that the memory device is ready to add the second command to the command queue; in response to receiving the second response, receiving, at the memory device from the host, the second command, wherein the second command comprises a second command descriptor block; receiving, by the memory device from the host, a second ready-to-transfer command to indicate that the host is ready to send or receive data requested in the second command; sending a second data transfer request from the memory device to the host in response to the second ready-to-transfer command; and transmitting data to or reading data from the memory device in response to sending the second data transfer request. transmitting data to or reading data from the memory device in response to transmitting the second data transfer request.

16. The method of claim 15, further comprising interrupting execution of the first command and executing the second command in response to placing the second command in the command queue using a parameter indicating that the second command is placed in the command queue with a highest priority for execution.

17. The method of claim 15, wherein the second data transfer request includes a data packet having information that allows command execution on the host and memory device.

18. The method of claim 15, wherein the method includes receiving the second command from the host on a command line at the memory device while executing the first command via a data transfer on a data bus.

19. The method of claim 15, the method including resuming execution of the first command after execution of the second command has begun.

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