Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area and a non-display area; a reference voltage supply line disposed in the non-display area and transmitting a reference voltage; and a driving voltage supply line disposed in the non-display area and transmitting a driving voltage. The reference voltage supply line includes a straight portion and a curved portion. The straight portion extends in a first direction, the curved portion extends from the straight portion to be curved, and the curved portion of the reference voltage supply line is disposed along the periphery of the display area.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0033123, filed with the Korean Intellectual Property Office on Mar. 22, 2019, the disclosure of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Exemplary embodiments of the inventive concept relate to a display device having stacked semiconductor layers. BACKGROUND ART

[0003] Recently, display devices such as organic light emitting diode (OLED) displays and liquid crystal display devices have been increasingly used. OLED displays have a self-emitting characteristic. The OLEDs of the OLED displays include two electrodes and an organic emission layer disposed therebetween, wherein electrons injected from one electrode (e.g., a cathode) and holes injected from the other electrode (e.g., an anode) are combined in the organic emission layer to generate excitons, and the excitons release energy to emit light.

[0004] In addition to the self-emitting characteristic that obviates the need for a separate light source, OLED displays also have high brightness characteristics and low operating voltage characteristics, and have an unrestricted viewing angle. SUMMARY OF THE INVENTION

[0005] According to an exemplary embodiment of the inventive concept, a display device includes: a substrate including a display area and a non-display area; a reference voltage supply line disposed in the non-display area and transmitting a reference voltage; and a driving voltage supply line disposed in the non-display area and transmitting a driving voltage. The reference voltage supply line includes a straight portion extending in a first direction and a curved portion extending from the straight portion to be curved, and the curved portion of the reference voltage supply line is disposed along a periphery of the display area.

[0006] The display device may further include a reference voltage connection line extending from the reference voltage supply line in a second direction intersecting the first direction and a reference voltage line extending in the second direction in the display area. The reference voltage line may be electrically connected to the reference voltage connection line through an opening.

[0007] The display device may further include a driving voltage connection line extending from the driving voltage supply line in the second direction and a driving voltage line extending in the second direction in the display area. The driving voltage line may be electrically connected to the driving voltage connection line through an opening.

[0008] The display device may further include an oxide semiconductor transistor including an oxide semiconductor layer and a polycrystalline semiconductor transistor including a polycrystalline semiconductor layer.

[0009] The display device may further include a driving transistor. The driving transistor may be an oxide semiconductor transistor, and a gate electrode of the driving transistor may be disposed on the same layer as the reference voltage supply line.

[0010] The display device may further include a flexible printed circuit substrate connected to the substrate. The reference voltage supply line and the driving voltage supply line may be disposed between the flexible printed circuit substrate and the display area.

[0011] The display device may further include a gate driver disposed in the non-display area, an initialization voltage supply line extending in the non-display area in a second direction, a gate signal output terminal connected to the gate driver, and a gate signal connection line connected to the gate signal output terminal through an opening. The initialization voltage supply line may be disposed on the same layer as the gate signal connection line.

[0012] Pixels adjacent to a curved portion of the reference voltage supply line may be arranged in a stepped shape.

[0013] The gate driver and the driving voltage supply line may be bent in the same direction as the curved portion of the reference voltage supply line in a region adjacent to the curved portion of the reference voltage supply line.

[0014] According to an exemplary embodiment of the inventive concept, a display device includes: a substrate including a display area and a non-display area; a buffer layer disposed on the substrate; a polycrystalline semiconductor layer disposed on the buffer layer; a lower gate insulating layer and a lower gate conductive layer disposed on the polycrystalline semiconductor layer; an oxide semiconductor layer disposed on the lower gate insulating layer; an upper gate insulating layer disposed on the oxide semiconductor layer; an upper gate conductive layer disposed on the upper gate insulating layer; an interlayer insulating layer disposed on the upper gate conductive layer; and a first data conductive layer disposed on the interlayer insulating layer. The upper gate conductive layer includes a reference voltage supply line and a reference voltage connection line disposed in the non-display area and transmitting a reference voltage, and a gate electrode of a driving transistor disposed in the display area.

[0015] The first data conductive layer may include a driving voltage supply line and a driving voltage connection line transmitting a driving voltage in the non-display area.

[0016] The reference voltage supply line may include a straight portion extending in a first direction in a plan view and a curved portion extending curved from the straight portion.

[0017] The lower gate insulating layer may include a first gate insulating layer and a second gate insulating layer disposed on the lower gate conductive layer, and the lower gate conductive layer may include an initialization voltage line transmitting an initialization voltage and a light emission control line transmitting a light emission control signal.

[0018] The upper gate conductive layer may further include a gate line for transmitting a gate signal, a voltage control line for transmitting a voltage control signal, and an initialization control line for transmitting an initialization control signal.

[0019] The oxide semiconductor layer may include a first oxide semiconductor layer and a second oxide semiconductor layer separated on the same layer.

[0020] The display device may further include a second transistor, a third transistor, and a fourth transistor. The second transistor may include a channel disposed in the second oxide semiconductor layer overlapping with the gate line, a first electrode of the second transistor may be connected to a data line for transmitting a data voltage, the third transistor may include a channel disposed in the second oxide semiconductor layer overlapping with the voltage control line, the fourth transistor may include a channel disposed in the first oxide semiconductor layer overlapping with the initialization control line, and a first electrode of the fourth transistor may be connected to an initialization voltage line.

[0021] The display device may further include a fifth transistor, the fifth transistor may include a channel disposed in the polycrystalline semiconductor layer overlapping with a light emission control line, and a first electrode of the fifth transistor may be connected to a drive voltage line for transmitting a drive voltage.

[0022] The display device may further include a reference voltage line for transmitting a reference voltage in a display area, and the first data conductive layer may include the reference voltage line.

[0023] The display device may further include a passivation layer disposed on the first data conductive layer and a second data conductive layer disposed on the passivation layer. The second data conductive layer may include a gate signal connection line and a data line, the gate signal connection line is disposed in a non-display area and transmits a gate signal from a gate driver.

[0024] The polycrystalline semiconductor layer and the first oxide semiconductor layer may be electrically connected through a connection member.

[0025] According to an exemplary embodiment of the inventive concept, a display device includes a rounded region, wherein the rounded region includes a display area and a non-display area. The rounded region includes: pixels arranged in a stepped shape and disposed in the display area; a gate driver having a curved form in the non-display area and including a plurality of stages attached and arranged along the circumference of the rounded region and configured to transmit a gate signal to the pixels; an initialization voltage supply line having a curved form in the non-display area and configured to transmit an initialization voltage to the pixels; a drive voltage supply line having a curved form in the non-display area and configured to transmit a drive voltage to the pixels; and a reference voltage supply line having a curved form in the non-display area and configured to transmit a reference voltage to the pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic top plan view of a display device according to an exemplary embodiment of the inventive concept.

[0027] Figure 2 is according to an exemplary embodiment of the inventive concept Figure 1 an enlarged top plan view of region A of.

[0028] Figure 3 is according to an exemplary embodiment of the inventive concept along Figure 2 a cross-sectional view taken along line III-III'.

[0029] Figure 4 is according to an exemplary embodiment of the inventive concept along Figure 2 a cross-sectional view taken along line IV-IV'.

[0030] Figure 5 is an equivalent circuit diagram of a pixel of a display device according to an exemplary embodiment of the inventive concept.

[0031] Figure 6 is a timing diagram of signals applied to a pixel of a display device according to an exemplary embodiment of the inventive concept.

[0032] Figure 7 is a layout diagram of a pixel region of a display device according to an exemplary embodiment of the inventive concept.

[0033] Figure 8 is according to an exemplary embodiment of the inventive concept along Figure 7 a cross-sectional view taken along line VIII-VIII'. DETAILED DESCRIPTION

[0034] Exemplary embodiments provide a display device in which luminance uniformity is maintained without luminance degradation of some pixels and its display quality is improved.

[0035] Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout this application, like reference numerals may indicate like elements.

[0036] In addition, in the drawings, for better understanding and ease of description, the dimensions and thicknesses of each element are arbitrarily shown, and the inventive concept is not limited thereto. In addition, for clarity, the thicknesses of layers, films, panels, regions (region or area), etc. may be exaggerated.

[0037] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there can also be an intermediate element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediate element. In addition, in the specification, the terms "on" or "above" mean located on or below the target portion, and do not necessarily mean located on the upper side of the target portion based on the direction of gravity.

[0038] In addition, throughout the specification, the phrase "plan view" means observing the target portion from the top, and the phrase "cross-sectional view" means observing the cross-section formed by vertically cutting the target portion from the side.

[0039] Figure 1 is a schematic top plan view of a display device according to an exemplary embodiment of the inventive concept. Refer to Figure 1 , the display device 10 includes a display panel 100 and a flexible printed circuit substrate 500.

[0040] The display panel 100 includes a substrate 110. The substrate 110 can be a flexible substrate that can be bent or twisted. The edge of the substrate 110 has a circular arc shape. In other words, the edge of the substrate 110 is a smooth curve. The substrate 110 includes a display area DA for displaying an image and a non-display area NA for the remaining area. In addition, the substrate 110 includes a rounded area RA provided with rounded edges. However, it is not limited thereto, and the rounded area RA can be an area where the edge of the display area DA is a curve, regardless of the shape of the substrate 110.

[0041] A plurality of signal lines and pixels PX connected to the plurality of signal lines are provided in the display area DA. The plurality of signal lines include gate lines 121, an initialization voltage line 127, data lines 171, a driving voltage line 175, and a reference voltage line 176. The pixel PX is the smallest unit for presenting an image, and the display device 10 can display an image through the pixel PX.

[0042] The gate lines 121 and the initialization voltage line 127 extend in a first direction x in the display area DA. The gate lines 121 transmit gate signals, and the initialization voltage line 127 transmits an initialization voltage. The data lines 171, the driving voltage line 175, and the reference voltage line 176 extend in a second direction y in the display area DA. The data lines 171 transmit data voltages corresponding to image signals, the driving voltage line 175 transmits a driving voltage, and the reference voltage line 176 transmits a reference voltage.

[0043] A common voltage supply line 740, a gate driver 400, an initialization voltage supply line 40, a driving voltage supply line 50, and a reference voltage supply line 60 are provided in the non-display area NA.

[0044] A common voltage supply line 740 is disposed along an edge of the substrate 110 and applies a common voltage to the pixels PX.

[0045] The gate driver 400 receives gate control signals to generate gate signals. The gate driver 400 is connected to the gate lines 121, and thus transmits the gate signals to the pixels PX through the gate lines 121. The gate driver 400 may be directly formed in the non-display area NA of the display panel 100 together with electrical devices such as thin film transistors in the display area DA through the same process.

[0046] The gate driver 400 includes a first gate driver 400a and a second gate driver 400b, which are respectively disposed on two opposite sides of the non-display area NA with respect to the display area DA. However, it is not limited thereto, and the gate driver 400 may be disposed on only one side with respect to the display area DA. The first gate driver 400a is connected to a plurality of first control signal lines SL1 to receive gate control signals, and the second gate driver 400b is connected to a plurality of second control signal lines SL2 to receive gate control signals.

[0047] The first gate driver 400a and the second gate driver 400b extend in the second direction y on the respective sides of the non-display area NA and extend to the rounded area RA. In the rounded area RA, the first gate driver 400a and the second gate driver 400b may be bent along the periphery of the display area DA. Thus, they may be connected to the pixels PX via both ends of the gate lines 121.

[0048] The first gate driver 400a and the second gate driver 400b may include a plurality of stages ST arranged in the second direction y (see Figure 2 ), and a detailed description thereof is provided below.

[0049] The initialization voltage supply line 40 includes a first initialization voltage supply line 40a disposed on one side of the non-display area NA and a second initialization voltage supply line 40b disposed on the other side of the non-display area NA. However, it is not limited thereto, and the initialization voltage supply line 40 may be disposed on only one side of the display area DA.

[0050] The first initialization voltage supply line 40a and the second initialization voltage supply line 40b extend along the second direction y on the respective sides of the non-display area NA and extend into the rounded area RA. The initialization voltage supply line 40 is connected to the initialization voltage line 127 to transmit the initialization voltage. The initialization voltage supply line 40 may be disposed between the gate driver 400 and the display area DA. Specifically, the first initialization voltage supply line 40a is disposed between the first gate driver 400a and the display area DA, and the second initialization voltage supply line 40b is disposed between the second gate driver 400b and the display area DA. However, the position of the initialization voltage supply line 40 is not limited thereto.

[0051] The driving voltage supply line 50 is disposed on the side of the substrate 110 on which the flexible printed circuit substrate 500 is disposed and extends along the first direction x. In addition, the driving voltage supply line 50 extends along the edge of the substrate 110 or the edge of the display area DA and is also disposed in the rounded area RA. Both ends of the driving voltage supply line 50 have a rounded and curved line shape, and the driving voltage supply line 50 forms a loop with one side open. In other words, the driving voltage supply line 50 includes a straight portion that extends linearly on a plane and curved portions that are disposed at both ends of the straight portion. The curved portions are disposed in the rounded area RA. The driving voltage supply line 50 is disposed along the periphery of the display area DA and thus along the rounded corners of the display area DA. The driving voltage supply line 50 is connected to the driving voltage line 175 to transmit the driving voltage. Both ends of the straight portion of the driving voltage supply line 50 include curved portions; however, a curved portion may be included only at one end of the straight portion of the driving voltage supply line 50.

[0052] The reference voltage supply line 60 is disposed on the side of the substrate 110 on which the flexible printed circuit substrate 500 is disposed and extends along the first direction x. The reference voltage supply line 60 may be substantially parallel to the driving voltage supply line 50. In addition, the reference voltage supply line 60 extends along the edge of the substrate 110 or the edge of the display area DA and is also disposed in the rounded area RA. Both ends of the reference voltage supply line 60 have a rounded and curved line shape, and the reference voltage supply line 60 forms a loop with one side open. In other words, the reference voltage supply line 60 includes a straight portion that extends linearly and curved portions that are disposed at both ends of the straight portion. The curved portions are disposed in the rounded area RA. The reference voltage supply line 60 is disposed along the periphery of the display area DA and thus along the rounded corners of the display area DA. The reference voltage supply line 60 is connected to the reference voltage line 176 to transmit the reference voltage. Even though it has been described that the curved portions are disposed at both ends of the straight portion of the reference voltage supply line 60, a curved portion may be disposed only at one end of the straight portion of the reference voltage supply line 60.

[0053] The flexible printed circuit substrate 500 can be bent, and one end of the flexible printed circuit substrate 500 is electrically connected to a plurality of signal lines of the display panel 100. The flexible printed circuit substrate 500 includes a data driver IC 550 that generates data voltages as gray voltages corresponding to input image signals. The data voltages generated from the data driver IC 550 are transmitted to the data lines 171 of the display panel 100. However, different from that shown, the data driver may alternatively be mounted in the non-display area NA of the display panel 100 in the form of an integrated circuit chip.

[0054] Now refer to Figures 2 to 4 The rounded region RA of the display device according to an exemplary embodiment of the inventive concept will be described in detail.

[0055] Figure 2 is an enlarged top plan view of region A according to an exemplary embodiment of the inventive concept Figure 1 of the display device.

[0056] Pixels PX disposed in the rounded region RA of the display device according to the exemplary embodiment may be arranged in a stepped shape. However, the arrangement shape of the pixels PX is not limited to that shown in Figure 2 . In Figure 2 , the pixels PX are arranged in lines in a first direction x and a second direction y. However, the arrangement of the pixels PX is not limited thereto, and the pixels PX may be arranged differently.

[0057] The first gate driver 400a in the non-display area NA includes a plurality of stages ST. The plurality of stages ST may be arranged in a line along the direction in which the first gate driver 400a extends. In other words, the plurality of stages ST may be arranged along the circumference of the rounded region RA. The plurality of stages ST may be connected in an attached manner. The plurality of stages ST may receive gate control signals through Figure 1 the first control signal line SL1 to sequentially generate gate signals.

[0058] The gate signal output terminal 123 connected to the stage ST and the gate signal connection line 122 connected to the gate signal output terminal 123 through the opening 33 are disposed in the non-display area NA. The gate signals generated from the stage ST are transmitted to the gate signal output terminal 123 and then to the gate signal connection line 122.

[0059] The gate signal connection line 122 and the gate line 121 disposed in the display area DA are connected through the opening 34. Accordingly, the gate signals transmitted to the gate signal connection line 122 are transmitted to the gate line 121. The opening 34 where the gate signal connection line 122 and the gate line 121 are connected may be disposed adjacent to the display area DA in the non-display area NA; however, the opening 34 may also be disposed in the display area DA.

[0060] The first initialization voltage supply line 40a is bent in a curved form in the rounded region RA. The first initialization voltage supply line 40a is connected to an initialization voltage connection line 41 extending in the first direction x. The initialization voltage connection line 41 may be a portion extending from the initialization voltage supply line 40 in the first direction x. In other words, the initialization voltage supply line 40 and the initialization voltage connection line 41 may be provided on the same layer. The initialization voltage connection line 41 is connected to the initialization voltage line 127 through an opening 35. Therefore, the initialization voltage can be transmitted to the initialization voltage line 127 through the initialization voltage supply line 40 and the initialization voltage connection line 41.

[0061] The opening 35 where the initialization voltage connection line 41 and the initialization voltage line 127 are connected may be provided adjacent to the display region DA in the non-display region NA; however, it is not limited thereto, and the opening 35 may be provided within the display region DA. The first initialization voltage supply line 40a, the initialization voltage connection line 41, and the gate signal connection line 122 may all be provided on the same layer.

[0062] The drive voltage supply line 50 is provided in the rounded region RA and is bent in a curved form. The drive voltage supply line 50 is connected to a drive voltage connection line 51 extending in the second direction y. The drive voltage connection line 51 may be a portion extending from the drive voltage supply line 50 in the second direction y. In other words, the drive voltage supply line 50 and the drive voltage connection line 51 may be provided on the same layer. The drive voltage connection line 51 is connected to the drive voltage line 175 through an opening 31. Therefore, the drive voltage can be transmitted to the drive voltage line 175 via the drive voltage supply line 50 and the drive voltage connection line 51. The opening 31 where the drive voltage line 175 and the drive voltage connection line 51 are connected may be provided adjacent to the display region DA in the non-display region NA. However, it is not limited thereto, and the opening 31 may be provided in the display region DA.

[0063] The reference voltage supply line 60 is provided to be bent in a curved form in the rounded region RA. The reference voltage supply line 60 is connected to a reference voltage connection line 61 extending in the second direction y. The reference voltage connection line 61 may be a portion extending from the reference voltage supply line 60 in the second direction y. In other words, the reference voltage supply line 60 and the reference voltage connection line 61 may be provided on the same layer. The reference voltage connection line 61 is connected to the reference voltage line 176 through an opening 30. Therefore, the reference voltage can be transmitted to the reference voltage line 176 through the reference voltage supply line 60 and the reference voltage connection line 61. The opening 30 where the reference voltage line 176 and the reference voltage connection line 61 are connected may be provided adjacent to the display region DA in the non-display region NA; however, it is not limited thereto, and the opening 30 may be provided in the display region DA.

[0064] One end of the data voltage connection line 172 is electrically connected to the flexible printed circuit substrate 500, and the other end is connected to the data line 171 disposed in the display area DA through the opening 32. The data voltage generated at the data driver IC 550 may be transmitted to the pixel PX via the data voltage connection line 172 and the data line 171.

[0065] Figure 3 is a cross-sectional view taken along line III-III' of an exemplary embodiment according to the inventive concept. Figure 2

[0066] Referring to Figure 3 , a buffer layer 111, a lower gate insulating layer 140, and an upper gate insulating layer 144 are disposed on the substrate 110. The lower gate insulating layer 140 includes a first gate insulating layer 141, a second gate insulating layer 142, and a third gate insulating layer 143 stacked in sequence. Hereinafter, the upper gate insulating layer 144 is referred to as a fourth gate insulating layer 144.

[0067] A reference voltage supply line 60 is disposed on the fourth gate insulating layer 144. The reference voltage supply line 60 may be disposed on the same layer as a third gate conductive layer (also referred to as an upper gate conductive layer) to be described later.

[0068] An interlayer insulating layer 160 is disposed on the reference voltage supply line 60. The interlayer insulating layer 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0069] A driving voltage supply line 50 is disposed on the interlayer insulating layer 160. The driving voltage supply line 50 may be disposed on the same layer as a first data conductive layer to be described later.

[0070] A passivation layer 180 is disposed on the driving voltage supply line 50, and a first initialization voltage supply line 40a, an initialization voltage connection line 41, and a gate signal connection line 122 are disposed on the passivation layer 180. The first initialization voltage supply line 40a, the initialization voltage connection line 41, and the gate signal connection line 122 may be disposed on the same layer as a second data conductive layer to be described later.

[0071] Figure 4 is a cross-sectional view taken along line IV-IV' of an exemplary embodiment according to the inventive concept. Referring to Figure 2 , a buffer layer 111 is disposed on the substrate 110, and a first gate insulating layer 141 is disposed on the buffer layer 111. Figure 4

[0072] ​​The data voltage connection line 172 is disposed on the first gate insulating layer 141. The second gate insulating layer 142 and the third gate insulating layer 143 are sequentially disposed on the data voltage connection line 172. Although the data voltage connection line 172 is disposed on the first gate insulating layer 141, the data voltage connection line 172 may be disposed on the second gate insulating layer 142.

[0073] The reference voltage supply line 60 and the reference voltage connection line 61 are disposed on the fourth gate insulating layer 144.

[0074] The interlayer insulating layer 160 is disposed on the reference voltage supply line 60 and the reference voltage connection line 61, and the driving voltage supply line 50 and the driving voltage connection line 51 are disposed on the interlayer insulating layer 160.

[0075] The passivation layer 180 is disposed on the driving voltage supply line 50 and the driving voltage connection line 51, and the first initialization voltage supply line 40a is disposed on the passivation layer 180.

[0076] The common voltage supply line 740, the gate driver 400, the initialization voltage supply line 40, the driving voltage supply line 50, and the reference voltage supply line 60 are disposed in the rounded region RA adjacent to the flexible printed circuit substrate 500. In addition, connection wirings for transmitting signals from the common voltage supply line 740, the gate driver 400, the initialization voltage supply line 40, the driving voltage supply line 50, and the reference voltage supply line 60 to the display region DA are also disposed in the rounded region RA.

[0077] In the case of the display device according to the comparative example, since there are not enough layers to dispose both the voltage supply line and the connection wiring, it is difficult to include the reference voltage supply line 60 in the design. In addition, in the comparative example including the reference voltage supply line 60, since the reference voltage supply line 60 does not extend to the rounded region RA, the reference voltage supply line 60 only includes a straight portion outside the rounded region RA. As a result, the reference voltage is not supplied to the pixels PX disposed at both edges based on the first direction x, and some of the pixels PX not supplied with the reference voltage may have problems such as brightness degradation.

[0078] In the display device according to the exemplary embodiment of the inventive concept, the common voltage supply line 740, the gate signal connection line 122, the initialization voltage supply line 40, the driving voltage supply line 50, and the reference voltage supply line 60 may be disposed on different layers, and the reference voltage supply line 60 may be disposed in the rounded region RA.

[0079] Specifically, since the reference voltage supply line 60 and the reference voltage connection line 61 are disposed between the fourth gate insulating layer 144 and the interlayer insulating layer 160, the reference voltage supply line 60 can extend into the rounded region RA. Accordingly, the reference voltage can be supplied to all the pixels PX in the display region DA, and luminance uniformity can be maintained without causing problems such as luminance degradation of some of the pixels PX.

[0080] Next, refer to Figures 5 to 8 to describe the pixel PX included in the display device according to an exemplary embodiment of the inventive concept.

[0081] Figure 5 is an equivalent circuit diagram of one pixel of the display device according to an exemplary embodiment of the inventive concept, Figure 6 and is a timing diagram of signals applied to one pixel of the display device according to an exemplary embodiment of the inventive concept.

[0082] Refer to Figure 5 . The pixel PX of the display device according to an exemplary embodiment of the inventive concept includes a plurality of signal lines and a plurality of transistors T1, T2, T3, T4, and T5 connected thereto, a storage capacitor Cst, and an organic light emitting diode OLED.

[0083] The plurality of signal lines include a data line 171, a driving voltage line 175, a reference voltage line 176, an initialization voltage line 127, a common voltage line 741, a gate line 121, a voltage control line 152, an initialization control line 153, and a light emission control line 154.

[0084] The data line 171 is a wiring for transmitting a data voltage DATA generated from a data driver, and the luminance emitted from the organic light emitting diode OLED changes according to the data voltage DATA applied to the pixel PX.

[0085] The driving voltage line 175 applies a driving voltage ELVDD, the reference voltage line 176 transmits a reference voltage Vref, the initialization voltage line 127 transmits an initialization voltage Vint for initializing a second storage electrode of the storage capacitor Cst, a second electrode of the driving transistor T1, and an anode of the organic light emitting diode OLED, and the common voltage line 741 applies a common voltage ELVSS to a cathode of the organic light emitting diode OLED. The voltages applied to the driving voltage line 175, the initialization voltage line 127, and the common voltage line 741 may be constant voltages.

[0086] Next, describe the plurality of transistors T1, T2, T3, T4, and T5. The plurality of transistors T1, T2, T3, T4, and T5 include a driving transistor T1 (referred to as a first transistor), a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0087] The driving transistor T1 includes a gate electrode connected to the first storage electrode of the storage capacitor Cst, a first electrode connected to the second electrode of the fifth transistor T5, and a second electrode connected to the anode of the organic light emitting diode OLED. The gate electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3. The second electrode of the driving transistor T1 is also connected to the second electrode of the fourth transistor T4 and the second storage electrode of the storage capacitor Cst. The driving transistor T1 outputs a driving current to the organic light emitting diode OLED according to the data voltage DATA stored in the storage capacitor Cst. The first electrode of the driving transistor T1 is connected to the driving voltage line 175 via the fifth transistor T5.

[0088] The second transistor T2 includes a gate electrode connected to the gate line 121, a first electrode connected to the data line 171, and a second electrode connected to the gate electrode of the driving transistor T1. The second electrode of the second transistor T2 is also connected to the second electrode of the third transistor T3 and the first storage electrode of the storage capacitor Cst. The second transistor T2 has n-type transistor characteristics and is turned on when a gate signal GWn of a high voltage is applied to the gate electrode. When the second transistor T2 is turned on, the data voltage DATA supplied through the data line 171 can be transmitted to the first storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1.

[0089] The third transistor T3 includes a gate electrode connected to the voltage control line 152, a first electrode connected to the reference voltage line 176, and a second electrode connected to the gate electrode of the driving transistor T1. The second electrode of the third transistor T3 is also connected to the second electrode of the second transistor T2 and the first storage electrode of the storage capacitor Cst. The third transistor T3 has n-type transistor characteristics and is turned on when a voltage control signal GRn of a high voltage is applied to the gate electrode. When the third transistor T3 is turned on, the reference voltage Vref from the reference voltage line 176 can be transmitted to the first storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1.

[0090] The fourth transistor T4 includes a gate electrode connected to an initialization control line 153, a first electrode connected to an initialization voltage line 127, and a second electrode connected to a second storage electrode of a storage capacitor Cst. The second electrode of the fourth transistor T4 is also connected to a second electrode of the driving transistor T1 and an anode of the organic light-emitting diode OLED. The fourth transistor T4 has n-type transistor characteristics and is turned on when a high-voltage initialization control signal GIn is applied to the gate electrode. When the fourth transistor T4 is turned on, an initialization voltage Vint from the initialization voltage line 127 can be transmitted to the second storage electrode of the storage capacitor Cst, the anode of the organic light-emitting diode OLED, and the second electrode of the driving transistor T1.

[0091] The fifth transistor T5 includes a gate electrode connected to a light-emitting control line 154, a first electrode connected to a driving voltage line 175, and a second electrode connected to a first electrode of the driving transistor T1. The fifth transistor T5 has p-type transistor characteristics and is turned on when a low-voltage light-emitting control signal EMn is applied to the gate electrode. When the fifth transistor T5 is turned on, a driving voltage ELVDD from the driving voltage line 175 can be transmitted to the first electrode of the driving transistor T1.

[0092] Some of the plurality of transistors T1, T2, T3, T4, and T5 included in the pixel PX have n-type transistor characteristics, where a semiconductor layer is formed of an oxide semiconductor, and the remaining transistors have p-type transistor characteristics, where a semiconductor layer is formed of a polycrystalline semiconductor. Hereinafter, a transistor including an oxide semiconductor will be referred to as an oxide semiconductor transistor, and a transistor including a polycrystalline semiconductor will be referred to as a polycrystalline semiconductor transistor.

[0093] In the display device according to an exemplary embodiment of the inventive concept, the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are "oxide semiconductor transistors", and the fifth transistor T5 is a "polycrystalline semiconductor transistor". However, it is not limited thereto, and the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be "polycrystalline semiconductor transistors", and the fifth transistor T5 may be an "oxide semiconductor transistor".

[0094] The storage capacitor Cst includes a first storage electrode connected to the gate electrode of the driving transistor T1 and a second storage electrode connected to the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4. The first storage electrode of the storage capacitor Cst is also connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3. The storage capacitor Cst can store the data voltage DATA supplied through the second transistor T2. The data voltage DATA stored in the storage capacitor Cst adjusts the degree to which the driving transistor T1 is turned on, thereby determining the magnitude of the driving current.

[0095] The organic light-emitting diode OLED includes an anode connected to the second electrode of the driving transistor T1 and a cathode to which a common voltage ELVSS is applied. The organic light-emitting diode OLED emits light according to the driving current output from the driving transistor T1 to represent gray scale.

[0096] Hereinafter, with reference to Figure 6 the operations of one pixel of a display device according to an exemplary embodiment of the inventive concept, which are divided into an initialization period, a threshold voltage storage period, a data write period, and a light emission period, will be described.

[0097] With reference to Figure 6 , during the initialization period, the initialization control signal GIn and the voltage control signal GRn have an on voltage level, and the light emission control signal EMn and the gate signal GWn have an off voltage level. Accordingly, the third transistor T3 and the fourth transistor T4 are turned on, and the second transistor T2 and the fifth transistor T5 are turned off. The reference voltage Vref is applied to the first storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1, and the initialization voltage Vint is applied to the second storage electrode of the storage capacitor Cst, the second electrode of the driving transistor T1, and the anode of the organic light-emitting diode OLED to initialize the driving transistor T1.

[0098] Next, during a threshold voltage storage period, the emission control signal EMn and the voltage control signal GRn have an on voltage level, and the initialization control signal GIn and the gate signal GWn have an off voltage level. As a result, the third transistor T3 and the fifth transistor T5 are turned on, and the second transistor T2 and the fourth transistor T4 are turned off. The reference voltage Vref is applied to the first storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1. In this case, the output side voltage of the driving transistor T1 is stored in the second storage electrode of the storage capacitor Cst. The output side voltage of the driving transistor T1 has a value obtained by subtracting the threshold voltage Vth from the reference voltage Vref as the voltage of the gate electrode. Since the voltage of the first storage electrode of the storage capacitor Cst is the reference voltage Vref, the voltage difference between the two electrodes of the storage capacitor Cst has the value of the threshold voltage Vth. In addition, since the value of (Vref - Vth) is set to be lower than the common voltage ELVSS, it can be set so that no current flows to the organic light emitting diode OLED. For example, the reference voltage Vref may be about 1V.

[0099] Next, during a data write period, the gate signal GWn has an on voltage level, and the emission control signal EMn, the initialization control signal GIn, and the voltage control signal GRn have an off voltage level. Accordingly, the second transistor T2 is turned on, and the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off. In this case, the data voltage DATA is applied to the first storage electrode of the storage capacitor Cst and the gate electrode of the driving transistor T1, and the voltage difference between the two electrodes of the storage capacitor Cst becomes the voltage (DATA + Vth).

[0100] Next, during an emission period, only the emission control signal EMn has an on voltage level, and the initialization control signal GIn, the voltage control signal GRn, and the gate signal GWn have an off voltage level. Accordingly, the fifth transistor T5 is turned on and the second transistor T2 to the fourth transistor T4 are turned off. The driving transistor T1 provides an output current based on the voltage (DATA + Vth) charged in the storage capacitor Cst, and the provided output current is proportional to the square of (Vgs - Vth). Since Vgs has the value of (DATA + Vth - ELVDD), the threshold voltage Vth is canceled out, so that an output current independent of the threshold voltage of the driving transistor T1 is output to the organic light emitting diode OLED. The organic light emitting diode OLED emits light according to the output current.

[0101] Figure 7 is a layout diagram of one pixel region of a display device according to an exemplary embodiment of the inventive concept, Figure 8 is according to an exemplary embodiment of the inventive concept along Figure 7A cross-sectional view taken along line VIII-VIII'.

[0102] Referring to Figure 7 , a display device according to an exemplary embodiment of the inventive concept includes a plurality of signal lines and a plurality of transistors. The plurality of signal lines include gate lines 121 extending in a first direction (horizontal direction), voltage control lines 152, light emission control lines 154, auxiliary driving voltage lines 177, initialization control lines 153, and initialization voltage lines 127, and include reference voltage lines 176, data lines 171, and driving voltage lines 175 extending in a second direction (vertical direction) intersecting the first direction.

[0103] The gate lines 121 transmit gate signals, the voltage control lines 152 transmit voltage control signals GRn, and the light emission control lines 154 transmit light emission control signals EMn. The auxiliary driving voltage lines 177 transmit a driving voltage ELVDD, and the initialization voltage lines 127 transmit an initialization voltage Vint.

[0104] The reference voltage lines 176, data lines 171, and driving voltage lines 175 transmit a reference voltage Vref, a data voltage DATA, and a driving voltage ELVDD, respectively. The auxiliary driving voltage lines 177 extend in the first direction across the driving voltage lines 175 extending in the second direction and are connected to the driving voltage lines 175 through openings 98. The auxiliary driving voltage lines 177 extending in the first direction and the driving voltage lines 175 extending in the second direction are included to prevent voltage drops.

[0105] A plurality of transistors T1, T2, T3, T4, and T5 are formed along the shaded semiconductor layer. The semiconductor layer includes a polycrystalline semiconductor layer 131 and oxide semiconductor layers 135 and 136. As described above, the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may include the oxide semiconductor layers 135 and 136, and the fifth transistor T5 may include the polycrystalline semiconductor layer 131.

[0106] The polycrystalline semiconductor layer 131 and the oxide semiconductor layers 135 and 136 may extend substantially in the second direction. However, they are not limited thereto, and they may have various shapes and have a curved shape.

[0107] The driving transistor T1 includes a gate electrode 155, a channel, a first electrode, and a second electrode. The channel of the driving transistor T1 is disposed at a first oxide semiconductor layer 136 overlapping the gate electrode 155 of the driving transistor T1 in a plan view, and the first electrode and the second electrode are disposed on corresponding sides of the channel in the first oxide semiconductor layer 136.

[0108] The gate electrode 155 of the driving transistor T1 is island-shaped and connected to one end of the first connection member 45 through the opening 92-1. One end of the first connection member 45 is connected to the first storage electrode 125 of the storage capacitor Cst through the opening 92-2. The other end of the first connection member 45 is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3 through the opening 92-3. The first electrode of the driving transistor T1 is electrically connected to the fourth connection member 48 through the opening 95-1, and the fourth connection member 48 is connected to the second electrode of the fifth transistor T5 through the opening 95-2. The second electrode of the driving transistor T1 is connected to the second connection member 46 through the opening 91, the second connection member 46 is connected to the sixth connection member 55 through the opening 82, and the sixth connection member 55 is electrically connected to the anode of the organic light-emitting diode OLED through the opening 81.

[0109] The second transistor T2 includes a gate electrode, a channel, a first electrode, and a second electrode. The gate electrode of the second transistor T2 may be a partial region of the gate line 121. The channel of the second transistor T2 is disposed in the second oxide semiconductor layer 135 that overlaps with the gate electrode of the second transistor T2 in a plan view, and the first electrode and the second electrode are disposed on the corresponding sides of the channel in the second oxide semiconductor layer 135.

[0110] The first electrode of the second transistor T2 is electrically connected to the third connection member 47 through the opening 99, and the third connection member 47 is electrically connected to the protruding portion of the data line 171 through the opening 83. The second electrode of the second transistor T2 is connected to the first connection member 45 through the opening 92-3. The second electrode of the second transistor T2 is also connected to the second electrode of the third transistor T3.

[0111] The third transistor T3 includes a gate electrode, a channel, a first electrode, and a second electrode. The gate electrode of the third transistor T3 may be a partial region of the voltage control line 152. The channel of the third transistor T3 is disposed in the second oxide semiconductor layer 135 that overlaps with the gate electrode of the third transistor T3 in a plan view, and the first electrode and the second electrode are disposed on the corresponding sides of the channel in the second oxide semiconductor layer 135. The first electrode of the third transistor T3 is electrically connected to the protruding portion of the reference voltage line 176 through the opening 93.

[0112] The fourth transistor T4 includes a gate electrode, a channel, a first electrode, and a second electrode. The gate electrode of the fourth transistor T4 may be a partial region of the initialization control line 153. The channel of the fourth transistor T4 is disposed in the first oxide semiconductor layer 136 that overlaps with the gate electrode of the fourth transistor T4, and the first electrode and the second electrode are disposed on the corresponding sides of the channel in the first oxide semiconductor layer 136.

[0113] The first electrode of the fourth transistor T4 is electrically connected to the fifth connection member 49 through the opening 94-1, and the fifth connection member 49 is electrically connected to the protruding portion of the initialization voltage line 127 through the opening 94-2. The second electrode of the fourth transistor T4 is connected to the second electrode of the driving transistor T1 and is also electrically connected to the second connection member 46 through the opening 91.

[0114] The fifth transistor T5 includes a gate electrode, a channel, a first electrode, and a second electrode. The gate electrode of the fifth transistor T5 may be a partial region of the light emission control line 154. The channel of the fifth transistor T5 is provided in the polycrystalline semiconductor layer 131 stacked with the gate electrode of the fifth transistor T5, and the first electrode and the second electrode are provided on the respective sides of the channel in the polycrystalline semiconductor layer 131.

[0115] The first electrode of the fifth transistor T5 is electrically connected to the protruding portion of the driving voltage line 175 through the opening 96.

[0116] The storage capacitor Cst includes a first storage electrode 125 and a second storage electrode 126. The first storage electrode 125 and the second storage electrode 126 are stacked in a plan view. The first storage electrode 125 is electrically connected to the first connection member 45 through the opening 92-2, and the second storage electrode 126 is electrically connected to the second connection member 46 through the opening 97, thereby being electrically connected to the sixth connection member 55.

[0117] Refer to Figure 8 , the display device according to an exemplary embodiment of the inventive concept includes a substrate 110.

[0118] A buffer layer 111 is provided on the substrate 110. The buffer layer 111 may include silicon oxide or silicon nitride. The buffer layer 111 is disposed between the substrate 110 and the polycrystalline semiconductor layer 131 to block impurities diffusing from the substrate 110 to the polycrystalline semiconductor layer 131, and may planarize the substrate 110 to relieve the stress of the polycrystalline semiconductor layer 131 formed on the buffer layer 111.

[0119] The polycrystalline semiconductor layer 131 of the polycrystalline semiconductor transistor is provided on the buffer layer 111. The polycrystalline semiconductor layer 131 may be formed of polycrystalline silicon, and the polycrystalline silicon is formed by crystallizing amorphous silicon through a crystallization method such as excimer laser annealing (ELA).

[0120] The lower gate insulating layer 140 and the lower gate conductive layer are provided on the polycrystalline semiconductor layer 131. The lower gate insulating layer 140 may include a first gate insulating layer 141, a second gate insulating layer 142, and a third gate insulating layer 143, and the lower gate conductive layer may include a first gate conductive layer and a second gate conductive layer. However, it is not limited thereto, and the lower gate insulating layer 140 and the lower gate conductive layer may include fewer layers or more layers.

[0121] For example, a first gate insulating layer 141 is disposed on the polycrystalline semiconductor layer 131. The first gate insulating layer 141 may include silicon oxide or silicon nitride.

[0122] A first gate conductive layer is formed on the first gate insulating layer 141 and includes a gate electrode of a polycrystalline semiconductor transistor, a light emission control line 154, an initialization voltage line 127, an auxiliary driving voltage line 177, and a first storage electrode 125 of a storage capacitor Cst.

[0123] A second gate insulating layer 142 is disposed on the first gate conductive layer. The second gate insulating layer 142 may include silicon oxide or silicon nitride.

[0124] A second gate conductive layer including a second storage electrode 126 of the storage capacitor Cst is disposed on the second gate insulating layer 142.

[0125] A third gate insulating layer 143 is disposed on the second gate conductive layer. The third gate insulating layer 143 may include silicon oxide or silicon nitride.

[0126] Oxide semiconductor layers 135 and 136 are disposed on the lower gate insulating layer 140 and the lower gate conductive layer. In other words, the oxide semiconductor layers 135 and 136 including a first oxide semiconductor layer 136 and a second oxide semiconductor layer 135 are disposed on the third gate insulating layer 143. The first oxide semiconductor layer 136 and the second oxide semiconductor layer 135 are spaced apart from each other. The first oxide semiconductor layer 136 may include a channel in a region overlapping with the gate electrode of the driving transistor T1 and the gate electrode of the fourth transistor T4. The second oxide semiconductor layer 135 may include a channel in a region overlapping with the gate electrode of the second transistor T2 and the gate electrode of the third transistor T3.

[0127] An upper gate insulating layer 144 (also referred to as a fourth gate insulating layer 144) and an upper gate conductive layer are disposed on the oxide semiconductor layers 135 and 136. In other words, the fourth gate insulating layer 144 is disposed on the oxide semiconductor layers 135 and 136, and a third gate conductive layer including a gate electrode 155 of the driving transistor T1, a gate line 121, a voltage control line 152, and an initialization control line 153 is disposed on the fourth gate insulating layer 144. Refer to Figure 4 , the third gate conductive layer may further include a reference voltage supply line 60 and a reference voltage connection line 61 in a non-display region NA.

[0128] An interlayer insulating layer 160 is disposed on the third gate conductive layer. The interlayer insulating layer 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0129] A first data conductive layer including a first connection member 45, a second connection member 46, a third connection member 47, a fourth connection member 48, a fifth connection member 49, and a reference voltage line 176 is disposed on an interlayer insulating layer 160. Refer to Figure 4 , the first data conductive layer may further include a driving voltage supply line 50 and a driving voltage connection line 51 in a non-display area NA. The interlayer insulating layer 160, the fourth gate insulating layer 144, the third gate insulating layer 143, the second gate insulating layer 142, and the first gate insulating layer 141 include openings for connecting the first data conductive layer formed on the interlayer insulating layer 160 to another conductive layer or a semiconductor layer.

[0130] A passivation layer 180 is disposed on the first data conductive layer. The passivation layer 180 includes an organic insulating material to planarize the first data conductive layer.

[0131] A second data conductive layer including a sixth connection member 55 and a data line 171 is disposed on the passivation layer 180. Refer to Figure 3 , the second data conductive layer may include an initialization voltage supply line 40, an initialization voltage connection line 41, and a gate signal connection line 122 in a non-display area NA. The passivation layer 180 includes an opening for connecting the second data conductive layer and the first data conductive layer.

[0132] A planarization layer may further be included on the second data conductive layer, and an organic light-emitting diode OLED may be disposed on the planarization layer.

[0133] An anode of the organic light-emitting diode OLED is disposed on the planarization layer. The anode is connected to the sixth connection member 55 through an opening 81 formed in the planarization layer.

[0134] A separator may be disposed on the planarization layer and the anode. The separator has an opening portion overlapping with the anode, and an organic emission layer is disposed in the opening portion. A cathode of the organic light-emitting diode OLED may be disposed on the organic emission layer and the separator. The anode, the organic emission layer, and the cathode form the organic light-emitting diode OLED. According to an exemplary embodiment of the inventive concept, the positions of the anode and the cathode may be exchanged. When holes and electrons are injected from the anode and the cathode into the organic emission layer, excitons formed by the injected holes and electrons emit light when dropping from an excited state to a ground state.

[0135] According to an exemplary embodiment of the inventive concept, the interval between semiconductors of a transistor of a display device may be narrowed or stacked, thereby increasing the design freedom.

[0136] In addition, in a display device, since a signal supply line may extend to pixels disposed in a peripheral portion, luminance degradation of some pixels may be prevented, luminance uniformity may be maintained, and display quality may be improved.

[0137] Although the inventive concept has been described with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that various modifications in form and detail may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A display device, the display device comprising: A substrate, including a display area and a non-display area; A reference voltage supply line, disposed in the non-display area and configured to transmit a reference voltage; And A driving voltage supply line, disposed in the non-display area and configured to transmit a driving voltage, wherein the reference voltage supply line includes a straight portion and a curved portion, the straight portion extends in a first direction, the curved portion extends from the straight portion in a curved manner, and the curved portion of the reference voltage supply line is disposed along the periphery of the display area.

2. The display device according to claim 1, the display device further comprising: A reference voltage connection line, extending from the reference voltage supply line in a second direction intersecting the first direction; A reference voltage line, extending in the display area in the second direction; A driving voltage connection line, extending from the driving voltage supply line in the second direction; And A driving voltage line, extending in the display area in the second direction, wherein the reference voltage line is electrically connected to the reference voltage connection line through an opening, and wherein the driving voltage line is electrically connected to the driving voltage connection line through an opening.

3. The display device according to claim 2, the display device further comprising: An oxide semiconductor transistor and a polycrystalline semiconductor transistor, the oxide semiconductor transistor includes an oxide semiconductor layer, the polycrystalline semiconductor transistor includes a polycrystalline semiconductor layer, wherein the oxide semiconductor transistor includes a driving transistor, and a gate electrode of the driving transistor is disposed on the same layer as the reference voltage supply line.

4. The display device according to claim 3, the display device further comprising: A gate driver, disposed in the non-display area; An initialization voltage supply line, extending in the non-display area in the second direction; A gate signal output terminal, connected to the gate driver; And A gate signal connection line, connected to the gate signal output terminal through an opening, wherein the initialization voltage supply line and the gate signal connection line are disposed on the same layer.

5. The display device according to claim 4, wherein, Pixels adjacent to the curved portion of the reference voltage supply line are arranged in a stepped shape, and the gate driver and the driving voltage supply line are bent in the same direction as the curved portion of the reference voltage supply line in a region adjacent to the curved portion of the reference voltage supply line.

6. A display device, the display device comprising: A substrate, including a display area and a non-display area; A buffer layer, disposed on the substrate; A polycrystalline semiconductor layer, disposed on the buffer layer; A lower gate insulating layer and a lower gate conductive layer, disposed on the polycrystalline semiconductor layer; An oxide semiconductor layer, disposed on the lower gate insulating layer and the lower gate conductive layer; An upper gate insulating layer, disposed on the oxide semiconductor layer; An upper gate conductive layer, disposed on the upper gate insulating layer; An interlayer insulating layer, disposed on the upper gate conductive layer; And A first data conductive layer, disposed on the interlayer insulating layer, wherein the upper gate conductive layer includes: a reference voltage supply line and a reference voltage connection line, disposed in the non-display area and configured to transmit a reference voltage; and a gate electrode of a driving transistor, disposed in the display area, and Among them, the reference voltage supply line includes a straight portion and a curved portion. The straight portion extends in a first direction in a plan view. The curved portion extends from the straight portion in a curved shape, and the curved portion of the reference voltage supply line is disposed along the periphery of the display area.

7. The display device according to claim 6, wherein, The first data conductive layer includes a driving voltage supply line and a driving voltage connection line that are configured to transmit a driving voltage in the non-display area.

8. The display device according to claim 7, wherein, The lower gate insulating layer includes a first gate insulating layer and a second gate insulating layer disposed on the lower gate conductive layer. The lower gate conductive layer includes an initialization voltage line configured to transmit an initialization voltage and a light emission control line configured to transmit a light emission control signal. And The upper gate conductive layer further includes a gate line configured to transmit a gate signal, a voltage control line configured to transmit a voltage control signal, and an initialization control line configured to transmit an initialization control signal.

9. The display device according to claim 8, the display device further comprising a second transistor, a third transistor, a fourth transistor and a fifth transistor, wherein, The oxide semiconductor layer includes a first oxide semiconductor layer and a second oxide semiconductor layer separated on the same layer. The second transistor includes a channel disposed in the second oxide semiconductor layer that overlaps with the gate line. A first electrode of the second transistor is connected to a data line configured to transmit a data voltage. The third transistor includes a channel disposed in the second oxide semiconductor layer that overlaps with the voltage control line. The fourth transistor includes a channel disposed in the first oxide semiconductor layer that overlaps with the initialization control line. A first electrode of the fourth transistor is connected to the initialization voltage line. The fifth transistor includes a channel disposed in the polycrystalline semiconductor layer that overlaps with the light emission control line. And A first electrode of the fifth transistor is connected to a driving voltage line configured to transmit a driving voltage.

10. The display device according to claim 9, the display device further comprising: A reference voltage line, configured to transmit the reference voltage in the display area; A passivation layer, disposed on the first data conductive layer; And A second data conductive layer, disposed on the passivation layer. Among them, the first data conductive layer includes the reference voltage line. And Among them, the second data conductive layer includes a gate signal connection line and the data line. The gate signal connection line is disposed in the non-display area and is configured to transmit the gate signal from a gate driver.

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