Electronic device with inverted lead pins

Abstract

An electronic device (300A) reduces the strength of an electric field generated by external access to low voltage lead pins (328, 330) of a package (306) of the electronic device (300A). The electronic device (300A) includes a low voltage side (302) and a high voltage side (304). The low voltage side (302) includes a low voltage die (312) attached to a low voltage die attach pad (314). The high voltage side (304) includes a high voltage die (316) attached to a high voltage die attach pad (318). Lead pins (328, 330) are attached to the low voltage attach pad (314) and the high voltage attach pad (318), respectively, and extend in opposite directions out of the package (306) of the electronic device (300A).

Description

TECHNICAL FIELD

[0001] The present application relates to electronic devices having inverted lead pins. BACKGROUND

[0002] Integrated circuits (ICs) require conductive connections to provide conductive connections between the contact pads of the IC and the package leads or lead pins of the IC. In some applications, the IC includes a low voltage side with a low voltage die and a high voltage side with a high voltage die. When the IC is powered on, an electric field is generated between the package of the IC and the die attach pads of the low voltage side and the high voltage side (internal electric field). The internal electric field is isolated by the package and has negligible effect on the IC. However, the electric field extends out of the package on the low voltage side of the IC toward the low voltage lead pins (external electric field). The external electric field creates an electrical arc between the lead pins of the low voltage side of the IC. An electrical arc can also occur between the low voltage lead pins and electrical terminals on a printed circuit board on which the IC is mounted. The electrical arc eventually causes damage to the electronic components including the IC. SUMMARY

[0003] In one example, an electronic device including a package is described. The package has a longitudinal centerline, a mounting portion on one side of the longitudinal centerline, and a non-mounting portion on an opposite side of the longitudinal centerline. A low voltage die attach pad is embedded in the non-mounting portion of the package and includes a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline. A low voltage die is attached to the first side of the low voltage die attach pad. An inverted low voltage lead pin extends from the package in a direction toward the mounting portion and away from the non-mounting portion of the package. A high voltage die attach pad is embedded in the non-mounting portion of the package and includes a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline. A high voltage die is attached to the first side of the high voltage die attach pad. An inverted high voltage lead pin extends from the package in a direction toward the mounting portion and away from the non-mounting portion of the package.

[0004] In another example, an integrated circuit including a package is described. The package has a longitudinal centerline extending from a low voltage side to a high voltage side of the package. The package further includes a mounting portion on one side of the longitudinal centerline and a non-mounting portion on an opposite side of the longitudinal centerline. A low voltage die attach pad is embedded in the package and includes a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package. In addition, the low voltage die pad is displaced from the longitudinal centerline toward the non-mounting portion of the package by a first offset. A low voltage die is attached to the first side of the low voltage die attach pad. A low voltage lead pin extends from the package in a direction away from the longitudinal centerline and opposite a direction of the first offset. A high voltage die attach pad is embedded in the package and includes a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package. A high voltage die pad is displaced from the longitudinal centerline toward the non-mounting portion of the package by the first offset. A high voltage die is attached to the first side of the high voltage die attach pad. An inverted high voltage lead pin extends from the package in a direction away from the longitudinal centerline and opposite a direction of the first offset.

[0005] In another example, a method includes attaching a low voltage die to a low voltage die attach pad and attaching a high voltage die to a high voltage die attach pad. A first end of at least one low voltage lead pin is attached to the low voltage die attach pad and a first end of at least one high voltage lead pin is attached to the high voltage die attach pad. The low voltage die and the high voltage die are placed in a cavity defined in a package body of an integrated circuit. The low voltage die, the high voltage die, the low voltage die attach pad, and the high voltage die attach pad are encapsulated in a package of the integrated circuit, where the low voltage die attach pad and the high voltage die attach pad are displaced from a longitudinal centerline of the package of the integrated circuit in a direction toward a non-mounting portion of the package by a first offset. Second ends of the at least one low voltage lead pin and the at least one high voltage lead pin disposed outside of the package are bent in a direction away from the longitudinal centerline of the package and opposite a direction of the first offset. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a top perspective view of an example integrated circuit.

[0007] Figure 2A is an end view of an example integrated circuit.

[0008] Figure 2B is an end view of an example integrated circuit. Figure 2A

[0009] Figure 3A is an inverted end view of an example electronic device.

[0010] Figure 3B is​Figure 3A Non-inverted end view of an example electronic device.

[0011] Figure 3C is Figure 3A End view infrared image of an example electronic device.

[0012] Figure 4 is an example process of manufacturing Figure 3A and Figure 3B an electronic device. DETAILED DESCRIPTION

[0013] Figure 1is a top perspective view of an example integrated circuit (IC) 100 including a low voltage side 102 and a high voltage side 104. This type of IC is subject to electric fields generated inside and outside of a package 106 of the IC 100 due to a potential difference between the low voltage side 102 and the high voltage side 104. Specifically, the low voltage side includes one or more low voltage dies 108 attached to a low voltage die attach pad 110 and low voltage lead pins 112 extending from the low voltage die attach pad 110. Similarly, the high voltage side 104 includes one or more high voltage dies 114 attached to a high voltage die attach pad 116 and high voltage lead pins 118 extending from the high voltage lead pins 118. In some example ICs, the high voltage side 104 can further include a power boost device 120 (e.g., a transformer) made of a magnetic material attached to a printed circuit board 122. The power boost device 120 generates a magnetic field to boost power supplied to the high voltage side 104. Due to the potential difference between the low voltage and high voltage die attach pads 110, 116 and the close proximity of the low voltage and high voltage die attach pads 110, 116 to each other, an electric field is generated between the low voltage die attach pad 110 and the high voltage die attach pad 116. Due to the close proximity of the high voltage die attach pad 116 to the low voltage lead pins 112, the electric field extends outside of the package 106 proximate to the low voltage lead pins 112. The electric field generated outside of the package 106 proximate to the low voltage lead pins causes an electrical arc to be generated between the IC and a printed circuit board (PCB) on which the IC is mounted, or simply between adjacent low voltage lead pins 112. The electrical arc in turn damages the IC and / or the PCB. Accordingly, described herein is an electronic device (e.g., an integrated circuit) and a method of manufacturing the electronic device that reduces or eliminates the strength of the electric field generated outside of a package of the electronic device proximate to low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low voltage attach pad and the high voltage attach pad and extend out of a package of the electronic device in opposite directions. In other words, the electronic device has an inverted configuration such that the distance between the high voltage die attach pad and the low voltage lead pins is such that no electric field is generated outside of the package proximate to the low voltage lead pins. That is, contrary to conventional practice, the dies and die attach pads are embedded into the package in an inverted manner. Furthermore, the lead pins extend from each side of the package in a perpendicular direction relative to a longitudinal axis of the electronic device, contrary to conventional practice. Figure 2A is similar to Figure 1An end view of an example integrated circuit (IC) 200A is shown, which includes a low voltage side 202 and a high voltage side 204 and a package 206 made of a molding compound (e.g., an epoxy compound) that electrically isolates the low voltage side 202 from the high voltage side 204. The package 206 includes a longitudinal centerline CL1 that extends from the low voltage side 202 to the high voltage side 204. As shown by the bidirectional arrow A between a first (non-mounting) surface 208 and a second (mounting) surface 210 of the package 206, the longitudinal centerline CL1 is centrally positioned in the package 206 in a direction that is perpendicular to the longitudinal centerline CL1. The mounting surface 210 of the package 206 is the side of the package 206 that faces the PCB when the IC 200A is mounted to the PCB. Thus, the portion of the package 206 between the longitudinal centerline CL1 and the non-mounting surface 208 is a non-mounting portion NMP of the package 206. Similarly, the portion of the package 206 between the longitudinal centerline CL1 and the mounting surface 210 is a mounting portion MP of the package 206.

[0014] The low voltage side 202 includes a low voltage die 212 attached to a low voltage die attach pad (DAP) 214. Similarly, the high voltage side 204 includes a high voltage die 216 attached to a high voltage die attach pad (DAP) 218. Both the low voltage die 212 and the high voltage die 216 have electronics disposed therein. The low voltage die 212 and the low voltage DAP 214 are electrically isolated from the high voltage die 216 and the high voltage DAP 218 by the package 206. The low voltage DAP 214 and the high voltage DAP 218 are embedded in the mounting portion MP of the package such that both the low voltage die 212 and the high voltage die 216 are centrally disposed along a longitudinal centerline CL1 of the package 206. In other words, both the low voltage die 212 and the high voltage die 216 are disposed halfway between the non-mounting surface 208 and the mounting surface 210 of the package 206. The IC 200A can further include a power boost device 220 (e.g., a transformer) made of a magnetic material attached to the high voltage DAP 218. The power boost device 220 generates a magnetic field to boost power supplied to the high voltage side 204. The IC 200A further includes low voltage lead pins 222 on the low voltage side 202 and high voltage lead pins 224 on the high voltage side 204. At least one low voltage pin 202 is attached to and extends from the low voltage DAP 214, and at least one high voltage pin 224 is attached to and extends from the high voltage DAP 218. The low voltage lead pins 222 and the high voltage lead pins 224 exit the package 206 at exits 226, 228, respectively, defined in the package 206, and extend outward from each side of the package 206 along the longitudinal centerline CL1. Both the low voltage lead pins 222 and the high voltage lead pins 224 are then bent in a direction toward the high voltage DAP 218 and the second surface 210 of the package 206. The attachment surfaces 230 of both the low voltage lead pins 222 and the high voltage lead pins 224 extend beyond the second surface 210 of the package 206 by a predetermined distance d (e.g., 0.314 microns to 0.414 microns). Figure 2B is an example IC 200B similar to Figure 2A the IC 200A shown in the end view infrared image. Figure 2AThe infrared image in FIG. 3B shows the presence or absence of an electric field dispersed inside and outside the package 206. Specifically, the shaded areas enclosed in the dashed circles 232 inside and outside the package 206 show the presence of an electric field. As described above, during startup and / or operation of the ICs 200A, 200B, an electric field 232 is generated by the potential difference between the low voltage side 202 and the high voltage side 204. Specifically, during startup, the voltage on the high voltage DAP 218 can spike to approximately 7000 volts, which in turn can cause damage to the low voltage side 202. The electric field 232A inside the package 206 is isolated by the package 206, and thus the impact on the IC or other nearby electronic components is negligible. However, the electric field 232B outside the package is located near the low voltage lead pin 222, which causes an electrical arc to develop between the IC and the printed circuit board (PCB) on which the IC is mounted, damaging the IC and / or the PCB. The electric field 232B is present due to the configuration of the low voltage lead pin 222 relative to the high voltage DAP 218. More specifically, as described above, the low voltage lead pin 222 is bent in a direction toward the high voltage DAP 218. Thus, both the high voltage DAP 218 and the low voltage lead pin 222 are on the same side of the longitudinal centerline CL1. As a result, the distance D1 between the high voltage DAP 218 and the low voltage lead pin 222 is close enough to generate the electric field 232B outside the package 206. The electric field 232B causes an electrical arc between the IC and the printed circuit board (PCB) on which the IC is mounted, which in turn causes damage to the IC and / or the PCB. Figure 3A is a top view of the example IC 300A, while Figure 3Bis a non-inverted end view of example IC 300A having a lead pin configuration that reduces the total electric field and substantially reduces or substantially eliminates the strength of the electric field external to the IC from accessing the low voltage lead pins. More specifically, the configuration of IC 300A increases the distance D2 between the low voltage lead pins and the high voltage die attach pads such that the electric field external to the package is sufficiently reduced so as to have no adverse effects or the electric field is eliminated. IC 300A includes a low voltage side 302 and a high voltage side 304 and a package 306 made of a molding compound (e.g., an epoxy compound) that electrically isolates the low voltage side 302 from the high voltage side 304. The package 306 includes a longitudinal centerline CL2 that extends from the low voltage side 302 to the high voltage side 304. As indicated by the bidirectional arrow A between the first (non-mounting) surface 308 and the second (mounting) surface 310 of the package 306, the longitudinal centerline CL2 is centrally positioned in the package 306 in a direction that is perpendicular to the longitudinal centerline CL2. The mounting surface 310 of the package 306 is the side of the package 306 that faces the PCB when the IC 300A is mounted to the PCB. In addition, the portion of the package 306 between the longitudinal centerline CL2 and the non-mounting surface 308 is the non-mounting portion NMP of the package 306. Similarly, the portion of the package 306 between the longitudinal centerline CL2 and the mounting surface 310 is the mounting portion MP of the package 306.

[0015] The low voltage side 302 includes a low voltage die 312 attached to a low voltage die attach pad (DAP) 314. Specifically, the low voltage die 312 is attached to one side (first side) of the low voltage die attach pad 314 that faces the longitudinal centerline CL2 and faces the mounting portion MP of the package 306 (away from the non-mounting portion NMP). The opposite side (second side) of the low voltage die attach pad 314 faces away from the longitudinal centerline CL2 and away from the mounting portion MP of the package 306 (towards the non-mounting portion NMP). Similarly, the high voltage side 304 includes a high voltage die 316 attached to a high voltage die attach pad (DAP) 318. Specifically, the high voltage die 316 is attached to one side (first side) of the high voltage die attach pad 318 that faces the longitudinal centerline CL2 and faces the mounting portion MP of the package 306 (away from the non-mounting portion NMP). The opposite side (second side) of the high voltage die attach pad 318 faces away from the longitudinal centerline CL2 and away from the mounting portion MP of the package 306 (towards the non-mounting portion NMP). Both the low voltage die 312 and the high voltage die 316 have electronic devices disposed therein. The low voltage die 312 and the low voltage DAP 314 are electrically isolated from the high voltage die 316 and the high voltage DAP 318 by the package 306. The low voltage DAP 314 and the high voltage DAP 318 are embedded in the non-mounting portion NMP of the package 306 and are displaced from the longitudinal centerline CL2 by a first offset OS1 such that both the low voltage die 312 and the high voltage die 316 are centrally disposed along the longitudinal centerline CL2 of the package 306. In other words, both the low voltage die 312 and the high voltage die 316 are disposed halfway between the non-mounting surface 308 and the mounting surface 310 of the package 306. This configuration is in contrast to the configuration of the IC 200A shown in Figure 2A the IC 200B shown in FIG. 2B. In the IC 200B, the low voltage die 312 is disposed on the non-mounting surface 308 of the package 306 and the high voltage die 316 is disposed on the mounting surface 310 of the package 306. In the IC 200A, the low voltage die 312 is disposed on the mounting surface 310 of the package 306 and the high voltage die 316 is disposed on the non-mounting surface 308 of the package 306. Figure 2AIn this example, the low-voltage DAP 214 and the high-voltage DAP 218 are embedded in the mounting portion MP of the package 206. In this example IC 300A, the IC 300A includes a power boost device that includes a first layer of magnetic material 320 attached to the high-voltage DAP 318, a printed circuit board 322 disposed on the first layer of magnetic material 320, and a second layer of magnetic material 324 (e.g., a transformer). The power boost device generates a magnetic field to boost (e.g., increase) power supplied to the high-voltage side 304. The power boost device can be attached to a first side of an extension portion 326 of the high-voltage DAP 318, where the extension portion 326 is embedded in the non-mounting portion NMP of the package 306 and the first side faces the longitudinal centerline CL2. The extension portion 326 is embedded in the non-mounting portion NMP of the package 306 such that the extension portion is displaced a second offset OS2 from the longitudinal centerline CL2 and the PCB 322 is centrally disposed along the longitudinal centerline CL2 of the package 306. The IC 300A further includes low-voltage lead pins 328 on the low-voltage side 302 and high-voltage lead pins 330 on the high-voltage side 304. A first end 332 of at least one low-voltage lead pin 328 is attached to and extends from the low-voltage DAP 314 and a first end 334 of at least one high-voltage lead pin 330 is attached to and extends from the high-voltage DAP 318. The first ends 332, 334 of both the low-voltage lead pins 328 and the high-voltage lead pins 330 are encapsulated in the package 306 along the centerline CL2. Both the low-voltage lead pins 328 and the high-voltage lead pins 330 exit the package 306 at exits 336, 338, respectively, defined in each side of the package 306 along the longitudinal centerline CL2 of the package 306. Second ends 340 of the low-voltage lead pins 328 and second ends 342 of the high-voltage lead pins 330 extend outwardly from each side of the package 306 along the longitudinal centerline CL2. The second ends 340 of the low-voltage lead pins 328 and the second ends 342 of the high-voltage lead pins 330 transition (e.g., bend, flex, etc.) in a direction away from the non-mounting portion NMP of the package 306 and thus away from the high-voltage DAP 318. Attachment surfaces 344 of both the low-voltage lead pins 328 and the high-voltage lead pins 330 extend beyond the second surface 310 of the package 306 by a predetermined distance d (e.g., 0.314 microns to 0.414 microns). As shown in FIG. 3A, the IC 300A has an inverted configuration. Once the IC 300A is flipped over for mounting, the low-voltage die 312 and the high-voltage die 316 are inverted with respect to the low-voltage DAP 314 and the high-voltage DAP 318. In other words, the low-voltage DAP 314 and the high-voltage DAP 318 are inverted with respect to the low-voltage die 312 and the high-voltage die 316. Figure 3B Figure 2A ​Compared to the example IC 200A shown, the low-voltage die and high-voltage die 316 are mounted on opposite sides of the low-voltage DAP 314 and high-voltage DAP 318, respectively. Therefore, when IC 300A is mounted to the PCB, the low-voltage die 312 and high-voltage die 316 are mounted upside down. However, this upside-down mounting does not affect the operation or performance of IC 300A, low-voltage die 312, high-voltage die 316, or the electronics inside dies 312 and 316. As described herein, the inverted configuration helps to reduce or eliminate the electric field outside the package 306.

[0016] Figure 3C It is similar to Figure 3A The example IC 300A is shown as an end-view infrared image of the example IC 300B. Figure 3A The infrared image shows the presence or absence of an electric field dispersed within package 306. Specifically, the shaded area enclosed by the dashed circle 346 within package 306 indicates the presence of an electric field. As mentioned above, electric field 346 is generated by the potential difference between the low-voltage side 302 and the high-voltage side 304. The electric field 346A within package 306 is isolated by package 306, therefore its effect on ICs or other nearby electronic components is negligible. However, in Figure 2A and Figure 2B The electric field 232B outside the package 206 shown no longer exists. Figure 3C In the example IC 300B shown. In other words, there is no longer an electric field outside the package 306 near the low-voltage lead 328. Due to the configuration of the low-voltage lead 328 relative to the high-voltage DAP 318, the electric field 346B outside the package no longer exists. More specifically, as described above, the low-voltage lead 328 transitions (e.g., bends, folds, etc.) in a direction away from the high-voltage DAP 318 and toward the first surface 308 of the package 306. Therefore, the high-voltage DAP 318 and the low-voltage lead 328 are on opposite sides of the longitudinal centerline CL2, which is consistent with... Figure 2A and Figure 2B The example ICs 200A and 200B shown are the opposite. Therefore, the distance D2 between the high-voltage DAP 318 and the low-voltage lead 328 is greater than the distance D1 between the high-voltage DAP 218 and the low-voltage lead 222 described above. As a result, the electric field strength is reduced so that it has no adverse effect on ICs 300A and 300B, or the electric field is eliminated.

[0017] Figure 4 It is manufacturing Figure 3AAn example process 400 for an electronic device is described. At 402, a low voltage die and a high voltage die (e.g., low voltage die 312 and high voltage die 316) are attached to a low voltage die attach pad and a high voltage die attach pad, respectively. At 404, a first end of at least one low voltage lead pin (e.g., low voltage lead pin 328) and a first end of at least one high voltage lead pin (e.g., high voltage lead pin 330) are attached to a low voltage DAP and a high voltage DAP, respectively. At 406, the low voltage die and the high voltage die are placed in a cavity defined in a body of a package of the electronic device (e.g., IC 300A). At 408, the low voltage die, the high voltage die, the low voltage die attach pad, and the high voltage die attach pad are encapsulated in the package of the integrated circuit. The encapsulation includes injecting an encapsulation material into the cavity of the body, where the encapsulation material surrounds the low voltage die attach pad and the high voltage die attach pad, the low voltage die and the high voltage die, and the first end of the at least one low voltage lead pin and the first end of the at least one high voltage lead pin. The encapsulation further includes curing the encapsulation material. At 410, a second end of the at least one low voltage lead pin and a second end of the at least one high voltage lead pin disposed outside of the package are manipulated to bend (e.g., bend, flex, angle, etc.) in a direction away from a longitudinal centerline of the package and opposite a direction of the first offset.

[0018] In this specification, the terms "on," "above," "under," and "below" (and derivatives thereof) mean the relative positioning of two adjacent surfaces in a selected orientation. Likewise, in this specification, the terms "top" and "bottom" mean relative surfaces in a selected orientation. Similarly, the terms "above" and "below" mean relative positioning in a selected orientation. Even though examples used throughout the specification represent one selected orientation, the selected orientation is arbitrary and other orientations are possible (e.g., upside down, rotated 90 degrees, etc.) within the scope of this specification. Additionally, in this specification, the term "based on" means based, at least in part, on.

[0019] Modifications can be made in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An electronic device comprising: a package having a longitudinal centerline, a mounting portion on one side of the longitudinal centerline, and a non-mounting portion on an opposite side of the longitudinal centerline; a low voltage die attach pad embedded in the non-mounting portion of the package, the low voltage die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a low voltage die attached to the first side of the low voltage die attach pad; a plurality of low voltage lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package; a high voltage die attach pad embedded in the non-mounting portion of the package, the high voltage die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a high voltage die attached to the first side of the high voltage die attach pad; and a plurality of high voltage lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package.

2. The electronic device of claim 1, wherein the low voltage die and the high voltage die are centrally disposed on the longitudinal centerline of the package.

3. The electronic device of claim 2, wherein the plurality of low voltage lead pins and the plurality of high voltage lead pins exit the package at an exit defined in the package along the longitudinal centerline of the package.

4. The electronic device of claim 1, wherein at least one of the plurality of low voltage lead pins extends from the low voltage die attach pad and at least one of the plurality of high voltage lead pins is attached to the high voltage die attach pad.

5. The electronic device of claim 1, wherein attachment surfaces of the plurality of low voltage lead pins and the plurality of high voltage lead pins extend a predetermined distance beyond a mounting surface of the package.

6. An electronic device comprising: a package having a longitudinal centerline, a mounting portion on one side of the longitudinal centerline, and a non-mounting portion on an opposite side of the longitudinal centerline; a low voltage die attach pad embedded in the non-mounting portion of the package, the low voltage die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a low voltage die attached to the first side of the low voltage die attach pad; a plurality of low voltage lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package; a high voltage die attach pad embedded in the non-mounting portion of the package, the high voltage die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a high voltage die attached to the first side of the high voltage die attach pad; a plurality of high voltage lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package; and ​ ​ a power boost device attached to the high voltage die attach pad, wherein the power boost device increases power supplied to the high voltage die attach pad.

7. The electronic device of claim 6, wherein the power boost device is made of a magnetic material that generates a magnetic field to increase power supplied to the high voltage die attach pad.

8. An integrated circuit, comprising: a package having a longitudinal centerline extending from a low voltage side to a high voltage side of the package, the package including a mounting portion on one side of the longitudinal centerline and a non-mounting portion on an opposite side of the longitudinal centerline; a low voltage die attach pad embedded in the package, the low voltage die attach pad having a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the low voltage die attach pad being displaced from the longitudinal centerline toward the non-mounting portion of the package by a first offset; a low voltage die attached to the first side of the low voltage die attach pad; a plurality of low voltage lead pins extending from the package in a direction away from the longitudinal centerline and opposite a direction of the first offset; a high voltage die attach pad embedded in the package, the high voltage die attach pad having a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the high voltage die attach pad being displaced from the longitudinal centerline toward the non-mounting portion of the package by the first offset; a high voltage die attached to the first side of the high voltage die attach pad; and a plurality of high voltage lead pins extending from the package in a direction away from the longitudinal centerline and opposite a direction of the first offset.

9. The integrated circuit of claim 8, wherein the low voltage die and the high voltage die are centrally disposed on the longitudinal centerline of the package.

10. The integrated circuit of claim 9, wherein the plurality of low voltage lead pins and the plurality of high voltage lead pins exit the package at an exit defined in the package along the longitudinal centerline of the package.

11. The integrated circuit of claim 8, wherein at least one of the plurality of low voltage lead pins is attached to the low voltage die attach pad and at least one of the plurality of high voltage lead pins is attached to the high voltage die attach pad.

12. The integrated circuit of claim 8, wherein attachment surfaces of the plurality of low voltage lead pins and the plurality of high voltage lead pins extend beyond a mounting surface of the package by a predetermined distance. ​ 13. The integrated circuit of claim 8, further comprising a power boost device to increase power supplied to the high voltage side, wherein the high voltage die attach pad comprises an extension portion embedded in the non-mounting portion of the package, the extension portion being displaced from the longitudinal centerline of the package toward the non-mounting portion of the package by a second offset, and wherein the power boost device is attached to the extension portion of the high voltage die attach pad.

14. The integrated circuit of claim 13, wherein the power enhancement device comprises: a first magnetic layer attached to a side of the extension portion of the high voltage die attach pad facing the longitudinal centerline; a printed circuit board attached to the first magnetic layer; and a second magnetic layer attached to the printed circuit board.

15. The integrated circuit of claim 14, wherein the printed circuit board is centrally disposed along the longitudinal centerline of the package.

16. A method for packaging an integrated circuit, comprising: attaching a low voltage die to a low voltage die attach pad and a high voltage die to a high voltage die attach pad; attaching first ends of at least one low voltage lead pin to the low voltage die attach pad and first ends of at least one high voltage lead pin to the high voltage die attach pad; placing the low voltage die and the high voltage die in a cavity defined in a package body of an integrated circuit; encapsulating the low voltage die, the high voltage die, the low voltage die attach pad, and the high voltage die attach pad in a package of the integrated circuit, wherein the low voltage die attach pad and the high voltage die attach pad are displaced from a longitudinal centerline of the package of the integrated circuit in a direction toward a non-mounting portion of the package by a first offset; and bending second ends of the at least one low voltage lead pin and the at least one high voltage lead pin disposed outside of the package in a direction away from the longitudinal centerline of the package and opposite the direction of the first offset.

17. The method of claim 16, wherein encapsulating comprises injecting an encapsulation material into the cavity of the body, the encapsulation material surrounding the low voltage die attach pad and the high voltage die attach pad, the low voltage die and the high voltage die, and the first ends of the at least one low voltage lead pin and the at least one high voltage lead pin in the cavity; and curing the encapsulation material.

18. The method of claim 16, wherein the low voltage die and the high voltage die are centrally encapsulated along the longitudinal centerline of the package.

19. The method of claim 16, wherein the first ends of the at least one low voltage lead pin and the at least one high voltage lead pin are encapsulated along the longitudinal centerline of the package.

20. The method of claim 16, wherein prior to bending the second ends of the at least one low voltage lead pin and the at least one high voltage lead pin, the method further comprises removing the package from a mold.

21. An electronic device, comprising: ​ a package having a longitudinal centerline, a mounting portion on one side of the longitudinal centerline, and a non-mounting portion on an opposite side of the longitudinal centerline; a first die attach pad embedded in the non-mounting portion of the package, the first die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a low voltage die attached to the first side of the first die attach pad; a second die attach pad embedded in the non-mounting portion of the package, the second die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a high voltage die attached to the first side of the second die attach pad; and a plurality of lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package.

22. The electronic device of claim 21, wherein the low voltage die is centrally disposed on the longitudinal centerline of the package.

23. The electronic device of claim 22, wherein the plurality of lead pins exit the package at an exit defined in the package along the longitudinal centerline of the package.

24. The electronic device of claim 21, wherein at least one of the plurality of lead pins is attached to the first die attach pad.

25. The electronic device of claim 21, wherein an attachment surface of the plurality of lead pins extends a predetermined distance beyond a mounting surface of the package.

26. An electronic device comprising: a package having a longitudinal centerline, a mounting portion on one side of the longitudinal centerline, and a non-mounting portion on an opposite side of the longitudinal centerline; a first die attach pad embedded in the non-mounting portion of the package, the first die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a low voltage die attached to the first side of the first die attach pad; a second die attach pad embedded in the non-mounting portion of the package, the second die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a high voltage die attached to the first side of the second die attach pad; a power boost device attached to the second die attach pad, wherein the power boost device increases power supplied to the second die attach pad; a plurality of lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package.

27. The electronic device of claim 26, wherein the power boost device is made of a magnetic material that generates a magnetic field to increase power supplied to the second die attach pad.

28. An integrated circuit comprising: a package having a longitudinal centerline extending from one side of the package to another side, the package including a mounting portion on one side of the longitudinal centerline and a non-mounting portion on an opposite side of the longitudinal centerline; a first die attach pad embedded in the non-mounting portion of the package, the first die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a low voltage die attached to the first side of the first die attach pad; a second die attach pad embedded in the non-mounting portion of the package, the second die attach pad having a first side facing the longitudinal centerline and a second side facing away from the longitudinal centerline; a high voltage die attached to the first side of the second die attach pad; a power boost device attached to the second die attach pad, wherein the power boost device increases power supplied to the second die attach pad; a plurality of lead pins extending from the package in a direction toward the mounting portion and away from the non-mounting portion of the package. a first die attach pad embedded in the package, the first die attach pad having a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the first die attach pad being displaced from the longitudinal centerline toward the non-mounting portion of the package by a first offset; a low voltage die attached to the first side of the first die attach pad; a second die attach pad embedded in the package, the second die attach pad having a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the second die attach pad being displaced from the longitudinal centerline toward the non-mounting portion of the package by a first offset; a high voltage die attached to the first side of the second die attach pad; and a plurality of lead pins extending from the package in a direction away from the longitudinal centerline and opposite the direction of the first offset.

29. The integrated circuit of claim 28, wherein the low voltage die is centrally disposed on the longitudinal centerline of the package.

30. The integrated circuit of claim 29, wherein the plurality of lead pins exit the package at an exit defined in the package along the longitudinal centerline of the package.

31. The integrated circuit of claim 28, wherein at least one of the plurality of lead pins is attached to the first die attach pad.

32. The integrated circuit of claim 28, wherein an attachment surface of the plurality of lead pins extends beyond a mounting surface of the package by a predetermined distance.

33. An integrated circuit comprising: a package having a longitudinal centerline extending from a first side to a second side of the package, the package including a mounting portion on one side of the longitudinal centerline and a non-mounting portion on an opposite side of the longitudinal centerline; a first die attach pad embedded in the package, the first die attach pad having a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the first die attach pad being displaced from the longitudinal centerline toward the non-mounting portion of the package by a first offset; a low voltage die attached to the first side of the first die attach pad; a second die attach pad embedded in the package, the second die attach pad having a first side facing the longitudinal centerline toward the mounting portion of the package and a second side facing away from the longitudinal centerline toward the non-mounting portion of the package, the second die attach pad being displaced from the longitudinal centerline toward the non-mounting portion of the package by a first offset; a high voltage die attached to the first side of the second die attach pad; and a plurality of lead pins extending from the package in a direction away from the longitudinal centerline and opposite the direction of the first offset. wherein the second die attach pad includes an extension portion embedded in the non-mounting portion of the package, the extension portion being displaced from the longitudinal centerline of the package toward the non-mounting portion of the package by a second offset, and wherein a power boost device is attached to the extension portion of the second die attach pad; and a plurality of lead pins extending from the package in a direction away from the longitudinal centerline of the package and opposite to the direction of the first offset.

34. The integrated circuit of claim 33, wherein the power enhancement device comprises: a first magnetic layer attached to a side of the extension portion of the second die attach pad facing the longitudinal centerline; a printed circuit board attached to the first magnetic layer; and a second magnetic layer attached to the printed circuit board.

35. The integrated circuit of claim 34, wherein the printed circuit board is centrally disposed along the longitudinal centerline of the package.

36. A method for packaging an integrated circuit, comprising: attaching a low voltage die to a first die attach pad; attaching a high voltage die to a second die attach pad; attaching a first end of at least one lead pin to the first die attach pad; placing the low voltage die and the high voltage die in a cavity defined in a package body of an integrated circuit; encapsulating the low voltage die and the high voltage die and the first die attach pad and the second die attach pad in a package of the integrated circuit, wherein the first die attach pad and the second die attach pad are displaced from a longitudinal centerline of the package of the integrated circuit in a direction toward a non-mounting portion of the package by a first offset; and bending a second end of the at least one lead pin disposed outside of the package in a direction away from the longitudinal centerline of the package and opposite to the direction of the first offset.

37. The method of claim 36, wherein encapsulating includes injecting an encapsulation material into the cavity of the package body, the encapsulation material surrounding the first die attach pad and the second die attach pad, the low voltage die and the high voltage die, and the first end of the at least one lead pin in the cavity; and curing the encapsulation material.

38. The method of claim 36, wherein the low voltage die is centrally encapsulated along the longitudinal centerline of the package.

39. The method of claim 36, wherein the first end of the at least one lead pin is encapsulated along the longitudinal centerline of the package.

40. A method for packaging an integrated circuit, comprising: attaching a low voltage die to a first die attach pad; attaching a high voltage die to a second die attach pad; attaching a power boost device to the second die attach pad; attaching a first end of at least one lead pin to the second die attach pad; placing the power boost device in a cavity defined in a package body of an integrated circuit; attaching a printed circuit board to the first magnetic layer; and attaching a second magnetic layer to the printed circuit board. encapsulating the power enhancement device and the first die attach pad and the second die attach pad in a package of the integrated circuit, wherein the first die attach pad and the second die attach pad are displaced from a longitudinal centerline of the package of the integrated circuit in a direction toward a non-mounting portion of the package by a first offset; and bending a second end of the at least one lead pin disposed outside of the package in a direction away from the longitudinal centerline of the package and opposite the direction of the first offset, wherein prior to bending the second end of the at least one lead pin, the method further comprises removing the package from a mold.

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