Display driver integrated circuit and operating method thereof

Abstract

The method of operating a display driver integrated circuit (DDIC) includes correcting first image data using correction data in a first operating mode. The first image data is received from a processor via an interface, and the correction data is stored in a first memory included in the DDIC. The method also includes: in response to a mode switching signal that controls the DDIC to switch to a second operating mode, storing second image data received from the processor in the first memory, and displaying the second image data on a display panel in the second operating mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0040971 filed on April 8, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present disclosure relate to a display driving integrated circuit (DDIC) and an operating method thereof. Background Art

[0004] Flat panel display devices may be used in electronic devices such as, for example, televisions, laptop computers, monitors, mobile devices, etc. to display images. Examples of flat panel display devices include liquid crystal displays (LCDs), organic light emitting displays (OLEDs), and the like.

[0005] A flat panel display device may include: a panel having a plurality of pixels; and a driving device for providing electrical signals to the pixels. An image may be formed by the electrical signals provided to the pixels from the driving device. The flat panel display device may display image data continuously received from a processor or image data stored in its internal memory according to an operation mode of the driving device. Summary of the invention

[0006] Exemplary embodiments of the present disclosure provide a display driver integrated circuit (DDIC) having an internal memory capable of performing both a function of an image correction lookup table and a function of an image storage buffer according to an operation mode.

[0007] According to an exemplary embodiment, an operating method of a display driver integrated circuit (DDIC) includes correcting first image data using correction data in a first operating mode. The first image data is received from a processor via an interface, and the correction data is stored in a first memory included in the DDIC. The method also includes: storing second image data received from the processor in the first memory in response to a mode switching signal that controls the DDIC to switch to a second operating mode; and displaying the second image data on a display panel in the second operating mode.

[0008] According to an exemplary embodiment, an operating method of a DDIC includes correcting first image data using correction data stored in an internal memory of the DDIC. The first image data is received from a processor and includes a plurality of image frames. The method also includes displaying the corrected first image data on a display panel. The method also includes: in response to a first mode switching signal, storing at least one image frame of the plurality of image frames that is not displayed on the display panel as second image data in the internal memory. The method also includes: when an update condition is met, receiving third image data from the processor; and updating the second image data using the third image data.

[0009] According to an exemplary embodiment, an operating method of a DDIC includes receiving first image data and second image data from a processor via an interface, correcting the first image data using correction data obtained from an internal memory of the DDIC, displaying the corrected first image data on a display panel, and deactivating the interface and storing the second image data in the internal memory.

[0010] According to an exemplary embodiment, the DDIC includes an interface communicating with a processor and a first memory storing correction data for correcting image data received from the processor or the image data. The first memory is connected to the interface. The DDIC also includes a timing controller that inputs the image data to the display panel in response to a timing control signal; and a controller that controls whether to activate the interface according to an operation mode of the DDIC. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a diagram illustrating an electronic device to which a display driver integrated circuit (DDIC) according to an exemplary embodiment is applied.

[0013] Figure 2 is a schematic block diagram of a display system including a DDIC according to an exemplary embodiment.

[0014] Figure 3 is a schematic block diagram of a display device including a DDIC according to an exemplary embodiment.

[0015] Figure 4 is a schematic block diagram of a DDIC according to an exemplary embodiment.

[0016] Figure 5 is a diagram illustrating a process of switching between operation modes according to a mode switching signal, the process being performed by a DDIC according to an exemplary embodiment.

[0017] Figure 6 and Figure 7 is a diagram illustrating the operation of a DDIC according to an exemplary embodiment.

[0018] Figure 8 and Fig. 9 is a flow chart illustrating a process of switching between operating modes, the process being performed by a DDIC, according to an exemplary embodiment.

[0019] Fig.10 is a block diagram of an electronic device including a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0020] Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.Throughout the drawings, like reference numerals may refer to like elements.

[0021] It will be understood that the terms "first", "second", "third", etc. are used herein to distinguish one element from another element, and the elements are not limited by these terms. Therefore, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0022] Figure 1 is a diagram illustrating an electronic device to which a display driver integrated circuit (DDIC) according to an exemplary embodiment is applied.

[0023] refer to Figure 1 The electronic device 1 may be implemented as a mobile device such as a smart phone, and may include a housing 10 and a display panel 20 .

[0024] The housing 10 may be formed in the shape of the electronic device 1. The housing 10 may include, for example, a first surface, a second surface opposite to the first surface, and a side surface disposed between the first surface and the second surface.

[0025] The display panel 20 and the cover glass may be sequentially arranged on the first surface of the housing 10. The display panel 20 may be exposed to the outside via the cover glass. The electronic device 1 may include a processor and a DDIC included in the housing 10. The processor may control the overall operation of the electronic device 1. The DDIC may drive the display panel 20 to display various types of image data, such as, for example, still images, videos, and texts. The back cover may be arranged on the second surface of the housing 10. The side of the housing 10 may be used as an antenna radiator.

[0026] The electronic device 1 can operate in various operation modes. For example, the electronic device 1 can operate in an active mode (also called a wake-up mode or a normal mode) or a sleep mode.

[0027] In the active mode, the electronic device 1 can perform various functions by providing sufficient power to various hardware modules and / or software modules. For example, in the active mode, the electronic device 1 can display various image data provided from the processor on the display panel 20. The image data displayed on the display panel 20 can be data obtained by correcting the original image data based on the correction data stored in the internal memory of the DDIC.

[0028] In sleep mode, the electronic device 1 may perform a limited number of functions by deactivating its various hardware modules and at least some of its software modules. For example, in sleep mode, the electronic device 1 may display only limited information on the display panel 20, such as, for example, time, weather, remaining battery power, etc., based on image data stored in the internal memory of the DDIC. By displaying only limited information (e.g., high priority information), the electronic device 1 may consume less power and use fewer resources.

[0029] exist Figure 1 In the example of , the electronic device 1 operates in the sleep mode and may display first image data 21 representing the current time and second image data 22 representing the current date on the display panel 20. The first image data 21 may be received earlier than the second image data 22.

[0030] The first image data 21 and the second image data 22 may be stored in the internal memory of the DDIC before the electronic device 1 enters the sleep mode. The first image data 21 and the second image data 22 stored in the internal memory may be updated with current information (e.g., referred to as third image data) by the DDIC or the processor at specific time intervals or whenever a specific event occurs (e.g., a user touch input occurs). In an exemplary embodiment, the third image data may be used to update the second image data 22 during the sleep mode. The event that causes the update may be a predefined event and is not limited to the occurrence of a user touch input. Figure 1 In the example of , the first image data 21 is updated at one-minute intervals starting from 05:23, and since the current date is "Monday, January 1", the second image data 22 is not updated.

[0031] In an exemplary embodiment, the internal memory of the DDIC can perform different functions in the active mode and the sleep mode of the electronic device 1. For example, in the active mode, the internal memory of the DDIC can store correction data for correcting image data. In this case, the DDIC can be used as a lookup table. Alternatively, in the sleep mode, the internal memory of the DDIC can store image data to be displayed on the display panel 20. In this case, the DDIC can be used as a display buffer. As described above, in the DDIC according to the exemplary embodiment, depending on the operation mode, one internal memory can be used as an image correction memory or a buffer memory, thereby reducing the size and power consumption of the DDIC. For example, unlike the comparative example in which a separate buffer is implemented for displaying image data in the sleep mode, in the exemplary embodiment, the same internal memory used as an image correction memory in the active mode can also be used as a buffer memory in the sleep mode, thereby reducing the size and power consumption of the DDIC.

[0032] Figure 2 is a schematic block diagram of a display system including a DDIC according to an exemplary embodiment.

[0033] refer to Figure 2 , the display system 2 according to the exemplary embodiment may include a processor 30 and a display device 40. The display device 40 may include a DDIC 50 and a display panel 60.

[0034] The processor 30 may include, for example, at least one of a central processing unit (CPU), an application processor (AP), or a communication processor (CP). For example, when the display system 2 is applied to a mobile device, the processor 30 may be an AP. When the display system 2 is applied to a desktop or laptop computer, the processor 30 may be a CPU.

[0035] The processor 30 may control one or more components of the display system 2 to process various types of data. For example, the processor 30 may generate image data to be displayed on the display panel 60, or may receive image data from a memory, a communication module, etc., and send the image data to the DDIC 50.

[0036] The display device 40 may include a DDIC 50 and a display panel 60. The DDIC 50 may include a gate driver and a source driver to input image data transmitted from the processor 30 to the display panel 60. The DDIC 50 also includes a timing controller to control the gate driver and the source driver.

[0037] The timing controller may control the gate driver and the source driver according to the timing control signal. The timing control signal may be generated and sent by the processor 30, or may be generated by the timing controller.

[0038] The DDIC 50 may communicate with the processor 30 based on a specific communication interface. In an exemplary embodiment, the DDIC 50 may communicate with the processor 30 based on a high-speed serial interface such as, for example, a Mobile Industry Processor Interface (MIPI).

[0039] The DDIC 50 may operate in a video mode in which both image data and a timing control signal are received from the processor 30 or in a command mode in which only image data is received from the processor 30. In the video mode, image data may be sent to the DDIC 50 from the processor 30 in real time. In the command mode, image data may be sent from the processor 30 to the DDIC 50 under the control of a tearing effect (TE) signal. In the command mode, when the image data is a still image, the DDIC 50 may store the received still image in an internal memory and display the still image from the internal memory on the display panel 60.

[0040] Figure 3 is a schematic block diagram of a display device including a DDIC according to an exemplary embodiment.

[0041] refer to Figure 3 , the display device 70 may include a DDIC 80 and a display panel 90 .

[0042] The DDIC 80 may include a timing controller 81, a gate driver 82, and a source driver 83. The display panel 90 may include a plurality of pixels PX arranged along a plurality of gate lines G1 to Gn and a plurality of source lines S1 to Sm, where n and m are positive integers.

[0043] In an exemplary embodiment, the display device 70 may display image data in units of frames. The time required to display one frame may be defined as a vertical period, and the vertical period may be determined by the scan rate of the display device 70. For example, when the scan rate of the display device 70 is 60 Hz, the vertical period may be 1 / 60 seconds (e.g., approximately 16.7 ms).

[0044] During one vertical period, the gate driver 82 may scan each of the gate lines G1 to Gn. The time required for the gate driver 82 to scan each of the gate lines G1 to Gn may be defined as a horizontal period, and the source driver 83 may input image data to the pixel PX during one horizontal period.

[0045] The horizontal period and the vertical period may be determined by the timing controller 81. When the DDIC 80 is connected to an external processor using MIPI, in the command mode, the horizontal period and the vertical period may be determined by the timing controller 81. In contrast, in the video mode, the horizontal period and the vertical period may be determined by the external processor.

[0046] Figure 4 is a schematic block diagram of a DDIC according to an exemplary embodiment.

[0047] DDIC 200 can operate in various operation modes such as normal mode, sleep mode, and low power mode. For example, DDIC 200 can operate in a first operation mode or a second operation mode according to a method of displaying image data. In the exemplary embodiments described herein, unless otherwise indicated by the context, the first operation mode is the normal mode, and the second operation mode is the sleep mode.

[0048] In the first operation mode, while the processor 100 is activated, the DDIC 200 may display image data continuously received from the processor 100 on the display panel 300. In the first operation mode, sufficient power may be supplied to the DDIC 200 to operate without any functional limitation.

[0049] In the second operation mode, while processor 100 is disabled, DDIC 200 may read image data from internal memory and display the image data on display panel 300. In the second operation mode, one or more components of DDIC 200 may be disabled so that DDIC 200 may operate with certain functions limited.

[0050] In the second operation mode, the processor 100 may be temporarily activated when the internal memory update condition is satisfied. For example, when the information to be displayed on the display panel 300 is changed, the processor 100 may be temporarily activated to send new image data. When the processor 100 is activated, the DDIC 200 may store the image data received from the processor 100 in the internal memory, and display the image data read from the internal memory on the display panel 300.

[0051] In an exemplary embodiment, the internal memory update condition may include a case where an event triggered by a user (e.g., generation of a user input via a button or a touch panel) occurs, a case where an interrupted event occurs on the electronic device (such as reception of a push message of an application), a case where a specific cycle occurs, etc. For example, in the second operation mode, the processor 100 may be activated every hour to send image data representing weather information to the display panel 300. In addition, when external data, such as a short message service (SMS) message, is received, the processor 100 may be activated to send image data representing the content of the received message to the display panel 300. Such an internal memory update condition may be set and changed by a user or a designer.

[0052] refer to Figure 4 , the DDIC 200 may include an interface 210, an image processor 220, a controller 230, a timing controller 240, a gate driver 250, and a source driver 260. The DDIC 200 may further include a first memory 270 as an internal memory.

[0053] DDIC 200 may receive image data from processor 100 via interface 210. DDIC 200 may also receive a timing control signal from processor 100 via interface 210. The timing control signal may include information on horizontal and vertical periods related to gate driver 250 and source driver 260.

[0054] The interface 210 may include a data channel for sending and receiving image data, and a clock channel for sending and receiving timing control signals. In an exemplary embodiment, the interface 210 may be a high-speed serial interface, such as MIPI. Alternatively, the interface 210 may be one of the interfaces according to various standards (e.g., mobile display digital interface (MDDI), embedded display port, etc.).

[0055] Depending on the operating mode of DDIC 200, interface 210 can operate with different clocks. In an exemplary embodiment, when DDIC 200 operates in a first operating mode, interface 210 can operate with a first clock. When DDIC 200 operates in a second operating mode, interface 210 can operate with a second clock having a frequency lower than that of the first clock. For example, in an exemplary embodiment, interface 210 can operate with a 64MHz clock in the first operating mode, and can operate with a 32MHz clock in the second operating mode. Therefore, when switching from the first operating mode to the second operating mode (for example, based on the mode switching signal MODE_CTRL, which will be described in further detail below), the operating clock for interface 210 can be changed.

[0056] The transmission rate of interface 210 may vary depending on the operating mode of DDIC 200. In an exemplary embodiment, the transmission rate of interface 210 in a first operating mode may be higher than the transmission rate of interface 210 in a second operating mode. For example, the transmission rate of interface 210 may be approximately 500 Mbps in the first operating mode, and may be approximately 400 Mbps in the second operating mode. Interface 210 may operate at a lower transmission rate in the second operating mode than in the first operating mode to prevent a tearing effect that may occur when the speed at which image data is updated in the internal memory becomes faster than the speed at which the image data is read. Therefore, image data sent in the second operating mode may be sent at a lower transmission rate than image data sent in the first operating mode.

[0057] When the operation mode switching occurs, the clock and transmission rate of the interface 210 can be changed under the control of the controller 230. In an exemplary embodiment, the controller 230 can change the clock and transmission rate of the interface 210 before the operation mode switching is completed. For example, when the first operation mode is switched to the second operation mode, the controller 230 can change the first clock used for the interface 210 to the second clock before the interface 210 is deactivated. In addition, when the second operation mode is switched to the first operation mode, the controller 230 can change the second clock used for the interface 210 to the first clock before the interface 210 is activated. The controller 230 can change the clock and transmission rate of the interface 210 before the operation mode switching is completed, thereby preventing transmission delays. Therefore, the controller 230 can control whether to activate the interface 210 according to the operation mode of the DDIC 200.

[0058] In the first operation mode, the image data received from the processor 100 may be input to the image processor 220. The timing control signal received from the processor 100 may be input to the timing controller 240.

[0059] When the first operation mode is switched to the second operation mode, the image data received from the processor 100 may be stored in the first memory 270. In the second operation mode, the processor 100 may be activated only when a specific operation condition is satisfied, and the image data received from the activated processor 100 may be stored in the first memory 270. For example, when a message is received or a specific cycle occurs, the DDIC 200 may update the image data stored in the first memory 270 with the image data received from the processor 100.

[0060] The image processor 220 may improve the quality of image data by compensating for degradation of the display panel 300. The image processor 220 may include a pixel data processing circuit, a pre-processing circuit, a gamma correction circuit, and the like.

[0061] In the first operation mode, the image processor 220 may correct image data to be input to the display panel 300 based on correction data stored in the first memory 270 .

[0062] The image data may be a digital value of a specific range, such as an 8-bit value, a 10-bit value, or a 16-bit value, and the correction data may include bit information of the image data to be changed to improve image quality. For example, the correction data may include index information of a bit to be changed among the bit values ​​included in the image data.

[0063] The correction data may be set in advance in consideration of panel characteristics, process parameters, etc. of the display panel 300, and may be stored in the second memory 400, which is arranged outside the DDIC 200. In an exemplary embodiment, the second memory 400 is an external memory of the DDIC 200, and may be a non-volatile memory such as, for example, a NAND flash memory. When the DDIC 200 enters the first operation mode, the correction data stored in the second memory 400 may be copied to the first memory 270 included in the DDIC 200.

[0064] The controller 230 may control the DDIC 200 to display certain image data on the display panel 300 according to an operation mode of the DDIC 200 .

[0065] For example, in the first operation mode, the controller 230 may control the image processor 220 to correct the image data received from the processor 100 based on the correction data stored in the first memory 270. In addition, the controller 230 may control the timing controller 240 to input the corrected image data to the display panel 300. In this case, the timing controller 240 may control the gate driver 250 and the source driver 260 using the timing control signal generated by the processor 100.

[0066] In the second operation mode, the controller 230 may control the first memory 270 to store image data that is not displayed on the display panel 300 among the image data received from the processor 100. In addition, the controller 230 may control the timing controller 240 to input the image data stored in the first memory 270 to the display panel 300. In this case, the timing controller 240 may control the gate driver 250 and the source driver 260 using the horizontal period and the vertical period determined by the timing controller 240.

[0067] In the second operation mode, when the internal memory update condition is satisfied, the controller 230 may control the first memory 270 to store the image data received from the processor 100. In an exemplary embodiment, the internal memory update condition may include a case where a specific event (such as reception of a message) occurs, a case where a specific cycle occurs, etc., and may be variously preset and changed by a user or a designer.

[0068] In the second operation mode, when the internal memory update condition is met, the controller 230 may send a control signal to the interface 210 to temporarily activate the processor 100 and the interface 210. In this case, the interface 210 may send a control signal to the processor 100, and the processor 100 may temporarily activate the processor 100 in response to the control signal to send the image data to be updated. In the second operation mode, the image data received from the processor 100 may be stored in the first memory 270.

[0069] In an exemplary embodiment, the image data stored in the first memory 270 may be data compressed using an image compression algorithm. For example, in the second operation mode, the image data received from the processor 100 may be compressed using a High Efficiency Video Coding (HEVC) algorithm, a Future Video Coding (FVC) algorithm, etc., and stored in the first memory 270.

[0070] When a specific mode switching condition is satisfied, the operation mode of the DDIC 200 may be switched. In an exemplary embodiment, the mode switching condition may include: a case where the movement of the electronic device including the DDIC 200 has a predetermined pattern, a case where a user input is generated via a touch panel or the like, or a case where no user input occurs for a specific period of time or longer, a case where the battery power level decreases to a predetermined threshold or lower, a case where the number of output frames of image data is greater than or equal to a predetermined threshold, etc.

[0071] When switching the operation mode of the DDIC 200, the controller 230 may control the operation of the components using the mode switching signal MODE_CTRL. In an exemplary embodiment, when the mode switching signal MODE_CTRL changes from a logic high to a logic low, the operation mode of the DDIC 200 may be switched from a first operation mode to a second operation mode. When the mode switching signal MODE_CTRL changes from a logic low to a logic high, the operation mode of the DDIC 200 may be switched from a second operation mode to a first operation mode. In each of the above cases, the time point at which the mode switching signal MODE_CTRL changes may be regarded as a time point at which the operation mode switching is requested. Reference Figure 5The relationship between the mode switching signal MODE_CTRL and the operation mode switching is described. In an exemplary embodiment, when the DDIC 200 operates in the first operation mode, the mode switching signal MODE_CTRL may be received from the processor 100, and when the DDIC 200 operates in the second operation mode, the mode switching signal MODE_CTRL may be generated by the controller 230.

[0072] In an exemplary embodiment, when the mode switching signal MODE_CTRL changes from logic low to logic high (rather than from logic high to logic low), the operation mode of the DDIC 200 may be switched from the first operation mode to the second operation mode.

[0073] In an exemplary embodiment, in response to the DDIC 200 receiving the mode switching signal MODE_CTRL for switching the DDIC 200 from the first operation mode (eg, normal mode) to the second operation mode (eg, sleep mode), the second image data 22 (refer to FIG. 1 ) received from the processor 100 is received. Figure 1 ) may be stored in the first memory 170. The second image data 22 may be displayed on the display panel 300 in the second operation mode (eg, sleep mode).

[0074] Figure 5 A case is shown where the DDIC 200 operates in the order of the first operation mode, the second operation mode, and the first operation mode.

[0075] refer to Figure 5 , in the first operation mode, the mode switching signal MODE_CTRL may be logic high.

[0076] When a mode change event occurs to switch from the first operation mode to the second operation mode, the mode switching signal MODE_CTRL may change from logic high to logic low under the control of the user or the processor 100 (operation a). In this case, the controller 230 may turn off the display (operation b), store the image data received from the processor 100 in the first memory 270 (operation c), and deactivate the interface 210 (operation d). When the interface 210 is deactivated, the mode switching is completed and the DDIC 200 operates in the second operation mode (operation e).

[0077] When a mode change event occurs to switch from the second operation mode to the first operation mode, the mode switching signal MODE_CTRL may change from logic low to logic high under the control of the user or the processor 100 (operation f). In this case, the controller 230 may turn on the display (operation g), copy the correction data stored in the second memory 400 to the first memory 270 (operation h), and activate the interface 210 (operation i). When the interface 210 is activated, the mode switching is completed and the DDIC 200 operates in the first operation mode (operation j).

[0078] The timing controller 240 may control the gate driver 250 and the source driver 260 to input image data to the pixels of the display panel 300 .

[0079] The timing controller 240 may control the operation timing of the gate driver 250 and the source driver 260 using a timing control signal. In the first operation mode, the timing control signal may be generated by the processor 100 and transmitted to the timing controller 240. In contrast, in the second operation mode, the timing control signal may be generated by the timing controller 240. That is, in the second operation mode, the timing controller 240 may control the gate driver 250 and the source driver 260 using a horizontal period and a vertical period determined by the timing controller 240. Therefore, while operating in the second operation mode, displaying image data on the display panel 300 may be performed under the timing control of the DDIC 200. Therefore, in an exemplary embodiment, the corrected first image data 21 (refer to Figure 1 ) is displayed on the display panel 300, and the second image data 22 (reference image data 22) may be displayed on the display panel 300 under the timing control of the DDIC 200 (via the timing controller 240 included in the DDIC 200) in the second operation mode. Figure 1 ) is displayed on the display panel 300.

[0080] Although in Figure 4 Controller 230 and timing controller 240 are shown as separate components in FIG. 1 , but exemplary embodiments are not limited thereto. For example, in exemplary embodiments, controller 230 and timing controller 240 may be integrally formed as a single component.

[0081] Figure 6 and Figure 7 is a diagram illustrating the operation of a DDIC according to an exemplary embodiment.

[0082] Figure 6 A process of displaying image data when the DDIC operates in a first operation mode (eg, normal mode) is shown.

[0083] refer to Figure 6 , in the first operation mode, all components of the processor 100 and the DDIC 200 may be activated.

[0084] Image data received from the processor 100 via the interface 210 may be input to the image processor 220 .

[0085] When the DDIC 200 enters the first operation mode, the correction data stored in the second memory 400 may be copied to the first memory 270. In this case, the first memory 270 may be used as a lookup table for correcting image data to improve image quality.

[0086] The correction data stored in the first memory 270 may be input to the image processor 220 under the control of the controller 230 .

[0087] The image processor 220 may correct the image data based on the correction data stored in the first memory 270. In an exemplary embodiment, the correction data may include index information of at least one bit to be changed among the bit values ​​included in the image data. The correction data may be set in advance in consideration of panel characteristics, process parameters, etc. of the display panel 300, and the correction data may be stored in the second memory 400 outside the DDIC 200.

[0088] The image processor 220 may output the corrected image data to the timing controller 240 .

[0089] The timing controller 240 may control the gate driver 250 and the source driver 260 using the timing control signal received from the processor 100 to display the corrected image data on the display panel 300 .

[0090] Figure 7 A process of displaying image data when the DDIC operates in the second operation mode (eg, sleep mode) is shown.

[0091] refer to Figure 7 In the second operation mode, some components of the processor 100 and the DDIC 200 may be disabled. For example, the processor 100 and the interface 210 may be disabled in the second operation mode.

[0092] When the DDIC 200 enters the second operation mode, the image data received from the processor 100 via the interface 210 may be copied to the first memory 270. In this case, the first memory 270 may be used as a display buffer. Therefore, instead of implementing a separate memory in the DDIC for use as a display buffer in the sleep mode as in the case of the comparative example, according to an exemplary embodiment, the first memory 270 may be used as a display buffer in the sleep mode.

[0093] In an exemplary embodiment, when a specific internal memory update condition is satisfied, the image data stored in the first memory 270 may be updated with the image data received from the processor 100. For example, when a specific cycle occurs or an event such as reception of a message occurs, the controller 230 may temporarily activate the interface 210 and control the first memory 270 to store the image data received from the processor 100.

[0094] The controller 230 may transmit the image data stored in the first memory 270 to the timing controller 240 via the image processor 220 .

[0095] The timing controller 240 may display image data on the display panel 300 by controlling the gate driver 250 and the source driver 260 using the horizontal period and the vertical period determined by the timing controller 240 .

[0096] Figure 8 and Fig. 9 is a flow chart illustrating a process of switching between operating modes, the process being performed by a DDIC, according to an exemplary embodiment.

[0097] Figure 8 A process of switching a DDIC from a first operating mode to a second operating mode is shown.

[0098] refer to Figure 8 In operation S810, the controller 230 may identify whether the DDIC 200 is switched from the first operation mode to the second operation mode. In an exemplary embodiment, the controller 230 may identify whether the DDIC 200 is switched from the first operation mode to the second operation mode by identifying whether the mode switching signal MODE_CTRL changes. For example, when the mode switching signal MODE_CTRL changes from a logic high to a logic low, it may be determined that the DDIC 200 is switched from the first operation mode to the second operation mode.

[0099] In operation S820, when it is determined in operation S810 that the DDIC 200 is switched to the second operation mode ("Yes"), the first memory 270 may store the image data received from the processor 100, and the process may proceed to operation S830. In an exemplary embodiment, when the mode switching signal MODE_CTRL changes, the image data stored in the first memory 270 may be the image data received from the processor 100.

[0100] In the second operation mode, the use of the first memory 270 for storing correction data to be used for correcting image data in the first operation mode may be switched to perform a function of a display buffer to store image data to be displayed on the display panel 300 .

[0101] In an exemplary embodiment, the image data may include a plurality of frames. In this case, the image data stored in the first memory 270 may include at least one frame that is not displayed on the display panel 300 among the plurality of frames received from the processor 100. The frames received from the processor 100 may be sequentially displayed on the display panel 300. In this case, image data received later than the image data displayed on the display panel 300 may be stored in the first memory 270.

[0102] In an exemplary embodiment, the first image data 21 (refer to Figure 1 ) includes a plurality of frames, and the second image data 22 (reference Figure 1 ) includes at least one frame among the plurality of frames that is not displayed on the display panel 300.

[0103] In an exemplary embodiment, the first image data 21 (refer to Figure 1 ) is corrected using the correction data stored in the first memory 270 and is displayed on the display panel 300. In response to the mode switching signal MODE_CTRL, at least one image frame among the plurality of image frames in the first memory 270 that is not displayed on the display panel 300 is used as the second image data 22 (reference Figure 1 The second image data 22 may be updated using the third image data received from the processor 100 in response to an update condition such as the above-described update condition being satisfied.

[0104] In an exemplary embodiment, the image data stored in the first memory 270 may be data compressed using an image compression algorithm. For example, in the second operation mode, the image data received from the processor 100 may be compressed using an HEVC algorithm, an FVC algorithm, etc., and then stored in the first memory 270.

[0105] When it is determined in operation S810 that the DDIC 200 is not switched to the second operation mode (eg, when the DDIC 200 is not currently in the second operation mode) (No), the controller 230 may repeat operation S810 until it is determined that the DDIC 200 is switched to the second operation mode.

[0106] In operation S830, the controller 230 may deactivate the interface 210. When the interface 210 is deactivated, the process of switching from the first operation mode to the second operation mode may be completed.

[0107] In the second operation mode, when a specific internal memory update condition is satisfied, the processor 100 and the interface 210 may be temporarily activated. In this case, the DDIC 200 may receive image data from the processor 100 via the temporarily activated interface 210 and store the image data in the first memory 270.

[0108] In operation S840 , the DDIC 200 may operate in the second operation mode and display the image data stored in the first memory 270 on the display panel 300 .

[0109] Table 1 below shows results of simulating power consumption of a DDIC having a separate display buffer in a sleep mode according to a comparative example and power consumption of a DDIC according to an exemplary embodiment.

[0110] [Table 1]

[0111]

[0112] Table 1 shows the results of power consumption measurement of each of the above DDICs while changing the display pattern of the display panel 300 to four types (all white, all black, 2x2 chessboard, and user interface) under the simulated operating conditions of 1.2 Gbps and 30 fps. In Table 1, "all white" indicates a white background, "all black" indicates a black background, "2x2 chessboard" indicates a black and white chessboard of size 2x2, and "user interface" indicates a user interface screen containing time information, date information, etc.

[0113] Table 1 shows that when the display buffer is not included, the power consumption of each internal power supply of each of the DDICs for all four display patterns and the total power consumption of each of the DDICs are reduced by about 10% or more compared to when the separate display buffer for the sleep mode is included. As described above, in the DDIC according to the exemplary embodiment, a separate display buffer for the sleep mode is not included, but an internal memory for storing correction data can be used as a display buffer for the sleep mode, thereby reducing power consumption.

[0114] Fig. 9 A process of switching the DDIC from the second operation mode to the first operation mode is shown.

[0115] refer to Fig. 9 , in operation S910, the controller 230 may identify whether the DDIC 200 is switched from the second operation mode to the first operation mode.

[0116] In operation S920, when it is determined in operation S910 that the DDIC 200 is switched to the first operation mode (YES), the controller 230 may copy the correction data stored in the second memory 400 to the first memory 270, and then the process may proceed to operation S930.

[0117] In the first operation mode, the use of the first memory 270 for storing image data to be displayed on the display panel 300 in the second operation mode can be switched to a function of performing a lookup table to be used for correcting the image data. As described above, in the DDIC 200 according to the exemplary embodiment, one internal memory 270 can be used as an image correction memory or a buffer memory according to the operation mode, thereby reducing the size and power consumption of the DDIC 200.

[0118] When it is determined in operation S910 that the DDIC 200 is not switched to the first operation mode (eg, when the DDIC 200 is not currently in the first operation mode) (No), the controller 230 may repeat operation S910 until it is determined that the DDIC 200 is switched to the first operation mode.

[0119] In operation S930, the controller 230 may activate the interface 210. When the interface 210 is activated, a process of switching from the second operation mode to the first operation mode may be completed.

[0120] In operation S940 , the DDIC 200 may operate in the first operation mode and display image data received from the processor 100 via the interface 210 on the display panel 300 .

[0121] In the first operation mode, the DDIC 200 may continuously receive a plurality of pieces of image data from the processor 100. In this case, the controller 230 may sequentially display the image data continuously received from the processor 100 on the display panel 300.

[0122] Fig.10 is a block diagram of an electronic device including a display device according to an exemplary embodiment.

[0123] refer to Fig.10 , the electronic device 1000 according to the exemplary embodiment may include a display 1010, a memory 1020, a communication module 1030, a sensor module 1040, a processor 1050, etc. Examples of the electronic device 1000 may include not only mobile devices such as smart phones, tablet computers, and laptop computers, but also devices such as televisions, desktop computers, etc. Components such as the display 1010, the memory 1020, the communication module 1030, the sensor module 1040, and the processor 1050 may communicate with each other via a bus 1060.

[0124] The display 1010 may include a DDIC and a display panel. In an exemplary embodiment, the DDIC uses an internal memory (which is used as a lookup table for image correction in a normal mode) as a display buffer for storing image data in a sleep mode, thereby being able to process image data in the sleep mode without using a separate display buffer. In addition, the DDIC may use the internal memory as a lookup table for image correction or a display buffer according to an operation mode, thereby reducing the size and power consumption of the DDIC.

[0125] As is conventional in the field of the present disclosure, exemplary embodiments are described in terms of functional blocks, units and / or modules and are shown in the accompanying drawings. Those skilled in the art will recognize that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units and / or modules are implemented by a microprocessor or the like, the blocks, units and / or modules can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software.

[0126] As described above, in the DDIC according to exemplary embodiments, an internal memory used as a lookup table for image correction in a normal mode is used as an image data storage memory in a sleep mode, and thus, image data may be processed without a separate display buffer in the sleep mode.

[0127] In addition, in the DDIC according to the exemplary embodiment, the internal memory may be used as a lookup table or a display buffer for image correction according to an operation mode, thereby reducing the size and power consumption of the DDIC.

[0128] While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.

Claims

1. An operating method of a display driver integrated circuit DDIC, the operating method comprising: correcting first image data using correction data in a first operating mode, wherein the first image data is received from a processor via an interface and the correction data is stored in a first memory included in the DDIC in the first operating mode; In response to a mode switching signal controlling the DDIC to switch to a second operation mode, second image data received from the processor is stored in the first memory in the second operation mode; and The second image data is displayed on a display panel in the second operation mode.

2. The operating method according to claim 1, further comprising: The second image data is updated using third image data in the second operating mode, wherein the third image data is received from the processor.

3. The operating method according to claim 1, wherein: The first image data includes a plurality of frames, and The second image data includes at least one frame among the plurality of frames that is not displayed on the display panel.

4. The operating method according to claim 1, further comprising: The interface is disabled in response to the mode switching signal controlling the DDIC to switch to the second operation mode.

5. The operating method according to claim 1, wherein: The frequency of the operating clock used for the interface in the second operation mode is lower than the frequency of the operating clock used for the interface in the first operation mode.

6. The operating method according to claim 1, further comprising: In response to the mode switching signal controlling the DDIC to switch to the second operation mode, an operation clock for the interface is changed.

7. The operating method according to claim 1, further comprising: Correction data stored in a second memory disposed outside the DDIC is copied to the first memory in response to the mode switching signal controlling the DDIC to switch to the first operation mode.

8. The operating method according to claim 1, wherein: The correction data includes bit index information for correcting at least some of bit values ​​included in the first image data.

9. An operating method of a display driver integrated circuit DDIC, the operating method comprising: correcting first image data using correction data stored in an internal memory of the DDIC, wherein the first image data is received from a processor and includes a plurality of image frames; displaying the corrected first image data on a display panel; In response to a first mode switching signal, storing at least one image frame among the plurality of image frames that is not displayed on the display panel as second image data in the internal memory instead of the correction data; When the update condition is satisfied, receiving third image data from the processor; and The second image data is updated using the third image data.

10. The operating method according to claim 9, wherein: Displaying the corrected first image data on the display panel is performed under the timing control of the processor.

11. The operating method according to claim 9, further comprising: The second image data is displayed on the display panel.

12. The operating method according to claim 11, wherein: Displaying the second image data on the display panel is performed under the timing control of the DDIC.

13. The operating method according to claim 9, further comprising: In response to the second mode switching signal, the correction data stored in the external memory is stored in the internal memory.

14. An operating method of a display driver integrated circuit DDIC, the operating method comprising: receiving first image data and second image data from a processor via an interface; obtaining correction data stored in an internal memory of the DDIC; correcting the first image data using the correction data; displaying the corrected first image data on a display panel; as well as The interface is deactivated and the second image data is stored in the internal memory in place of the correction data.

15. The operating method according to claim 14, wherein: The first image data is received earlier than the second image data.

16. The operating method according to claim 14, further comprising: The second image data is displayed on the display panel under the timing control of the DDIC.

17. The operating method according to claim 14, further comprising: The second image data is updated using third image data received from the processor.

18. The operating method according to claim 17, wherein: A transmission rate of the third image data is lower than a transmission rate of the first image data and a transmission rate of the second image data.

19. The operating method according to claim 14, further comprising: In response to a mode switching signal, correction data stored in an external memory is stored in the internal memory.

20. The operating method according to claim 19, wherein: The mode switching signal changes from logic low to logic high.

21. A display driver integrated circuit DDIC, comprising: an interface, the interface communicating with the processor; a first memory storing correction data for correcting image data received from the processor or the image data, wherein the first memory is connected to the interface; a timing controller that inputs the image data to a display panel in response to a timing control signal; as well as a controller, the controller controlling whether to activate the interface according to an operation mode of the DDIC, Wherein, when the DDIC operates in a first operation mode, the first memory stores the correction data, and when the DDIC operates in a second operation mode, the first memory stores the image data.

22. The DDIC of claim 21, wherein: When the operation mode of the DDIC is changed, the controller changes an operation clock for the interface.

23. The DDIC of claim 21, wherein: The timing control signal is received from the processor when the DDIC operates in the first operating mode, and the timing control signal is generated by the controller when the DDIC operates in the second operating mode.

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