Display device and driving method thereof

Abstract

The present invention discloses a display device and a driving method thereof. The driving method of the display device comprises: supplying a first light-emitting stop pulse having a first pulse width to a pixel during a first frame driven at a first frequency; supplying a second light-emitting stop pulse having a second pulse width to the pixel during a second frame driven at a second frequency; and supplying a third light-emitting stop pulse having a third pulse width to the pixel during a third frame driven at the second frequency. The first frequency is different from the second frequency. The second pulse width is between the first pulse width and the third pulse width.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0044486 filed in the Korean Intellectual Property Office on April 16, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of some example embodiments of the present invention relate to a display device and a driving method thereof. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information has increased. In response to this, the use of display devices such as liquid crystal display devices, organic light emitting display devices, or micro LED display devices is increasing.

[0005] The number of frames to be displayed per second varies according to the driving frequency of the display device. For example, when the display device is driven at a frequency of 60 Hz, the display device can display 60 frames per second. Similarly, when the display device is driven at a frequency of 90 Hz, the display device can display 90 frames per second.

[0006] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0007] Aspects of some example embodiments of the present invention may include a display device and a driving method thereof that may reduce or minimize instantaneous brightness variation when a driving frequency of the display device is changed.

[0008] A driving method for a display device according to some example embodiments of the present invention includes: supplying a first light-emitting stop pulse having a first pulse width to a pixel during a first frame driven at a first frequency; supplying a second light-emitting stop pulse having a second pulse width to the pixel during a second frame driven at a second frequency; and supplying a third light-emitting stop pulse having a third pulse width to the pixel during a third frame driven at the second frequency, wherein the first frequency is different from the second frequency, and the second pulse width is between the first pulse width and the third pulse width.

[0009] According to some example embodiments, the first frequency may be lower than the second frequency, and the second pulse width may be smaller than the first pulse width and larger than the third pulse width.

[0010] According to some example embodiments, during the first frame, at least one light emission stop pulse having a first pulse width may be further supplied to the pixel.

[0011] According to some example embodiments, during a third frame, at least one light emission stop pulse having a third pulse width may be further supplied to the pixel.

[0012] According to some example embodiments, during the second frame, after the second light emission stop pulse, at least one light emission stop pulse having a third pulse width may be further supplied to the pixel.

[0013] According to some example embodiments, during the second frame, after the second light emitting stop pulse, at least one fourth light emitting stop pulse having a fourth pulse width between the second pulse width and the third pulse width may be further supplied to the pixel.

[0014] According to some example embodiments, during the second frame, after the fourth light emission stop pulse, at least one fifth light emission stop pulse having a fifth pulse width less than the fourth pulse width and greater than or equal to the third pulse width may be further supplied to the pixel.

[0015] According to some example embodiments, the first frequency may be higher than the second frequency, and the second pulse width may be greater than the first pulse width and may be less than the third pulse width.

[0016] According to some example embodiments, during the first frame, at least one light emission stop pulse having a first pulse width may be further supplied to the pixel.

[0017] According to some example embodiments, during a third frame, at least one light emission stop pulse having a third pulse width may be further supplied to the pixel.

[0018] According to some example embodiments, during the second frame, after the second light emission stop pulse, at least one light emission stop pulse having a third pulse width may be further supplied to the pixel.

[0019] According to some example embodiments, during the second frame, after the second light emitting stop pulse, at least one fourth light emitting stop pulse having a fourth pulse width between the second pulse width and the third pulse width may be further supplied to the pixel.

[0020] According to some example embodiments, during the second frame, after the fourth light emitting stop pulse, at least one fifth light emitting stop pulse having a fifth pulse width greater than the fourth pulse width and less than or equal to the third pulse width may be further supplied to the pixel.

[0021] A display device according to some example embodiments of the present invention includes: a light emitting driver; a first pixel coupled to a first light emitting line extending from the light emitting driver; and a second pixel connected to a second light emitting line extending from the light emitting driver and different from the first light emitting line. The light emitting driver supplies a first light emission stop pulse having a first pulse width to the first pixel during a first frame driven at a first frequency, supplies a second light emission stop pulse having a second pulse width to the first pixel during a second frame driven at a second frequency, and supplies a third light emission stop pulse having a third pulse width to the first pixel during a third frame driven at the second frequency. The light emitting driver supplies a light emission stop pulse to the second pixel at a different time from the first pixel in each frame. The second pulse width is between the first pulse width and the third pulse width.

[0022] According to some example embodiments, the first frequency may be lower than the second frequency, the second pulse width may be smaller than the first pulse width and larger than the third pulse width, the light emitting driver may further supply at least one light emitting stop pulse having the first pulse width to the first pixel during the first frame, and the light emitting driver may further supply at least one light emitting stop pulse having the third pulse width to the first pixel during the third frame.

[0023] According to some example embodiments, the light emitting driver may further supply at least one light emitting stop pulse having a third pulse width to the first pixel after the second light emitting stop pulse during the second frame.

[0024] According to some example embodiments, the light emitting driver may further supply at least one fourth light emitting stop pulse having a fourth pulse width between the second pulse width and the third pulse width to the first pixel after the second light emitting stop pulse during the second frame, and the light emitting driver may further supply at least one fifth light emitting stop pulse having a fifth pulse width less than the fourth pulse width and greater than or equal to the third pulse width to the first pixel after the fourth light emitting stop pulse during the second frame.

[0025] According to some example embodiments, the first frequency may be higher than the second frequency, the second pulse width may be greater than the first pulse width and less than the third pulse width, the light emitting driver may further supply at least one light emitting stop pulse having the first pulse width to the first pixel during the first frame, and the light emitting driver may further supply at least one light emitting stop pulse having the third pulse width to the first pixel during the third frame.

[0026] According to some example embodiments, the light emitting driver may further supply at least one light emitting stop pulse having a third pulse width to the first pixel after the second light emitting stop pulse during the second frame.

[0027] According to some example embodiments, the light emitting driver may further supply at least one fourth light emitting stop pulse having a fourth pulse width between the second pulse width and the third pulse width to the first pixel after the second light emitting stop pulse during the second frame, and the light emitting driver may further supply at least one fifth light emitting stop pulse having a fifth pulse width greater than the fourth pulse width and less than or equal to the third pulse width to the first pixel after the fourth light emitting stop pulse during the second frame.

[0028] The display device and the driving method thereof according to the present invention can reduce or minimize instantaneous brightness changes when the driving frequency of the display device changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A more complete understanding of the present invention, as well as numerous additional features and aspects of the present invention, will become more apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings, in which like reference numerals refer to like parts, and in which:

[0030] Figure 1 are diagrams illustrating display devices according to some example embodiments of the present invention.

[0031] Figure 2 is a diagram illustrating pixels according to some example embodiments of the present invention.

[0032] Figure 3 is a diagram illustrating a method of driving a pixel according to some example embodiments of the present invention.

[0033] Figure 4 are diagrams illustrating light emitting drivers according to some example embodiments of the present invention.

[0034] Figure 5 is a diagram illustrating light emission levels according to some example embodiments of the present invention.

[0035] Figure 6 2 is a diagram illustrating a driving method of a light emitting stage according to some example embodiments of the present invention.

[0036] Figure 7 is a diagram illustrating instantaneous brightness changes that occur when the driving frequency is changed from a low frequency to a high frequency.

[0037] Figures 8 to 10 is a graphic representation used to minimize or reduce Figure 7 A diagram of aspects of some example embodiments of brightness changes in the case of FIG.

[0038] Figures 11 to 13 is a diagram illustrating an example embodiment for minimizing or reducing brightness variation when a driving frequency is changed from a high frequency to a low frequency. DETAILED DESCRIPTION

[0039] Hereinafter, aspects of some example embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals refer to the same elements throughout the text. However, the present invention may be embodied in various different forms and should not be understood as being limited to the illustrated embodiments herein. On the contrary, these embodiments are provided as examples so that the disclosure is comprehensive and complete, and fully convey the aspects and features of the present invention to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present invention may not be described. Unless otherwise noted, throughout the drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their descriptions may not be repeated. In the drawings, for clarity, the relative sizes of elements, layers and regions may be exaggerated.

[0040] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part without departing from the spirit and scope of the present invention.

[0041] For ease of illustration, spatially relative terms such as "below," "beneath," "below," "beneath," "above," "above," etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the drawings. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, the elements described as being "below" or "below" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the example terms "below" and "below" may encompass both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0042] It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, directly connected to or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. As used herein, the "one" in the singular is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and "comprise" and their variations are used in this specification to indicate the presence of stated features, integral bodies, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their combinations. As used herein, the term "and / or" includes any and all combinations of one or more of the items listed in the association. Expressions such as "at least one of", when located after a column of elements, modify the entire column of elements and do not modify the individual elements in the column.

[0044] As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. In addition, when describing embodiments of the present invention, the use of "may" refers to "one or more embodiments of the present invention." As used herein, the term "use" and variations thereof may be considered synonymous with the term "utilizing" and variations thereof, respectively. In addition, the term "exemplary" means an example or illustration.

[0045] The display device and / or any other related device or component according to the embodiment of the present invention described herein can be implemented using any suitable hardware, firmware (such as application specific integrated circuit), software or a combination of software, firmware and hardware. For example, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel unit. Various components may be formed on an integrated circuit (IC) chip or on a separate IC chip. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or may be formed on a substrate. In addition, the various components of these devices may be processes or threads running on one or more processors, wherein the processor is located in one or more computing devices for executing computer program instructions and interacting with other system components to perform various functions described herein. In addition, those skilled in the art will recognize that the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a specific computing device may be distributed on one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present invention.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined in this article.

[0047] refer to Figure 1 , a display device 10 according to some example embodiments of the present invention includes a timing controller 11 , a data driver 12 , a scan driver 13 , a light emitting driver 14 , and a pixel unit 15 .

[0048] The timing controller 11 may receive the grayscale value and control signal of each frame from the external processor. The timing controller 11 may render the grayscale value so as to correspond to the specification of the display device 10. For example, the external processor may provide a red grayscale value, a green grayscale value, and a blue grayscale value for each unit point. However, for example, when the pixel unit 15 has When the structure (Pentile is a registered trademark of Samsung Display Co., Ltd.), adjacent unit points share pixels, and therefore, pixels may not correspond one-to-one to corresponding gray values. In this case, gray values ​​need to be rendered. When pixels correspond one-to-one to corresponding gray values, gray values ​​may not need to be rendered. Rendered or unrendered gray values ​​can be provided to the data driver 12. The timing controller 11 can provide control signals suitable for each specification to the data driver 12, the scan driver 13, the light emitting driver 14, etc. to display the frame.

[0049] The data driver 12 may generate data voltages to be supplied to the data lines D1, D2, D3 to Dn using the grayscale values ​​and the control signal. For example, the data driver 12 may sample the grayscale values ​​using the clock signal and apply data voltages corresponding to the grayscale values ​​to the data lines D1 to Dn (n may be an integer greater than zero) in units of pixel rows.

[0050] The scan driver 13 may receive a clock signal, a scan start signal, etc. from the timing controller 11 , and generate scan signals (m may be an integer greater than zero) to be supplied to the scan lines S1 , S2 , S3 to Sm.

[0051] The scan driver 13 may supply (e.g., sequentially supply) a scan signal having a pulse of an on level to the scan lines S1, S2, S3 to Sm. The scan driver 13 may include a scan stage configured in the form of a shift register. The scan driver 13 may generate a scan signal in a manner of sequentially transmitting a scan start signal (which is in the form of a pulse of an on level) to a subsequent scan stage under the control of a clock signal.

[0052] The light-emitting driver 14 may receive a clock signal, a light-emitting stop start signal, etc. from the timing controller 11, and generate a light-emitting signal to be provided to the light-emitting lines E1, E2, E3 to Eo. For example, the light-emitting driver 14 may provide (e.g., sequentially provide) a light-emitting signal having a pulse of a cut-off level to the light-emitting lines E1 to Eo. For example, each of the light-emitting stages of the light-emitting driver 14 may be configured in the form of a shift register, and may generate a light-emitting signal in a manner of sequentially transmitting a light-emitting stop start signal (which is a pulse shape of a cut-off level) to a subsequent light-emitting stage under the control of a clock signal. o may be an integer greater than zero.

[0053] The pixel unit 15 includes a plurality of pixels PXij (i and j may be natural numbers). Each of the pixels PXij may be connected to a corresponding data line, a corresponding scan line, and a corresponding light emitting line. In addition, the pixel PXij may be connected to a first power line and a second power line. The pixel PXij may refer to a pixel in which a scan transistor is connected to the i-th scan line and the j-th data line.

[0054] Figure 2 is a diagram illustrating pixels according to some example embodiments of the present invention.

[0055] refer to Figure 2 , the pixel PXij includes transistors T1, T2, T3, T4, T5, T6 and T7, a storage capacitor Cst and a light emitting diode LD.

[0056] Hereinafter, a circuit configured with a P-type transistor will be described as an example. However, those skilled in the art will be able to design a circuit configured with an N-type transistor by setting the polarity of the voltage applied to its gate terminal differently. Similarly, those skilled in the art will be able to design a circuit configured with a combination of a P-type transistor and an N-type transistor. P-type transistors are collectively referred to as transistors in which the current flowing when the voltage difference between the gate electrode and the source electrode increases in the negative direction increases. N-type transistors are collectively referred to as transistors in which the current flowing when the voltage difference between the gate electrode and the source electrode increases in the positive direction increases. Transistors can be formed into various forms, such as thin film transistors (TFTs), field effect transistors (FETs), and bipolar junction transistors (BJTs).

[0057] The transistor T1 has a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The transistor T1 may be referred to as a driving transistor.

[0058] The transistor T2 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the data line Dj, and a second electrode connected to the second node N2. The transistor T2 may be referred to as a scan transistor.

[0059] The transistor T3 may have a gate electrode connected to the i-th scan line Si, a first electrode connected to the first node N1, and a second electrode connected to the third node N3. The transistor T3 may be referred to as a diode-connected transistor.

[0060] The transistor T4 may have a gate electrode connected to the i-1th scan line S(i-1), a first electrode connected to the first node N1, and a second electrode connected to the initialization line INTL. According to some example embodiments, the gate electrode of the transistor T4 may be connected to another scan line. The transistor T4 may be referred to as a gate initialization transistor.

[0061] The transistor T5 may have a gate electrode connected to the i-th emission line Ei, a first electrode connected to the first power line ELVDDL, and a second electrode connected to the second node N2. The transistor T5 may be referred to as a light emitting transistor. According to some example embodiments, the gate electrode of the transistor T5 may be connected to another emission line.

[0062] The transistor T6 may have a gate electrode connected to the i-th emission line Ei, a first electrode connected to the third node N3, and a second electrode connected to the anode of the light emitting diode LD. The transistor T6 may be referred to as a light emitting transistor. According to some example embodiments, the gate electrode of the transistor T6 may also be connected to another emission line.

[0063] The transistor T7 may have a gate electrode connected to the i-th scan line, a first electrode connected to the initialization line INTL, and a second electrode connected to the anode of the light emitting diode LD. The transistor T7 may be referred to as an anode initialization transistor. According to some example embodiments, the gate electrode of the transistor T7 may be connected to another scan line.

[0064] A first electrode of the storage capacitor Cst may be connected to the first power line ELVDDL, and a second electrode may be connected to the first node N1.

[0065] The light emitting diode LD may have an anode connected to the second electrode of the transistor T6 and a cathode connected to the second power line ELVSSL. The light emitting diode LD may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode.

[0066] A first power voltage may be applied to the first power line ELVDDL, a second power voltage may be applied to the second power line ELVSSL, and an initialization voltage may be applied to the initialization line INTL.

[0067] Figure 3 is a diagram illustrating a method of driving a pixel according to some example embodiments of the present invention.

[0068] The data voltage DATA(i-1)j for the i-1th pixel is applied to the data line Dj, and a scan signal of an on level is applied to the i-1th scan line S(i-1).

[0069] Since the scan signal of the off level (high level) is applied to the i-th scan line Si, the transistor T2 is turned off and the data voltage DATA(i-1)j for the i-1-th pixel is prevented from being input to the pixel PXij.

[0070] Since the transistor T4 is turned on, the first node N1 is connected to the initialization line INTL, and the voltage of the first node N1 is initialized. Since the light emitting signal of the off level is applied to the i-th light emitting line Ei, the transistors T5 and T6 are in the off state, and unnecessary light emission of the light emitting diode LD according to the initialization voltage application process is prevented.

[0071] The data voltage DATAij for the i-th pixel PXij is applied to the data line Dj, and the scan signal of the on level is applied to the i-th scan line Si. Therefore, the transistors T2, T1 and T3 are turned on, and the data line Dj is electrically connected to the first node N1. Therefore, the compensation voltage obtained by subtracting the threshold voltage of the transistor T1 from the data voltage DATAij is applied to the second electrode (i.e., the first node N1) of the storage capacitor Cst, and the storage capacitor Cst maintains a voltage corresponding to the difference between the first power supply voltage and the compensation voltage. This period may be referred to as a threshold voltage compensation period.

[0072] At this time, the transistor T7 is in a turned-on state, and therefore, the anode of the light emitting diode LD is connected to the initialization line INTL, and the light emitting diode LD is precharged with an amount of charge corresponding to the voltage difference between the initialization voltage and the second power supply voltage (eg, initialized).

[0073] When a light emission signal of a turn-on level is applied to the i-th light emission line Ei, transistors T5 and T6 may be turned on. Thus, a path of the first power line ELVDDL, transistor T5, transistor T1, transistor T6, light emitting diode LD and the second power line ELVSSL is formed as a driving current path.

[0074] The driving current flowing through the first electrode and the second electrode of the transistor T1 is adjusted according to the voltage held in the storage capacitor Cst. The light emitting diode LD emits light with brightness corresponding to the driving current. The light emitting diode LD emits light until a light emitting signal of a cutoff level is applied to the i-th light emitting line Ei.

[0075] Figure 4 are diagrams illustrating light emitting drivers according to some example embodiments of the present invention.

[0076] For ease of description, Figure 4 Four lighting stages ST1 , ST2 , ST3 and ST4 are illustrated.

[0077] refer to Figure 4 , the light emitting driver 14 according to some example embodiments of the present invention may include a plurality of light emitting stages ST1 to ST4. The light emitting stages ST1 to ST4 may be connected to corresponding light emitting lines E1 to E4, respectively, and may be commonly connected to clock lines CLK1 and CLK2. The light emitting stages ST1 to ST4 may have substantially the same circuit structure.

[0078] Each of the light emitting stages ST1 to ST4 may include a first input terminal 101 , a second input terminal 102 , a third input terminal 103 , and an output terminal 104 .

[0079] The first input terminal 101 may receive an output signal (e.g., a light emitting signal) of a previous light emitting stage or a light emitting stop start signal ESS. For example, the first input terminal 101 of the first light emitting stage ST1 may receive the light emitting stop start signal ESS, and the first input terminals 101 of the remaining light emitting stages ST2 to ST4 may receive light emitting signals of corresponding previous light emitting stages.

[0080] The second input terminal 102 of the j-th (j is an integer) light-emitting stage can be connected to the first clock line CLK1, and the third input terminal 103 of the j-th light-emitting stage can be connected to the second clock line CLK2. The second input terminal 102 of the j+1-th light-emitting stage can be connected to the second clock line CLK2, and the third input terminal 103 of the j+1-th light-emitting stage can be connected to the first clock line CLK1. That is, the first clock line CLK1 and the second clock line CLK2 can be alternately connected to the second input terminal 102 and the third input terminal 103 of each light-emitting stage.

[0081] The pulse of the first clock signal applied to the first clock line CLK1 and the pulse of the second clock signal applied to the second clock line CLK2 do not overlap each other in time. At this time, each of the pulses may be an on level.

[0082] The light emitting stages ST1 to ST4 may receive a first power supply VDD and a second power supply VSS. The first power supply VDD may be set to a voltage of an off level, and the second power supply VSS may be set to a voltage of an on level. The voltage level of the light emitting signal may be determined based on one of the first power supply VDD and the second power supply VSS.

[0083] Figure 5 is a diagram illustrating light emission levels according to some example embodiments of the present invention.

[0084] For ease of description, Figure 5 Two lighting stages ST1 and ST2 are illustrated.

[0085] refer to Figure 5 , the first light emitting stage ST1 according to some example embodiments of the present invention may include an input unit 210 , an output unit 220 , a first signal processing unit 230 , a second signal processing unit 240 , a third signal processing unit 250 , and a first stabilizing unit 260 .

[0086] The output unit 220 may supply the voltage of the first power source VDD or the voltage of the second power source VSS to the output terminal 104 in response to the voltages of the first node Ne1 and the second node Ne2. The output unit 220 may include a transistor M10 and a transistor M11.

[0087] The transistor M10 may be connected between the first power source VDD and the output terminal 104. The gate electrode of the transistor M10 may be connected to the first node Ne1. The transistor M10 may be turned on or off in response to the voltage of the first node Ne1. For example, when the transistor M10 is turned on, the voltage of the first power source VDD supplied to the output terminal 104 may be output as a light emitting signal of a cut-off level through the first light emitting line E1.

[0088] The transistor M11 may be connected between the output terminal 104 and the second power source VSS. The gate electrode of the transistor M11 may be connected to the second node Ne2. The transistor M11 may be turned on or off in response to the voltage of the second node Ne2. For example, when the transistor M11 is turned on, the voltage of the second power source VSS supplied to the output terminal 104 may be output as a light-emitting signal of a turn-on level through the first light-emitting line E1.

[0089] The input unit 210 may control voltages of the third node Ne3 and the fourth node Ne4 in response to signals supplied to the first input terminal 101 and the second input terminal 102. The input unit 210 may include a transistor M7, a transistor M8, and a transistor M9.

[0090] The transistor M7 may be connected between the first input terminal 101 and the fourth node Ne4. The gate electrode of the transistor M7 may be connected to the second input terminal 102. When the first clock signal of the on level is supplied to the second input terminal 102, the transistor M7 may be turned on to electrically connect the first input terminal 101 to the fourth node Ne4.

[0091] The transistor M8 may be connected between the third node Ne3 and the second input terminal 102. A gate electrode of the transistor M8 may be connected to the fourth node Ne4. The transistor M8 may be turned on or off in response to a voltage of the fourth node Ne4.

[0092] The transistor M9 may be connected between the third node Ne3 and the second power supply VSS. The gate electrode of the transistor M9 may be connected to the second input terminal 102. When the first clock signal of the on level is supplied to the second input terminal 102, the transistor M9 may be turned on to supply the voltage of the second power supply VSS to the third node Ne3.

[0093] The first signal processing unit 230 may control the voltage of the first node Ne1 in response to the voltage of the second node Ne2. The first signal processing unit 230 may include a transistor M12 and a third capacitor C3.

[0094] The transistor M12 may be connected between the first power source VDD and the first node Ne1. A gate electrode of the transistor M12 may be connected to the second node Ne2. The transistor M12 may be turned on or off in response to a voltage of the second node Ne2.

[0095] The third capacitor C3 may be connected between the first power source VDD and the first node Ne1. The third capacitor C3 may maintain a voltage applied to the first node Ne1.

[0096] The second signal processing unit 240 may be connected to the fifth node Ne5, and control the voltage of the first node Ne1 in response to the signal supplied to the third input terminal 103. The second signal processing unit 240 may include a transistor M5, a transistor M6, a first capacitor C1, and a second capacitor C2.

[0097] The first capacitor C1 may be connected between the second node Ne2 and the third input terminal 103. The first capacitor C1 may maintain a voltage difference between the third input terminal 103 and the second node Ne2.

[0098] A first terminal of the second capacitor C2 may be connected to the fifth node Ne5, and a second terminal of the second capacitor C2 may be connected to the transistor M5.

[0099] The transistor M5 may be connected between the first node Ne1 and the second terminal of the second capacitor C2. The gate electrode of the transistor M5 may be connected to the third input terminal 103. When the second clock signal is supplied to the third input terminal 103, the transistor M5 may be turned on to electrically connect the second terminal of the second capacitor C2 to the first node Ne1.

[0100] The transistor M6 may be connected between the third input terminal 103 and the second terminal of the second capacitor C2. A gate electrode of the transistor M6 may be connected to the fifth node Ne5.

[0101] The third signal processing unit 250 may control the voltage of the fourth node Ne4 in response to the voltage of the third node Ne3 and the signal supplied to the third input terminal 103. The third signal processing unit 250 may include a transistor M3 and a transistor M4.

[0102] The transistor M3 and the transistor M4 may be connected in series between the first power supply VDD and the fourth node Ne4. The gate electrode of the transistor M3 may be connected to the third node Ne3. The gate electrode of the transistor M4 may be connected to the third input terminal 103.

[0103] The first stabilizing unit 260 may be connected between the second signal processing unit 240 and the input unit 210. The first stabilizing unit 260 may limit the voltage drop width of the third node Ne3 and the fourth node Ne4. The first stabilizing unit 260 may include a transistor M1 and a transistor M2.

[0104] The transistor M1 may be connected between the third node Ne3 and the fifth node Ne5. The gate electrode of the transistor M1 may be connected to the second power supply VSS. The transistor M2 may be connected between the second node Ne2 and the fourth node Ne4. The gate electrode of the transistor M2 may be connected to the second power supply VSS.

[0105] The second light emitting stage ST2 may have substantially the same configuration as the first light emitting stage ST1 except for signals supplied to the first, second, and third input terminals 101, 102, and 103 as described above.

[0106] Figure 6 is a diagram illustrating a method of driving a light emitting stage according to some example embodiments of the present invention.

[0107] Figure 6 A timing diagram referring to the first light emitting stage ST1 is illustrated.

[0108] refer to Figure 6 , the pulses of the first clock signal and the second clock signal are illustrated as each having a period of two horizontal periods and appearing in different horizontal periods. For example, the pulse of the second clock signal can be a signal that is shifted by half a period (e.g., one horizontal period 1H) based on the pulse of the first clock signal.

[0109] The light emission stop start pulse ESP of the off level (e.g., high level) of the light emission stop start signal ESS is set to overlap at least once with the pulse of the low level of the first clock signal supplied to the second input terminal 102. The light emission stop start pulse ESP may be supplied with a width greater than the width of the pulse of the first clock signal (e.g., supplied with four horizontal periods 4H). The pulse P1 of the first light emission signal supplied to the first input terminal 101 of the second light emission stage ST2 may also overlap at least once with the pulse of the low level of the clock signal supplied to the second input terminal 102 of the second light emission stage ST2.

[0110] The first clock signal of a low level is supplied to the second input terminal 102 at the first time point te1. For example, a pulse may be generated in the first clock signal. Therefore, the transistor M7 and the transistor M9 may be turned on.

[0111] When the transistor M7 is turned on, the first input terminal 101 may be electrically connected to the fourth node Ne4. Since the transistor M2 maintains a turned-on state, the first input terminal 101 may be electrically connected to the second node Ne2 through the fourth node Ne4. The light emission stop start signal ESS of a high level is not supplied to the first input terminal 101 at the first time point te1, and therefore, a voltage of a low level (e.g., VSS) may be supplied to the fourth node Ne4 and the second node Ne2.

[0112] When a voltage of a low level is supplied to the second node Ne2 and the fourth node Ne4, the transistor M8, the transistor M11, and the transistor M12 may be turned on.

[0113] When the transistor M12 is turned on, the voltage of the first power source VDD is supplied to the first node Ne1, and thus, the transistor M10 may be turned off.

[0114] When the transistor M11 is turned on, the voltage of the second power source VSS may be supplied to the output terminal 104. Therefore, a low-level light emitting signal may be supplied to the first light emitting line E1 at the first time point te1.

[0115] When the transistor M8 is turned on, the first clock signal is supplied to the third node Ne3. Since the transistor M1 maintains a turned-on state, the first clock signal can be supplied to the fifth node Ne5 through the third node Ne3.

[0116] When the transistor M9 is turned on, the voltage of the second power supply VSS is supplied to the third node Ne3 and the fifth node Ne5. For example, the first clock signal may be at a low level, and therefore, the third node Ne3 and the fifth node Ne5 may be charged with (e.g., stably charged with) the voltage of the second power supply VSS. Therefore, the transistor M3 and the transistor M6 are turned on.

[0117] When the transistor M6 is turned on, a high-level second clock signal (e.g., VDD) is supplied to the second terminal of the second capacitor C2 from the third input terminal 103. Since the transistor M5 is in the off state, the first node Ne1 can maintain the voltage of the first power supply VDD regardless of the voltages of the fifth node Ne5 and the second terminal of the second capacitor C2.

[0118] When the transistor M3 is turned on, the voltage of the first power source VDD may be supplied to the transistor M4. At this time, the transistor M4 is in a turned-off state, and thus, the fourth node Ne4 may maintain a low level.

[0119] At the second time point te2, the high-level first clock signal is supplied to the second input terminal 102. For example, the pulse may disappear in the first clock signal. Therefore, the transistor M7 and the transistor M9 may be turned off. At this time, the second node Ne2 and the first node Ne1 may maintain the previous voltage through the first capacitor C1 and the third capacitor C3, and the transistor M8, the transistor M11 and the transistor M12 remain in the on state.

[0120] When the transistor M8 is turned on, the first clock signal of a high level is supplied to the third node Ne3 and the fifth node Ne5 from the second input terminal 102. Therefore, the transistor M3 and the transistor M6 are set to a cut-off state.

[0121] At the third time point te3, the second clock signal of the low level is supplied to the third input terminal 103. For example, a pulse is generated in the second clock signal. Therefore, the transistor M4 and the transistor M5 are turned on.

[0122] If the transistor M5 is turned on, the second terminal of the second capacitor C2 is electrically connected to the first node Ne1. Since the transistor M12 is in the on state, the first node Ne1 maintains the voltage of the first power source VDD.

[0123] When the transistor M4 is turned on, the second electrode of the transistor M3 is electrically connected to the second node Ne2. Since the transistor M3 is in an off state, the voltage of the first power source VDD is not supplied to the fourth node Ne4 and the second node Ne2.

[0124] When the second clock signal of the low level is supplied to the third input terminal 103, the voltage of the second node Ne2 drops to a voltage lower than the voltage of the second power supply VSS through the coupling of the first capacitor C1. Therefore, the voltage applied to the gate electrode of the transistor M11 and the gate electrode of the transistor M12 drops to a voltage lower than the voltage of the second power supply VSS, and thus, the driving characteristics of the transistors can be improved.

[0125] Regardless of the voltage drop of the second node Ne2, the fourth node Ne4 can substantially maintain the voltage of the second power supply VSS due to the transistor M2. Since the voltage of the second power supply VSS is continuously applied to the gate electrode of the transistor M2, the voltage of the fourth node Ne4 corresponding to the source electrode of the transistor M2 does not drop to a voltage lower than a value obtained by adding the threshold voltage to the voltage of the second power supply VSS. Therefore, the voltage difference between the first electrode and the second electrode of the transistor M7 is reduced (e.g., minimized), and thus, the characteristic change of the transistor M7 can be prevented.

[0126] At the fourth time point te4, the light emission stop start pulse ESP is supplied to the first input terminal 101, and the low-level first clock signal is supplied to the second input terminal 102. For example, a pulse is generated in the first clock signal. Therefore, the transistor M7 and the transistor M9 are turned on.

[0127] When the transistor M7 is turned on, the first input terminal 101 is electrically connected to the fourth node Ne4 and the second node Ne2. Therefore, the fourth node Ne4 and the second node Ne2 are charged with a high level voltage, and the transistors M8, M11, and M12 are turned off.

[0128] When the transistor M9 is turned on, the voltage of the second power supply VSS is supplied to the third node Ne3 and the fifth node Ne5, and the transistors M3 and M6 are turned on. At this time, even when the transistor M3 is turned on, since the transistor M4 is in the off state, the voltage of the fourth node Ne4 is maintained.

[0129] When the transistor M6 is turned on, the second terminal of the second capacitor C2 is electrically connected to the third input terminal 103. Since the transistor M5 is in a turned-off state, the first node Ne1 maintains a voltage of a high level.

[0130] At the fifth time point te5, the low-level second clock signal is supplied to the third input terminal 103. Therefore, the transistors M4 and M5 are turned on. Since the third node Ne3 and the fifth node Ne5 are charged with the voltage of the second power supply VSS, the transistors M3 and M6 are in the on state.

[0131] The second clock signal of low level is applied to the first node Ne1 through the turned-on transistors M5 and M6, and the transistor M10 is turned on. If the transistor M10 is turned on, the voltage of the first power supply VDD is supplied to the output terminal 104 as a light emitting signal. Therefore, the light emitting signal of high level can be supplied to the first light emitting line E1. For example, the first light emitting stop pulse P1 can be supplied to the first light emitting line E1.

[0132] When the transistor M3 and the transistor M4 are turned on, the voltage of the second power source VDD is supplied to the fourth node Ne4 and the second node Ne2. Therefore, the transistor M8 and the transistor M11 can stably maintain the off state.

[0133] When the second clock signal of the low level is supplied to the second terminal of the second capacitor C2, the voltage of the fifth node Ne5 drops to a voltage lower than the voltage of the second power supply VSS through coupling of the second capacitor C2. Therefore, the voltage applied to the gate electrode of the transistor M6 drops to a voltage lower than the voltage of the second power supply VSS, and therefore, the driving characteristics of the transistor M6 can be improved.

[0134] Regardless of the voltage of the fifth node Ne5, the voltage of the third node Ne3 can be substantially maintained at the voltage of the second power supply VSS through the transistor M1. Since the voltage of the second power supply VSS is continuously applied to the gate electrode of the transistor M1, the voltage of the third node Ne3 corresponding to the source electrode of the transistor M1 does not drop to a voltage lower than or equal to a voltage obtained by adding a threshold voltage to the voltage of the second power supply VSS. Therefore, regardless of the voltage drop of the fifth node Ne5, the third node Ne3 can substantially maintain the voltage of the second power supply VSS. In this case, the voltage difference between the source electrode and the drain electrode of the transistor M8 is reduced (e.g., minimized), and thus the characteristic change of the transistor M8 can be prevented.

[0135] At the sixth time point te6, the first clock signal of the low level is supplied to the second input terminal 102. Therefore, the transistor M7 and the transistor M9 are turned on. At this time, the supply of the light emission stop start pulse ESP may be stopped.

[0136] When the transistor M7 is turned on, the fourth node Ne4 and the second node Ne2 are electrically connected to the first input terminal 101, and thus, a low level voltage from the first input terminal 101 is supplied to the fourth node Ne4 and the second node Ne2. Therefore, the transistors M8, M11, and M12 are turned on.

[0137] When the transistor M8 is turned on, the first clock signal of a low level is supplied to the third node Ne3 and the fifth node Ne5.

[0138] When the transistor M12 is turned on, the voltage of the first power source VDD is supplied to the first node Ne1, and the transistor M10 is turned off.

[0139] When the transistor M11 is turned on, the voltage of the second power source VSS is supplied to the output terminal 104. Therefore, a low-level light emission signal may be supplied to the first light emission line E1. For example, supply of the first light emission stop pulse P1 to the first light emission line E1 may be stopped.

[0140] The second light emitting stage ST2 receiving the light emitting signal from the output terminal 104 of the first light emitting stage ST1 also supplies the light emitting signal to the second light emitting line E2 while repeating the above process. For example, the light emitting stage according to some example embodiments of the present invention may sequentially supply the light emitting stop pulse to the light emitting lines E1 to Eo while repeating the above process.

[0141] According to the above description, by adjusting the width of the luminescence stop start pulse ESP (for example, the interval between the fourth time point te4 and the sixth time point te6), the width of the luminescence stop pulses P1, P2 and P3 of the cutoff level of the luminescence signal can be adjusted.

[0142] Figure 7 is a diagram illustrating instantaneous brightness changes that occur when the driving frequency is changed from a low frequency to a high frequency.

[0143] The display device 10 may be driven at a first frequency in the first frame LFF1 and the previous frame. The display device 10 may be driven at a second frequency after the first frame LFF1. For example, the display device 10 may be driven at a second frequency in the second frame HFF2, the third frame HFF3, and subsequent frames. Here, the first frequency and the second frequency may be different from each other.

[0144] exist Figure 7 In the example, the case where the first frequency is lower than the second frequency will be described. Figure 7 As shown in , the display device 10 may be driven at a low frequency until a first frame LFF1 , and may be driven at a high frequency after a second frame HFF2 .

[0145] In the first frame LFF1 driven at the first frequency, the light emitting driver 14 may supply a first light emitting stop pulse having a first pulse width PW1 to the pixel through the first light emitting line E1.

[0146] In the second frame HFF2 driven at the second frequency, the light emitting driver 14 may supply a second light emitting stop pulse having a second pulse width PW2 to the pixel through the first light emitting line E1.

[0147] In the third frame HFF3 driven at the second frequency, the light emitting driver 14 may supply a third light emitting stop pulse having a third pulse width PW3 to the pixel through the first light emitting line E1.

[0148] The second frame period of the second frame HFF2 driven at a high frequency is shorter than the first frame period of the first frame LFF1 driven at a low frequency. Therefore, in order to adjust the emission duty cycle, the second pulse width PW2 in the second frame period may be shorter than the first pulse width PW1. The emission duty cycle may refer to the ratio between the light-emitting period and the non-emitting period of the light-emitting diode in one cycle. The third pulse width PW3 in the third frame HFF3 driven at the second frequency may be equal to the second pulse width PW2. The third frame period of the third frame HFF3 may be equal to the second frame period.

[0149] A frequency mixing period FMP in which the first frame period overlaps with the second frame period may occur. In the frequency mixing period FMP, the first pulse width PW1 corresponding to the first frequency and the second pulse width PW2 corresponding to the second frequency may exist at the same time. Therefore, the light emitting diode of the pixel unit 15 can be driven at different emission duty ratios, and the user can visually recognize instantaneous brightness changes such as flickering phenomena.

[0150] Figures 8 to 10 Is a graphic used to minimize Figure 7 A diagram of aspects of some example embodiments of brightness changes in the case of FIG.

[0151] First, we will describe Figure 8 Aspects of example embodiments of the present invention.

[0152] In the first frame LFF1a driven at the first frequency, the light emitting driver 14 may supply a first light emitting stop pulse P1a having a first pulse width PW1a to the pixel through the first light emitting line E1.

[0153] In the second frame HFF2a driven at the second frequency, the light emitting driver 14 may supply the second light emitting stop pulse P2a having the second pulse width PW2a to the pixel through the first light emitting line E1.

[0154] In the third frame HFF3 a driven at the second frequency, the light emitting driver 14 may supply the third light emitting stop pulse P3 a having the third pulse width PW3 a to the pixel through the first light emitting line E1 .

[0155] The first frequency and the second frequency may be different from each other. For example, the first frequency may be lower than the second frequency.

[0156] The second pulse width PW2a may be between the first pulse width PW1a and the third pulse width PW3a. For example, the second pulse width PW2a may be smaller than the first pulse width PW1a, and may be larger than the third pulse width PW3a.

[0157] According to some example embodiments, a difference in the emission duty ratio between the first frame LFF1a and the second frame HFF2a is reduced in the frequency mixing period FMPa, and thus, an instantaneous brightness variation may be reduced.

[0158] According to some example embodiments, the timing controller 11 may increase the grayscale value of the second frame HFF2a so as to compensate for the reduced emission duty ratio of the second frame HFF2a. For example, the timing controller 11 may increase the grayscale value of the second frame HFF2a received from the external processor and provide the grayscale value to the data driver 12. The timing controller 11 may maintain the grayscale values ​​of the first frame LFF1a and the third frame HFF3a received from the external processor and provide them to the data driver 12.

[0159] We will now describe Fig. 9 Aspects of example embodiments of the present invention.

[0160] In the first frame LFF1 b driven at the first frequency, the light emitting driver 14 may supply the first light emitting stop pulse P11 b having the first pulse width PW11 b to the pixel through the first light emitting line E1 .

[0161] In the second frame HFF2b driven at the second frequency, the light emitting driver 14 may supply the second light emitting stop pulse P2b having the second pulse width PW2b to the pixel through the first light emitting line E1.

[0162] In the third frame HFF3 b driven at the second frequency, the light emitting driver 14 may supply the third light emitting stop pulse P31 b having the third pulse width PW31 b to the pixel through the first light emitting line E1 .

[0163] The first frequency and the second frequency may be different from each other. For example, the first frequency may be lower than the second frequency.

[0164] The second pulse width PW2b may be between the first pulse width PW11b and the third pulse width PW31b. For example, the second pulse width PW2b may be smaller than the first pulse width PW11b, and may be larger than the third pulse width PW31b.

[0165] In the first frame LFF1b, the light emitting driver 14 may further supply at least one of light emitting stop pulses P12b and P13b having the same pulse widths PW12b and PW13b as the first pulse width PW11b to the pixel through the first light emitting line E1.

[0166] In the third frame HFF3 b , the light emitting driver 14 may further supply at least one of the light emitting stop pulses P32 b and P33 b having the same pulse widths PW32 b and PW33 b as the third pulse width PW31 b to the pixel through the first light emitting line E1 .

[0167] In the second frame HFF2b, the light emitting driver 14 may further supply at least one of light emitting stop pulses P4b and P5b having the same pulse widths PW4b and PW5b as the third pulse width PW31b to the pixel through the first light emitting line E1 after the second light emitting stop pulse P2b.

[0168] According to some example embodiments, a difference in the emission duty ratio between the first frame LFF1b and the second frame HFF2b is reduced in the frequency mixing period FMPb, and thus, an instantaneous brightness variation may be reduced.

[0169] For example, when each of the luminous signals includes Fig. 9 When the plurality of light stop pulses shown in the second frame HFF2b are adjusted, the front light stop pulse P2b among the plurality of light stop pulses in the second frame HFF2b is very important in the frequency mixing period FMPb. Therefore, by adjusting only the pulse width PW2b of the front light stop pulse P2b in the second frame HFF2b, the instantaneous brightness change can be reduced.

[0170] According to some example embodiments, the timing controller 11 may increase the grayscale value of the second frame HFF2b so as to compensate for the reduced emission duty cycle of the second frame HFF2b. For example, the timing controller 11 may increase the grayscale value of the second frame HFF2b received from the external processor and provide the grayscale value to the data driver 12. The timing controller 11 may maintain the grayscale values ​​of the first frame LFF1b and the third frame HFF3b received from the external processor and provide them to the data driver 12.

[0171] We will now describe Fig.10 Aspects of example embodiments of the present invention.

[0172] In the first frame LFF1 c driven at the first frequency, the light emitting driver 14 may supply a first light emitting stop pulse P11 c having a first pulse width PW11 c to the pixel through the first light emitting line E1 .

[0173] In the second frame HFF2c driven at the second frequency, the light emitting driver 14 may supply the second light emitting stop pulse P2c having the second pulse width PW2c to the pixel through the first light emitting line E1.

[0174] In the third frame HFF3 c driven at the second frequency, the light emitting driver 14 may supply a third light emitting stop pulse P31 c having a third pulse width PW31 c to the pixel through the first light emitting line E1 .

[0175] The first frequency and the second frequency may be different from each other. For example, the first frequency may be lower than the second frequency.

[0176] The second pulse width PW2c may be between the first pulse width PW11c and the third pulse width PW31c. For example, the second pulse width PW2c may be smaller than the first pulse width PW11c, and may be larger than the third pulse width PW31c.

[0177] In the first frame LFF1c, the light emitting driver 14 may further supply at least one of light emitting stop pulses P12c and P13c having the same pulse widths PW12c and PW13c as the first pulse width PW11c to the pixel through the first light emitting line E1.

[0178] In the third frame HFF3c, the light emitting driver 14 may further supply at least one of the light emitting stop pulses P32c and P33c having the same pulse widths PW32c and PW33c as the third pulse width PW31c to the pixel through the first light emitting line E1.

[0179] In the second frame HFF2c, the light emitting driver 14 may further supply at least one fourth light emitting stop pulse P4c having a fourth pulse width PW4c between the second pulse width PW2c and the third pulse width PW31c to the pixel through the first light emitting line E1 after the second light emitting stop pulse P2c.

[0180] In the second frame HFF2c, the light emitting driver 14 may further supply at least one fifth light emitting stop pulse P5c having a fifth pulse width PW5c less than the fourth pulse width PW4c and greater than or equal to the third pulse width PW31c to the pixel through the first light emitting line E1 after the fourth light emitting stop pulse P4c.

[0181] According to some example embodiments, a difference in the emission duty ratio between the first frame LFF1c and the second frame HFF2c is reduced in the frequency mixing period FMPc, and thus, an instantaneous brightness variation may be reduced.

[0182] For example, when each of the luminous signals includes Fig.10When the plurality of light stop pulses shown in the second frame HFF2c are shown, the front light stop pulses P2c and P4c among the plurality of light stop pulses of the second frame HFF2c are very important in the frequency mixing period FMPc. Therefore, by adjusting the pulse widths PW2c, PW4c and PW5c of the light stop pulses P2c, P4c and P5c of the second frame HFF2c to decrease sequentially, the instantaneous brightness change can be reduced.

[0183] According to some example embodiments, the timing controller 11 may increase the grayscale value of the second frame HFF2c so as to compensate for the reduced emission duty ratio of the second frame HFF2c. For example, the timing controller 11 may increase the grayscale value of the second frame HFF2c received from the external processor and provide the grayscale value to the data driver 12. The timing controller 11 may maintain the grayscale values ​​of the first frame LFF1c and the third frame HFF3c received from the external processor and provide them to the data driver 12.

[0184] Figures 11 to 13 is a diagram illustrating an example embodiment for minimizing brightness variation when a driving frequency is changed from a high frequency to a low frequency.

[0185] Figure 7 The case where the driving frequency of the display device 10 is changed from a low frequency to a high frequency is illustrated, but even when the driving frequency is changed from a high frequency to a low frequency, a frequency mixing period occurs, and therefore, the user can visually recognize instantaneous brightness changes such as a flicker phenomenon.

[0186] In the following, the following will describe Fig.11 Aspects of example embodiments of the present invention.

[0187] In the first frame HFF1d driven at the first frequency, the light emitting driver 14 may supply the first light emitting stop pulse P1d having the first pulse width PW1d to the pixel through the first light emitting line E1.

[0188] In the second frame LFF2d driven at the second frequency, the light emitting driver 14 may supply the second light emitting stop pulse P2d having the second pulse width PW2d to the pixel through the first light emitting line E1.

[0189] In the third frame LFF3d driven at the second frequency, the light emitting driver 14 may supply the third light emitting stop pulse P3d having the third pulse width PW3d to the pixel through the first light emitting line E1.

[0190] The first frequency and the second frequency may be different from each other. For example, the first frequency may be higher than the second frequency.

[0191] The second pulse width PW2d may be between the first pulse width PW1d and the third pulse width PW3d. For example, the second pulse width PW2d may be greater than the first pulse width PW1d and may be less than the third pulse width PW3d.

[0192] According to some example embodiments, a difference in the emission duty ratio between the first frame HFF1d and the second frame LFF2d is reduced in the frequency mixing period FMPd, and thus, an instantaneous brightness variation may be reduced.

[0193] According to some example embodiments, the timing controller 11 may reduce the grayscale value of the second frame LFF2d so as to compensate for the increased emission duty ratio of the second frame LFF2d. For example, the timing controller 11 may reduce the grayscale value of the second frame LFF2d received from the external processor and provide the grayscale value to the data driver 12. The timing controller 11 may maintain the grayscale values ​​of the first frame HFF1d and the third frame LFF3d received from the external processor and provide them to the data driver 12.

[0194] We will now describe Fig.12 Aspects of example embodiments of the present invention.

[0195] In the first frame HFF1e driven at the first frequency, the light emitting driver 14 may supply the first light emitting stop pulse P11e having the first pulse width PW11e to the pixel through the first light emitting line E1.

[0196] In the second frame LFF2e driven at the second frequency, the light emitting driver 14 may supply the second light emitting stop pulse P2e having the second pulse width PW2e to the pixel through the first light emitting line E1.

[0197] In the third frame LFF3 e driven at the second frequency, the light emitting driver 14 may supply the third light emitting stop pulse P31 e having the third pulse width PW31 e to the pixel through the first light emitting line E1 .

[0198] The first frequency and the second frequency may be different from each other. For example, the first frequency may be higher than the second frequency.

[0199] The second pulse width PW2e may be between the first pulse width PW11e and the third pulse width PW31e. For example, the second pulse width PW2e may be greater than the first pulse width PW11e, and may be less than the third pulse width PW31e.

[0200] In the first frame HFF1e, the light emitting driver 14 may further supply at least one of the light emitting stop pulses P12e and P13e having the same pulse widths PW12e and PW13e as the first pulse width PW11e to the pixel through the first light emitting line E1.

[0201] In the third frame LFF3e, the light emitting driver 14 may further supply at least one of the light emitting stop pulses P32e and P33e having the same pulse widths PW32e and PW33e as the third pulse width PW31e, respectively, to the pixel through the first light emitting line E1.

[0202] In the second frame LFF2e, the light emitting driver 14 may further supply at least one of light emitting stop pulses P4e and P5e having the same pulse widths PW4e and PW5e as the third pulse width PW31e to the pixel through the first light emitting line E1 after the second light emitting stop pulse P2e.

[0203] According to some example embodiments, a difference in the emission duty ratio between the first frame HFF1e and the second frame LFF2e is reduced in the frequency mixing period FMPe, and thus, an instantaneous brightness variation may be reduced.

[0204] For example, when each of the luminous signals includes Fig.12 When the plurality of light stop pulses shown in the second frame LFF2e are adjusted, the front light stop pulse P2e among the plurality of light stop pulses of the second frame LFF2e is very important in the frequency mixing period FMPe. Therefore, by adjusting only the pulse width PW2e of the front light stop pulse P2e in the second frame LFF2e, the instantaneous brightness change can be reduced.

[0205] According to some example embodiments, the timing controller 11 may reduce the grayscale value of the second frame LFF2e so as to compensate for the increased emission duty ratio of the second frame LFF2e. For example, the timing controller 11 may reduce the grayscale value of the second frame LFF2e received from the external processor and provide the grayscale value to the data driver 12. The timing controller 11 may maintain the grayscale values ​​of the first frame HFF1e and the third frame LFF3e received from the external processor and provide them to the data driver 12.

[0206] We will now describe Fig.13 Aspects of example embodiments of the present invention.

[0207] In the first frame HFF1f driven at the first frequency, the light emitting driver 14 may supply a first light emitting stop pulse P11f having a first pulse width PW11f to the pixel through the first light emitting line E1.

[0208] In the second frame LFF2f driven at the second frequency, the light emitting driver 14 may supply the second light emitting stop pulse P2f having the second pulse width PW2f to the pixel through the first light emitting line E1.

[0209] In the third frame LFF3f driven at the second frequency, the light emitting driver 14 may supply a third light emitting stop pulse P31f having a third pulse width PW31f to the pixel through the first light emitting line E1.

[0210] The first frequency and the second frequency may be different from each other. For example, the first frequency may be higher than the second frequency.

[0211] The second pulse width PW2f may be between the first pulse width PW11f and the third pulse width PW31f. For example, the second pulse width PW2f may be greater than the first pulse width PW11f, and may be less than the third pulse width PW31f.

[0212] In the first frame HFF1f, the light emitting driver 14 may further supply at least one of the light emitting stop pulses P12f and P13f having the same pulse widths PW12f and PW13f as the first pulse width PW11f to the pixel through the first light emitting line E1.

[0213] In the third frame LFF3f, the light emitting driver 14 may further supply at least one of the light emitting stop pulses P32f and P33f respectively having the same pulse widths PW32f and PW33f as the third pulse width PW31f to the pixel through the first light emitting line E1.

[0214] In the second frame LFF2f, the light emitting driver 14 may further supply at least one fourth light emitting stop pulse P4f having a fourth pulse width PW4f between the second pulse width PW2f and the third pulse width PW31f to the pixel through the first light emitting line E1 after the second light emitting stop pulse P2f.

[0215] In the second frame LFF2f, the light emitting driver 14 may further supply at least one fifth light emitting stop pulse P5f having a fifth pulse width PW5f greater than the fourth pulse width PW4f and less than or equal to the third pulse width PW31f to the pixel through the first light emitting line E1 after the fourth light emitting stop pulse P4f.

[0216] According to some example embodiments, a difference in the emission duty ratio between the first frame HFF1f and the second frame LFF2f is reduced in the frequency mixing period FMPf, and thus, an instantaneous brightness variation may be reduced.

[0217] For example, when each of the luminous signals includes Fig.13When the plurality of light stop pulses shown in the figure are shown in the figure, the front light stop pulses P2f and P4f among the plurality of light stop pulses of the second frame LFF2f are very important in the frequency mixing period FMPf. Therefore, by adjusting the pulse widths PW2f, PW4f and PW5f of the light stop pulses P2f, P4f and P5f of the second frame LFF2f so as to sequentially reduce them, the instantaneous brightness change can be reduced.

[0218] According to some example embodiments, the timing controller 11 may reduce the grayscale value of the second frame LFF2f so as to compensate for the increased emission duty ratio of the second frame LFF2f. For example, the timing controller 11 may reduce the grayscale value of the second frame LFF2f received from the external processor and provide the grayscale value to the data driver 12. The timing controller 11 may maintain the grayscale values ​​of the first frame HFF1f and the third frame LFF3f received from the external processor and provide them to the data driver 12.

[0219] The drawings and detailed description of the present invention mentioned so far are merely examples of the present invention, are only used for the purpose of describing the present invention, and should not be interpreted as limiting the scope of the present invention as defined by the appended claims. Therefore, those skilled in the art will understand that various modifications and equivalent embodiments made thereby are possible. Therefore, the true scope of the present invention should be determined by the technical concepts of the appended claims and their equivalents.

Claims

1. A method for driving a display device, comprising: During a first frame driven at a first frequency, supplying a first light emission stop pulse having a first pulse width to the pixel; During a second frame driven at a second frequency, supplying a second light emission stop pulse having a second pulse width to the pixel; as well as supplying a third light emission stop pulse having a third pulse width to the pixel during a third frame driven at the second frequency, wherein the first frequency is different from the second frequency, and The second pulse width is between the first pulse width and the third pulse width.

2. The method for driving a display device according to claim 1, wherein the first frequency is lower than the second frequency, and The second pulse width is smaller than the first pulse width and larger than the third pulse width.

3. The driving method of the display device according to claim 2, wherein during the first frame period, at least one light emission stop pulse having the first pulse width is further supplied to the pixel, and During the third frame, at least one light emission stop pulse having the third pulse width is further supplied to the pixel. 4 . The driving method of the display device according to claim 3 , wherein during the second frame, after the second light emission stop pulse, at least one light emission stop pulse having the third pulse width is further supplied to the pixel.

5. The driving method of the display device according to claim 3, wherein during the second frame, after the second light emitting stop pulse, at least one fourth light emitting stop pulse having a fourth pulse width between the second pulse width and the third pulse width is further supplied to the pixel.

6. The method for driving a display device according to claim 1, wherein the first frequency is higher than the second frequency, and The second pulse width is greater than the first pulse width and less than the third pulse width.

7. The driving method of the display device according to claim 6, wherein during the first frame period, at least one light emission stop pulse having the first pulse width is further supplied to the pixel, and During the third frame, at least one light emission stop pulse having the third pulse width is further supplied to the pixel. 8 . The driving method of the display device according to claim 7 , wherein during the second frame, after the second light emission stop pulse, at least one light emission stop pulse having the third pulse width is further supplied to the pixel.

9. The driving method of the display device according to claim 7, wherein during the second frame, after the second light-emitting stop pulse, at least one fourth light-emitting stop pulse having a fourth pulse width between the second pulse width and the third pulse width is further supplied to the pixel.

10. A display device, comprising: Light emitting driver; a first pixel coupled to a first light emitting line extending from the light emitting driver; as well as a second pixel connected to a second light emitting line extending from the light emitting driver and different from the first light emitting line, wherein the light emitting driver supplies a first light emitting stop pulse having a first pulse width to a first pixel during a first frame driven at a first frequency, supplies a second light emitting stop pulse having a second pulse width to the first pixel during a second frame driven at a second frequency, and supplies a third light emitting stop pulse having a third pulse width to the first pixel during a third frame driven at the second frequency, wherein during each frame, the light emitting driver supplies a light emitting stop pulse to the second pixel at a different time from that of the first pixel, and The second pulse width is between the first pulse width and the third pulse width.

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