storage devices

Abstract

This application provides a storage device. The storage device includes: a cell array comprising a plurality of cells; an address translation detector that outputs a translation detection signal regarding whether the address of a write command has changed; and control logic circuitry that, in response to the write command, generates one of a plurality of word line enable signals for performing a write operation on the cell array, and terminates the write operation based on the translation detection signal. The word line enable signal includes: a long-term active word line enable signal that remains active before the address changes, and a segmented word line enable signal that is divided into a plurality of sub-word line enable signals before the address changes.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0045314, filed with the Korean Intellectual Property Office on April 18, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a storage device. Background Technology

[0004] With the increasing speed and power consumption of electronic devices, the storage devices built into these devices also require high-speed read / write operations and low operating voltage. Random access memory (RAM) can be volatile or non-volatile. Volatile RAM loses the information stored in it each time power is lost, while non-volatile RAM retains its contents even when power is disconnected.

[0005] However, in the case of such non-volatile random access memory, there are success rates and write error rates (WER) for write operations, and operations must be performed in the direction of lower write error rates. The write error rate is related to write time and the number of writes. Summary of the Invention

[0006] The present invention provides a highly reliable storage device.

[0007] According to an exemplary embodiment of the present invention, a storage device includes: a cell array comprising a plurality of cells; an address register configured to receive a first address and latch the first address; an address transition detector configured to: receive a second address and detect a change from the latched first address to the second address, and output a transition detection signal when the change in the second address is detected; and control logic circuitry configured to initiate a write operation on the cell array using the first address via a write signal, and terminate the write operation in response to the transition detection signal.

[0008] According to an exemplary embodiment of the present invention, a storage device includes: a cell array comprising a plurality of cells; an address translation detector configured to output a translation detection signal regarding whether the address of a write command has changed; and control logic circuitry configured to generate one of a plurality of word line enable signals in response to the write command for performing a write operation on the cell array, and to terminate the write operation based on the translation detection signal. The plurality of word line enable signals include: a long-term active word line enable signal that remains active before the address change, and a segmented word line enable signal that is divided into a plurality of sub-word line enable signals before the address change.

[0009] According to an exemplary embodiment of the present invention, a storage device includes: a cell array including a plurality of storage cells, each of the plurality of storage cells including a pinned layer having a fixed magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer disposed between the pinned layer and the free layer; an address transition detector configured to detect whether the address of a write command has changed, and output a transition detection signal in response to the detection result; a mode register configured to generate a precharge pulse in response to an operating mode of the storage device; and control logic circuitry configured to perform a write operation on the address via a write signal, and terminate the write operation on the address according to the transition detection signal, and further configured to generate one of a plurality of word line on signals in response to the precharge pulse. The operating mode includes a first mode and a second mode. In the first mode, the word line on signal remains active before the address of the write command changes, and in the second mode, the word line on signal is terminated and another word line on signal is generated before the address of the write command changes.

[0010] However, the inventive concept is not limited to the aspects set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art upon reference to the following detailed description of the inventive concept. Attached Figure Description

[0011] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating some embodiments of a storage device based on the concept of the present invention;

[0013] Figure 2 It is used for detailed explanation Figure 1 The logic circuit diagram of the address register;

[0014] Figure 3 It is used for detailed explanation Figure 1 A block diagram of the address translation detector;

[0015] Figure 4 It is used for detailed explanation Figure 3 The logic circuit diagram of the pre-register;

[0016] Figure 5 It is used for detailed explanation Figure 3 The logic circuit diagram of the comparator;

[0017] Figure 6 It is used for explanation Figure 1 A timing diagram of the address translation detector operating over time for storage devices;

[0018] Figure 7 It is used for explanation Figure 1 A timing diagram of write operations on a storage device over time;

[0019] Figure 8 It is used for detailed explanation Figure 1 The equivalent circuit diagram of the cell array;

[0020] Figure 9 This is an equivalent circuit diagram illustrating a cell array of a storage device according to some embodiments of the present invention.

[0021] Figure 10 It is used for explanation Figure 9 A perspective view of the structure of the storage cells in the cell array;

[0022] Figure 11 This is a block diagram illustrating some embodiments of a storage device based on the concept of the present invention;

[0023] Figure 12 It is used for detailed explanation Figure 11 The logic circuit diagram of the mode register;

[0024] Figure 13 It is used for detailed explanation Figure 12 The logic circuit diagram of an automatic pulse generator;

[0025] Figure 14 It is used for explanation Figure 11 The timing diagram of the mode register operating on time;

[0026] Figure 15 It is used for explanation Figure 11 A timing diagram of storage device operations over time;

[0027] Figure 16 This is a block diagram illustrating some embodiments of a storage device according to the present invention; and

[0028] Figure 17 It is used for explanation Figure 1 The timing diagram of the control logic of the storage device operates on a time-based basis. Detailed Implementation

[0029] In the following text, reference will be made to Figures 1 to 8 A storage device according to some embodiments of the concept of the present invention is described.

[0030] Figure 1 This is a block diagram illustrating some embodiments of a storage device based on the concept of the present invention.

[0031] Reference Figure 1 The storage device according to some embodiments of the present invention may include an address register 100, a clock generator 110, an address translation detector 120, a command decoder 130, a row decoder 140, a column decoder 150, control logic 160 (also referred to as control logic circuitry), a word line driver 170, a cell array 180, a multiplexer (BL MUX) 190, a write driver 200, a sense amplifier 210, and an I / O buffer 220.

[0032] Address register 100 can receive address XA from an external source. For example, address register 100 can receive address XA from a memory controller. Address register 100 can latch the received address XA by dividing it into row address RA and column address CA. Address register 100 can send row address RA and column address CA to row decoder 140 and column decoder 150, respectively.

[0033] Address register 100 can receive the first clock PCK from clock generator 110. Address register 100 can receive the write signal WRITE (or simply WR) from command decoder 130. Address register 100 can latch the row address RA and column address CA of the write command using the write signal WRITE and the first clock PCK.

[0034] Address register 100 can send row address RA and column address CA to address translation detector 120.

[0035] Clock generator 110 can receive a clock CK from an external source. Clock generator 110 can generate a first clock PCK and a second clock PRE_PCK based on clock CK. Here, the first clock PCK and the second clock PRE_PCK can have the same period as clock CK. For example, the first clock PCK and the second clock PRE_PCK can have the same frequency as clock CK. However, the first clock PCK can be offset compared to clock CK. For example, the first clock PCK can be delayed compared to clock CK. The second clock PRE_PCK can be similar to clock CK, but not the first clock PCK. The second clock PRE_PCK can be equal to or slightly offset from clock CK. For example, the second clock PRE_PCK can be in phase with clock CK. Therefore, the rising edge of the second clock PRE_PCK can be at the same time as or slightly later than the rising edge of clock CK, while the rising edge of the first clock PCK can be after the rising edge of the second clock PRE_PCK or after the rising edge of clock CK.

[0036] Clock generator 110 can provide a first clock PCK to address register 100 and a second clock PRE_PCK to address translation detector 120. Therefore, the output of address register 100 synchronized with the first clock PCK can be made later than the output of address translation detector 120 synchronized with the second clock PRE_PCK. For ease of description, for example, as... Figure 6 As shown, address XA may include a first address XA[i] and a second address XA[j] immediately following the first address XA[i]. Address register 100 may latch the first address XA[i] and the second address XA[j] in response to a first clock PCK that is delayed compared to clock CK, and address transition detector 120 may latch the first address XA[i] and the second address XA[j] in response to a second clock PRE_PCK that is in phase with clock CK. In this case, as Figure 6 As shown, at time point t4, in response to the second clock PRE_PCK, the first address XA[i] latched in the address transition detector 120 is switched to the second address XA[j]. However, the address register 100 still holds the latched first address XA[i], and the latched first address XA[i] in the address register 100 is switched to the second address XA[j] at time point t7. Therefore, the address transition detector 120 can detect the address change from the first address XA[i] to the second address XA[j] between time point t4 and time point t7.

[0037] Address translation detector 120 can receive address XA from an external source. Address translation detector 120 can receive a second clock PRE_PCK from clock generator 110. Address translation detector 120 can receive row address RA and column address CA from address register 100. Address translation detector 120 can receive the write signal WRITE from command decoder 130.

[0038] Address translation detector 120 can detect whether the address XA of the write command has been changed, and generate a translation detection signal ADDR_DETB. Address translation detector 120 can send the translation detection signal ADDR_DETB to control logic 160. As described above, Figure 6 As shown, upon receiving the second address XA[j], the address translation detector 120 can change its previously latched address (e.g., the first address XA[i]) to the second address XA[j] in response to a second clock PRE_PCK that is in phase with the clock CK. The address translation detector 120 also receives the first address XA[i] latched by the address register 100 in response to a first clock PCK that is delayed compared to the clock CK (i.e., the address register 100 latches the second address XA[j] later than the address translation detector 120). The address translation detector 120 detects the change in address XA by comparing the latched address of the address translation detector 120 (the second address XA[j]) with the latched address of the address register 100 (the first address XA[i]). The configuration and operation of the address translation detector 120 will be described in detail below.

[0039] Command decoder 130 can receive clock CK, negative chip select signal CSN, and negative write enable signal WEN from an external source. When the negative chip select signal CSN is high, it can be interpreted as no signal being applied, and when the negative chip select signal CSN is low, it can be interpreted as a signal being applied. Since this may differ depending on the internal implementation, this embodiment is not limited to this.

[0040] The negative write enable signal WEN can be a signal corresponding to a write command. That is, when a write command is applied, the negative write enable signal WEN can be applied to a low level. The negative write enable signal WEN can be a signal indicating that a write operation needs to be performed using a write command. The negative chip select signal CSN can be a signal that selects the chip to drive in a memory device composed of multiple chips.

[0041] Command decoder 130 can generate a write signal WRITE based on the negative chip select signal CSN and the negative write enable signal WEN, and can send the write signal WRITE synchronously with the clock CK. Command decoder 130 can send the write signal WRITE to address register 100, address translation detector 120 and control logic 160.

[0042] Row decoder 140 can receive row address RA from address register 100. Row decoder 140 can receive word line enable signal WL_ON from control logic 160. Row decoder 140 can decode row address RA to generate decoded row address DRA. Row decoder 140 can send decoded row address DRA to word line driver 170. Row decoder 140 can only send decoded row address DRA when it receives word line enable signal WL_ON.

[0043] The word line driver 170 can control the voltage of the word line WL of the control array 180 according to the decoded row address DRA. For example, the word line driver 170 can apply a voltage for reading or writing to the word line WL selected by the row address RA, and can apply one or more voltages to suppress reading or writing to other word lines WL not selected by the decoded row address DRA.

[0044] Column decoder 150 can receive column address CA from address register 100. Column decoder 150 can receive word line enable signal WL_ON from control logic 160. Column decoder 150 can decode column address CA to generate decoded column address DCA. Column decoder 150 can send the decoded column address DCA to multiplexer 190. Column decoder 150 can only send the decoded column address DCA when it receives the word line enable signal WL_ON.

[0045] Control logic 160 can receive the write signal WRITE from command decoder 130. Control logic 160 can receive the transition detection signal ADDR_DETB from address transition detector 120. Control logic 160 can generate a word line enable signal WL_ON and a write driver enable signal WREN using the write signal WRITE and the transition detection signal ADDR_DETB.

[0046] Control logic 160 can apply each of the word line enable signal WL_ON and the write driver enable signal WREN to a high level based on the write signal WRITE. For example, Figure 17 As shown, in response to the falling edge of the write signal WRITE, control logic 160 can generate a word line enable signal WL_ON and a write driver enable signal WREN that go high. Control logic 160 can apply the word line enable signal WL_ON to row decoder 140 and column decoder 150, and can apply the write driver enable signal WREN to write driver 200.

[0047] Control logic 160 can apply each of the word line enable signal WL_ON and the write driver enable signal WREN to a low level based on the transition detection signal ADDR_DETB. For example, as Figure 17As shown, in response to the falling edge of the transition detection signal ADDR_DETB, control logic 160 generates a word line on signal WL_ON that goes low and a write driver enable signal WREN. This allows control logic 160 to terminate the write operation.

[0048] Cell array 180 may include multiple memory cells. In cell array 180, word lines WL and bit lines BL can form multiple rows and multiple columns. Furthermore, source lines SL can also be paired with bit lines BL. Address XA can be used to specify the memory cell corresponding to any word line WL and any bit line BL.

[0049] Cell array 180 can receive voltage applied to each word line WL from word line driver 170. Cell array 180 can be connected to multiplexer 190 via source line SL and bit line BL. Data stored or to be stored in cell array 180 can be output to multiplexer 190 via bit line BL, or input from multiplexer 190 via source line SL.

[0050] Multiplexer 190 can receive the decoded column address DCA from column decoder 150. Multiplexer 190 can be connected to cell array 180 via source line SL and bit line BL. Multiplexer 190 can use the decoded column address DCA to select the output of a specific bit line BL from the outputs of multiple bit lines BL and output it to the common bit line BL_COM.

[0051] Similarly, multiplexer 190 can select a specific source line SL using the decoded column address DCA to input the common source line SL_COM. That is, multiplexer 190 can also be used as a demultiplexer.

[0052] Write driver 200 can be connected to a memory cell of cell array 180 via source line SL. During a write operation, write driver 200 can apply write current (or voltage) to the source line SL selected via common source line SL_COM via multiplexer 190 in response to write driver enable signal WREN. For example, write driver 200 can apply write current for a predetermined period of time while write driver enable signal WREN is held high (i.e., during a write operation). Write driver 200 can apply one or more voltages to suppress writes to other source lines SL not selected via multiplexer 190.

[0053] The write driver 200 may receive the write driver enable signal WREN from the control logic 160. The write driver 200 may need to receive the write driver enable signal WREN to perform a write operation.

[0054] The write driver 200 can receive data from the I / O buffer 220 via write input / output (WIO). The write driver 200 can send data received via write input / output (WIO) to the multiplexer 190 via the common source line SL_COM.

[0055] The sense amplifier 210 can be connected to the memory cells of the cell array 180 via the source line SL and the bit line BL. During a read operation, the sense amplifier 210 can sense the current (or voltage) of the source line SL and the bit line BL selected by the multiplexer 190, the common source line SL_COM, and the common bit line BL_COM.

[0056] The sense amplifier 210 can receive data from the multiplexer 190 via the common source line SL_COM and the common bit line BL_COM. The sense amplifier 210 can send the data received via the common source line SL_COM and the common bit line BL_COM to the I / O buffer 220 via the read input / output RIO.

[0057] I / O buffer 220 can be connected to each of write driver 200 and sense amplifier 210 via write input / output (WIO) and read input / output (RIO). I / O buffer 220 can exchange data with external devices. Specifically, I / O buffer 220 can load data sent from external devices via data input (DIN) and data output (DOUT) into write driver 200. I / O buffer 220 can transmit data detected by sense amplifier 210 to external devices.

[0058] Figure 2 It is used for detailed explanation Figure 1 The logic circuit diagram of the address register.

[0059] Reference Figure 1 and Figure 2 Address register 100 may include multiple D flip-flops. Address XA may include, for example, a first address XA. <0> Up to address XA <16> However, this is just an example, and this embodiment is not limited to this.

[0060] Address register 100 may include 17 D flip-flops, each D flip-flop corresponding to the first address XA. <0> Up to address XA <16> One of them. Each D flip-flop can use a first clock PCK and a negative write signal / WRITE as clocks to perform synchronization. Here, the negative write signal / WRITE can be a signal obtained by inverting the write signal WRITE.

[0061] When the write signal WRITE is low, the negative write signal / WRITE can be high, and vice versa. That is, when a write command is received, the negative write signal / WRITE can be low. Therefore, when the negative write signal / WRITE goes low, there is a possibility that the clock signal entering the seventeenth D flip-flop may be blocked.

[0062] That is, this allows address register 100 to latch address XA based on the arrival of a write command. For example, when a write command is applied to command decoder 130 as a negative write enable signal WEN, it is delayed compared to address XA because it is output as the write signal WRITE via clock CK, and can therefore be input to address register 100. Thus, after address XA is latched for the first time, the write signal WRITE can go high.

[0063] When the write signal WRITE goes high, the latched address XA remains unchanged because the negative write signal / WRITE goes low and the clock portion of the D flip-flop goes low. When the write signal WRITE goes low again, the latched address XA will be latched again.

[0064] Each D flip-flop latches the first address XA <0> Up to address XA <16> And it can output the address RA of the first line. <0> Up to line eleven, address RA <10> and the first column address CA <0> Up to the sixth column address CA <5> At this point, the first line address RA <0> Up to line eleven, address RA <10> It can be the row address RA and the first column address CA. <0> Up to the sixth column address CA <5> It can be the column address CA. The row address RA can be sent to the row decoder 140 and the address translation detector 120, and the column address CA can be sent to the column decoder 150 and the address translation detector 120.

[0065] Figure 3 It is used for detailed explanation Figure 1 A block diagram of the address translation detector.

[0066] Reference Figures 1 to 3 The address translation detector 120 may include a pre-register 121 and a comparator 123.

[0067] Front register 121 can latch address XA similarly to address register 100. Front register 121 can receive write signal WRITE, address XA, and second clock PRE_PCK. This allows front register 121 to latch the previous row address PRE_RA and the previous column address PRE_CA.

[0068] The row address PRE_RA can be latched slightly earlier than the row address RA, and the column address PRE_CA can be latched slightly earlier than the column address CA. This is because the second clock PRE_PCK is offset from the clock CK by a smaller margin compared to the first clock PCK.

[0069] Comparator 123 can receive the row address RA and column address CA from address register 100. Comparator 123 can receive the previous row address PRE_RA and the previous column address PRE_CA from front register 121. Comparator 123 can also receive the write signal WRITE.

[0070] Comparator 123 can compare the row address RA with the previous row address PRE_RA, compare the column address CA with the previous column address PRE__CA, and output a transition detection signal ADDR_DETB based on the comparison result between the row address RA and the previous row address PRE_RA and / or the comparison result between the column address CA and the previous column address PRE__CA.

[0071] Figure 4 It is used for detailed explanation Figure 3 The logic circuit diagram of the front register.

[0072] Reference Figures 1 to 4 The front register 121 may have a structure similar to that of the address register 100. The front register 121 may include multiple D flip-flops.

[0073] The front register 121 may include 17 D flip-flops, each D flip-flop corresponding to the first address XA <0> Up to address XA <16> One of them. Each D flip-flop can use a second clock, PRE_PCK, as the clock to perform synchronization.

[0074] Therefore, the front register 121 can latch address XA based on the entry of the write signal WRITE.

[0075] Each D flip-flop can latch the first address XA <0> Up to address XA <16> And it can output the first forward address PRE_RA <0> Up to the eleventh line forward address PRE_RA <10> and the first front address PRE_CA <0> Up to the sixth front address PRE_CA <5> At this point, the first forward address is PRE_RA. <0> Up to the eleventh line forward address PRE_RA <10> It can be the preceding address PRE_RA, or the first preceding column address PRE_CA. <0> Up to the sixth front address PRE_CA <5> It can be the preceding address PRE_CA. The preceding address PRE_RA can be sent to comparator 123, and the preceding address PRE_CA can be sent to comparator 123.

[0076] Figure 5 It is used for detailed explanation Figure 3 The logic circuit diagram of the comparator.

[0077] Reference Figures 1 to 5 Comparator 123 can convert the first line address RA <0> Up to line eleven, address RA <10> With the first forward address PRE_RA <0> Up to the eleventh line forward address PRE_RA <10> The comparison is performed. Comparator 123 also compares the addresses of columns 1 through 11 (CA) with the addresses of columns 1 through 11 (PRE_CA). If the entire address set is not identical, a transition detection signal (ADDR_DETB) can be output.

[0078] However, since only write commands are used, the negative write signal / WRITE is used as input, and the output can be cut off when there are no write commands.

[0079] Figure 6 It is used for explanation Figure 1 The address translation detector of the storage device operates according to a timing diagram based on time.

[0080] Reference Figures 1 to 6 Multiple write commands WR can be applied to each rising edge of the clock CK. Specifically, write commands WR can be applied at the first time point t1, the second time point t2, the third time point t3, the fourth time point t4, and the fifth time point t5.

[0081] Simultaneously, both the negative chip select signal CSN and the negative write enable signal WEN can be applied to a low level, and the address (XA[]) can be applied. As the address (XA[]), address i (XA[i]) is applied, and then address j (XA[j]) can be applied. Therefore, the write command WR is the write command WR to address i (XA[i]) at the first time point t1, the second time point t2, and the third time point t3. However, the write command WR can also be the write command WR to address j (XA[j]) at the fourth time point t4 and the fifth time point t5.

[0082] Data (DI[]) can also be written to the WR command, just like an address (XA[]).

[0083] As described above, the second clock PRE_PCK can be a clock equal to or slightly delayed and offset from clock CK. Compared to the second clock PRE_PCK, the first clock PCK can be a clock that is delayed and offset by a relatively larger degree than clock CK. However, since only the delay offset is performed, both the first clock PCK and the second clock PRE_PCK have the same period as clock CK.

[0084] The negative write signal / WRITE can be applied after the address (XA[]) is applied. The negative write signal / WRITE can be temporarily applied high before a new write command WR with a changed address (XA[]) is applied.

[0085] The row address (RA[]) and column address (CA[]) can be latched by the first clock PCK, which is delayed and has a relatively large offset, so address i (XA[i]) can be latched at the sixth time point t6. In contrast, the previous row address (PRE_RA[]) and previous column address (PRE_CA[]) can be latched by the second clock PRE_PCK, which is delayed and has a relatively small offset, so address i (XA[i]) can be latched at the first time point t1.

[0086] Depending on the time difference, the point in time when the address is converted to the new address j (XA[j]) may also change. In row address (RA[]) and column address (CA[]), address j (XA[j]) can be latched at the seventh time point t7. In contrast, in the previous row address (pre_RA[]) and previous column address (pre_CA[]), address j (XA[j]) can be latched at the fourth time point t4.

[0087] Therefore, although the row address (PRE_RA[]) and column address (PRE_CA[]) can be latched starting from address j (XA[j]) at the fourth time point t4, the transition detection signal ADDR_DETB can be changed to low level because the row address (RA[]) and column address (CA[]) can still latch address i (XA[i]).

[0088] The transition detection signal ADDR_DETB remains low until the row address (RA[]) and column address (CA[]) can latch address j (XA[j]) at the seventh time point t7, and then becomes high again at the seventh time point t7.

[0089] Figure 7 It is used for explanation Figure 1 A timing diagram of write operations on a storage device based on time.

[0090] Reference Figures 1 to 7 The write input / output WIO can be applied at the first time point t1 after the write command WR is applied to the rising edge of the clock CK.

[0091] By writing the WRITE signal, the word line enable signal WL_ON can go high, and then the word line driver 170 can apply a voltage to the word line WL. For example, in response to the falling edge of the WRITE signal, the control logic 160 can change the word line enable signal WL_ON to go high at time point t8. Figure 7 The diagram shows the case where a voltage is first applied to word line i (WL[i]) corresponding to address i (XA[i]), and then a voltage is applied to word line j (WL[i]) corresponding to address j (XA[j]).

[0092] The write driver enable signal WREN can also be changed to a high level at time point t8 via the write signal WRITE, just like the word line on signal WL_ON.

[0093] Control logic 160 can change the word line enable signal WL_ON to a low level at the ninth time point t9 via the transition detection signal ADDR_DETB, and can change it back to a high level at the tenth time point t10. Furthermore, similar to the word line enable signal WL_ON, control logic 160 can also change the write driver enable signal WREN to a low level at the ninth time point t9 via the transition detection signal ADDR_DETB, and can change it back to a high level at the tenth time point t10. For example, write driver 200 can apply write current during a predetermined time (i.e., the write time) between the eighth time point t8 and the ninth time point t9, during which both the write driver enable signal WREN and the word line enable signal WL_ON remain high. The period during which the word line enable signal WL_ON remains high can be referred to as the pulse width.

[0094] Therefore, the write operation time WOT of word line i (WL[i]) can be maintained between the eighth time point t8 and the ninth time point t9. That is, during the duration of the write operation time WOT, the word line on signal WL_ON can remain high until the address XA of the write command WR changes to word line j (WL[j]), i.e., the duration of the word line on signal WL_ON can be maintained without changing to a low level. For example, before the address XA changes from word line i (WL[i]) to word line j (WL[j]), the word line on signal WL_ON of word line i (WL[i]) can remain high without changing to a low level.

[0095] That is, the ON ratio of the duration of the word line ON signal WL_ON, which represents the write operation time, can be 100%.

[0096] Figure 8 It is used for detailed explanation Figure 1 The equivalent circuit diagram of the cell array.

[0097] Reference Figures 1 to 8 The cell array 180 includes a memory cell MC. The memory cell MC is connected to the first source line SL1 to the nth source line SLn, the first bit line BL1 to the nth bit line BLn, and the first word line WL1 to the mth word line WLm.

[0098] The memory cells MC are arranged in rows and columns. The rows of the memory cells MC are connected to the first word line WL1 to the m-th word line WLm. The columns of the memory cells MC are connected to the first source line SL1 to the n-th source line SLn and the first bit line BL1 to the n-th bit line BLn.

[0099] The storage device according to some embodiments of the present invention may be a variable resistance storage device. For example, the storage device according to some embodiments of the present invention may include at least one of phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM).

[0100] The write error rate (WER) is the ratio of errors that occur during a write operation and is related to the write time, which is the hold time of the write operation. For example, the probability of a write error occurring within the duration of the write pulse (i.e., the write time) is called the write error rate (WER). The write pulse duration must be long enough to ensure a low write error rate (WER)—the probability that a bit will remain unswitched after the write pulse is turned off in the presence of random thermal effects. In an exemplary embodiment, some variable resistance memory devices can have a low write error rate when the word line ON signal WL_ON is segmented by a short write time and repeated multiple times before the address XA changes, compared to a case where the write time is long and not segmented before the address XA changes. When a low write error rate is achieved at the segmented word line ON signal, the variable resistance memory device can be referred to as a first type of variable resistance memory device.

[0101] In exemplary embodiments, some variable resistance memory devices can exhibit low write error rates when the write time is long and not segmented before address XA changes. Therefore, in newly discovered variable resistance memories with characteristics of both write error rate and write time, the write error rate can be reduced when the write time is long without segmentation. A variable resistance memory device exhibiting a low write error rate under a long-hold-time word line on signal can be referred to as a second type of variable resistance memory device.

[0102] Therefore, the storage device according to some embodiments of the present invention is a storage device having the following characteristics: when the write time is held for a long time, the write error rate is reduced, and the write error rate can be minimized by keeping the on-time of the write operation duration at 100% (i.e., not splitting the word line on signal WL_ON before the address XA changes, or keeping the word line on signal WL_ON active before the address XA changes). In exemplary embodiments, the word line on signal can be selectively split or the word line on signal held for a long time can be applied to have a low write error rate. (Refer to...) Figures 11 to 15 Describe in detail this selective application of the word line turn-on signal.

[0103] Therefore, a highly reliable storage device in which written data is well stored can be provided.

[0104] In the following text, reference will be made to Figure 1 , Figure 9 and Figure 10 A storage device according to some embodiments of the concept of the present invention is described. Parts that are repeated in the above embodiments will be simplified or omitted.

[0105] Figure 9 This is an equivalent circuit diagram illustrating a cell array of a storage device according to some embodiments of the present invention. Figure 10 It is used for explanation Figure 9 A perspective view of the structure of the storage cells in the cell array.

[0106] Reference Figure 1 , Figure 9 and Figure 10 In some embodiments of the present invention, the memory cell MC of the cell array 180 of the memory device includes a select transistor ST and a variable resistor element VR. For example, in some embodiments of the present invention, the memory device may be a magnetic random access memory.

[0107] The select transistor ST includes a first junction 113 formed in a body 111 and connected to the source line SL, a second junction 114 formed in the body 111 and connected to the bit line BL via a variable resistor element VR, and a gate 112 formed on the body 111 between the first junction 113 and the second junction 114. The gate 112 may correspond to the word line WL.

[0108] The variable resistive element VR comprises a pinned layer PL, a tunnel barrier layer TL, and a free layer FL. The pinned layer PL has a fixed magnetization direction. The free layer FL has a magnetization direction that changes according to the voltage (or current) applied to the variable resistive element VR. The current is the current used to perform the write operation and can be defined as the write current. For example, this current can be the current used to switch the magnetization direction of the free layer FL to perform the write operation, and can be defined as the switching current used for the write operation.

[0109] The resistance of the variable resistor element VR can be changed depending on whether the magnetization direction of the free layer FL is the same as or different from the magnetization direction of the pinned layer PL. The variable resistor element VR can store data in the form of resistance value.

[0110] Gate 112 can extend in a direction perpendicular to the direction in which bit line BL extends, and can be connected to the gate of another column of memory cells. The gates of memory cells MC in the same row can be connected together to form word line WL.

[0111] In an exemplary embodiment, when the write time is segmented to perform a write operation on a given address, the magnetic random access memory (which may be referred to as a first type of magnetic random access memory) has a low write error rate. In an exemplary embodiment, when a long write time is maintained and no segmentation occurs before the address changes, the magnetic random access memory (which may be referred to as a second type of magnetic random access memory) has a low write error rate. In an exemplary embodiment, the second type of magnetic random access memory is able to retain data stored in the memory during high-temperature solder reflow, and the switching current is relatively increased.

[0112] Therefore, as in some embodiments of the present invention, the write operation can be maintained for a long time until the write operation is stopped by the address translation detector 120, so as to reduce the write error rate of the magnetic access memory.

[0113] The following will refer to Figures 11 to 15 This section describes a storage device based on some embodiments of the concept proposed in this invention. Parts that are repeated in the above embodiments will be simplified or omitted.

[0114] Figure 11 This is a block diagram illustrating some embodiments of a storage device based on the concept of the present invention.

[0115] Reference Figure 11 The storage device according to some embodiments of the present invention may further include a first mode register 230.

[0116] The first mode register 230 can receive external information MRS. The first mode register 230 can also receive external clock CK or a third clock SCK. Although... Figure 11The first mode register 230 can receive both clock CK and third clock SCK, but it can also receive only one of clock CK and third clock SCK.

[0117] The first mode register 230 can output a precharge pulse synchronized with clock CK or third clock SCK. The first mode register 230 can receive a write signal WRITE from command decoder 130. The first mode register 230 can generate a precharge pulse PRE using external information MRS and the write signal WRITE. The first mode register 230 can send the precharge pulse PRE to control logic 160.

[0118] The first mode register 230 can select multiple operating modes. As an example, the first mode register 230 can select either a first mode that does not generate a precharge pulse PRE or a second mode that generates a precharge pulse PRE.

[0119] The first mode is a write operation where control logic 160 does not segment write commands for the same address XA. The second mode is a write operation where control logic 160 segments write commands for the same address XA. In the second mode, a precharge pulse PRE can be applied to control logic 160.

[0120] In addition, the first mode register 230 can also select a third mode. The third mode generates a precharge pulse PRE just like the second mode, but the application period of the precharge pulse PRE can be different from that of the second mode. That is, in the third mode, although the write operation is segmented, the write operation can be segmented more or less than in the second mode.

[0121] Control logic 160 can receive a precharge pulse PRE. When the precharge pulse PRE is received, control logic 160 can change the word line enable signal WL_ON and the write driver enable signal WREN from high to low within a predetermined time period. For example, control logic 160 can respond to the precharge pulse PRE by terminating the word line enable signal WL_ON and the write driver enable signal WREN, and applying another word line enable signal and another write driver enable signal, thereby applying multiple word line enable signals and multiple write driver enable signals when a write operation is performed at a given address XA. In this case, the word line enable signal WL_ON can be referred to as the split word line enable signal WL_ON, and the multiple word line enable signals WL_ON can be referred to as multiple sub-word line enable signals. This allows the write operation to be split and executed multiple times for a write command at the same address XA.

[0122] The storage device according to this embodiment can perform various write operation modes based on the characteristics of the write error rate. For example, if the storage device can maintain a low write error rate for a long time, the first mode register 230 receives external information MRS indicating this characteristic and does not send a precharge pulse PRE to the control logic 160 during the write time.

[0123] In contrast, if the storage device can have a low write error rate when the write time is segmented and kept short, the first mode register 230 receives external information MRS indicating this characteristic and can send a precharge pulse PRE to the control logic 160 to generate multiple word line on signals with shorter write times.

[0124] This external information (MRS) can be a pre-specified and fixed value during the manufacturing of the storage device. For example, the external information MRS can be provided using test pins, or it can be stored in an OTP (One-Time Programmable) module such as a fuse.

[0125] Therefore, regardless of the characteristics of the write error rate of a portion of the cell array 180 coupled to the storage device according to this embodiment, these characteristics can be optimized by the first mode register 230 and the control logic 160.

[0126] Alternatively, in the storage device according to this embodiment, the external information MRS can be adjusted in real time based on user input. Therefore, even when the characteristics of a portion of the cell array 180 change or require real-time adjustment, optimized write operations can be performed by adjusting the external information MRS.

[0127] Figure 12 It is used for detailed explanation Figure 11 The logic circuit diagram of the mode register.

[0128] Reference Figure 11 and Figure 12 The first mode register 230 may include signal logic 233 and an automatic pulse generator 235.

[0129] Signal logic 233 may be a portion that receives external information MRS to generate a precharge signal. Signal logic 233 may synchronize the write signal WRITE with clock CK. The invention is not limited thereto. In an example embodiment, signal logic 233 may synchronize the write signal WRITE with a third clock SCK. In this case, the external information MRS may include, for example, a first external information MRS. <0> To the fourth external information MRS <3> Four signals. However, this is just an example, and the number of external information MRS can vary.

[0130] Signal logic 233 may include multiple D flip-flops. The number of D flip-flops can be the same as the number of external information MRS. The D flip-flops can be reset when the write signal WRITE goes low. When the first external information MRS... <0> To the fourth external information MRS <3> When any one of them is applied to a high level, signal logic 233 can generate a precharge signal.

[0131] The automatic pulse generator 235 can convert the precharge signal into a precharge pulse PRE in pulse form. Therefore, the precharge pulse PRE can be sent to the control logic 160.

[0132] Figure 13 It is used for detailed explanation Figure 12 The logic circuit diagram of the automatic pulse generator.

[0133] Reference Figure 13 The automatic pulse generator 235 may include a delay chain 237, a NAND gate, and an inverter.

[0134] Delay chain 237 may include multiple inverters. Delay chain 237 can create a delay between the input and the output. Therefore, automatic pulse generator 235 can convert the precharge signal of signal logic 233 into a precharge pulse in pulse form.

[0135] Figure 14 It is used for explanation Figure 11 The mode register operates according to the timing diagram.

[0136] Reference Figure 14 As an example, in the first external information MRS <0> To the fourth external information MRS <3> In the middle, only the second external information MRS <1> It can be applied as a high level, and the remaining external information can be applied as a low level. When the first external information MRS... <0> To the fourth external information MRS <3> When any external information is applied to a high level, the first mode register 230 can generate a precharge pulse PRE.

[0137] Figure 15 It is used for explanation Figure 11 A timing diagram of storage device operations based on time.

[0138] Reference Figures 11 to 15 When the address of the write command is changed or the precharge pulse PRE is applied, the control logic 160 can change the word line turn-on signal WL_ON from high to low.

[0139] Similarly, when the address (XA[]) of the write command WR is changed or the precharge pulse PRE is applied, the control logic 160 can also change the write driver enable signal WREN from high to low.

[0140] therefore, Figure 7 The write operation time WOt can be divided into multiple write operation times within the write command WR at the same address XA. Each write operation time is determined by the corresponding word line on signal WL_ON (i.e., the corresponding sub-word line on signal). Specifically, the write operation time WOt can be divided into a first write operation time WOt-1 from the eighth time point t8 to the eleventh time point t11 ​​and a second write operation time WOt-2 from the twelfth time point t12 to the thirteenth time point t13 by the precharge pulse PRE. In an example embodiment, the first write operation time WOt-1 can start in response to the rising edge of the write signal WRITE and end in response to the precharge pulse PRE, and the second write operation time WOt-2 can start in response to the precharge pulse PRE and end in response to the transition detection signal ADDR_DETB, as shown below. Figure 7 As described in [the document], no write operation is performed between the eleventh time point t11 ​​and the twelfth time point t12. Therefore, the on-time of the write operation time WOt can be reduced to less than 100%. In this case, the size of each segmented write operation time WOt can be the same. For example, the first write operation time WOt-1 can be executed within the pulse width of the first word line on signal WL_ON-1, and the second write operation time WOt-2 can be executed within the pulse width of the second word line on signal WL_ON-2. In an exemplary embodiment, the first word line on signal WL_ON-1 and the second word line on signal WL_ON-2 can have the same pulse width. However, this embodiment is not limited to this.

[0141] Furthermore, even if the address (XA[]) changes, the write operation time WOt can still end. Therefore, the new write operation time WOt can start from the fourteenth time point t14 with the new address (XA[]).

[0142] In the following text, reference will be made to Figure 16 A storage device according to some embodiments of the concept of the present invention is described. Parts that are repeated in the above embodiments will be simplified or omitted.

[0143] Figure 16 This is a block diagram illustrating some embodiments of a storage device based on the concept of the present invention.

[0144] Reference Figure 16 The storage device according to some embodiments of the present invention may include a second mode register 231.

[0145] The second mode register 231 can receive internal information SDI from within the device. The second mode register 231 can also receive a third clock SCK from an external source. Although... Figure 16The second mode register 231 is shown to receive both clock CK and third clock SCK, but it is also possible to receive only one of clock CK and third clock SCK.

[0146] The second mode register 231 can output a precharge pulse PRE synchronized with clock CK or a third clock SCK. The second mode register 231 can receive a write signal WRITE from command decoder 130. The second mode register 231 can generate the precharge pulse PRE using internal information SDI and the write signal WRITE. The second mode register 231 can send the precharge pulse PRE to control logic 160.

[0147] The internal information SDI can be, for example, the write current of a magnetic random access memory (MRMemory). That is, when the memory device is MRMemory, if a write operation is performed, the magnetization direction of the free layer can be switched while the write current flows through the memory cells of the cell array 180. If the magnitude of the write current (i.e., the switching current) is small (i.e., less than a reference value), the write operation can be segmented and performed multiple times to reduce the write error rate. However, when the magnitude of the switching current is large (i.e., greater than a reference value), the write operation can be held for as long as possible without segmentation to reduce the write error rate.

[0148] The second mode register 231 can determine the magnitude of the switching current. In an exemplary embodiment, the second mode register 231 may include a comparator that receives a reference value and a write current and outputs a comparison result. If the magnitude of the switching current is equal to or less than the reference value, a precharge pulse PRE can be applied to the control logic 160, and if the magnitude of the switching current is equal to or greater than the reference value, a precharge pulse PRE can not be applied to the control logic 160.

[0149] Therefore, control logic 160 can segment or maintain the write operation time WOT. If a precharge pulse PRE is applied, the number of operations to be divided into the write operation time WOT can be determined based on the value set in the second mode register 231.

[0150] In summarizing the detailed description, those skilled in the art will understand that many changes and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed in this invention are used only in a general and descriptive sense and are not intended for limiting purposes.

Claims

1. A storage device, comprising: A cell array comprising multiple cells; The address register is configured to receive a first address and latch the first address; The address transition detector is configured to: receive a second address and detect a change from the latched first address to the second address, and output a transition detection signal when the latched first address is detected to change to the second address; as well as The control logic circuit is configured to initiate a write operation on the cell array using the first address via a write signal, and terminate the write operation in response to a transition detection signal received from the address transition detector.

2. The storage device according to claim 1, further comprising: The mode register is configured to generate a precharge pulse. The control logic circuit is further configured to terminate the write operation in response to the precharge pulse.

3. The storage device according to claim 2, in, The mode register includes: The signal logic is configured to generate a precharge signal based on external information indicating the write operation mode; and An automatic pulse generator is configured to convert the precharge signal into the precharge pulse.

4. The storage device according to claim 3, in, The external information is sent from the test pin or a one-time programmable module.

5. The storage device according to claim 2, in, The mode register is also configured to receive internal information to generate the precharge pulse, and The internal information refers to the switching current of the write operation.

6. The storage device according to claim 5, in, The mode register is further configured to compare the magnitude of the switching current with a reference value to generate the pre-charge pulse.

7. The storage device according to claim 6, in, The mode register is further configured to generate the precharge pulse when the magnitude of the switching current is less than the reference value.

8. The storage device according to claim 7, in, The cell array includes multiple storage cells. Each of the plurality of storage units includes: Pinned layers with a fixed magnetization direction A free layer with variable magnetization direction; and A tunnel barrier layer is placed between the pinned layer and the free layer, and The switching current of the write operation corresponds to the current used to switch the magnetization direction of the free layer.

9. The storage device according to claim 1, in, The address translation detector includes: The previous register is configured to latch the second address, and A comparator coupled to the front register and the address register, and the comparator is configured to compare a first address latched by the address register with a second address latched by the front register.

10. The storage device according to claim 9, further comprising: A clock generator is configured to receive an external clock to generate a first clock and a second clock, provide the first clock to the address register, and provide the second clock to the front register. Wherein, the second clock is in phase with the external clock, and Wherein, the first clock is delayed compared to the external clock.

11. The storage device according to claim 10, in, The first clock and the second clock have the same frequency as the external clock.

12. The storage device according to claim 1, further comprising: The command decoder is configured to send a write signal to the address translation detector and the address register according to a write command.

13. A storage device, comprising: A cell array comprising multiple cells; The address translation detector is configured to output a translation detection signal indicating whether the address of a write command has changed. as well as The control logic circuit is configured to generate one of a plurality of word line on signals in response to the write command for performing a write operation on the cell array, and to terminate the write operation based on the transition detection signal received from the address transition detector. The plurality of word line enable signals include: a long-term active word line enable signal that remains active before the address changes, and a segmented word line enable signal that is divided into a plurality of sub-word line enable signals before the address changes.

14. The storage device of claim 13, further comprising: The mode register is configured to receive external information to generate a precharge pulse. The control logic circuit is further configured to generate one of the plurality of word line activation signals based on the precharge pulse.

15. The storage device according to claim 14, in, The plurality of sub-word line turn-on signals include a first sub-word line turn-on signal and a second sub-word line turn-on signal that are separated from each other by the pre-charge pulse.

16. The storage device according to claim 15, in, The first sub-word line turn-on signal and the second sub-word line turn-on signal have the same pulse width.

17. The storage device according to claim 13, in, The storage device includes at least one of phase-change random access memory, magnetic random access memory, resistive random access memory, and ferroelectric random access memory.

18. The storage device according to claim 13, in, The storage device is a magnetic random access memory (MRMemory), and the storage device further includes a mode register configured to generate a precharge pulse based on the magnitude of the switching current of the MRMemory. The control logic circuit is further configured to generate one of the plurality of word line activation signals based on the precharge pulse.

19. A storage device, comprising: A cell array includes multiple storage cells, each of the multiple storage cells including a pinned layer with a fixed magnetization direction, a free layer with a variable magnetization direction, and a tunnel barrier layer disposed between the pinned layer and the free layer. The address translation detector is configured to detect whether the address of the write command has changed, and outputs a translation detection signal in response to the detection result; A mode register is configured to generate a precharge pulse in response to an operating mode of the storage device; as well as The control logic circuit is configured to perform a write operation on the address via a write signal, and to terminate the write operation on the address according to the transition detection signal, and is further configured to generate one of a plurality of word line on signals in response to the precharge pulse. The operation modes include a first mode and a second mode. In the first mode, the word line on signal remains active until the address of the write command changes, and In the second mode, the word line enable signal is terminated and another word line enable signal is generated before the address of the write command is changed.

20. The storage device according to claim 19, wherein, The mode register uses external or internal information to determine the operating mode.

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