Display device

Abstract

A display device comprising: a substrate comprising a display area and a peripheral area surrounding the display area, pixels comprising light-emitting elements being located in the display area; and a common voltage line on the substrate configured to provide a common voltage to the pixels, the common voltage line comprising: a peripheral common voltage line in the peripheral area of the substrate surrounding the display area and connected to a common electrode of the light-emitting elements; and a plurality of display common voltage lines, the plurality of display common voltage lines passing through the display area and each display common voltage line contacting a different portion of the peripheral common voltage line, the plurality of display common voltage lines being spaced apart from the common electrode of the light-emitting elements.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a display apparatus. BACKGROUND

[0002] Recently, flat panel display apparatuses such as liquid crystal display apparatuses, organic light emitting display apparatuses, etc., have been widely used. An organic light emitting display apparatus is a self-emissive display apparatus, and unlike a liquid crystal display apparatus, an organic light emitting display apparatus does not require a separate light source, and thus, a thickness and a weight can be reduced relative to other display apparatuses. In addition, an organic light emitting display apparatus exhibits relatively high quality characteristics such as low power consumption, high brightness, fast response speed, etc., and thus, is attracting attention as a next generation display apparatus.

[0003] A display apparatus can include a plurality of pixels each including a light emitting element including a pixel electrode, a common electrode, and an emission layer. The display apparatus can further include a driving voltage line for providing a driving voltage to the pixels and a common voltage line for providing a common voltage to the pixels.

[0004] The common electrode of the light emitting element can have a relatively small thickness, and thus, a voltage drop of the common voltage provided to the common electrode of the light emitting element can occur. When the voltage drop of the common voltage occurs, brightness uniformity between the pixels can be reduced.

[0005] The above information disclosed in this Background section is only for enhancing the understanding of the background of the disclosure, and therefore, it can not necessarily constitute the prior art. SUMMARY

[0006] Aspects of some example embodiments include a display apparatus in which a voltage drop of a common voltage can be minimized or reduced, and brightness uniformity can be improved.

[0007] A display apparatus according to some example embodiments includes a substrate including a display area in which a pixel including a light emitting element is located and a peripheral area surrounding the display area, and a common voltage line on the substrate providing a common voltage to the pixel. The common voltage line can include a peripheral common voltage line in the peripheral area of the substrate surrounding the display area and connected to a common electrode of the light emitting element, and a plurality of display common voltage lines passing through the display area and each contacting a different portion of the peripheral common voltage line, the plurality of display common voltage lines being spaced apart from the common electrode of the light emitting element.

[0008] According to some example embodiments, the plurality of display common voltage lines can include a plurality of first display common voltage lines extending in a first direction, and each of the first display common voltage lines contacts a facing portion of the peripheral common voltage line with respect to the display area.

[0009] According to some example embodiments, the display device can further include a data line passing through the display area in the first direction and providing a data signal to the pixel. The plurality of first display common voltage lines can be on substantially the same layer as a layer of the data line.

[0010] According to some example embodiments, the display device can further include a reference voltage line passing through the display area in the first direction and providing a reference voltage to the pixel. The plurality of first display common voltage lines can be on substantially the same layer as a layer of the reference voltage line.

[0011] According to some example embodiments, the plurality of display common voltage lines can further include a plurality of second display common voltage lines extending in a second direction crossing the first direction, and each of the second display common voltage lines contacts a facing portion of the peripheral common voltage line with respect to the display area.

[0012] According to some example embodiments, the plurality of second display common voltage lines can be on a different layer from a layer of the plurality of first display common voltage lines, and each of the plurality of second display common voltage lines can be connected to the plurality of first display common voltage lines through a contact hole.

[0013] According to some example embodiments, the plurality of second display common voltage lines can be on substantially the same layer as a layer of an electrode of a capacitor included in the pixel.

[0014] According to some example embodiments, the peripheral common voltage line can have a closed shape substantially surrounding the display area.

[0015] According to some example embodiments, the display device can further include a peripheral conductive layer between the peripheral common voltage line and a common electrode of the light emitting element in the peripheral area surrounding the display area. The peripheral common voltage line can be connected to the common electrode of the light emitting element through the peripheral conductive layer.

[0016] According to some example embodiments, the peripheral conductive layer can be on substantially the same layer as a layer of a pixel electrode of the light emitting element.

[0017] According to some example embodiments, the pixel can include a first transistor providing a driving current to the light emitting element, and the first transistor can be an n-type transistor.

[0018] According to some example embodiments, the first transistor can include an oxide semiconductor.

[0019] According to some example embodiments, the pixel can further include: a second transistor that supplies the data signal to the first transistor; a third transistor that supplies a reference voltage to the first transistor; and a fourth transistor that supplies an initialization voltage to the light emitting element. The second transistor, the third transistor, and the fourth transistor can be n-type transistors.

[0020] According to some example embodiments, the second transistor, the third transistor, and the fourth transistor can include an oxide semiconductor.

[0021] According to some example embodiments, the pixel can further include: a fifth transistor that supplies a driving voltage to the light emitting element, and the fifth transistor can be a p-type transistor.

[0022] According to some example embodiments, the fifth transistor can include polysilicon.

[0023] According to some example embodiments, the display device can further include: a driving voltage line that supplies a driving voltage to the pixel. The driving voltage line can include: a peripheral driving voltage line that corresponds to one side of the display area in a peripheral area of the substrate, and a plurality of display driving voltage lines that pass through the display area, the plurality of display driving voltage lines being connected to the peripheral driving voltage line and to the pixel electrode of the light emitting element.

[0024] According to some example embodiments, the plurality of display driving voltage lines can be on a different layer than the plurality of display common voltage lines.

[0025] According to some example embodiments, the plurality of display driving voltage lines can include: a plurality of first display driving voltage lines that extend in a first direction and are connected to the peripheral driving voltage line.

[0026] According to some example embodiments, the plurality of display driving voltage lines can further include: a plurality of second display driving voltage lines that extend in a second direction that crosses the first direction and are respectively connected to the plurality of first display driving voltage lines.

[0027] The common voltage line of the display device according to some example embodiments can include a peripheral common voltage line and a plurality of display common voltage lines that pass through the display area, each of the plurality of display common voltage lines contacting a different portion of the peripheral common voltage line and being spaced apart from (or not directly contacting) the common electrode of the light emitting element. Accordingly, a voltage drop of the common voltage can be minimized or reduced, and brightness uniformity of the display device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a block diagram illustrating a display apparatus according to some example embodiments.

[0030] Figure 2 is a plan view illustrating an example of a common voltage line in a display apparatus included in Figure 1 .

[0031] Figure 3 is a plan view illustrating an example of a drive voltage line in a display apparatus included in Figure 1 .

[0032] Figure 4 is a circuit diagram illustrating an example of a pixel in a display apparatus included in Figure 1 .

[0033] Figure 5 is a waveform diagram illustrating a method of driving a pixel in Figure 4 .

[0034] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 are layout diagrams illustrating an example of implementing a pixel in Figure 4 .

[0035] Figure 13 is a plan view illustrating an example of a common voltage line in a display apparatus included in Figure 1 .

[0036] Figure 14 is a plan view illustrating an example of a drive voltage line in a display apparatus included in Figure 1 .

[0037] Figure 15 , Figure 16 and Figure 17 are layout diagrams illustrating an example of implementing a pixel in Figure 4 . DETAILED DESCRIPTION

[0038] Hereinafter, aspects of a display apparatus according to some example embodiments will be explained in more detail with reference to the accompanying drawings.

[0039] Figure 1 is a block diagram illustrating a display apparatus according to some example embodiments.

[0040] Referring to Figure 1 , the display apparatus can include a display unit 10, a scan driver 20, a data driver 30, an emission control driver 40, and a controller 50.

[0041] The display unit 10 can include a plurality of pixels PX for displaying an image. For example, the pixels PX can be located at intersections between scan lines SL, data lines DL, and emission control lines ECL, and can be arranged in a substantially matrix form. Each of the pixels PX can include a light-emitting element LE. The light-emitting element LE can include a pixel electrode E1 and a common electrode E2. Each of the pixels PX can further include a plurality of transistors. According to some example embodiments, some of the transistors can be implemented as n-type transistors including an oxide semiconductor, and others of the transistors can be implemented as p-type transistors including polysilicon. The pixels PX can be formed of a first semiconductor layer and a second semiconductor layer, and a first conductive layer to a fifth conductive layer. For example, the p-type transistors can be formed of the first semiconductor layer and the first conductive layer, and the n-type transistors can be formed of the second semiconductor layer, the second conductive layer, and the third conductive layer. Reference will be made to FIGS. 2A and 2B below for a more detailed description of the pixels PX. Figures 4 to 12 The pixels PX will be described in more detail.

[0042] The scan driver 20 can sequentially supply a scan signal SC to the pixels PX through the scan lines SL on the basis of a first control signal CTL1. According to some example embodiments, the scan signal SC can include a first gate signal, a second gate signal, and a third gate signal.

[0043] The data driver 30 can supply a data signal DT to the pixels PX through the data lines DL on the basis of a second control signal CTL2.

[0044] The emission control driver 40 can sequentially supply an emission control signal EM to the pixels PX through the emission control lines ECL on the basis of a third control signal CTL3.

[0045] The controller 50 can control the scan driver 20, the data driver 30, and the emission control driver 40. The controller 50 can generate the first to third control signals CTL1, CTL2, and CTL3 to control the scan driver 20, the data driver 30, and the emission control driver 40, respectively. The first control signal CTL1 for controlling the scan driver 20 can include a scan start signal, a scan clock signal, and the like. The second control signal CTL2 for controlling the data driver 30 can include digital image data, a horizontal start signal, and the like. The third control signal CTL3 for controlling the emission control driver 40 can include an emission control start signal, an emission control clock signal, and the like.

[0046] The display device can further include a power supply to provide the driving voltage ELVDD, the common voltage ELVSS, the reference voltage VREF, and the initialization voltage VINT to the display unit 10. The driving voltage ELVDD can be provided to the display unit 10 through a driving voltage line, and the common voltage ELVSS can be provided to the display unit 10 through a common voltage line. For example, the driving voltage ELVDD can be provided to a pixel electrode E1 of the light emitting element LE included in the pixel PX, and the common voltage ELVSS can be provided to a common electrode E2 of the light emitting element LE included in the pixel PX.

[0047] Figure 2 is a plan view illustrating an example of a common voltage line included in the display device of Figure 1 . Figure 3 is a plan view illustrating an example of a driving voltage line included in the display device of Figure 1 .

[0048] Referring to Figure 1 , Figure 2 and Figure 3 , the display device can include a substrate 110, a common voltage line 200, and a driving voltage line 300.

[0049] The substrate 110 can include a display area DA and a peripheral area PA. The display unit 10 can be located in the display area DA of the substrate 110, and thus, the pixel PX can be located in the display area DA. An image can be displayed from the display area DA by the light emitting pixel PX. The peripheral area PA can be located outside the display area DA. For example, the peripheral area PA can surround the display area DA. According to some example embodiments, the scan driver 20, the data driver 30, and the emission control driver 40 can be located in the peripheral area PA of the substrate 110. The pixel PX can not be located in the peripheral area PA, and thus, the peripheral area PA can be a non-display area.

[0050] As illustrated in Figure 2 , the common voltage line 200 can be located on the substrate 110, and can provide the common voltage ELVSS to the pixel PX. The common voltage line 200 can include a peripheral common voltage line 210, a connection common voltage line 220, and a plurality of display common voltage lines. According to some example embodiments, the plurality of display common voltage lines can include a plurality of first display common voltage lines 231.

[0051] The peripheral common voltage line 210 can be located in the peripheral area PA of the substrate 110 to surround the display area DA. According to some example embodiments, the peripheral common voltage line 210 can have a closed shape substantially surrounding the display area DA. For example, when the display area DA has a rectangular shape in a plan view, the peripheral common voltage line 210 can extend along four sides of the display area DA. In such an example, the peripheral common voltage line 210 can have a quadrilateral frame shape including an upper side, a lower side, a left side, and a right side in a plan view.

[0052] The peripheral common voltage line 210 can be connected to the common electrode E2 of the light emitting element LE included in the pixel PX. According to some example embodiments, a peripheral conductive layer can be formed in the peripheral area PA between the peripheral common voltage line 210 and the common electrode E2 of the light emitting element LE. The peripheral conductive layer can be positioned to surround the display area DA. The peripheral common voltage line 210 can be connected to the common electrode E2 of the light emitting element LE through the peripheral conductive layer. For example, the peripheral conductive layer can be located on substantially the same layer as a layer of the pixel electrode E1 of the light emitting element LE. Since the peripheral common voltage line 210 is connected to the common electrode E2 of the light emitting element LE in the peripheral area PA, the common voltage line 200 can provide the common voltage ELVSS to the pixel PX.

[0053] The connection common voltage line 220 can extend from the peripheral common voltage line 210 in the first direction DR1. The connection common voltage line 220 can be connected to the common voltage pad 400. The common voltage pad 400 can provide the common voltage ELVSS to the connection common voltage line 220.

[0054] The first display common voltage line 231 can pass through the display area DA. Each of the first display common voltage lines 231 can contact a different portion of the peripheral common voltage line 210. According to some example embodiments, the first display common voltage line 231 can extend in the first direction DR1, and each of the first display common voltage lines 231 can contact a facing portion of the peripheral common voltage line 210 with respect to the display area DA. For example, each of the first display common voltage lines 231 can contact the upper side and the lower side of the peripheral common voltage line 210.

[0055] According to some example embodiments, the first display common voltage line 231 can be spaced apart from (or not directly contact) the common electrode E2 of the light emitting element LE. As described above, since the peripheral common voltage line 210 is connected to the common electrode E2 of the light emitting element LE in the peripheral area PA, the common voltage ELVSS can be supplied to the common electrode E2 of the light emitting element LE despite the first display common voltage line 231 being spaced apart from (or not directly contacting) the common electrode E2 of the light emitting element LE.

[0056] The current generated in the common electrode E2 of the light emitting element LE inside the display area DA can move to the common electrode E2 inside the peripheral area PA, and the current can flow from the upper side to the lower side of the peripheral common voltage line 210 along the first display common voltage line 231 passing through the display area DA. Accordingly, the voltage drop of the common voltage ELVSS can be minimized or reduced. Further, the brightness uniformity of the display apparatus can be improved by minimizing or reducing the voltage drop of the common voltage ELVSS.

[0057] As Figure 3 As illustrated in FIG. 3, the driving voltage line 300 can be located on the substrate 110 and can supply the driving voltage ELVDD to the pixel PX. The driving voltage line 300 can include a peripheral driving voltage line 310, a connection driving voltage line 320, and a plurality of display driving voltage lines. According to some example embodiments, the plurality of display driving voltage lines can include a plurality of first display driving voltage lines 331 and a plurality of second display driving voltage lines 332.

[0058] The peripheral driving voltage line 310 can be located in the peripheral area PA of the substrate 110 to correspond to one side of the display area DA. For example, when the display area DA has a rectangular shape in a plan view, the peripheral driving voltage line 310 can be positioned to correspond to any one side of the display area DA. In such an example, the any one side corresponding to the peripheral driving voltage line 310 can be a side of the display area DA adjacent to the driving voltage pad 500.

[0059] The connection driving voltage line 320 can extend from the peripheral driving voltage line 310 in the first direction DR1. The connection driving voltage line 320 can be connected to the driving voltage pad 500. The driving voltage pad 500 can supply the driving voltage ELVDD to the connection driving voltage line 320.

[0060] The first display driving voltage line 331 can pass through the display area DA, and can be connected to the peripheral driving voltage line 310. According to some example embodiments, the first display driving voltage line 331 can extend in the first direction DR1. The first display driving voltage line 331 can be connected to the pixel electrode E1 of the light emitting element LE. For example, the first display driving voltage line 331 can be connected to the pixel electrode E1 of the light emitting element LE of each of the pixels PX included in any one pixel column.

[0061] The second display driving voltage line 332 can pass through the display area DA, and each of the second display driving voltage lines 332 can be connected to the first display driving voltage line 331. According to some example embodiments, the second display driving voltage line 332 can extend in a second direction DR2 crossing the first direction DR1. The second display driving voltage line 332 can be connected to the pixel electrode E1 of the light emitting element LE. For example, the second display driving voltage line 332 can be connected to the pixel electrode E1 of the light emitting element LE of each of the pixels PX included in any one pixel row.

[0062] According to some example embodiments, the second display driving voltage line 332 can be located on a different layer from the first display driving voltage line 331 inside the display area DA. Each of the second display driving voltage lines 332 can be connected to the first display driving voltage line 331 located on the different layer through a contact hole.

[0063] The first display driving voltage line 331 and the second display driving voltage line 332 can be located on a different layer from the first display common voltage line 231 inside the display area DA. Accordingly, the first display driving voltage line 331 and the second display driving voltage line 332 can be insulated from the first display common voltage line 231.

[0064] Hereinafter, a structure of a pixel according to some example embodiments will be described in more detail with reference to Figures 4 to 12

[0065] Figure 4 is a circuit diagram illustrating an example of a pixel PX included in a display apparatus according to some example embodiments. Figure 1

[0066] Referring to Figure 4 , the pixel PX can include a plurality of transistors T1, T2, T3, T4, and T5, a storage capacitor Cst, and a light emitting element LE. The transistors T1, T2, T3, T4, and T5 can include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0067] ​​The first transistor T1 can be a driver transistor that supplies a driving current corresponding to the data signal DT to the light emitting element LE. According to some example embodiments, the first transistor T1 can be an n-type double-gate transistor including an oxide semiconductor. For example, the first transistor T1 can have a first gate electrode connected to the first node N1, a first electrode connected to the second node N2, a second electrode connected to the fifth transistor T5, and a second gate electrode connected to the first electrode.

[0068] The second transistor T2 can be a switching transistor that supplies the data signal DT to the first transistor T1 in response to the first gate signal GW. According to some example embodiments, the second transistor T2 can be an n-type double-gate transistor including an oxide semiconductor. For example, the second transistor T2 can have a first gate electrode that receives the first gate signal GW, a first electrode connected to the first node N1, a second electrode that receives the data signal DT, and a second gate electrode connected to the first gate electrode.

[0069] The third transistor T3 can be a reference voltage transistor that supplies the reference voltage VREF to the first transistor T1 in response to the second gate signal GR. According to some example embodiments, the third transistor T3 can be an n-type double-gate transistor including an oxide semiconductor. For example, the third transistor T3 can have a first gate electrode that receives the second gate signal GR, a first electrode connected to the first node N1, a second electrode that receives the reference voltage VREF, and a second gate electrode connected to the first gate electrode.

[0070] The fourth transistor T4 can be an initialization transistor that supplies the initialization voltage VINT to the light emitting element LE in response to the third gate signal GI. According to some example embodiments, the fourth transistor T4 can be an n-type double-gate transistor including an oxide semiconductor. For example, the fourth transistor T4 can have a first gate electrode that receives the third gate signal GI, a first electrode connected to the second node N2, a second electrode that receives the initialization voltage VINT, and a second gate electrode connected to the first gate electrode.

[0071] The fifth transistor T5 can be an emission control transistor that supplies the driving voltage ELVDD to the light emitting element LE in response to the emission control signal EM. According to some example embodiments, the fifth transistor T5 can be a p-type transistor including polysilicon. For example, the fifth transistor T5 can have a gate electrode that receives the emission control signal EM, a first electrode that receives the driving voltage ELVDD, and a second electrode connected to the second electrode of the first transistor T1.

[0072] The storage capacitor Cst can store a voltage corresponding to the data signal DT and a threshold voltage of the first transistor T1. The storage capacitor Cst can include a first capacitor electrode connected to the first node N1 and a second capacitor electrode connected to the second node N2.

[0073] The light emitting element LE can emit light based on a driving current provided from the first transistor T1. The light emitting element LE can include a first electrode connected to the second node N2 and receiving a driving voltage ELVDD through the first transistor T1 and the fifth transistor T5, a second electrode receiving a common voltage ELVSS, and an emission layer between the first electrode and the second electrode.

[0074] The emission layer can include at least one of an organic light emitting material and a quantum dot material. According to some example embodiments, the organic light emitting material can include a low molecular weight polymer or a high molecular weight polymer. For example, the low molecular weight polymer can include copper phthalocyanine, N,N'-diphenylbenzidine, tris(8-hydroxyquinoline)aluminum, etc., and the high molecular weight polymer can include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylacetylene, polyfluorene, etc.

[0075] According to some example embodiments, the quantum dot material can include a core including a II-VI compound, a III-V compound, a IV-VI compound, a IV element, a IV compound, and combinations thereof. For example, the II-VI compound can include CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS, HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, etc., and the III-V compound can include GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, etc.

[0076] For example, the group IV-VI compound can include SnS, SnSe, SnTe, PbS, PbSe, PbTe, SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, SnPbSSe, SnPbSeTe, SnPbSTe, etc., the group IV element can include Si, Ge, etc., and the group IV compound can include SiC, SiGe, etc.

[0077] According to some example embodiments, the quantum dot material can have a core-shell structure including a core and a shell surrounding the core. The shell can serve as a protective layer for preventing chemical denaturation of the core to maintain a semiconductor property of the core and as a charging layer for imparting an electrophoretic property to the quantum dot material.

[0078] The shell can include, for example, a metallic or non-metallic oxide material, a semiconductor compound, and combinations thereof. For example, the metallic or non-metallic oxide material can include SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, etc., and the semiconductor compound can include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc.

[0079] According to some example embodiments, the emission layer can emit different colors of light. For example, the emission layer can emit red light, green light, and blue light. According to some example embodiments, the emission layer can emit one color of light. For example, the emission layer can emit blue light. In such embodiments, a color conversion element that converts a color of light emitted from the light emitting element LE or transmits light can be located on the light emitting element LE. The color conversion element can include a material (e.g., quantum dots, etc.) for converting a color of light. For example, the color conversion element can convert blue light into red light or green light, or can transmit blue light.

[0080] Figure 5 is a waveform diagram illustrating an example of a method of driving a pixel PX in a display panel 100. Figure 4 is a waveform diagram illustrating an example of a method of driving a pixel PX in a display panel 100.

[0081] Referring to Figure 4 and Figure 5The emission control signal EM having a high level voltage can be supplied to turn off the fifth transistor T5. When the fifth transistor T5 is turned off, the driving voltage ELVDD can not be supplied to the first transistor T1. Accordingly, the light emitting element LE can not emit light during a period in which the emission control signal EM having a high level voltage is supplied.

[0082] The third gate signal GI having a high level voltage and the second gate signal GR having a high level voltage can be supplied during the first period T11. When the third gate signal GI having a high level voltage is supplied, the fourth transistor T4 which is an n-type transistor can be turned on. When the fourth transistor T4 is turned on, the initialization voltage VINT can be supplied to the second node N2. In this case, a parasitic capacitor CLE of the light emitting element LE can be discharged. The initialization voltage VINT can be less than a voltage obtained by adding a threshold voltage of the light emitting element LE to the common voltage ELVSS.

[0083] When the second gate signal GR having a high level voltage is supplied, the third transistor T3 which is an n-type transistor can be turned on. When the third transistor T3 is turned on, the reference voltage VREF can be supplied to the first node N1. The reference voltage VREF can be set to a voltage which turns on the first transistor T1. According to some example embodiments, a voltage (VREF-VINT) obtained by subtracting the initialization voltage VINT from the reference voltage VREF can be greater than a threshold voltage of the first transistor T1.

[0084] The third gate signal GI having a low level voltage can be supplied during the second period T12 to turn off the fourth transistor T4. In addition, the emission control signal EM having a low level voltage can be supplied during a part of the second period T12.

[0085] When the emission control signal EM having a low level voltage is supplied, the fifth transistor T5 can be turned on. When the fifth transistor T5 is turned on, the driving voltage ELVDD can be supplied to the first electrode of the first transistor T1. When the driving voltage ELVDD is supplied to the first electrode of the first transistor T1, the voltage of the second node N2 can increase. The first node N1 can maintain the reference voltage VREF during the second period T12. Accordingly, the voltage of the second node N2 can increase to a voltage obtained by subtracting the threshold voltage of the first transistor T1 from the reference voltage VREF. In this case, the storage capacitor Cst can store the threshold voltage of the first transistor T1.

[0086] The second gate signal GR having a low level voltage can be supplied after the second period T12. When the second gate signal GR having a low level voltage is supplied, the third transistor T3 can be turned off.

[0087] The data signal DT and the first gate signal GW having a high level voltage can be provided during the third period T13. When the first gate signal GW having a high level voltage is provided, the second transistor T2 as an n-type transistor can be turned on. When the second transistor T2 is turned on, the data signal DT can be provided to the first node N1. The data signal DT provided to the first node N1 can be stored in the storage capacitor Cst. For example, a voltage corresponding to the data signal DT and a threshold voltage of the first transistor T1 can be stored in the storage capacitor Cst during the second period T12 and the third period T13.

[0088] The emission control signal EM having a low level voltage can be provided during the fourth period T14. The first gate signal GW having a high level voltage can be provided during the fourth period T14. The second transistor T2 can maintain an on state during the fourth period T14, and thus, the first node N1 can maintain a voltage of the data signal DT. When the emission control signal EM having a low level voltage is provided, the fifth transistor T5 can be turned on.

[0089] When the fifth transistor T5 is turned on, the driving voltage ELVDD can be provided to the first transistor T1. When the first transistor T1 is turned on, a predetermined current can flow through the second node N2. To increase a voltage of the second node N2, a voltage corresponding to a current flowing from the first transistor T1 can be stored in a capacitor (C=Cst+CLE) by coupling the storage capacitor Cst and the parasitic capacitor CLE. Increasing the voltage of the second node N2 can correspond to mobility of the first transistor T1, and can be different between the pixels PX. As a result, the mobility of the first transistor T1 can be compensated for. A time allocated to the fourth period T14 can be determined experimentally to compensate for the mobility of the first transistor T1 included in each of the pixels PX.

[0090] The first gate signal GW having a low level voltage can be provided during the fifth period T15 to turn off the second transistor T2. The first transistor T1 can control an amount of current flowing from the driving voltage ELVDD through the light emitting element LE to the common voltage ELVSS based on a voltage of the first node N1 during the fifth period T15. Thus, the light emitting element LE can generate light having a predetermined brightness based on the amount of current.

[0091] Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 is a layout diagram illustrating an example of a pixel PX in the display apparatus 100 of FIG. 1. Figure 4 ​

[0092] Referring to Figures 6 to 12 The first semiconductor layer 120, the first conductive layers 131, 132, 133, and 332, the second conductive layers 141, 142, 143, and 144, the second semiconductor layers 151 and 152, the third conductive layers 161, 162, 163, and 164, the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177, and the fifth conductive layers 181, 231, and 183 can be sequentially located on the substrate 110. The first semiconductor layer 120, the first conductive layers 131, 132, 133, and 332, the second conductive layers 141, 142, 143, and 144, the second semiconductor layers 151 and 152, the third conductive layers 161, 162, 163, and 164, the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177, and the fifth conductive layers 181, 231, and 183 can form the first to fifth transistors T1, T2, T3, T4, and T5 and the storage capacitor Cst on the substrate 110.

[0093] The substrate 110 can include a transparent and insulating substrate. For example, the substrate 110 can be formed of a glass substrate, a quartz substrate, a plastic substrate, etc. According to some example embodiments, the substrate 110 can include a structure in which an organic insulating layer and an inorganic insulating layer are alternately placed. For example, the substrate 110 can be formed of a structure in which a first organic insulating layer including polyimide (PI), a first inorganic insulating layer including a silicon compound and / or amorphous silicon, a second organic insulating layer including polyimide, and a second inorganic insulating layer including a silicon compound are sequentially stacked.

[0094] As Figure 6 illustrated in FIG. 1A, the first semiconductor layer 120 can be located on the substrate 110. A buffer layer can be interposed between the substrate 110 and the first semiconductor layer 120 to insulate between the substrate 110 and the first semiconductor layer 120. The buffer layer can prevent impurities from permeating from the substrate 110, and can control a transmission rate of heat in a crystallization process for forming the first semiconductor layer 120. The buffer layer can include a silicon compound, a metal oxide, etc.

[0095] The first semiconductor layer 120 can include a source region, a drain region, and a channel region of the fifth transistor T5.

[0096] According to some example embodiments, the first semiconductor layer 120 can be formed of polysilicon. For example, after an amorphous silicon layer is deposited on the buffer layer, the amorphous silicon layer can be crystallized to form a polysilicon layer. Then, the polysilicon layer can be patterned to form the first semiconductor layer 120.

[0097] As Figure 7As illustrated in the middle, the first conductive layers 131, 132, 133, and 332 can be located on the first semiconductor layer 120. A first insulating layer can be interposed between the first semiconductor layer 120 and the first conductive layers 131, 132, 133, and 332 to insulate between the first semiconductor layer 120 and the first conductive layers 131, 132, 133, and 332. The first insulating layer can include a silicon compound, a metal oxide, or the like.

[0098] The first conductive layers 131, 132, 133, and 332 can include an initialization voltage line 131, an emission control line 132, a first capacitor electrode 133, and a second display driving voltage line 332. The initialization voltage line 131, the emission control line 132, and the second display driving voltage line 332 can extend substantially in the second direction DR2. A portion of the emission control line 132 overlapping the first semiconductor layer 120 can function as a gate electrode of a fifth transistor T5. The first semiconductor layer 120 and the emission control line 132 can form the fifth transistor T5. The first conductive layers 131, 132, 133, and 332 can be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0099] As Figure 8 As illustrated in the middle, the second conductive layers 141, 142, 143, and 144 can be located on the first conductive layers 131, 132, 133, and 332. A second insulating layer can be interposed between the first conductive layers 131, 132, 133, and 332 and the second conductive layers 141, 142, 143, and 144 to insulate between the first conductive layers 131, 132, 133, and 332 and the second conductive layers 141, 142, 143, and 144. The second insulating layer can include a silicon compound, a metal oxide, or the like.

[0100] The second conductive layers 141, 142, 143, and 144 can include a first lower gate line 141, a second lower gate line 142, a third lower gate line 143, and a second capacitor electrode 144. The first lower gate line 141, the second lower gate line 142, and the third lower gate line 143 can extend substantially in the second direction DR2. The first capacitor electrode 133 and the second capacitor electrode 144 can form a storage capacitor Cst. The second conductive layers 141, 142, 143, and 144 can be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0101] As Figure 9As illustrated in FIG. 1, the second conductive layers 141, 142, 143, and 144 can be located on the first insulating layer 131. The second semiconductor layers 151 and 152 can be located on the second conductive layers 141, 142, 143, and 144. The third insulating layer can be interposed between the second conductive layers 141, 142, 143, and 144 and the second semiconductor layers 151 and 152 to insulate between the second conductive layers 141, 142, 143, and 144 and the second semiconductor layers 151 and 152. The third insulating layer can include a silicon compound, a metal oxide, or the like.

[0102] The second semiconductor layers 151 and 152 can include a first semiconductor pattern 151 and a second semiconductor pattern 152. The first semiconductor pattern 151 can include source, drain, and channel regions of the first transistor T1 and source, drain, and channel regions of the fourth transistor T4. The second semiconductor pattern 152 can include source, drain, and channel regions of the second transistor T2 and source, drain, and channel regions of the third transistor T3.

[0103] A portion of the first capacitor electrode 133 overlapping the first semiconductor pattern 151 can serve as a lower gate electrode of the first transistor T1. A portion of the first lower gate line 141 overlapping the second semiconductor pattern 152 can serve as a lower gate electrode of the second transistor T2. A portion of the second lower gate line 142 overlapping the second semiconductor pattern 152 can serve as a lower gate electrode of the third transistor T3. A portion of the third lower gate line 143 overlapping the first semiconductor pattern 151 can serve as a lower gate electrode of the fourth transistor T4.

[0104] According to some example embodiments, the second semiconductor layers 151 and 152 can be formed of an oxide semiconductor. For example, after an oxide semiconductor layer is deposited on the third insulating layer, the oxide semiconductor layer can be patterned to form the second semiconductor layers 151 and 152.

[0105] As Figure 10 As illustrated in FIG. 1, the third conductive layers 161, 162, 163, and 164 can be located on the second semiconductor layers 151 and 152. The fourth insulating layer can be interposed between the second semiconductor layers 151 and 152 and the third conductive layers 161, 162, 163, and 164 to insulate between the second semiconductor layers 151 and 152 and the third conductive layers 161, 162, 163, and 164. The fourth insulating layer can include a silicon compound, a metal oxide, or the like.

[0106] The third conductive layers 161, 162, 163, and 164 can include a first upper gate line 161, a second upper gate line 162, a third upper gate line 163, and a first conductive pattern 164. The first upper gate line 161, the second upper gate line 162, and the third upper gate line 163 can extend substantially in the second direction DR2. A portion of the first conductive pattern 164 which overlaps the first semiconductor pattern 151 can function as an upper gate electrode of the first transistor T1. A portion of the first upper gate line 161 which overlaps the second semiconductor pattern 152 can function as an upper gate electrode of the second transistor T2. A portion of the second upper gate line 162 which overlaps the second semiconductor pattern 152 can function as an upper gate electrode of the third transistor T3. A portion of the third upper gate line 163 which overlaps the first semiconductor pattern 151 can function as an upper gate electrode of the fourth transistor T4. The third conductive layers 161, 162, 163, and 164 can be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0107] The first capacitor electrode 133, the first semiconductor pattern 151, and the first conductive pattern 164 can form the first transistor T1, and the first lower gate line 141, the second semiconductor pattern 152, and the first upper gate line 161 can form the second transistor T2. The second lower gate line 142, the second semiconductor pattern 152, and the second upper gate line 162 can form the third transistor T3, and the third lower gate line 143, the first semiconductor pattern 151, and the third upper gate line 163 can form the fourth transistor T4.

[0108] As Figure 11 The fourth conductive layers 171, 331, 173, 174, 175, 176, and 177 can be located on the third conductive layers 161, 162, 163, and 164, as illustrated in FIG. 1C. A fifth insulating layer can be interposed between the third conductive layers 161, 162, 163, and 164 and the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177 to insulate between the third conductive layers 161, 162, 163, and 164 and the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177. The fifth insulating layer can include a silicon compound, a metal oxide, etc.

[0109] The fourth conductive layers 171, 331, 173, 174, 175, 176, and 177 can include a reference voltage line 171, a first display driving voltage line 331, a second conductive pattern 173, a third conductive pattern 174, a fourth conductive pattern 175, a fifth conductive pattern 176, and a sixth conductive pattern 177. The reference voltage line 171 and the first display driving voltage line 331 can extend substantially in the first direction DR1. The reference voltage line 171 can be connected to the second semiconductor pattern 152 through a first contact hole CH1. The first display driving voltage line 331 can be connected to the first semiconductor layer 120 through a second contact hole CH2, and can be connected to a second display driving voltage line 332 through a third contact hole CH3. The second conductive pattern 173 can be connected to the second capacitor electrode 144 through a fourth contact hole CH4, and can be connected to the first semiconductor pattern 151 through a fifth contact hole CH5. The third conductive pattern 174 can be connected to the first capacitor electrode 133 through a sixth contact hole CH6, can be connected to the second semiconductor pattern 152 through a seventh contact hole CH7, and can be connected to the first conductive pattern 164 through an eighth contact hole CH8. The fourth conductive pattern 175 can be connected to the first semiconductor layer 120 through a ninth contact hole CH9, and can be connected to the second semiconductor pattern 152 through a tenth contact hole CH10. The fifth conductive pattern 176 can be connected to the second semiconductor pattern 152 through an eleventh contact hole CH11. The sixth conductive pattern 177 can be connected to the initialization voltage line 131 through a twelfth contact hole CH12, and can be connected to the first semiconductor pattern 151 through a thirteenth contact hole CH13. The fourth conductive layers 171, 331, 173, 174, 175, 176, and 177 can be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc.

[0110] As Figure 12 illustrated in FIG. 1C, the fifth conductive layers 181, 231, and 183 can be located on the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177. A sixth insulating layer can be interposed between the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177 and the fifth conductive layers 181, 231, and 183 to insulate between the fourth conductive layers 171, 331, 173, 174, 175, 176, and 177 and the fifth conductive layers 181, 231, and 183. The sixth insulating layer can include polyimide, etc.

[0111] The fifth, 231, and 183 conductive layers can include data lines 181, first display common voltage lines 231, and seventh conductive patterns 183. The data lines 181 and the first display common voltage lines 231 can extend substantially along the first direction DR1. The data lines 181 can be connected to the fifth conductive patterns 176 through the fourteenth contact holes CH14. The seventh conductive patterns 183 can be connected to the second conductive patterns 173 through the fifteenth contact holes CH15. The fifth, 231, and 183 conductive layers can be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like.

[0112] As described above, the first display common voltage lines 231 can extend along the first direction DR1 inside the pixels PX. According to some example embodiments, the first display common voltage lines 231 can be located on substantially the same layer as the layers of the data lines 181.

[0113] As described above, the first display drive voltage lines 331 can extend along the first direction DR1 inside the pixels PX, and the second display drive voltage lines 332 can extend along the second direction DR2 inside the pixels PX. According to some example embodiments, the first display drive voltage lines 331 can be located on substantially the same layer as the layers of the reference voltage lines 171, and the second display drive voltage lines 332 can be located on substantially the same layer as the layers of the initialization voltage lines 131, the emission control lines 132, and the first capacitor electrodes 133. The first display drive voltage lines 331 and the second display drive voltage lines 332, which are located on different layers from each other, can be connected via the third contact holes CH3.

[0114] Figure 13 is a plan view illustrating another example of a common voltage line included in a display apparatus in Figure 1 . Figure 14 is a plan view illustrating another example of a drive voltage line included in a display apparatus in Figure 1 .

[0115] Referring to Figure 1 , Figure 13 , and Figure 14 , a display apparatus can include a substrate 110, common voltage lines 200, and drive voltage lines 300.

[0116] As illustrated in Figure 13 , the common voltage lines 200 can be located on the substrate 110 and can provide a common voltage ELVSS to the pixels PX. The common voltage lines 200 can include peripheral common voltage lines 210, connection common voltage lines 220, and a plurality of display common voltage lines. According to some example embodiments, the plurality of display common voltage lines can include a plurality of first display common voltage lines 231 and a plurality of second display common voltage lines 232.

[0117] The first display common voltage lines 231 can pass through the display area DA. Each of the first display common voltage lines 231 can contact a different portion of the peripheral common voltage line 210. According to some example embodiments, the first display common voltage lines 231 can extend along the first direction DR1, and each of the first display common voltage lines 231 can contact a facing portion of the peripheral common voltage line 210 with respect to the display area DA. For example, each of the first display common voltage lines 231 can contact the upper side and the lower side of the peripheral common voltage line 210.

[0118] The second display common voltage lines 232 can pass through the display area DA. Each of the second display common voltage lines 232 can contact a different portion of the peripheral common voltage line 210. According to some example embodiments, the second display common voltage lines 232 can extend along the second direction DR2, and each of the second display common voltage lines 232 can contact a facing portion of the peripheral common voltage line 210 with respect to the display area DA. For example, each of the second display common voltage lines 232 can contact the left side and the right side of the peripheral common voltage line 210.

[0119] According to some example embodiments, the second display common voltage lines 232 can be located on a different layer than the first display common voltage lines 231. Each of the second display common voltage lines 232 can be connected to the first display common voltage lines 231 located on the different layer through a contact hole.

[0120] According to some example embodiments, the first display common voltage lines 231 and the second display common voltage lines 232 can be spaced apart from (or not directly contact) the common electrode E2 of the light emitting element LE. As described above, since the peripheral common voltage line 210 is connected to the common electrode E2 of the light emitting element LE in the peripheral area PA, the common voltage ELVSS can also be provided to the common electrode E2 of the light emitting element LE despite the first display common voltage lines 231 and the second display common voltage lines 232 being spaced apart from (or not directly contacting) the common electrode E2 of the light emitting element LE.

[0121] The current generated in the common electrode E2 of the light emitting element LE inside the display area DA can move to the common electrode E2 inside the peripheral area PA, and the current can flow from the upper side to the lower side of the peripheral common voltage line 210 along the first display common voltage line 231 passing through the display area DA, and / or can flow from the left side to the right side of the peripheral common voltage line 210 along the second display common voltage line 232 passing through the display area DA. Thus, the voltage drop of the common voltage ELVSS can be minimized or reduced. Further, the brightness uniformity of the display apparatus can be improved by minimizing or reducing the voltage drop of the common voltage ELVSS.

[0122] As Figure 14 illustrated in FIG. 1, the drive voltage line 300 can be located on the substrate 110, and can provide the drive voltage ELVDD to the pixel PX. The drive voltage line 300 can include the peripheral drive voltage line 310, the connection drive voltage line 320, and a plurality of display drive voltage lines. According to some example embodiments, the plurality of display drive voltage lines can include a plurality of first display drive voltage lines 331.

[0123] The first display drive voltage line 331 can be located on a different layer than the layers of the first display common voltage line 231 and the second display common voltage line 232 inside the display area DA. Thus, the first display drive voltage line 331 can be insulated from the first display common voltage line 231 and the second display common voltage line 232.

[0124] Figure 15 、 Figure 16 and Figure 17 is a layout diagram illustrating another example of a pixel PX implemented in Figure 4 .

[0125] Referring to Figures 6 to 10 、 Figures 15 to 17 and Figure 15The first semiconductor layer 120, the first conductive layers 131, 132, 133 and 232, the second conductive layers 141, 142, 143 and 144, the second semiconductor layer 151 and 152, the third conductive layers 161, 162, 163 and 164, the fourth conductive layers 171, 231, 173, 174, 175, 176, 177 and 178, and the fifth conductive layers 181, 331 and 183 may be sequentially located on the substrate 110. The first semiconductor layer 120, the first conductive layers 131, 132, 133 and 232, the second conductive layers 141, 142, 143 and 144, the second semiconductor layer 151 and 152, the third conductive layers 161, 162, 163 and 164, the fourth conductive layers 171, 231, 173, 174, 175, 176, 177 and 178, and the fifth conductive layers 181, 331 and 183 can form the first to fifth transistors T1, T2, T3, T4 and T5 and the storage capacitor Cst on the substrate 110.

[0126] like Figure 16 As illustrated, first conductive layers 131, 132, 133, and 232 may be located on the first semiconductor layer 120. The first conductive layers 131, 132, 133, and 232 may include an initialization voltage line 131, an emission control line 132, a first capacitor electrode 133, and a second display common voltage line 232. The initialization voltage line 131, the emission control line 132, and the second display common voltage line 232 may extend substantially along a second direction DR2.

[0127] like Figure 17 As illustrated, fourth conductive layers 171, 231, 173, 174, 175, 176, 177, and 178 may be located on third conductive layers 161, 162, 163, and 164. Fourth conductive layers 171, 231, 173, 174, 175, 176, 177, and 178 may include a reference voltage line 171, a first display common voltage line 231, a second conductive pattern 173, a third conductive pattern 174, a fourth conductive pattern 175, a fifth conductive pattern 176, a sixth conductive pattern 177, and an eighth conductive pattern 178. The reference voltage line 171 and the first display common voltage line 231 may extend substantially along a first direction DR1. The first display common voltage line 231 may be connected to a second display common voltage line 232 via a third contact hole CH3. The eighth conductive pattern 178 may be connected to the first semiconductor layer 120 via a sixteenth contact hole CH16.

[0128] like ​As illustrated in the middle, the fifth conductive layers 181, 331, and 183 can be located on the fourth conductive layers 171, 231, 173, 174, 175, 176, 177, and 178. The fifth conductive layers 181, 331, and 183 can include data lines 181, a first display driving voltage line 331, and a seventh conductive pattern 183. The data lines 181 and the first display driving voltage line 331 can extend substantially in the first direction DR1. The first display driving voltage line 331 can be connected to the eighth conductive pattern 178 through a seventeenth contact hole CH17.

[0129] As described above, the first display common voltage line 231 can extend in the first direction DR1 inside the pixel PX, and the second display common voltage line 232 can extend in the second direction DR2 inside the pixel PX. According to some example embodiments, the first display common voltage line 231 can be located on substantially the same layer as that of the reference voltage line 171, and the second display common voltage line 232 can be located on substantially the same layer as that of the initialization voltage line 131, the emission control line 132, and the first capacitor electrode 133. The first display common voltage line 231 and the second display common voltage line 232, which are located on different layers from each other, can be connected through a third contact hole CH3.

[0130] As described above, the first display driving voltage line 331 can extend in the first direction DR1 inside the pixel PX. According to some example embodiments, the first display driving voltage line 331 can be located on substantially the same layer as that of the data line 181.

[0131] The display apparatus according to an embodiment can be applied to a display apparatus included in a computer, a notebook, a mobile phone, a smart phone, a smart pad, a PMP, a PDA, an MP3 player, etc.

[0132] Although a display apparatus according to some example embodiments has been described with reference to the accompanying drawings, the illustrated embodiments are examples, and can be modified and changed by those skilled in the relevant art without departing from the technical spirit described in the appended claims and equivalents thereof.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a peripheral area surrounding the display area, wherein pixels including light-emitting elements are located in the display area; as well as A common voltage line on the substrate, the common voltage line being configured to provide a common voltage to the pixel, the common voltage line comprising: A peripheral common voltage line, wherein the peripheral common voltage line is located in the peripheral region of the substrate to surround the display area and to connect to the common electrode of the light-emitting element; as well as Multiple display common voltage lines are all common voltage lines that pass through the display area, and each display common voltage line contacts a different part of the peripheral common voltage line. None of the multiple display common voltage lines directly contacts the common electrode of the light-emitting element.

2. The display device according to claim 1, wherein, The plurality of display common voltage lines include: a plurality of first display common voltage lines extending along a first direction, and each first display common voltage line contacts the facing portion of the peripheral common voltage line relative to the display area.

3. The display device according to claim 2, further comprising: A data line that passes through the display area along the first direction and is configured to provide data signals to the pixel, and A reference voltage line that passes through the display area along the first direction and is configured to provide a reference voltage to the pixel. The plurality of first display common voltage lines are on the same layer as the data lines or the reference voltage lines.

4. The display device according to claim 2, wherein, The plurality of display common voltage lines further include: a plurality of second display common voltage lines extending along a second direction intersecting the first direction, and each second display common voltage line contacts the facing portion of the peripheral common voltage line relative to the display area.

5. The display device according to claim 4, wherein, The plurality of second display common voltage lines are on a different layer than the plurality of first display common voltage lines. Each of the plurality of second display common voltage lines is connected to the plurality of first display common voltage lines via a contact hole, and The plurality of second display common voltage lines are on the same layer as the electrodes of the capacitor included in the pixel.

6. The display device according to claim 1, wherein, The peripheral common voltage line has a closed shape surrounding the display area.

7. The display device according to claim 1, further comprising: A peripheral conductive layer, wherein the peripheral conductive layer surrounds the display area between the peripheral common voltage line and the common electrode of the light-emitting element in the peripheral region. The peripheral common voltage line is connected to the common electrode of the light-emitting element through the peripheral conductive layer, and The peripheral conductive layer is located on the same layer as the pixel electrode of the light-emitting element.

8. The display device according to claim 1, wherein, The pixel includes a first transistor configured to provide driving current to the light-emitting element. Wherein, the first transistor is an n-type transistor, and The first transistor comprises an oxide semiconductor.

9. The display device according to claim 8, wherein, The pixel further includes: A second transistor configured to provide a data signal to the first transistor; A third transistor configured to provide a reference voltage to the first transistor; and The fourth transistor is configured to provide an initialization voltage to the light-emitting element. Wherein, the second transistor, the third transistor, and the fourth transistor are n-type transistors, and The second transistor, the third transistor, and the fourth transistor comprise oxide semiconductors.

10. The display device according to claim 8, wherein, The pixel further includes a fifth transistor configured to provide a driving voltage to the light-emitting element. The fifth transistor is a p-type transistor, and The fifth transistor comprises polycrystalline silicon.

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