Semiconductor devices

Abstract

Provided is a semiconductor device that is provided with a current sensing portion on the same semiconductor substrate as a main semiconductor element and that can improve the reverse recovery tolerance of a parasitic diode. A portion of the area directly below an OC pad (22) is a sensing effective region (12a) of a unit cell configured with a current sensing portion (12). Directly below the OC pad (22), an area surrounding the sensing effective region (12a) is a sensing ineffective region (12b) of a unit cell not configured with a current sensing portion (12). In the sensing ineffective region (12b), a floating p-type base region (34b') provided in a surface region of the front side of the semiconductor substrate is surrounded by an n-type base region (34b') surrounding the sensing effective region (12a). ‑ The p-type region (32b) is separated from the p-type base region (34b) of the sensing active region (12a). ‑ The p-type region (32b) has a larger surface area than the sensing effective region (12a). The distance (w1) between the p-type base regions (34b') and (34b) is greater than 0.1 μm and as small as possible.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Silicon (Si) has been used as a material for power semiconductor devices that control high voltage and high current. Power semiconductor devices include bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), etc. These can be used according to their application.

[0003] For example, bipolar transistors and IGBTs have higher current density than MOSFETs and can handle large currents, but cannot switch at high speeds. Specifically, bipolar transistors are limited to use at switching frequencies of several kHz, and IGBTs are limited to use at switching frequencies of tens of kHz. On the other hand, power MOSFETs have lower current density than bipolar transistors and IGBTs and are difficult to handle large currents, but can perform high-speed switching operations up to several MHz.

[0004] In addition, MOSFET is different from IGBT in that it can connect the p-type base region to the n-type - The parasitic diode formed by the pn junction of the drift region is used as a freewheeling diode for protecting the MOSFET. Therefore, when the MOSFET is used as an inverter device, it can be used without adding an external freewheeling diode to the MOSFET, which has attracted attention in terms of economic efficiency.

[0005] There is a strong demand for power semiconductor devices with both high current and high speed in the market. All efforts have been made to improve IGBT and power MOSFET, and they have been developed to almost the limit of materials. Therefore, from the perspective of power semiconductor devices, semiconductor materials that can replace silicon have been studied. Silicon carbide (SiC) has attracted much attention as a semiconductor material that can produce (manufacture) next-generation power semiconductor devices with low on-voltage, high-speed characteristics, and excellent high-temperature characteristics.

[0006] In addition, silicon carbide is a chemically very stable semiconductor material with a band gap as wide as 3eV, and can be used as a semiconductor extremely stably even at high temperatures. In addition, since the maximum electric field strength of silicon carbide is more than one order of magnitude greater than that of silicon, it is highly anticipated as a semiconductor material that can fully reduce on-state resistance. The specialty of such silicon carbide is that it is also a semiconductor with a band gap wider than that of other silicon (hereinafter referred to as a wide band gap semiconductor).

[0007] The structure of a conventional semiconductor device will be described by taking an n-channel MOSFET using silicon carbide (SiC) as a wide bandgap semiconductor as an example. Fig.13 FIG. 1 is a top view showing the layout of a conventional semiconductor device viewed from the front side of a semiconductor substrate. Fig.13 In FIG. 1 , the p-type base region 134 b of the sensing active region 112 a and the p-type base region 134 b ′ of the main inactive region 101 b are indicated by different shadows. Fig.14 , Fig.15 Yes means Fig.13 Cross-sectional view of the cross-sectional structure of the active area.

[0008] exist Fig.14 2 shows the cross-sectional structure of the main active region 101 a and the current sensing portion 112 (the cross-sectional structure at the cutting line X101 - X102 - X103 - X104 - X105 ). Fig.15 2 shows the cross-sectional structures of the main effective area 101 a , the sensing effective area 112 a , and the temperature sensing portion 113 (cross-sectional structures at cutting lines X101 - X102 , cutting lines X104 - X105 , and cutting lines Y101 - Y102 ).

[0009] Figure 13 to Figure 15 The conventional semiconductor device 120 shown has a main semiconductor element 111 and one or more circuit parts for protecting and controlling the main semiconductor element 111 in an active region 101 of a semiconductor substrate 110 including silicon carbide. The main semiconductor element 111 is a vertical MOSFET and is composed of a plurality of unit cells (functional units: not shown) arranged adjacent to each other in an effective region (hereinafter referred to as a main effective region) 101a of the active region 101.

[0010] The source pad 121a of the main semiconductor element 111 is provided on the front surface of the semiconductor substrate 110 in the main active region 101a. The circuit portion for protecting and controlling the main semiconductor element 111 is arranged in a region (hereinafter referred to as the main inactive region) 101b other than the main active region 101a in the active region 101. No unit cell of the main semiconductor element 111 is arranged in the main inactive region 101b.

[0011] The surface area of ​​the main ineffective region 101b is larger than that of a semiconductor device that does not include a circuit portion for protecting and controlling the main semiconductor element 111 (a semiconductor device that has only a gate pad disposed in the main ineffective region). Examples of the circuit portion for protecting and controlling the main semiconductor element 111 include a current sensing portion 112, a temperature sensing portion 113, an overvoltage protection portion (not shown), and an arithmetic circuit portion (not shown).

[0012] The current sensing unit 112 is a vertical MOSFET having a smaller number of unit cells (functional units of the element) than the number of unit cells of the main semiconductor element 111 and having the same structure as the main semiconductor element 111. The current sensing unit 112 is configured separately from the main semiconductor element 111. The current sensing unit 112 operates under the same conditions as the main semiconductor element 111 and detects an overcurrent (OC: Over Current) flowing to the main semiconductor element 111.

[0013] The unit cell of the current sensing unit 112 is arranged in a part of the region (hereinafter referred to as a sensing effective region) 112a directly below the electrode pad (hereinafter referred to as an OC pad) 122 of the current sensing unit 112. The region (hereinafter referred to as a sensing ineffective region) 112b directly below the OC pad 122 except for the sensing effective region 112a is an area where the unit cell of the current sensing unit 112 is not arranged, and does not function as the current sensing unit 112.

[0014] In almost the entire region of the sensing ineffective region 112b, a p-type base region 134b' is provided on the surface of the semiconductor substrate 110. - There is a p + The p-type base region 134b' and the p-type base region 162b' of the sensing ineffective region 112b + The type region 162b′ passes through the surface region of the semiconductor substrate 110. - The type region 132b is separated from the sensing active area 112a.

[0015] The p-type base region 134b' of the sensing ineffective region 112b is connected to the p-type base region 134a of the main semiconductor element 111 and is fixed to the source potential of the main semiconductor element 111. + The type region 162b' extends to the entire region of the main ineffective region 101b except the sensing effective region 112a, and is disposed directly below the electrode pads except the source pad 121a.

[0016] Electrode pads other than source pad 121a are provided on the front surface of semiconductor substrate 110 in main ineffective region 101b. Fig.13, the source pad 121a, the gate pad 121b, the OC pad 122, and the electrode pads (anode pad 123a and cathode pad 123b) of the temperature sensing unit 113 are respectively labeled S, G, OC, A, and K. Reference numeral 102 denotes an edge termination region.

[0017] Reference numerals 133a to 150a, 161a, and 162a denote respective portions of the trench gate MOSFET constituting the main semiconductor element 111. Reference numerals 133b to 150b, 161b, and 162b denote respective portions of the trench gate MOSFET constituting the current sensing unit 112. Reference numerals 131, 132, and 151 are n-type common to the main semiconductor element 111 and the current sensing unit 112. + Type drain region, n - The reference numerals 180a to 180c are field insulating films.

[0018] In addition, as the current increases, the trench gate structure in which a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate is more cost-effective than the planar gate structure in which a channel is formed along the front surface of the semiconductor substrate. The reason is that the trench gate structure can increase the unit cell (structural unit of the element) density per unit area, so the current density per unit area can be increased.

[0019] Since the temperature rise rate corresponding to the occupied volume of the unit cell increases with the increase in the current density of the device, a double-sided cooling structure is required to improve the discharge efficiency and stabilize the reliability. In addition, considering the reliability, a high-function structure is required in which a current sensing part, a temperature sensing part, an overvoltage protection part and other high-function parts are arranged on the same semiconductor substrate as the vertical MOSFET as the main semiconductor element as a circuit part for protecting and controlling the main semiconductor element.

[0020] As a conventional semiconductor device, a device is proposed in which a main invalid region including high-function parts such as a current sensing part, a temperature sensing part, and an overvoltage protection part is provided on the same semiconductor substrate as a main semiconductor element of a planar gate structure (for example, see the following patent documents 1 and 2). The following patent documents 1 and 2 disclose a configuration in which electrode pads other than a source pad and an OC pad are concentratedly arranged on one side of a semiconductor substrate.

[0021] As a conventional semiconductor device, a semiconductor device is proposed in which a main semiconductor element and a current sensing portion of a plurality of trench gate structures are provided on the same semiconductor substrate, and a current sensing portion is provided on each main semiconductor element (for example, see Patent Document 3 below). Patent Document 3 below discloses a configuration in which OC pads of a plurality of current sensing portions are concentratedly provided on one side of a semiconductor substrate.

[0022] Prior art literature

[0023] Patent Literature

[0024] Patent Document 1: Japanese Patent Application Publication No. 2017-079324

[0025] Patent Document 2: International Publication No. 2018 / 135147

[0026] Patent Document 3: Japanese Patent Application Publication No. 2018-107331 Summary of the invention

[0027] Technical issues

[0028] However, in the conventional semiconductor device 120, the p-type base region 134b' of the main ineffective region 101b is electrically connected to the source potential of the main semiconductor element 111, thereby + Type region 162b' and n - Since the p-type base region 134b' of the sensing ineffective region 112b extends over almost the entire region of the main ineffective region 101b except the sensing effective region 112a, the larger the surface area of ​​the main ineffective region 101b, the larger the action area of ​​the parasitic diode formed by the p-type base region 134b' of the main ineffective region 101b.

[0029] When the conventional semiconductor device 120 is mounted on a circuit device, the parasitic diode formed by the p-type base region 134b' of the main ineffective region 101b is connected to the p-type base region 134a of the main semiconductor element 111 and the n-type base region 134b' of the main ineffective region 101b when the main semiconductor element 111 switches from off to on. - The parasitic diode formed by the pn junction of the drift region 132 is turned off together. At this time, the holes (holes) generated by the main ineffective region 101b flow into the sensing effective region 112a, and the hole current (reverse recovery current) is concentrated in the current sensing portion 112. Therefore, the larger the surface area of ​​the main ineffective region 101b, the larger the current flows through the current sensing portion 112 and the more concentrated the electric field is, which is easy to destroy the current sensing portion 112.

[0030] The present invention aims to solve the above-mentioned problems of the prior art and to provide a semiconductor device including a current sensing portion on the same semiconductor substrate as a main semiconductor element and capable of improving the reverse recovery resistance of a parasitic diode.

[0031] Technical Solution

[0032] In order to solve the above-mentioned problems and achieve the purpose of the present invention, the semiconductor device of the present invention has the following characteristics. The first first conductive type region is arranged inside a semiconductor substrate containing a semiconductor having a band gap wider than the band gap of silicon. The first second conductive type region is arranged between the first main surface of the above-mentioned semiconductor substrate and the above-mentioned first first conductive type region. The first insulated gate field effect transistor uses the above-mentioned first first conductive type region as a drift region and the above-mentioned first second conductive type region as a base region. The first source pad of the above-mentioned first insulated gate field effect transistor is arranged on the first main surface of the above-mentioned semiconductor substrate and is electrically connected to the above-mentioned first second conductive type region.

[0033] The second second conductivity type region is located between the first main surface of the semiconductor substrate and the first first conductivity type region, and is arranged in a region different from the first second conductivity type region. The second insulated gate field effect transistor uses the first first conductivity type region as a drift region and the second second conductivity type region as a base region. The second insulated gate field effect transistor has a plurality of cells whose number is less than the number of cells of the first insulated gate field effect transistor and whose cell structure is the same as that of the first insulated gate field effect transistor. The second source pad of the second insulated gate field effect transistor is arranged on the first main surface of the semiconductor substrate in a manner separated from the first source pad, and is electrically connected to the second second conductivity type region.

[0034] The third floating second conductive type region is disposed between the first main surface of the semiconductor substrate and the first first conductive type region in an inactive region other than the first active region of the cell configured with the first insulated gate type field effect transistor and the second active region of the cell configured with the second insulated gate type field effect transistor, in a manner separated from the first active region and the second active region, and surrounds the periphery of the second active region. The drain electrode shared by the first insulated gate type field effect transistor and the second insulated gate type field effect transistor is electrically connected to the second main surface of the semiconductor substrate.

[0035] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the semiconductor device further comprises a second first conductivity type region disposed between the second second conductivity type region and the third second conductivity type region and surrounding the second second conductivity type region. The surface area of ​​the second first conductivity type region is larger than the surface area of ​​the second effective region.

[0036] Furthermore, in the semiconductor device of the present invention, in the above invention, a distance between the second second conductivity type region and the third second conductivity type region is 0.1 μm or more.

[0037] In the semiconductor device of the present invention, in the above invention, the second effective region is a portion of the region directly below the second source pad, and the third second conductivity type region is provided in a region directly below the second source pad excluding the second effective region.

[0038] In addition, the semiconductor device of the present invention is characterized in that, in the above invention, the semiconductor device further comprises one or more electrode pads and a fourth second conductive type region. The electrode pad is provided on the first main surface of the semiconductor substrate in the ineffective region in a manner separated from the first source pad and the second source pad. The fourth second conductive type region is provided between the first main surface of the semiconductor substrate and the first first conductive type region directly below all the electrode pads in a manner separated from the third second conductive type region, and is electrically connected to the first second conductive type region.

[0039] Furthermore, in the semiconductor device of the present invention, in the above invention, the electrode pad is a gate pad of the first insulated gate field effect transistor.

[0040] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the semiconductor device includes the electrode pad of a diode for detecting the temperature of the first insulated gate field effect transistor.

[0041] Furthermore, the semiconductor device of the present invention is characterized in that, in the above invention, the semiconductor device includes the electrode pad of a diode for protecting the first insulated gate field effect transistor from an overvoltage.

[0042] Furthermore, in the semiconductor device of the present invention, in the above invention, the second insulated gate field effect transistor detects an overcurrent flowing through the first insulated gate field effect transistor.

[0043] Effects of the Invention

[0044] According to the semiconductor device of the present invention, as a semiconductor device including a current sensing portion on the same semiconductor substrate as a main semiconductor element, an effect of being able to improve the reverse recovery resistance of a parasitic diode is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a plan view showing the layout of the semiconductor device according to the first embodiment as viewed from the front side of the semiconductor substrate.

[0046] Figure 2 Yes means Figure 1 Cross-sectional view of the cross-sectional structure of the active area.

[0047] Figure 3Yes means Figure 1 Cross-sectional view of the cross-sectional structure of the active area.

[0048] Figure 4 This is a circuit diagram showing an equivalent circuit of the semiconductor device according to the first embodiment.

[0049] Figure 5 This is a cross-sectional view showing a state of the semiconductor device according to the first embodiment during the manufacturing process.

[0050] Figure 6 This is a cross-sectional view showing a state of the semiconductor device according to the first embodiment during the manufacturing process.

[0051] Figure 7 This is a cross-sectional view showing a state of the semiconductor device according to the first embodiment during the manufacturing process.

[0052] Figure 8 This is a cross-sectional view showing a state of the semiconductor device according to the first embodiment during the manufacturing process.

[0053] Fig. 9 This is a cross-sectional view showing a state of the semiconductor device according to the first embodiment during the manufacturing process.

[0054] Fig.10 This is a cross-sectional view showing a state of the semiconductor device according to the first embodiment during the manufacturing process.

[0055] Fig.11 It is a plan view showing the layout of the semiconductor device according to the second embodiment as viewed from the front side of the semiconductor substrate.

[0056] Fig.12 This is a characteristic diagram showing the current amount of the blocking current based on the reverse recovery withstand capability of the embodiment.

[0057] Fig.13 This is a plan view showing the layout of a conventional semiconductor device as viewed from the front side of a semiconductor substrate.

[0058] Fig.14 Yes means Fig.13 Cross-sectional view of the cross-sectional structure of the active area.

[0059] Fig.15 Yes means Fig.13 Cross-sectional view of the cross-sectional structure of the active area.

[0060] Explanation of symbols

[0061] 1: Active area

[0062] 1a: Main effective area

[0063] 1b: Main invalid area

[0064] 2: Edge terminal area

[0065] 10: Semiconductor substrate

[0066] 11: Main semiconductor components

[0067] 12: Current sensing unit

[0068] 12a: Sensing effective area

[0069] 12b: Sensing invalid area

[0070] 13: Temperature sensing unit

[0071] 14: Gate pad

[0072] 15: Resistor

[0073] 16: Parasitic diode of main semiconductor element

[0074] 17: Parasitic diode of current sensing unit

[0075] 18: Lead-out electrode

[0076] 19: Connection between gate pad and gate metal electrode

[0077] 20, 20': Semiconductor devices

[0078] 21a: Source pad (electrode pad)

[0079] 21b: Gate pad (electrode pad)

[0080] 22: OC pad (electrode pad)

[0081] 23a: Anode pad (electrode pad)

[0082] 23b: Cathode pad (electrode pad)

[0083] 31:n + Type starting substrate

[0084] 32:n - Drift zone

[0085] 32a, 32b: n - Type Area

[0086] 33a, 33b: n-type current diffusion region

[0087] 34a, 34b, 34b', 34c: p-type base region

[0088] 35a, 35b: n + Type Source Region

[0089] 36a, 36b, 36c: p++ Type contact area

[0090] 37a, 37b: Grooves

[0091] 38a, 38b: Gate insulating film

[0092] 39a, 39b: Gate electrode

[0093] 40, 83: Interlayer insulation film

[0094] 40a, 40b, 83a, 83b: contact holes

[0095] 41a, 41b: NiSi film

[0096] 42a, 42b: first TiN film

[0097] 43a, 43b: first Ti film

[0098] 44a, 44b: Second TiN film

[0099] 45a, 45b: Second Ti film

[0100] 46a, 46b: Barrier metal

[0101] 47a~47d:Coating

[0102] 48a~48d:Terminal pin

[0103] 49a~49c: First protective film

[0104] 50a~50c: Second protective film

[0105] 51: Drain electrode

[0106] 61a, 61b, 62a, 62b, 62b', 62c, 91, 93: p + Type Area

[0107] 71:n - Silicon Carbide Layer

[0108] 71a:n - The thickness of the SiC layer increases

[0109] 72: p-type silicon carbide layer

[0110] 80a~80c:Field insulating film

[0111] 81: p-type polysilicon layer

[0112] 82: n-type polysilicon layer

[0113] 92, 94: n-type region

[0114] GND: Ground point

[0115] X: Direction parallel to the front surface of the semiconductor chip (first direction)

[0116] Y: A direction parallel to the front surface of the semiconductor chip and perpendicular to the first direction (second direction)

[0117] Z: Depth direction

[0118] d1:p + Depth of the area

[0119] d2: p + Distance between type areas

[0120] d3: Depth of the n-type region

[0121] t1: Thickness of the field insulating film

[0122] t11:n - The first layer of silicon carbide is stacked on n + Type starting substrate thickness

[0123] t12:n - The thickness of the silicon carbide layer increases the thickness of the part

[0124] t13: thickness of p-type silicon carbide layer

[0125] w1: The distance between the p-type base region of the sensing ineffective region and the p-type base region of the sensing effective region DETAILED DESCRIPTION

[0126] Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the accompanying drawings, in the layers and regions prefixed with n or p, it is indicated that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n or p respectively indicate that the impurity concentration is higher and lower than the impurity concentration of the layer or region not marked with + and -. It should be noted that in the following descriptions of the embodiments and the accompanying drawings, the same symbols are marked for the same structures, and repeated descriptions are omitted.

[0127] (Implementation Method 1)

[0128] The semiconductor device of Embodiment 1 is configured by using a semiconductor having a band gap wider than that of silicon (Si) (wide-bandgap semiconductor) as a semiconductor material. The structure of the semiconductor device of Embodiment 1 is described by taking, for example, silicon carbide (SiC) as an example of a wide-bandgap semiconductor. Figure 1 1 is a plan view showing the layout of the semiconductor device according to Embodiment 1 as viewed from the front side of the semiconductor substrate. Figure 1In the figure, different shadows are used to represent the p-type base region (second second conductive type region) 34b of the sensing effective region (second effective region) 12a, the p-type base region (third second conductive type region) 34b' of the sensing ineffective region (ineffective region) 12b, and the p-type base region (fourth second conductive type region) 34c of the main ineffective region 1b (in the figure). Fig.11 The same is true in ).

[0129] Figure 1 The semiconductor device 20 of the first embodiment shown has a main semiconductor element (first insulated gate field effect transistor) 11 and one or more circuit parts for protecting and controlling the main semiconductor element 11 in the active region 1 of the same semiconductor substrate (semiconductor chip) 10. The main semiconductor element 11 is a vertical MOSFET in which a drift current flows in the depth direction Z of the semiconductor substrate 10 in the on state. The main semiconductor element 11 is composed of a plurality of unit cells (functional units of the element) connected in parallel to each other via a source pad (first source pad) 21a.

[0130] The unit cells of the main semiconductor element 11 are arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 10. The main semiconductor element 11 performs the main operation of the semiconductor device 20 of the first embodiment. The main semiconductor element 11 is arranged in an effective region (main effective region: first effective region) 1a of the active region 1. The main effective region 1a is a region where the main current of the main semiconductor element 11 flows when the main semiconductor element 11 is turned on. The main effective region 1a has a substantially rectangular planar shape, for example, and occupies more than half of the surface area of ​​the active region 1.

[0131] The circuit part for protecting and controlling the main semiconductor element 11 is a high-function part such as a current sensing part (a second insulated gate field effect transistor) 12, a temperature sensing part 13, an overvoltage protection part (not shown), and an operation circuit part (not shown), and is arranged in the main ineffective area 1b of the active area 1. The main ineffective area 1b is an area where the unit cell of the main semiconductor element 11 is not arranged, and does not function as the main semiconductor element 11. The main ineffective area 1b has a substantially rectangular planar shape, for example, and is arranged between the main active area 1a and the edge terminal area 2.

[0132] The edge termination region 2 is a region between the active region 1 and the end of the semiconductor substrate 10, which surrounds the active region 1, relaxes the electric field on the front side of the semiconductor substrate 10, and maintains a withstand voltage. A withstand voltage structure (not shown) such as a field limiting ring (FLR) and a junction termination (JTE) structure is configured in the edge termination region 2. The withstand voltage refers to the limit voltage that does not cause malfunction or damage to the device.

[0133] The source pad (electrode pad) 21a of the main semiconductor element 11 is arranged on the front surface of the semiconductor substrate 10 in the main active area 1a. The main semiconductor element 11 has a larger current capacity than other circuit parts. Therefore, the source pad 21a of the main semiconductor element 11 has a planar shape substantially the same as that of the main active area 1a, and covers almost the entire surface of the main active area 1a. The source pad 21a of the main semiconductor element 11 is arranged separately from the electrode pads other than the source pad 21a.

[0134] The electrode pads other than the source pad 21a are separated from the edge terminal region 2 and are arranged separately from each other on the front surface of the semiconductor substrate 10 in the main ineffective region 1b. The electrode pads other than the source pad 21a are the gate pad 21b of the main semiconductor element 11, the electrode pad (hereinafter referred to as the OC pad (second source pad)) 22 of the current sensing portion 12, the electrode pads (hereinafter referred to as the anode pad and the cathode pad) 23a, 23b of the temperature sensing portion 13, the electrode pad of the overvoltage protection portion (hereinafter referred to as the OV pad: not shown) and the electrode pad of the operation circuit portion (not shown), etc.

[0135] The electrode pads other than the source pad 21a are, for example, substantially rectangular in plan view and have a surface area required for bonding terminal pins 48b to 48d and wires described later. Figure 1 FIG. 2 shows a case where the electrode pads other than the source pad 21a are arranged in a row along the boundary between the main ineffective region 1b and the edge termination region 2 (in FIG. Fig.11 In addition, Figure 1 In the figure, the source pad 21a, the gate pad 21b, the OC pad 22, the anode pad 23a and the cathode pad 23b are respectively illustrated as rectangles marked with S, G, OC, A and K (in Fig.11 The same is true in ).

[0136] The current sensing unit 12 operates under the same conditions as the main semiconductor element 11, and has a function of detecting an overcurrent (OC) flowing to the main semiconductor element 11. The current sensing unit 12 is configured separately from the main semiconductor element 11. The current sensing unit 12 is a vertical MOSFET having a smaller number (e.g., about 10) of unit cells having the same structure as the main semiconductor element 11 than the number of unit cells of the main semiconductor element 11 (e.g., about 10,000), and a surface area smaller than that of the main semiconductor element 11.

[0137] The unit cells of the current sensing part 12 are arranged in a part of the area (hereinafter referred to as the sensing effective area) 12a directly below the OC pad 22. The sensing effective area 12a has a rectangular planar shape, for example. The unit cells of the current sensing part 12 are arranged adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 10. The direction in which the unit cells of the current sensing part 12 are adjacent to each other is, for example, the same as the direction in which the unit cells of the main semiconductor element 11 are adjacent to each other. The unit cells of the current sensing part 12 are connected in parallel to each other through the OC pad 22.

[0138] In addition, directly below the OC pad 22, the area other than the sensing effective area 12a is the sensing ineffective area 12b that does not function as the current sensing unit 12. The unit cell of the current sensing unit 12 is not arranged in the sensing ineffective area 12b. In almost the entire area of ​​the sensing ineffective area 12b, a p-type base region 34b' is provided in the surface area of ​​the front surface of the semiconductor substrate 10. The p-type base region 34b' surrounds the periphery of the sensing effective area 12a in a substantially rectangular shape, for example. The p-type base region 34b' has a function of making the electric field uniform in the front surface of the semiconductor substrate 10 in the sensing ineffective area 12b and improving the withstand voltage.

[0139] The p-type base region 34b' is formed by n - The p-type base region 34b′ is separated from the p-type base region (first second conductivity type region) 34a of the main semiconductor element 11, the p-type base region 34c described later of the main ineffective region 1b, and the p-type region (not shown) for element isolation. - The p-type region 32b is separated from the p-type base region 34b of the sensing active region 12a. The p-type region for element separation is a floating p-type region that is arranged in a substantially rectangular shape surrounding the active region 1 in the edge termination region 2 and is connected to the n-type region 32b. - The pn junction of the ?-type drift region 32 forms a parasitic diode which electrically separates the active region 1 from the edge termination region 2 .

[0140] The p-type base region 34b' is adjacent to the p-type base region 34b of the sensing effective region 12a in a manner that separates the p-type base region 34b' from the sensing ineffective region 12b and the p-type base region 34b of the sensing effective region 12a. Specifically, an n-type base region 34b' is disposed between the p-type base region 34b' of the sensing ineffective region 12b and the p-type base region 34b of the sensing effective region 12a to surround the sensing effective region 12a in a substantially rectangular shape. - Type area 32b. - The p-type region 32b has a larger surface area than the sensing effective region 12a. The distance w1 between the p-type base region 34b' of the sensing ineffective region 12b and the p-type base region 34b of the sensing effective region 12a is, for example, 0.1 μm or more, and is preferably as small as possible.

[0141] The reason why the distance w1 between the p-type base region 34b' of the sensing ineffective region 12b and the p-type base region 34b of the sensing effective region 12a is preferably as small as possible is as follows. The larger the distance w1 between the p-type base region 34b' of the sensing ineffective region 12b and the p-type base region 34b of the sensing effective region 12a, the smaller the n-type base regions 34b' and 34b disposed between the p-type base regions 34b' and 34b - The larger the surface area of ​​the type region 32b, the larger the surface area of ​​the type region 32b. - In the portion of the type region 32b, the electric field is locally concentrated on the field insulating film, which reduces the withstand voltage. Therefore, by making the distance w1 as small as possible, the n - The surface area of ​​the type region 32b can be reduced, thereby suppressing the reduction in the withstand voltage in the sensing ineffective region 12b.

[0142] The p-type base region 34b' does not share a potential (source potential) with the main semiconductor element 11, but becomes floating (floating potential). By floating the p-type base region 34b', the parasitic diode 17 (see Figure 4 ) is turned off, the hole current generated in the main effective region 1a flows excessively to the p-type base region 34b of the sensing effective region 12a. As a result, the electric field applied to the current sensing portion 12 can be relaxed, so that the reverse recovery tolerance of the parasitic diode of the main ineffective region 1b can be improved.

[0143] In the region except for the region directly below the OC pad 22 of the main ineffective region 1b (region except for the current sensing portion 12: ineffective region), a p-type base region 34c may be provided in the surface region of the front side of the semiconductor substrate 10. The p-type base region 34c of the main ineffective region 1b is connected to the p-type base region 34a of the main semiconductor element 11 and is fixed to the source potential of the main semiconductor element 11. The larger the surface area of ​​the p-type base region 34c, the greater the parasitic diode 17 (see Figure 4 ) forward voltage. Figure 1 2 shows a case where the p-type base region 34 c is provided in almost the entire region of the main ineffective region 1 b except for the region directly below the OC pad 22 .

[0144] The p-type base region 34c of the main ineffective region 1b and the second p + The p-type region 62c is arranged separately from the p-type region for element isolation. + The p-type regions 62b' and 62c are arranged separately from the p-type region for element isolation, so that when the parasitic diode 17 formed in the main ineffective region 1b is turned off, the n-type region 2 in the edge termination region 2 can be suppressed. -Holes generated in the p-type drift region 32 and flowing from the back surface side of the semiconductor substrate 10 to the main ineffective region 1 b in the p-type region for element isolation are concentrated in the current sensing portion 12 .

[0145] The temperature sensing portion 13 has a function of detecting the temperature of the main semiconductor element 11 using the temperature characteristics of a diode. The temperature sensing portion 13 is disposed directly below the anode pad 23a and the cathode pad 23b. The temperature sensing portion 13 may be formed, for example, of a polysilicon (poly-Si) layer on a field insulating film (field insulating film 80c in Embodiment 1) provided on the front surface of the semiconductor substrate 10, or may be formed of a pn junction of a p-type region and an n-type region formed inside the semiconductor substrate 10.

[0146] The overvoltage protection unit (not shown) is a diode that protects the main semiconductor element 11 from overvoltage (OV: OverVoltage) such as surge. The current sensing unit 12, the temperature sensing unit 13, and the overvoltage protection unit are controlled by the operation circuit unit. The main semiconductor element 11 is controlled based on the output signals of the current sensing unit 12, the temperature sensing unit 13, and the overvoltage protection unit. The operation circuit unit is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS: Complementary MOS) circuit.

[0147] Next, the cross-sectional structure of the active region 1 of the semiconductor device 20 according to the first embodiment will be described. Figure 2 , Figure 3 Yes means Figure 1 A cross-sectional view of the cross-sectional structure of the active area. Figure 2 , a cross-sectional structure of the main active region 1a and the current sensing portion 12 (a cross-sectional structure at the cutting line X1-X2-X3-X4-X5) is shown. Figure 3 2 shows the cross-sectional structures of the main effective area 1 a , the sensing effective area 12 a , and the temperature sensing portion 13 (cross-sectional structures at the cutting line X1 - X2 , the cutting line X4 - X5 , and the cutting line Y1 - Y2 ).

[0148] exist Figure 2 , Figure 3 In FIG. 1 , only a part of the unit cell is shown in each of the main active region 1a and the sensing active region 12a, but the unit cells in the main active region 1a and the sensing active region 12a have the same structure. Figure 2 , Figure 3 In the figure, the cross-sectional structure directly below the gate pad 21b is omitted, but the cross-sectional structure directly below the gate pad 21b is the same as the cross-sectional structure directly below the anode pad 23a and the cathode pad 23b. Figure 3 In the embodiment, the sensing ineffective region 12b between the main effective region 1a and the sensing effective region 12a is omitted.

[0149] The main semiconductor element 11 is a vertical MOSFET having a MOS gate (an insulating gate having a three-layer structure of metal-oxide film-semiconductor) on the front side of the semiconductor substrate 10 in the main active region 1a. Here, the case where the main semiconductor element 11 and the circuit portion for protecting and controlling the main semiconductor element 11 have a wiring structure having the same structure as that using a pin-shaped wiring member (terminal pins 48a to 48d described later) is described as an example, but a wiring structure using a wire may be used instead of the pin-shaped wiring member.

[0150] The semiconductor substrate 10 is formed on a substrate including silicon carbide. + The starting substrate 31 is made n - The main semiconductor element 11 has a p-type drift region 32 and a p-type base region 34a provided on the front side of the semiconductor substrate 10. + Type source region 35a, p ++ A typical MOS gate is formed of the type contact region 36a, the trench 37a, the gate insulating film 38a and the gate electrode 39a.

[0151] The trench 37a penetrates the p-type silicon carbide layer 72 in the depth direction Z from the front surface of the semiconductor substrate 10 (the surface of the p-type silicon carbide layer 72) to the n-type silicon carbide layer 72. - The grooves 37a may be arranged, for example, in a stripe shape extending in a direction parallel to the front surface of the semiconductor substrate 10, or in a matrix shape when viewed from the front surface of the semiconductor substrate 10. Figure 2 , Figure 3 The first direction X along which the electrode pads 21b, 23a, 23b, and 22 are arranged is shown in FIG. Figure 1 ) The stripe-shaped groove 37a extends. Symbol Y is a direction parallel to the front surface of the semiconductor chip and perpendicular to the first direction.

[0152] A gate electrode 39a is provided inside the trench 37a via a gate insulating film 38a. P-type base regions 34a and n-type base regions 34a are selectively provided on the surface region of the front side of the semiconductor substrate 10 between two adjacent trenches 37a (mesa region). + Type source region 35a and p ++ Type contact area 36a. + Type source region 35a and p ++ The p-type contact region 36 a is provided between the front surface of the semiconductor substrate 10 and the p-type base region 34 a .

[0153] n + The source region 35a is arranged at a ratio of p ++ The p-type contact region 36a is located near the groove 37a side. ++Type contact area 36a. Without setting p ++ In the case of the type contact region 36a, the ratio n + The p-type source region 35 a is located away from the trench 37 a , and the p-type base region 34 a reaches the front surface of the semiconductor substrate 10 and is exposed on the front surface of the semiconductor substrate 10 .

[0154] In the semiconductor substrate 10, a portion closer to the n-type base region 34a is provided so as to be in contact with the p-type base region 34a. + Type drain region (n + The position of the starting substrate 31 is provided with n - The p-type base region 34a and the n-type drift region 32 can be - An n-type current diffusion region 33a is provided between the n-type drift regions 32 so as to be in contact with these regions. The n-type current diffusion region 33a is a so-called current diffusion layer (CSL) that reduces the spreading resistance of carriers.

[0155] In addition, inside the semiconductor substrate 10, near the n-type base region 34a, + The position of the type drain region may be provided with a first p + Type region 61a, second p + Type region 62a. The first p + The p-type region 61a is provided separately from the p-type base region 34a and faces the bottom surface of the trench 37a in the depth direction Z. + The type region 62a is connected to the first p + The first p-type region 61a is disposed in the mesa region in a manner separated from the trench 37a and in contact with the p-type base region 34a. + Type region 61a, second p + The type region 62a has a function of relaxing the electric field applied to the bottom surface of the trench 37a.

[0156] The interlayer insulating film 40 is provided on the entire front surface of the semiconductor substrate 10 and covers the gate electrode 39a. All gate electrodes 39a of the main semiconductor element 11 are connected to the gate pad 21b (see FIG. 21 ) via a gate flow channel (not shown) in the portion omitted from the illustration. Figure 1 The gate channel is provided on the front surface of the semiconductor substrate via a field insulating film in the edge termination region 2 and is a gate polysilicon layer surrounding the periphery of the active region 1 in a substantially rectangular shape.

[0157] The first contact hole 40a that penetrates the interlayer insulating film 40 in the depth direction Z and reaches the semiconductor substrate 10 exposes the n of the main semiconductor element 11. + Type source region 35a and p ++Inside the first contact hole 40a, a nickel silicide (NiSi, Ni2Si or thermally stable NiSi2: hereinafter referred to as NiSi) film 41a is provided on the front surface of the semiconductor substrate 10.

[0158] The NiSi film 41a is in ohmic contact with the semiconductor substrate 10 in the first contact hole 40a and is in contact with the n + Type source region 35a and p ++ The p-type contact area 36a is electrically connected. ++ In the case of the p-type contact region 36a, the p-type base region 34a is exposed in the first contact hole 40a and electrically connected to the NiSi film 41a instead of the p-type base region 36a. ++ Type contact area 36a.

[0159] In the main effective region 1a, a barrier metal 46a is provided on the entire surface of the interlayer insulating film 40 and the NiSi film 41a. The barrier metal 46a has a function of preventing mutual reaction between metal films separated by the barrier metal 46a or between regions facing each other by the barrier metal 46a. The barrier metal 46a may have, for example, a stacked structure in which a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a, and a second Ti film 45a are stacked in sequence.

[0160] The first TiN film 42a is provided only on the surface of the interlayer insulating film 40 and covers the entire surface of the interlayer insulating film 40. The first Ti film 43a is provided on the surfaces of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a. The barrier metal 46a is not provided on the temperature sensing portion 13, for example.

[0161] The source pad 21a is embedded in the first contact hole 40a and is provided on the entire surface of the second Ti film 45a. The source pad 21a is connected to the nSi film 41a via the barrier metal 46a and the NiSi film 41a. + P-type source region 35a is electrically connected to p-type base region 34a, and functions as a source electrode of main semiconductor element 11. Source pad 21a is, for example, an aluminum (Al) film or an Al alloy film having a thickness of about 5 μm.

[0162] Specifically, when the source pad 21a is set to an Al alloy film, the source pad 21a can be, for example, an aluminum-silicon (Al-Si) film containing less than 5% of silicon as a whole, or an aluminum-silicon-copper (Al-Si-Cu) film containing less than 5% of silicon as a whole and less than 5% of copper (Cu) as a whole, or an aluminum-copper (Al-Cu) film containing less than 5% of copper as a whole.

[0163] One end of a terminal pin 48a is bonded to the source pad 21a via a plating film 47a and a solder layer (not shown). The other end of the terminal pin 48a is bonded to a metal rod (not shown) arranged to face the front surface of the semiconductor substrate 10. In addition, the other end of the terminal pin 48a is exposed outside the housing (not shown) on which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). The terminal pin 48a is a rod-shaped (cylindrical) wiring component having a predetermined diameter.

[0164] The terminal pin 48a is solder-joined to the plating film 47a in a state of standing substantially vertically to the front surface of the semiconductor substrate 10. The terminal pin 48a is an external connection terminal for extracting the potential of the source electrode pad 21a to the outside, and is connected to the external ground potential (lowest potential). The surface of the source electrode pad 21a except the plating film 47a is covered with a first protective film 49a, and the boundary between the plating film 47a and the first protective film 49a is covered with a second protective film 50a. The first protective film 49a and the second protective film 50a are, for example, polyimide films.

[0165] The drain electrode 51 is in ohmic contact with the entire back surface of the semiconductor substrate 10 (n + The back side of the type starting substrate 31). On the drain electrode 51, a drain pad (electrode pad: not shown) is provided in a laminated structure formed by laminating a Ti film, a nickel (Ni) film, and a gold (Au) film in this order. The drain pad is solder-bonded to a metal substrate (not shown), and at least a portion of the drain pad is in contact with the base of a cooling fin (not shown) via the metal substrate.

[0166] By bonding the terminal pins 48a to the front surface of the semiconductor substrate 10 and bonding the back surface to the metal substrate, the semiconductor device 20 of the first embodiment has a double-sided cooling structure in which cooling structures are provided on both surfaces of the semiconductor substrate 10. That is, the heat generated by the semiconductor substrate 10 is dissipated from the fin portion of the cooling fin in contact with the back surface of the semiconductor substrate 10 via the metal substrate, and from the metal rod to which the terminal pins 48a on the front surface of the semiconductor substrate 10 are bonded.

[0167] The current sensing portion 12 includes a p-type base region 34 b and an n-type base region 34 b having the same structure as the corresponding portions of the main semiconductor element 11 . + Type source region 35b, p ++ The p-type contact region 36b, the trench 37b, the gate insulating film 38b, the gate electrode 39b and the interlayer insulating film 40. The respective parts of the MOS gate of the current sensing unit 12 are provided in the sensing effective region 12a of the main ineffective region 1b. The p-type base region 34b of the current sensing unit 12 is composed of a p-type silicon carbide layer 72 similarly to the p-type base region 34a of the main semiconductor element 11.

[0168] In the current sensing unit 12, similarly to the main semiconductor element 11, the p ++ The current sensing unit 12 may also include an n-type current diffusion region 33b and a first p-type contact region 36b similarly to the main semiconductor element 11. + Type region 61b, the second p + The gate electrode 39b of the current sensing unit 12 is connected to the gate pad 21b (see Figure 1 The gate electrode 39 b of the current sensing unit 12 is covered with an interlayer insulating film 40 .

[0169] In the sensing effective region 12a, a second contact hole 40b is provided in the interlayer insulating film 40, penetrating in the depth direction Z and reaching the semiconductor substrate 10. The n of the current sensing unit 12 is exposed in the second contact hole 40b. + Type source region 35b and p ++ In the second contact hole 40b, similarly to the main semiconductor element 11, a contact region 36b is provided. + Type source region 35b and p ++ The NiSi film 41b is electrically connected to the type contact region 36b.

[0170] When p is not set ++ In the case of the p-type contact region 36b, the p-type base region 34b is exposed in the second contact hole 40b and electrically connected to the NiSi film 41b instead of the p-type contact region 36b. ++ In the sensing active region 12a, a barrier metal 46b is provided on the entire surface of the interlayer insulating film 40 and the entire surface of the NiSi film 41b, similarly to the main semiconductor element 11. Reference numerals 42b to 45b respectively denote a first TiN film, a first Ti film, a second TiN film, and a second Ti film constituting the barrier metal 46b.

[0171] The OC pad 22 is provided on the entire surface of the barrier metal 46b so as to be embedded in the second contact hole 40b. The OC pad 22 is connected to the n-type electrode of the current sensing unit 12 via the barrier metal 46b and the NiSi film 41b. + The p-type source region 35b and the p-type base region 34b are electrically connected. The OC pad 22 functions as a source electrode of the current sensing unit 12. The OC pad 22 is formed of, for example, the same material as that of the source pad 21a.

[0172] In the sensing ineffective region 12b of the main ineffective region 1b, a p-type base region 34b' is provided in the surface region of the front surface of the semiconductor substrate as described above. The p-type base region 34b' is composed of a p-type silicon carbide layer 72 similarly to the p-type base region 34a of the main semiconductor element 11. The p-type base region 34b' is arranged between the p-type base region 34a of the main semiconductor element 11, the p-type base region 34c of the main ineffective region 1b, and the p-type region for element isolation (not shown) and the p-type base region 34b of the current sensing unit 12.

[0173] As described above, the p-type base region 34b' is formed by n - The p-type region 32a is separated from the p-type base region 34a of the main semiconductor element 11, the p-type base region 34c of the main ineffective region 1b, and the p-type region for element isolation. - The p-type region 32b is separated from the p-type base region 34b of the current sensing unit 12. - The p-type regions 32a and 32b penetrate the p-type silicon carbide layer 72 in the depth direction Z to reach the n-type silicon carbide layer 72. - The diffusion region of the p-type silicon carbide layer 71 is provided on the surface region of the front side of the semiconductor substrate 10. - Between the drift regions 32, a second p + Type area 62b'.

[0174] In almost the entire region of the main inactive region 1b except for the region directly below the OC pad 22, a p-type base region 34c is provided on the surface region of the front surface of the semiconductor substrate 10 as described above. The p-type base region 34c is composed of a p-type silicon carbide layer 72 similarly to the p-type base region 34b of the current sensing unit 12. A p-type silicon carbide layer 72 may be provided between the p-type base region 34c and the front surface of the semiconductor substrate 10. ++ The p-type base region 34c and the n-type contact region 36c can be - A second p type drift region 32 is provided between the regions 34c and 32 in contact with the regions 34c and 32. + Type area 62c.

[0175] In the region other than the sensing effective region 12a of the main ineffective region 1b and the edge termination region 2, a field insulating film (80a, 80b, 80c) is provided with the same thickness on the entire surface of the front surface of the semiconductor substrate 10. The thickness t1 of the field insulating film is, for example, not less than 0.6 μm and not more than 0.8 μm, for example, about 0.7 μm. Figure 2 , Figure 3 In the figure, the portion of the field insulating film near the boundary between the main effective region 1a and the main ineffective region 1b is denoted by reference numeral 80a. The portion of the field insulating film in the main ineffective region 1b in the sensing ineffective region 12b is denoted by reference numeral 80b, and the portion other than the sensing ineffective region 12b is denoted by reference numeral 80c.

[0176] In the sensing ineffective region 12b, on the field insulating film 80b, the barrier metal 46b and the OC pad 22 extend from the sensing effective region 12a. In the sensing ineffective region 12b, the terminal pin 48b is bonded to the OC pad 22 in the same wiring structure as that on the source pad 21a. The terminal pin 48b is a round rod-shaped (cylindrical) wiring member having a smaller diameter than the terminal pin 48a.

[0177] The terminal pin 48b is an external connection terminal for extracting the potential of the OC pad 22 to the outside, and is connected to the external resistor element 15 (see Figure 4 ) connects the OC pad 22 to the ground potential. By arranging the terminal pin 48b in the sensing ineffective region 12b, it is possible to suppress the pressure generated when the terminal pin 48b is joined from being applied to the unit cell of the current sensing unit 12. Reference numerals 47b, 49b, and 50b are plating films, first protective films, and second protective films constituting the wiring structure on the OC pad 22, respectively.

[0178] The temperature sensing portion 13 is, for example, a polysilicon diode formed by a pn junction of a p-type polysilicon layer 81 as a p-type anode region and an n-type polysilicon layer 82 as an n-type cathode region. The p-type polysilicon layer 81 and the n-type polysilicon layer 82 are provided on a field insulating film 80c in the main ineffective region 1b. The temperature sensing portion 13 is electrically insulated from the main semiconductor element 11 and the current sensing portion 12 by the field insulating film 80c.

[0179] The field insulating film 80c, the p-type polysilicon layer 81, and the n-type polysilicon layer 82 are covered by an interlayer insulating film 83. The anode pad 23a contacts the p-type polysilicon layer 81 in a third contact hole 83a of the interlayer insulating film 83, and the cathode pad 23b contacts the n-type polysilicon layer 82 in a fourth contact hole 83b of the interlayer insulating film 83. The material of the anode pad 23a and the cathode pad 23b is, for example, the same as that of the source pad 21a.

[0180] Terminal pins 48c and 48d are connected to the anode pad 23a and the cathode pad 23b respectively in the same wiring structure as the wiring structure on the source pad 21a. The terminal pins 48c and 48d are external connection terminals for extracting the potential of the anode pad 23a and the cathode pad 23b to the outside. The terminal pins 48c and 48d are round rod-shaped wiring components with a predetermined diameter.

[0181] Reference numerals 47c and 47d are plating films constituting the wiring structure on the anode pad 23a and the wiring structure on the cathode pad 23b, respectively. Reference numerals 49c and 50c are first and second protective films constituting the wiring structure on the temperature sensing portion 13, respectively. ++Type contact region 36c and the second p + The type region 62 c extends in a surface region of the front surface of the semiconductor substrate 10 .

[0182] Although not shown in the figure, the gate pad 21b is provided on the field insulating film 80c. A barrier metal may be provided between the gate pad 21b and the field insulating film 80c in the same stacked structure as the barrier metal 46a. The material of the gate pad 21b is, for example, the same as that of the source pad 21a. A terminal pin is also bonded to the gate pad 21b in a wiring structure (not shown) that is the same as that on the source pad 21a.

[0183] Just below the gate pad portion 14, similarly to just below the anode pad 23a and the cathode pad 23b, the p-type base regions 34c and 34d are formed. ++ Type contact region 36c and the second p + The p-type region 62c extends in the surface region of the front side of the semiconductor substrate 10. That is, in the entire surface of the electrode pads except the OC pad 22 of the main ineffective region 1b, in the depth direction Z, the p-type base region 34c, the p-type base region 62c, and the p-type base region 62c extend in the surface region of the front side of the semiconductor substrate 10. ++ Type contact region 36c and the second p + Type area 62c is opposite.

[0184] The p-type base region 34c, p ++ Type contact region 36c and the second p + The p-type region 62c has, for example, p-type base regions 34a and 34b of the main semiconductor element 11. ++ Type contact region 36a and the second p + The same depth and impurity concentration as the type region 62a.

[0185] The operation of the semiconductor device 20 according to the first embodiment will be described. Figure 4 is a circuit diagram showing an equivalent circuit of the semiconductor device of Embodiment 1. Figure 4 As shown, the current sensing unit 12 is connected in parallel to the unit cells of the plurality of MOSFETs constituting the main semiconductor element 11. The ratio of the sense current flowing in the current sensing unit 12 to the main current flowing in the main semiconductor element 11 (hereinafter referred to as the current sensing ratio) is preset.

[0186] The current sensing ratio can be set by, for example, changing the number of unit cells in the main semiconductor element 11 and the current sensing unit 12. In the current sensing unit 12, a sensing current smaller than the main current flowing in the main semiconductor element 11 flows in accordance with the current sensing ratio. The source of the main semiconductor element 11 is connected to the ground point GND of the ground potential. A resistor element 15 as an external component is connected between the source of the current sensing unit 12 and the ground point GND.

[0187] When a positive voltage is applied to the drain electrode 51 relative to the source electrode (source pad 21a) of the main semiconductor element 11, if a voltage higher than the threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11, the p-type base region 34a of the main semiconductor element 11 is n-type. + The portion sandwiched between the n-type source region 35a and the n-type current diffusion region 33a forms an n-type inversion layer (channel). As a result, the main current flows from the drain to the source of the main semiconductor element 11, and the main semiconductor element 11 is turned on.

[0188] At this time, under the same conditions as the main semiconductor element 11, when a positive voltage is applied to the drain electrode 51 relative to the source electrode (OC pad 22) of the current sensing unit 12, if a voltage higher than the threshold voltage is applied to the gate electrode 39b of the current sensing unit 12, the p-type base region 34b of the sensing active region 12a is n-type. + The portion sandwiched between the n-type source region 35b and the n-type current diffusion region 33b forms an n-type inversion layer. As a result, the sensing current flows from the drain to the source of the current sensing unit 12, and the current sensing unit 12 is turned on.

[0189] The sense current flows to the ground point GND through the resistor 15 connected to the source of the current sensing unit 12. As a result, a voltage drop occurs in the resistor 15. When an overcurrent is applied to the main semiconductor element 11, the sense current of the current sensing unit 12 increases in accordance with the magnitude of the overcurrent in the main semiconductor element 11, and the voltage drop in the resistor 15 also increases. By monitoring the magnitude of the voltage drop in the resistor 15, the overcurrent in the main semiconductor element 11 can be detected.

[0190] On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11, the first p + Type region 61a, second p + The n-type region 62a and the n-type current diffusion region 33a and n - The pn junction between the type drift region 32 is reverse biased. A voltage less than the threshold voltage is also applied to the gate electrode 39b of the current sensing unit 12, and the first p + Type region 61b, the second p + The n-type region 62b and the n-type current diffusion region 33b and n - The pn junction between the type drift regions 32 is also reverse biased. As a result, the main current of the main semiconductor element 11 and the sense current of the current sensing unit 12 are blocked, and the main semiconductor element 11 and the current sensing unit 12 are maintained in the off state.

[0191] When the main semiconductor element 11 is turned off, if a negative voltage is applied to the drain electrode 51 relative to the source electrode of the main semiconductor element 11, the p-type base region 34a of the main effective region 1a of the active region 1 and the first p + Type region 61a, second p + The n-type region 62a and the n-type current diffusion region 33a and n - The parasitic diode 16 formed by the pn junction between the active region 1 and the p-type drift region 32 is turned on. + Type region 62a and n - The parasitic diode 16 formed by the pn junction between the type drift regions 32 is turned on.

[0192] When the current sensing unit 12 is turned off, a negative voltage is applied to the drain electrode 51 relative to the source electrode of the current sensing unit 12. + Type region 61b, the second p + The n-type region 62b and the n-type current diffusion region 33b and n - The parasitic diode 17 formed by the pn junction between the p-type region and the n-type drift region 32 is turned on. - The parasitic diode formed by the pn junction of the drift region 32 is turned on.

[0193] On the other hand, since the floating p-type base region 34b' is not provided in the sensing ineffective region 12b of the main ineffective region 1b, no parasitic diode is formed. The region of the main ineffective region 1b where no parasitic diode is formed is arranged so as to surround the periphery of the sensing effective region 12a. Therefore, there is a region where no parasitic diode is formed between the parasitic diode 16 of the main semiconductor element 11 and the parasitic diode 17 of the current sensing unit 12.

[0194] Therefore, when the main semiconductor element 11 and the current sensing unit 12 are switched from off to on and the parasitic diode is turned off, the n - The hole current generated in the drift region 32 (the reverse recovery current of the parasitic diode 16 of the main semiconductor element 11) is not easily flown into the p-type base region 34b of the current sensing part 12 through the floating p-type base region 34b' of the sensing ineffective region 12b, and is drawn toward the source pad 21a through the p-type base region 34a of the main semiconductor element 11.

[0195] The hole current that can be drawn to the OC pad 22 through the p-type base region 34b of the current sensing unit 12 is almost entirely the n-type current near the sensing active region 12a. -The hole current generated in the p-type drift region 32 (the reverse recovery current of the parasitic diode 17 of the current sensing section 12) can be suppressed from excessively flowing to the p-type base region 34b of the sensing effective region 12a. As a result, the electric field applied to the current sensing section 12 can be relaxed, so the ESD tolerance of the current sensing section 12 can be increased, and the reverse recovery tolerance of the parasitic diode of the main ineffective region 1b can be improved.

[0196] Next, a method for manufacturing the semiconductor device 20 according to the first embodiment will be described. Figures 5 to 10 1 is a cross-sectional view showing a state of the semiconductor device of Embodiment 1 during the manufacturing process. Figures 5 to 10 Only the main semiconductor element 11 is shown in the figure, but the parts of all the elements made (manufactured) on the same semiconductor substrate 10 as the main semiconductor element 11 are formed simultaneously with the parts of the main semiconductor element 11. Figure 1 to Figure 3 The formation of each portion of the current sensing portion 12 , the temperature sensing portion 13 , and the gate pad portion 14 will be described.

[0197] First, if Figure 5 As shown, a silicon carbide-containing n + Type starting substrate (semiconductor wafer) 31. + The starting substrate 31 may be, for example, a nitrogen (N)-doped silicon carbide single crystal substrate. + The front side of the starting substrate 31 is made larger than n + The starting substrate 31 is doped with nitrogen at a low concentration. - When the main semiconductor element 11 is of 3300V withstand voltage class, n - The thickness t11 of the silicon carbide layer 71 may be, for example, approximately 30 μm.

[0198] Next, if Figure 6 As shown, by photolithography and ion implantation of p-type impurities such as Al, in the main effective region 1a, n - The surface regions of the type silicon carbide layer 71 selectively form the first p + Type region 61a and p + Type region 91. The p + Type region 91 is the second p + A portion of the type region 62a. The first p + Type region 61a and p + Type area 91 in for example Figure 1 The layers are alternately and repeatedly arranged in the first direction X.

[0199] The first p adjacent to each other + Type region 61a and p +The distance d2 between the type regions 91 may be, for example, about 1.5 μm. + Type region 61a and p + The depth d1 and impurity concentration of the type region 91 may be, for example, approximately 0.5 μm and 5.0×10 18 / cm 3 Then, remove the first p + Type region 61a and p + An ion implantation mask (not shown) is used in forming the type region 91.

[0200] Next, by photolithography and ion implantation of n-type impurities such as nitrogen, n-type impurities are formed in the n-type region 1a throughout the entire region of the main effective region 1a. - The surface region of the first p-type silicon carbide layer 71 forms an n-type region 92. The n-type region 92 is formed in the first p-type silicon carbide layer 71. + Type region 61a and p + The n-type regions 91 are formed in contact with these regions. The depth d3 and the impurity concentration of the n-type region 92 may be, for example, approximately 0.4 μm and 1.0×10 17 / cm 3 about.

[0201] The n-type region 92 is a part of the n-type current diffusion region 33a. - The n-type region 92 and the first p-type silicon carbide layer 71 are + Type region 61a and p + Type region 91 and n + The portion of the starting substrate 31 is n - Then, the ion implantation mask (not shown) used in forming the n-type region 92 is removed. The n-type region 92 and the first p-type region 92 may be changed. + Type region 61a and p + The formation order of the type region 91.

[0202] Next, if Figure 7 As shown, in n - The n-type silicon carbide layer 71 is further doped with n-type impurities such as nitrogen to a thickness t12 of, for example, 0.5 μm. - The type silicon carbide layer is epitaxially grown, and the n - The thickness of the silicon carbide layer 71 increases.

[0203] Next, photolithography and ion implantation of p-type impurities such as Al were used to deposit the n - The thickness of the portion 71a of the silicon carbide layer 71 is increased to reach the p + The depth of the type region 91 selectively forms p + Type area 93. The p adjacent to each other in the depth direction Z+ The type regions 91 and 93 are connected to each other to form a second p + Type region 62a. + The width and impurity concentration of the type region 93 are, for example, + Then, remove the p + An ion implantation mask (not shown) is used in forming the type region 93.

[0204] Next, photolithography and ion implantation of n-type impurities such as nitrogen are performed on n - The portion 71a of the silicon carbide layer 71 with increased thickness selectively forms an n-type region 94 at a depth reaching the n-type region 92. The impurity concentration of the n-type region 94 is, for example, substantially the same as that of the n-type region 92. The n-type regions 92 and 94 adjacent to each other in the depth direction Z are connected to each other to form an n-type current diffusion region 33a. The p-type region 94 may be changed. + The formation order of the n-type region 93 and the n-type region 94. Then, the ion implantation mask (not shown) used in the formation of the n-type region 94 is removed.

[0205] Next, if Figure 8 As shown, in n - A p-type silicon carbide layer 72 doped with a p-type impurity such as Al is epitaxially grown on the p-type silicon carbide layer 71. The thickness t13 and the impurity concentration of the p-type silicon carbide layer 72 may be, for example, approximately 1.3 μm and 4.0×10 17 / cm 3 Therefore, in n + n - The semiconductor substrate (semiconductor wafer) 10 having a p-type silicon carbide layer 71 and a p-type silicon carbide layer 72 is formed.

[0206] Next, a set of steps including photolithography, ion implantation, and removal of the ion implantation mask are repeated under different conditions to selectively form n-type silicon carbide layers 72 and 1a in the main effective region 1a. + Type source region 35a, p ++ Type contact regions 36a and n - Type area 32a (refer to Figure 2 ). - The type region 32a separates the area directly below the OC pad 22 of the main ineffective region 1b from the main effective region 1a.

[0207] Can change n + Type source region 35a, p ++ Type contact regions 36a and n - In the main effective area 1a, n + Type source region 35a and p++ The contact area 36a and n - The portion sandwiched by the p-type silicon carbide layers 71 is the p-type base region 34a. In each of the above-mentioned ion implantations, for example, a resist film or an oxide film can be used as a mask for ion implantation.

[0208] Next, for the diffusion region (first p + Type region 61a, second p + type region 62a, n-type current diffusion region 33a, n + Type source region 35a, p ++ Type contact regions 36a and n - The type region 32a) is subjected to heat treatment (activation annealing) for about 2 minutes at a temperature of about 1700°C for impurity activation. The activation annealing can be performed once after all the diffusion regions are formed, or it can be performed each time a diffusion region is formed by ion implantation.

[0209] Next, if Fig. 9 As shown, by photolithography and dry etching, a through-n + The trench 37a is formed by forming a first p-type source region 35a and a p-type base region 34a. The trench 37a is formed by forming a first p-type source region 35a and a p-type base region 34a. + The depth of the groove region 61a is determined by the etching mask used to form the groove 37a. For example, a resist film or an oxide film may be used. Then, the etching mask is removed.

[0210] Next, if Fig.10 As shown, a gate insulating film 38a is formed along the surface of the semiconductor substrate 10 and the inner wall of the groove 37a. The gate insulating film 38a can be, for example, a thermal oxide film formed at a temperature of about 1000°C in an oxygen (O2) atmosphere, or a deposited film obtained by high temperature oxidation (HTO: High Temperature Oxide). Next, inside the groove 37a, a polysilicon layer doped with phosphorus is formed on the gate insulating film 38a as a gate electrode 39a.

[0211] All elements other than the main semiconductor element 11 (for example, the current sensing part 12, the overvoltage protection part such as a diffused diode, and the CMOS (Complementary MOS) constituting the operation circuit part) can be formed in the main invalid region 1b of the semiconductor substrate 10 simultaneously with the corresponding parts of the main semiconductor element 11 during the formation of the above-mentioned parts of the main semiconductor element 11.

[0212] For example, the diffusion regions of the elements arranged in the semiconductor substrate 10 can be formed simultaneously with the diffusion regions of the same conductivity type, impurity concentration and diffusion depth in the diffusion regions constituting the main semiconductor element 11. In addition, the gate trench, gate insulating film and gate electrode of the elements arranged in the semiconductor substrate 10 can be formed simultaneously with the trench 37a, gate insulating film 38a and gate electrode 39a of the main semiconductor element 11, respectively. - The type region 32b can be connected to the n - The type region 32 a is simultaneously formed in the main ineffective region 1 b of the semiconductor substrate 10 .

[0213] Next, field insulating films 80a to 80c are formed on the front surface of the semiconductor substrate 10. Next, a polysilicon layer, for example, a phosphorus-doped polysilicon layer, which becomes an n-type polysilicon layer 82, is deposited on the field insulating film 80c, and a portion of the polysilicon layer is used as a p-type region to form a p-type polysilicon layer 81. Next, the polysilicon layer is patterned so that only the portions that become the p-type polysilicon layer 81 and the n-type polysilicon layer 82 remain. A gate flow channel (not shown) can be formed simultaneously with the formation of the p-type polysilicon layer 81 and the n-type polysilicon layer 82.

[0214] Next, interlayer insulating films 40 and 83 are formed on the entire front surface of the semiconductor substrate 10. The interlayer insulating films 40 and 83 may be, for example, PSG (Phospho Silicate Glass). The thickness of the interlayer insulating films 40 and 83 may be, for example, about 1 μm. Next, the interlayer insulating film 40 and the gate insulating films 38a and 38b are selectively removed by photolithography and etching to form the first contact hole 40a and the second contact hole 40b.

[0215] At this time, an n-type region is formed in which the main semiconductor element 11 is exposed. + Type source region 35a and p ++ The first contact hole 40a of the type contact region 36a is formed in the sensing effective region 12a to expose the current sensing portion 12. + Type source region 35b and p ++ Next, the interlayer insulating films 40 and 83 are planarized (reflowed) by heat treatment.

[0216] Next, first TiN films 42a and 42b are formed on the entire front surface of the semiconductor substrate 10 by, for example, sputtering. The first TiN films 42a and 42b cover the entire surface of the interlayer insulating films 40 and 83, and cover the portions of the front surface of the semiconductor substrate 10 exposed in the first contact holes 40a and the second contact holes 40b (n + Type source regions 35a, 35b and p ++ Type contact areas 36a, 36b).

[0217] Next, the portions of the first TiN films 42a and 42b covering the semiconductor substrate 10 in the first contact hole 40a and the second contact hole 40b are removed by photolithography and etching, thereby forming the n + Type source regions 35a, 35b and p ++ Thus, the first TiN films 42a and 42b are left as barrier metals 46a and 46b on the entire surface of the interlayer insulating films 40 and 83.

[0218] Next, a Ni film (not shown) is formed on the semiconductor portion (front surface of the semiconductor substrate 10) exposed in the first contact hole 40a and the second contact hole 40b by, for example, sputtering. At this time, a Ni film is also formed on the first TiN films 42a and 42b. Next, the contact position of the Ni film with the semiconductor portion is silicided by, for example, heat treatment at about 970°C, thereby forming NiSi films 41a and 41b that are in ohmic contact with the semiconductor portion.

[0219] During the heat treatment for silicidation of nickel, the first TiN films 42a and 42b are arranged between the interlayer insulating film 40 and 83 and the Ni film, so that nickel atoms in the Ni film can be prevented from diffusing into the interlayer insulating film 40 and 83. Since the portion of the Ni film on the interlayer insulating film 40 and 83 is not in contact with the semiconductor portion, it is not silicidated. Thereafter, the portion of the Ni film on the interlayer insulating film 40 and 83 is removed to expose the interlayer insulating film 40 and 83.

[0220] Next, a Ni film, for example, is formed on the back surface of the semiconductor substrate 10. Next, the Ni film is silicided by, for example, a heat treatment at about 970°C, and a NiSi film is formed as the drain electrode 51 in ohmic contact with the semiconductor portion (the back surface of the semiconductor substrate 10). The heat treatment for silicide when forming the NiSi film that becomes the drain electrode 51 can be performed simultaneously with the heat treatment for forming the NiSi films 41a and 41b on the front surface of the semiconductor substrate 10.

[0221] Next, by sputtering, first Ti films 43a, 43b, second TiN films 44a, 44b, second Ti films 45a, 45b, which become barrier metals 46a, 46b, and Al films (or Al alloy films) which become source pads 21a, gate pads 21b, and OC pads 22 are sequentially stacked on the front surface of the semiconductor substrate 10. The thickness of the Al film is, for example, about 5 μm or less.

[0222] Next, the metal film deposited on the front surface of the semiconductor substrate 10 is patterned by photolithography and etching, and portions that become the barrier metals 46a, 46b, the source pad 21a, the gate pad 21b, the OC pad 22, the OV pad (not shown) of the overvoltage protection unit, and the electrode pad (not shown) of the operation circuit unit remain. The metal film on the front surface of the semiconductor substrate 10 is formed in a state where the temperature sensing unit 13 is covered with, for example, a resist mask.

[0223] Next, after removing the resist mask covering the temperature sensing portion 13, the interlayer insulating film 83 is selectively removed by photolithography and etching to form a third contact hole 83a and a fourth contact hole 83b, respectively exposing the p-type polysilicon layer 81 and the n-type polysilicon layer 82 in the third contact hole 83a and the fourth contact hole 83b. Next, the interlayer insulating film 83 is planarized by heat treatment.

[0224] Next, an Al film (or Al alloy film) is formed on the front surface of the semiconductor substrate 10 so as to be buried in the third contact hole 83a and the fourth contact hole 83b and patterned, thereby forming the anode pad 23a and the cathode pad 23b of the temperature sensing unit 13. Next, a Ti film, a Ni film, and a gold (Au) film are sequentially stacked on the surface of the drain electrode 51 by, for example, sputtering to form a drain pad (not shown).

[0225] Next, the front surface of the semiconductor substrate 10 is protected by a polyimide film by, for example, chemical vapor deposition (CVD). Next, the polyimide film is selectively removed by photolithography and etching to form first protective films 49a to 49c covering the electrode pads respectively, and these first protective films 49a to 49c are opened.

[0226] Next, after the usual electroplating pre-treatment, the plating films 47a to 47d are formed on the portions of the electrode pads 21a, 21b, 22, 23a, and 23b exposed in the openings of the first protective films 49a to 49c by the usual electroplating treatment. At this time, the first protective films 49a to 49c function as masks to suppress the wetting and spreading of the plating films 47a to 47d. The thickness of the plating films 47a to 47d can be, for example, about 5 μm.

[0227] Next, a polyimide film is formed to cover the boundaries between the plating films 47a to 47d and the first protective films 49a to 49c by, for example, CVD. Next, the terminal pins 48a to 48d are joined to the plating films 47a to 47d through solder layers (not shown). At this time, the second protective films 50a to 50c function as masks that inhibit the wetting and spreading of the solder layers.

[0228] Thereafter, the semiconductor substrate 10 is diced (cut) and singulated into individual chips, thereby completing the process. Figure 1 to Figure 3 A semiconductor device 20 is shown.

[0229] As described above, according to Embodiment 1, a unit cell of the current sensing part is arranged in a part directly below the OC pad of the main inactive region of the active region as a sensing effective region, and a region surrounding the sensing effective region directly below the OC pad of the main inactive region is used as a sensing ineffective region where the unit cell of the current sensing part is not arranged. A floating p-type base region is arranged in the sensing ineffective region. Thus, a parasitic diode is formed only in the sensing effective region directly below the OC pad of the main inactive region, and a parasitic diode is not formed in the sensing ineffective region.

[0230] That is, there is a sensing ineffective region where no parasitic diode is formed between the parasitic diode of the main semiconductor element in the main effective region and the parasitic diode of the current sensing part in the sensing effective region. Therefore, when the main semiconductor element and the current sensing part are switched from off to on at the same time, and the parasitic diodes of the main semiconductor element and the current sensing part are turned off at the same time, the hole current (reverse recovery current of the parasitic diode of the main semiconductor element) generated in the main effective region can be suppressed from flowing into the current sensing part, and the reverse recovery tolerance of the parasitic diode in the main ineffective region can be improved.

[0231] In addition, according to Embodiment 1, by configuring the p-type base region in the surface region of the front surface of the semiconductor substrate in the sensing ineffective region, the electric field can be made uniform in the front surface of the semiconductor substrate in the sensing ineffective region, thereby improving the withstand voltage. Therefore, in the sensing ineffective region, it is possible to suppress the electric field from being locally concentrated on the field insulating film, and to suppress the insulation breakdown of the field insulating film.

[0232] (Implementation Method 2)

[0233] Next, a semiconductor device according to Embodiment 2 will be described. Fig.11 2 is a plan view showing the layout of the semiconductor device of the second embodiment as viewed from the front side of the semiconductor substrate. The semiconductor device 20' of the second embodiment is different from the semiconductor device 20 of the first embodiment (see FIG. Figure 1 to Figure 3 ) is different in that it has the feature of making n near the main invalid area 1b - The hole current generated in the drift region 32 is led to a metal electrode (hereinafter referred to as an extraction electrode) 18 at a ground point GND of a ground potential.

[0234] The extraction electrode 18 is provided on the front surface of the semiconductor substrate 10 in the main ineffective region 1b and is electrically connected to the p-type base region 34c. The extraction electrode 18 is fixed to the potential of the source pad 21a (source potential: ground potential). The extraction electrode 18 is provided, for example, at the outer peripheral portion of the main ineffective region 1b except for the portion where the connection portion 19 between the gate pad 21b and the gate metal electrode (not shown) is arranged. The gate metal electrode is a metal layer provided on the gate flow channel and electrically connected to the gate flow channel.

[0235] The extraction electrode 18 has parasitic diodes 16 and 17 in the active region 1 (see Figure 4 ) is turned off, the n-type base region 34c of the main effective region 1a and / or the edge terminal region 2 is connected to the n-type base region 34c of the main effective region 1a and / or the edge terminal region 2 - The hole current generated in the drift region 32 and flowing into the main ineffective region 1b is guided to the ground point GND of the ground potential. Fig.11 In FIG. 1 , the inner periphery of the extraction electrode 18 is indicated by a dotted line. The outer periphery of the extraction electrode 18 is the same as the outer periphery of the main ineffective region 1 b.

[0236] As described above, according to Embodiment 2, the same effect as that of Embodiment 1 can be obtained. In addition, according to Embodiment 2, by providing an extraction electrode that is fixed at the source potential and electrically connected to the p-type base region in the main invalid region, when the parasitic diode in the active region is turned off, the hole current flowing to the main invalid region can be extracted from the extraction electrode, so that the reverse recovery tolerance of the parasitic diode in the main invalid region can be further improved.

[0237] (Example)

[0238] Next, the reverse recovery resistance of the semiconductor device 20 according to the first embodiment will be examined. Fig.12 The semiconductor device 20 of the first embodiment described above (hereinafter referred to as the embodiment: see Figure 1 ) and a conventional semiconductor device 120 (hereinafter referred to as a conventional example: Fig.13 The results are shown in Figure 2. Fig.12 .

[0239] like Fig.12 As shown, it is confirmed that in the embodiment, compared with the conventional example, the parasitic diodes 16 and 17 (see Figure 4 ) is turned off, the amount of hole current drawn to the source pad 21a through the p-type base region 34a of the main active region 1a increases. This is because in the embodiment, n is arranged in the main inactive region 1b so as to surround the periphery of the sensing active region 12a. -The type region 32b makes it difficult for the hole current generated near the main ineffective region 1b to flow to the sensing effective region 12a, and the reverse recovery resistance of the parasitic diode 17 of the main ineffective region 1b is improved.

[0240] Although not shown in the figure, the inventors have confirmed that the same effects as those of the examples can be obtained in the semiconductor device 20 ′ according to the second embodiment.

[0241] As described above, the present invention is not limited to the above-mentioned embodiments, and various changes can be made without departing from the scope of the main purpose of the present invention. For example, in the main invalid region, the surface area of ​​the floating p-type base region is increased by extending the floating p-type base region from the sensing invalid region to the area other than directly below the OC pad, thereby increasing the reverse recovery tolerance of the parasitic diode formed in the main invalid region. At this time, the surface area of ​​the p-type base region fixed to the source potential of the main semiconductor element in the main invalid region is reduced by the portion of the increased surface area of ​​the floating p-type base region. In addition, the p-type base region fixed to the source potential of the main semiconductor element can be extended to directly below the OC pad in the main invalid region.

[0242] In the main ineffective region, the ratio of the surface area of ​​the floating p-type base region to the surface area of ​​the p-type base region fixed to the source potential of the main semiconductor element can be determined by, for example, the trade-off between the forward voltage and the reverse recovery tolerance of the parasitic diode formed in the main ineffective region. In addition, for example, a planar gate structure can be provided instead of a trench gate structure. In addition, the present invention can also be applied when a wide bandgap semiconductor other than silicon carbide is used as a semiconductor material instead of silicon carbide as a semiconductor material. In addition, the present invention is also applicable even if the conductivity type (n-type, p-type) is reversed.

[0243] Industrial Applicability

[0244] As described above, the semiconductor device of the present invention is useful for a semiconductor device including a current sensing portion on the same semiconductor substrate as a main semiconductor element, and is particularly suitable for a semiconductor device that needs to set a larger surface area of ​​a main inactive region where the main semiconductor element does not function.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate comprising a semiconductor having a band gap wider than that of silicon; A first first conductivity type region, which is disposed inside the semiconductor substrate; a first second conductivity type region, which is arranged between the first main surface of the semiconductor substrate and the first first conductivity type region; A first insulated gate field effect transistor, which uses the first first conductivity type region as a drift region and the first second conductivity type region as a base region; A first source pad of the first insulated gate field effect transistor is disposed on the first main surface of the semiconductor substrate and is electrically connected to the first second conductivity type region; a second second conductivity type region, which is disposed in a region different from the first second conductivity type region and between the first main surface of the semiconductor substrate and the first first conductivity type region; a second insulated gate field effect transistor, which uses the first first conductivity type region as a drift region and the second second conductivity type region as a base region, and has a plurality of cells whose number is less than that of the first insulated gate field effect transistor and whose cell structure is the same as that of the first insulated gate field effect transistor; a second source pad of the second insulated gate field effect transistor, which is disposed on the first main surface of the semiconductor substrate in a manner separated from the first source pad and is electrically connected to the second second conductivity type region; a third floating second conductive type region, which is disposed between the first main surface of the semiconductor substrate and the first first conductive type region in an inactive region other than the first active region of the cell configured with the first insulated gate type field effect transistor and the second active region of the cell configured with the second insulated gate type field effect transistor, in a manner separated from the first active region and the second active region, and surrounds the periphery of the second active region; as well as A drain electrode is electrically connected to the second main surface of the semiconductor substrate and is shared by the first insulated gate field effect transistor and the second insulated gate field effect transistor.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises a second first conductivity type region, the second first conductivity type region being disposed between the second second conductivity type region and the third second conductivity type region and surrounding the second second conductivity type region. The surface area of ​​the second first conductivity type region is larger than the surface area of ​​the second effective region.

3. The semiconductor device according to claim 1, wherein: The distance between the second second conductivity type region and the third second conductivity type region is 0.1 μ m or more.

4. The semiconductor device according to claim 1, wherein: The second effective area is a portion of the area directly below the second source pad. The third second conductive type region is disposed in a region directly below the second source pad except for the second active region.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: One or more electrode pads are provided on the first main surface of the semiconductor substrate in the ineffective region in a manner separated from the first source pad and the second source pad; as well as The fourth second conductive type region is disposed between the first main surface of the semiconductor substrate and the first first conductive type region directly below all the electrode pads in a manner separated from the third second conductive type region and is electrically connected to the first second conductive type region.

6. The semiconductor device according to claim 5, wherein: The electrode pad is a gate pad of the first insulated gate field effect transistor.

7. The semiconductor device according to claim 5, wherein: The semiconductor device includes the electrode pad of the diode for detecting the temperature of the first insulated gate field effect transistor.

8. The semiconductor device according to claim 5, wherein: The semiconductor device includes the electrode pad of the diode that protects the first insulated gate field effect transistor from an overvoltage.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that The second insulated gate field effect transistor detects an overcurrent flowing through the first insulated gate field effect transistor.

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