Semiconductor structure and method for forming the same

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same. The semiconductor structure includes a first active region, a gate structure, a gate cut-off feature, and a channel isolation feature. The first active region is located on a substrate and extends along a first direction. The gate structure is located on the first active region and extends along a second direction. The second direction is perpendicular to the first direction. The gate cut-off feature is adjacent to one end of the gate structure. The channel isolation feature extends along the second direction and is located between the first and second active regions. The gate structure includes a metal electrode directly contacting the gate cut-off feature. The channel isolation feature includes a liner on a sidewall extending along the second direction and a dielectric filling layer between the sidewalls. The gate cut-off feature is adjacent to one end of the channel isolation feature, and the dielectric filling layer is in direct contact with the gate cut-off feature.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure, and in particular to a semiconductor structure having a wrap-around gate transistor. Background Art

[0002] Integrated circuits are formed on a semiconductor substrate and include various components, such as transistors, diodes, and / or resistors, which are configured and connected together and to functional circuits. In particular, the integrated circuit also includes a field effect transistor (FET), such as a metal oxide semiconductor field effect transistor (MOSFET) or a complementary MOSFET, wherein each field effect transistor includes a gate electrode to control the active region of the corresponding FET. When semiconductor components (such as MOSFETs) are scaled down through various technology generations, high dielectric constant dielectric materials and metals are used to form metal gate structures. However, in the method of forming metal gate structures for n-type MOS (nMOS) transistors and p-type MOS (pMOS) transistors, various problems arise when integrating processes and materials for this purpose. For example, when a metal gate is formed by gate replacement, since the gate dielectric layer is also formed on the sidewalls, the window of the line-end process is insufficient, leaving less openings that cannot be filled with metal or metal alloys to form the gate electrode. In addition, after the metal gate structure has been formed, when forming a channel isolation trench for a gate-all-around (GAA) FET, it may take a long time to remove the metal gate electrode, the gate dielectric layer, and the channel members, thereby damaging the device performance and reducing the yield. Therefore, it is desirable to have a new device structure and a manufacturing method thereof to solve the above problems. Summary of the invention

[0003] The present disclosure provides a semiconductor structure. The semiconductor structure includes a first active region, a gate structure, a gate cut-off feature and a channel isolation feature. The first active region is located on a substrate and extends along a first direction. The gate structure is located on the first active region and extends along a second direction, wherein the second direction is perpendicular to the first direction. The gate cut-off feature is adjacent to one end of the gate structure. The channel isolation feature extends along the second direction and is located between the first active region and a second active region. The gate structure includes a metal electrode directly contacting the gate cut-off feature. The channel isolation feature includes a liner on a sidewall extending along the second direction and a dielectric filling layer between the sidewalls. The gate cut-off feature is adjacent to one end of the channel isolation feature, and the dielectric filling layer is in direct contact with the gate cut-off feature.

[0004] Furthermore, an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first active region, a first gate structure, a gate cut-off feature and a channel isolation feature. The first active region is located on a substrate and extends along a first direction. The first gate structure is located on the first active region and extends along a second direction, wherein the second direction is perpendicular to the first direction. The gate cut-off feature is adjacent to one end of the first gate structure. The channel isolation feature extends along the second direction and is located between a second gate structure and a third gate structure. The channel isolation feature is arranged between the first active region and a second active region extending along the first direction. The second gate structure and the third gate structure include a gate dielectric layer. The channel isolation feature includes a pad located on the sidewall and a dielectric filling layer surrounded by the sidewall. The pad of the channel isolation feature is in direct contact with the gate dielectric layer of the second and third gate structures.

[0005] Furthermore, the present disclosure provides a method for forming a semiconductor structure. The method includes: providing a semiconductor structure, wherein the semiconductor structure includes a first active region and a plurality of dummy gate structures above the first active region; forming a channel isolation feature to divide the first active region into a first section and a second section; after forming the channel isolation feature, removing the dummy gate structure; patterning the first active region to form a plurality of channel components; forming a plurality of gate structures on the semiconductor structure to surround the channel components; etching the gate structure to form a gate cut-off opening; and depositing a dielectric material in the gate cut-off opening to form a gate cut-off feature. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a flow chart showing a method for manufacturing a semiconductor structure having a multi-fin structure according to some embodiments of the present disclosure.

[0007] Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Fig.10a and Fig.11a 1 is a top view showing a semiconductor structure at various manufacturing stages according to some embodiments of the present disclosure.

[0008] Figure 2b , Figure 3b , Figure 4b , Figure 5b , Figure 6b , Figure 7b , Figure 8b , Figure 9b , Fig.10b and Fig.11b It is to show that according to some embodiments of the present disclosure Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Fig.10a and Fig.11a A cross-sectional view of a semiconductor structure along line XX' at various manufacturing stages.

[0009] Figure 2c , Figure 3c , Figure 4c , Figure 5c , Figure 6c , Figure 7c , Figure 8c , Fig.9c , Fig.10c and Fig.11c It is to show that according to some embodiments of the present disclosure Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Fig.10a and Fig.11a sectional views of the semiconductor structure along line Y1 -Y1 ′ at various manufacturing stages.

[0010] Figure 5d , Figure 6d , Figure 7d , Figure 8d , Figure 9d , Fig.10d and Fig.11d It is to show that according to some embodiments of the present disclosure Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Fig.10a and Fig.11a sectional views of the semiconductor structure along line Y2-Y2' at various manufacturing stages.

[0011] Figure 12-Figure 17 is a top view showing a semiconductor structure according to some embodiments of the present disclosure.

[0012] The reference numerals are described as follows:

[0013] 100: Methods

[0014] 102, 104, 106, 108, 110, 112, 114, 116, 118: Box

[0015] 200: Semiconductor structure

[0016] 203: Isolation Features

[0017] 204: Active Zone

[0018] 2041: Silicon layer

[0019] 2042: Germanium layer

[0020] 206: Pseudo-gate structure

[0021] 208, 212, 228: Hard mask layer

[0022] 210: ILD layer

[0023] 213: Opening

[0024] 214, 2140: concave part

[0025] 216: First dielectric layer

[0026] 218: Second dielectric layer

[0027] 219: Channel Isolation Features

[0028] 220: Gate trench

[0029] 224: Gate dielectric layer

[0030] 226: Gate electrode

[0031] 227: Metal Gate Structure

[0032] 230: Gate cut-off opening

[0033] 232: Gate cut-off feature DETAILED DESCRIPTION

[0034] It should be understood that the following description provides many different embodiments, or examples, to implement the different features of various embodiments. The following description of specific component examples and arrangements is to simplify the present disclosure. These are of course only examples and are not intended to be limiting. In addition, the present disclosure repeats reference numbers and / or text in each example. These repetitions are for the purpose of simplicity and clarity and do not self-define the relationship between the various embodiments and / or structures discussed.

[0035] In addition, the present disclosure repeats reference numbers and / or text in various examples. These repetitions are for the purpose of simplicity and clarity and are not self-defining the relationship between the various embodiments and / or structures discussed. In addition, the form of a feature on another feature, a feature connected to, and / or coupled to another feature in the present disclosure may include an embodiment in which the features are directly in contact, and may also include an embodiment in which additional features are inserted into the features, so that the features may not be in direct contact. In addition, spatially relative terms, for example, "lower", "higher", "horizontal", "vertical", "above...", "below...", "up", "down", "top", "bottom", etc. and their derivatives (such as horizontally, downwardly, upwardly, etc.) are used in the case of the present disclosure. One feature is related to another feature. Spatially related terms are intended to cover different directions of the device having the feature. In addition, "about" or "approximately" used herein, unless otherwise specified, the term is intended to cover numbers within the range of ±10% of the number. For example, the term "about 5nm" includes a size range of 4.5nm to 5.5nm.

[0036] The present disclosure provides various embodiments of semiconductor structures formed on a semiconductor substrate. The semiconductor structure includes various devices, such as a field effect transistor (FET) having a metal gate structure, and its metal gate structure has a gate dielectric layer of a dielectric material with a high dielectric constant and a gate electrode of a metal or metal alloy. The semiconductor structure also includes a channel isolation feature and a gate cut feature integrated with the metal gate structure. In some conventional methods, the channel isolation feature and the gate cut feature are formed before using a functional metal gate structure to replace a polysilicon dummy gate. In those conventional methods, the filling window for the gate dielectric and the gate electrode between the active region and the gate cut feature may be too small to form a reliable gate electrode, resulting in low yield. In some other conventional methods of forming the channel isolation feature after forming the metal structure, it may be difficult to etch through the active region of the GAA FET to form a channel isolation trench for the channel isolation feature. In some embodiments, the present disclosure provides a method of forming a channel isolation feature before forming a metal gate and forming a gate cut feature after forming a metal gate to reduce process complexity and expand the process window, thereby improving productivity and device performance.

[0037] Figure 1 1 is a flow chart showing a method 100 for fabricating a semiconductor structure having a fin field effect transistor (FinFET) or a gate-all-around fin field effect transistor (GAA FET) and a metal gate structure according to some embodiments. The method 100 includes blocks 102, 104, 106, 108, 110, 112, 114, 116, and 118. Figure 2a-Figure 11a , Figure 2b-Figure 11b , Figure 2c-Figure 11c and Figure 5d-Figure 11d The method 100 is described with reference to a top view and a cross-sectional view of a semiconductor structure 200 . Figure 2a-Figure 11a is a top view of the semiconductor structure 200 . Figure 2b to Figure 11b is Figure 2a-Figure 11a A cross-sectional view of the semiconductor structure along line XX' in FIG. Figure 2c-Figure 11c is Figure 2a-Figure 11a A cross-sectional view of the semiconductor structure along line Y1-Y1' in FIG. Figure 5d-Figure 11d is Figure 2a-Figure 11a 1. A cross-sectional view of the semiconductor structure along line Y2-Y2' in FIG. Additional steps may be provided before, during, and after method 100, and certain steps described may be moved, replaced, or eliminated for other embodiments of method 100.

[0038] refer to Figure 1 as well as Figure 2a , Figure 2b and Figure 2c The method 100 includes block 102 , where a semiconductor structure 200 is provided. The semiconductor structure 200 includes an active region 204 and a plurality of dummy gate structures 206 above the active region 204 . Figure 2a , Figure 2b and Figure 2c The semiconductor structure in is fabricated on a substrate, which is not shown for simplicity. The substrate includes germanium, silicon germanium or other suitable semiconductor materials. The substrate may alternatively be made of other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as silicon carbide, indium arsenide or indium phosphide; or suitable alloy semiconductors, such as silicon germanium carbide, gallium arsenide phosphide or gallium indium phosphide. The substrate may also include various doped regions, such as n-type well regions and p-type well regions. In one embodiment, the substrate includes an epitaxial semiconductor layer. In another embodiment, the substrate includes a buried dielectric material layer for isolation formed by an appropriate technique, such as a technique known as separation by implanted oxygen (SIMOX). In some embodiments, the substrate may be a semiconductor on an insulator, such as silicon on insulator (SOI).

[0039] Still refer to Figure 2a , Figure 2b and Figure 2c , the semiconductor structure 200 includes an active region (or semiconductor feature) 204, which will be formed as a channel region and source / drain region of one or more field effect transistors (FETs). The active region 204 protrudes from the substrate and includes a bottom embedded in the insulating feature 203, and the isolation feature 203 may also be referred to as a shallow trench isolation (STI) feature 203. In various embodiments, the active region 204 can be formed by patterning the substrate or patterning one or more epitaxial layers formed on the substrate. Figure 2c In an embodiment of the present invention, the active region 204 is formed by alternately stacking different semiconductor layers. In one exemplary embodiment, the alternately stacked semiconductor layers include a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers in an alternating manner. In some embodiments, the first semiconductor layer includes silicon and the second semiconductor layer includes germanium. In some cases, a hard mask is deposited on the alternately stacked semiconductor layers and patterned by a lithography process. The hard mask layer includes a dielectric, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride and / or a semiconductor carbide. In an exemplary embodiment, the hard mask layer includes a silicon oxide film and a silicon nitride film. The hard mask layer can be formed by thermal growth, atomic layer deposition (ALD), chemical vapor deposition (CVD), high density plasma chemical vapor deposition (HDP-CVD), and other suitable deposition processes. A photoresist layer (or photoresist) for defining a fin structure can be formed on the hard mask layer. An exemplary photoresist layer includes a photosensitive material that undergoes a qualitative change when exposed to, for example, ultraviolet (UV) light, deep ultraviolet (DUV) light, or extreme ultraviolet (EUV) light. The qualitative change can be used to selectively remove exposed or unexposed portions of the photoresist layer by a developing process. This process of forming a patterned photoresist layer is also called photolithographic patterning.

[0040] In one embodiment, the photoresist layer is patterned by a lithography process, leaving a portion of the photoresist material disposed on the semiconductor structure 200. After patterning the photoresist layer, an etching process is performed on the semiconductor structure 200 to create an opening in the hard mask layer, thereby transferring the pattern of the photoresist layer to the hard mask layer. The remaining photoresist layer can be removed after patterning the hard mask layer. An exemplary lithography process includes photoresist layer spin coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist layer development, cleaning and air drying (e.g., hard baking). Alternatively, the lithography process may be performed, added to, or replaced by other methods, such as maskless lithography, electron beam direct writing, and ion beam direct writing. The etching process for patterning the hard mask layer may include wet etching, dry etching, or a combination of the above processes. The etching process may include multiple etching steps. For example, a silicon oxide film in the hard mask layer can be etched by a diluted hydrofluorine solution, and a silicon nitride film in the hard mask layer can be etched by a phosphoric acid solution.

[0041] In the etching process, the portions of the stacked semiconductor layers that are not covered by the patterned hard mask layer are then etched. The patterned hard mask layer is used as an etching mask in the etching process to pattern the stacked semiconductor layers. The etching process may include any suitable etching technique, such as dry etching, wet etching and / or other etching methods (e.g., reactive ion etching (RIE)). In some embodiments, the etching process includes multiple etching steps with different etching chemical compositions, which are designed to etch the stacked semiconductor layers to form grooves with specific groove profiles to enhance device performance and pattern density. In some examples, the semiconductor material of the stacked semiconductor layers can be etched by a dry etching process using a fluorine-based etchant. After the etching process, the active region 204 is defined above the substrate.

[0042] One or more dielectric materials are filled in the recesses defined between adjacent active regions 204 to form shallow trench isolation features 203. Suitable fill dielectric materials include semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, fluorosilicone glass (FSG), low dielectric constant dielectric materials, and / or combinations thereof. In various exemplary embodiments, the dielectric material is formed by a high density plasma chemical vapor deposition (HDP-CVD) process, a sub-atmospheric pressure chemical vapor deposition (SACVD) process, a high aspect ratio process (HARP), a flow chemical vapor deposition (FCVD) and / or a spin coating process. The deposition of the dielectric material may be continued by a chemical mechanical polishing / planarization (CMP) process to remove excess dielectric material and planarize the top surface of the semiconductor structure. The chemical mechanical polishing process may utilize a hard mask layer as a polishing stop layer to avoid polishing to the active region 204.

[0043] Then, the STI feature 203 is pulled back or etched back so that the active region 204 protrudes above the STI feature 203. The pull-back / etch-back process uses one or more etching steps (such as dry etching, wet etching, or a combination thereof) to selectively etch back the STI feature 203. For example, when the STI feature 203 is silicon oxide, a hydrofluoric acid wet etching process can be used for etching. Figure 2a , Figure 2b and Figure 2c 204 extend along the X direction and are spaced apart from each other along the Y direction. In some embodiments, the pullback of the STI features 203 can also remove the hard mask on top of the active region 204. In an embodiment where the alternating stack of semiconductor layers includes silicon layers and germanium layers and is formed on a substrate, the active region 204 includes a silicon layer 2041 interlaced with a germanium layer 2042. In some cases, the silicon layer 2041 can be formed as a channel member of a GAA device, such as a nanowire GAA transistor or a nanosheet GAA transistor.

[0044] Still refer to Figure 2a , Figure 2b and Figure 2c As shown in the figure, the semiconductor structure 200 further includes a plurality of dummy gate structures 206. The dummy gate structures 206 have an elongated shape and extend along the Y direction. Each dummy gate structure 206 is disposed on one or more active regions 204 ( Figure 2aOnly one is shown in the figure). The dummy gate structures 206 may each include a dummy gate dielectric layer and a dummy gate electrode on the dummy gate dielectric layer. The dummy gate dielectric layer includes a dielectric material such as silicon oxide, and the dummy gate electrode includes polysilicon. The dummy gate structures 206 may also be referred to as placeholder gate structures because they will be replaced by metal gate structures, such as metal gate structure 227, as described below. The formation of the dummy gate structure 206 includes depositing a dummy gate material (including forming silicon oxide and polysilicon in this exemplary embodiment); and patterning the gate material through a development process and etching. A hard mask layer 208 may be formed on the dummy gate material and serve as an etching mask during the formation of the dummy gate structure 206. The hard mask layer 208 may include any suitable material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and other suitable materials and / or combinations thereof. In one embodiment, the hard mask layer 208 includes a plurality of films, such as silicon oxide and silicon nitride. In some embodiments, the patterning process for forming the dummy gate structure 206 includes forming a patterned photoresist layer by a lithography process; etching the hard mask layer 208 using the patterned photoresist layer as an etching mask; and etching the dummy gate material using the patterned hard mask layer as an etching mask to form the dummy gate structure 206.

[0045] One or more gate spacers (not shown for simplicity) are formed on the sidewalls of the dummy gate structure 206. The gate spacers can be used to offset the source / drain features that are subsequently formed and can be used to design or modify the source / drain structure profile. The gate spacers may include any suitable dielectric material, such as semiconductor oxides, semiconductor nitrides, semiconductor carbides, semiconductor oxynitrides, other suitable dielectric materials, and / or combinations thereof. The gate spacers may include multiple films, such as two films (silicon oxide film and silicon nitride film) or three films (silicon oxide film, silicon nitride film, and silicon oxide film). The formation of the gate spacers includes deposition and anisotropic etching, such as dry etching.

[0046] Despite Figure 2a , Figure 2b and Figure 2cAlthough not clearly shown in the figure, the semiconductor structure 200 may include source / drain features adjacent to the plurality of dummy gate structures 206. The source and drain may include a lightly doped drain (LDD) feature and a heavily doped source and drain (S / D). In some embodiments, a plurality of field effect transistors (FETs) may be formed on the semiconductor structure, and each field effect transistor includes a source / drain feature formed on a corresponding active region 204, and the source / drain feature is inserted by one of the dummy gate structures 206. A channel region is formed in a portion of the active region 204, which is below the corresponding dummy gate structure 206. The channel region is laterally sandwiched between two source / drain features.

[0047] Source / drain features can be formed by selective epitaxial growth to produce a strain effect with enhanced carrier mobility and device performance. The pseudo gate structure 206 and the gate spacer define the source / drain region where the source / drain features are formed. In some embodiments, the source / drain features are formed by one or more epitaxial processes, wherein silicon features, silicon germanium features, silicon carbide features, and / or other suitable features are grown in a crystalline state on the active region 204. Alternatively, prior to epitaxial growth, an etching process is used to etch back the source / drain region. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, and / or other suitable processes. The epitaxial process can use gas and / or liquid precursors that interact with the components of the active region 204.

[0048] The source / drain features can be doped in-situ during the epitaxial process by introducing dopants, and the dopants include: P-type dopants, such as boron or BF2; N-type dopants, such as phosphorus or arsenic; and / or other suitable dopants, including combinations thereof. If the source and drain are not doped in-situ, an implantation process (i.e., an interface implantation process) is performed to introduce the corresponding dopants into the source and drain. In an exemplary embodiment, the source / drain features in the n-type FET include silicon carbide or silicon doped with phosphorus, and the source / drain features in the p-type FET include germanium or silicon germanium doped with boron. In some other embodiments, the source / drain features include more than one semiconductor material layer. For example, a silicon germanium layer is epitaxially grown on a substrate in the source / drain region, and a silicon layer is epitaxially grown on the silicon germanium layer. Thereafter, one or more annealing processes may be performed to activate the source / drain features. Suitable annealing processes include rapid thermal annealing (RTA), laser annealing processes, other suitable annealing techniques, or combinations thereof.

[0049] refer to Figure 1 and Figure 3a-3cThe method 100 includes block 104 , in which an interlayer dielectric (ILD) layer 210 is formed over the semiconductor structure 200 . Figure 3a is a schematic top view of the semiconductor structure 200 . Figure 3b yes Figure 3a The cross-sectional view of the semiconductor structure 200 along the line XX' is shown in FIG. Figure 3c yes Figure 3a 200 is a cross-sectional view of the semiconductor structure 200 along the Y1-Y1' line. The ILD layer 210 is arranged in the space between the adjacent pseudo gate structures 206. After the pseudo gate structure 206 is removed, the ILD layer 210 and the gate spacer define the gate trench, and the metal gate structure will be formed in the gate trench. The ILD layer 210 can also be a part of the electrical interconnection structure, and the electrical interconnection structure is the various elements of the electrically interconnected semiconductor structure 200. In such an embodiment, the ILD layer 210 is an insulator that supports and isolates the conductive wires, wires and via contacts. The ILD layer 210 may include any suitable dielectric material, such as semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, other suitable dielectric materials or combinations thereof. In some embodiments, the formation of the ILD layer 210 includes deposition and CMP to provide a planarized top surface. The hard mask 208 can be removed at this stage, for example, by CMP or another etching process.

[0050] refer to Figure 1 and Figure 4a-4c , Figure 5a-5d and Figure 6a-6d , method 100 includes block 106, in which channel isolation features 219 are formed. Figure 4a-4c , block 106 includes forming a hard mask 212 over the planarized top surface of the semiconductor structure 200. The hard mask 212 is then patterned by a lithography process and etched to form a patterned hard mask 212 having one or more openings 213 as shown in FIGS. 5a-5d. The semiconductor structure 200 is then etched using the patterned hard mask 212 as an etching mask to form one or more channel isolation trenches 214 through one or more dummy gate structures 206, a portion of the ILD layer 210, a portion of the STI feature 203, and a portion of the active region 204. Figure 5c In some embodiments shown, the etching process may be selected to etch the active region 204 faster, so that the active region 204 is overetched to have a lower bottom surface than the STI feature 203 to form the recess 2140. This ensures that the active region 204 is cut off and divided into multiple segments on the STI feature 203. Each cut off and isolated segment can become a separate active region and can include multiple channel members.

[0051] Reference now Figure 6a-6d . A dielectric material is deposited on the semiconductor structure 200, including within the channel isolation trench 214, to form a channel isolation feature 219. The channel isolation feature 219 cuts off the active region 204 and divides it into two active regions. In some embodiments, the channel isolation feature 219 includes more than one layer deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable deposition techniques. In some embodiments, a semiconductor oxide material is first conformally deposited to form a first dielectric layer 216 as a liner, and a dielectric material is deposited over the first dielectric layer 216 to form a second dielectric layer 218 as a dielectric fill layer. In some cases, the semiconductor oxide material for the first dielectric layer 216 (or liner 216) includes silicon oxide, and the dielectric material for the second dielectric layer 218 includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or a combination thereof. Since the first dielectric layer 216 is better attached to the active region 204 than the second dielectric layer 218 and isolates the second dielectric layer 218 from the active region 204, the first dielectric layer 216 can act as a liner to prevent unintended surface charges or stress caused by direct contact between the second dielectric layer 218 and the active region 204. Figure 6a-6d Although not explicitly shown, the first dielectric layer 216 and the second dielectric layer 218 are planarized to remove the hard mask 212 , such that the ILD layer 210 , the dummy gate structure 206 , the first dielectric layer 216 , and the second dielectric layer 218 are coplanar.

[0052] refer to Figure 1 and Figure 7a-7d , the method 100 includes block 108. In block 108, the plurality of dummy gate structures 206 are removed. In some embodiments, the dummy gate structures 206 are removed by an etching process such as wet etching, dry etching, or a combination thereof to selectively remove the dummy gate structures 206. If the dummy gate structures 206 include more than one layer, such as a dummy gate dielectric layer and a dummy electrode, the etching process may include multiple etching steps to remove the dummy gate structures. Figure 7a-7d In some embodiments shown, the removal of the dummy gate structure 206 leaves a plurality of gate trenches 220. In some cases, the gate trenches 220 expose the first dielectric layer 216 on the sidewalls of the channel isolation features 219, such as Figure 7c In addition, the gate trench 220 exposes the active region 204, as shown in FIG. Figure 7dIn an embodiment, the active region 204 includes alternating stacks of silicon layers 2041 and germanium layers 2042, and the silicon layers 2041 and the germanium layers 2042 are exposed in the gate trench 220. In some embodiments, the operation of block 108 does not remove the first dielectric layer 216 of the channel isolation feature 219, and the first dielectric layer 216 is exposed in the gate trench 220. In some alternative embodiments, the operation of block 108 removes the first dielectric layer 216 at both ends of the channel isolation feature 219 along the Y direction (Y1), so that the second dielectric layer 218 is exposed in the gate trench 220.

[0053] refer to Figure 1 and Figure 8a-8d , the method 100 includes block 110, where the active region 204 is patterned. In some embodiments where the active region 204 includes alternating stacks of silicon layers 2041 and germanium layers 2042, the germanium layers 2042 exposed in the gate trenches 220 are selectively removed to form a plurality of channel members formed by the silicon layers 2041. Figure 8a Only two silicon layers 2041 are shown in the figure, the present disclosure is not limited thereto, and more silicon layers 2041 may be included. In some embodiments, the channel member is elongated, and the transistor formed according to method 100 may be referred to as a nanowire GAA transistor. In some alternative embodiments, the channel member is plate-shaped, and the transistor formed according to method 100 may be referred to as a nanoplate GAA transistor.

[0054] refer to Figure 1 and Figure 9a-9d , the method 100 includes block 112, where a plurality of metal gate structures 227 are formed. In block 112, each metal gate structure 227 includes a gate dielectric layer 224 and a gate electrode 226, and may be formed by depositing one or more dielectric materials and one or more metal layers, followed by planarization to remove excess dielectric materials and metal layers on the top surface of the ILD layer 210. The metal gate structure is formed on the substrate and spans across portions of the active region 204 and surrounds a channel feature in the active region 204. Figure 9dIn the example shown, a gate dielectric layer 224 surrounds each channel feature formed by the silicon layer 2041 , and a gate electrode 226 surrounds the gate dielectric layer 224 . The one or more dielectric materials include high dielectric constant dielectric materials, such as metal oxides, metal nitrides, such as lanthanum oxide, aluminum oxide, zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, strontium titanate (STO), barium titanate, barium zirconate (BTO), barium zirconate, hafnium zirconate, hafnium silicate, hafnium lanthanide, lanthanum silicate, aluminum silicate, hafnium tantalate, hafnium titanate, barium strontium titanate, titanate) or other suitable dielectric materials, such as silicon nitride (SiN) and silicon oxynitride (SiON). Figure 9d In the illustrated embodiment, the gate dielectric layer 224 is formed around the channel member formed by the silicon layer 2041. The gate dielectric layer 224 may also include an interfacial layer sandwiched between the high-k dielectric layer and the active region 204. The interfacial layer may include silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials. The interfacial layer may be deposited by a suitable method (e.g., ALD, CVD, ozone oxidation, etc.). The high-k dielectric layer may be deposited on the interfacial layer (if the interfacial layer is present) by a suitable technique, such as ALD, CVD, metal organic CVD (MOCVD), PVD, thermal oxidation, combinations thereof, and / or other suitable techniques.

[0055] The gate electrode 226 may be formed around the gate dielectric layer 224 and may include titanium, silver, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten oxide, copper, tungsten, or any other suitable conductive material. In some embodiments, different metals or metal nitrides are used for nFET and pFET elements to impart different work functions. The gate electrode 226 may include a variety of conductive materials. In some embodiments, the gate electrode 226 may also include a capping layer, a first barrier layer, a work function metal layer, a second barrier layer, and a fill metal layer. In a further embodiment, the capping layer includes titanium nitride, tantalum nitride, or other suitable materials, which are formed by a suitable deposition technique such as ALD. Each of the first barrier layer and the second barrier layer includes titanium nitride, tantalum nitride or other suitable materials formed by a suitable deposition technique such as ALD. In some examples, the barrier layer may not exist in the gate electrode or only one of them may exist. The work function metal layer includes a conductive layer of a metal or metal alloy having a suitable work function, thereby enhancing the device performance of the corresponding FET. The work function (WF) metal layers of pFET and nFET are different, which are respectively called n-type WF metal and p-type WF metal. The selection of WF metal depends on the FET to be formed on the active region. For example, the semiconductor structure 200 includes a first active region for nFET and a second active region for pFET. Therefore, n-type WF metal and p-type WF metal are respectively formed in the corresponding metal gate structure. In particular, n-type WF metal is a metal with a first work function, so that the threshold voltage of the related nFET can be reduced. The work function of n-type WF metal is close to the silicon conduction band energy (silicon conduction band energy, Ec) or a lower work function, so that electrons can escape more easily. For example, the work function of an n-type WF metal is about 4.2 eV or less. A p-type WF metal is a metal having a second work function, which reduces the critical voltage of a related pFET. The work function of a p-type WF metal is close to the silicon valence band energy (Ev) or higher work function, and has strong electron bonding energy to nuclei. For example, the WF of a p-type work function metal is about 5.2 eV or higher.In some embodiments, the n-type WF metal includes tantalum (Ta). In other embodiments, the n-type WF metal includes titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), or a combination thereof. In other embodiments, the n-type metal includes Ta, TiAl, TiAlN, tungsten nitride (WN), or a combination thereof. The n-type WF metal may include various metal-based films as a stack to optimize component performance and process compatibility. In some embodiments, the p-type WF metal includes titanium nitride (TiN) or tantalum nitride (TaN). In other embodiments, the p-metal includes TiN, TaN, tungsten nitride (WN), titanium aluminum (TiAl), or a combination thereof. The p-type WF metal may include various metal-based films as a stack to optimize component performance and process compatibility. The work function metal is deposited by an appropriate technique (e.g., PVD). In various embodiments, the fill metal layer includes aluminum, tungsten, or other suitable metals. The fill metal layer may be deposited by an appropriate technique such as PVD or plating.

[0056] refer to Figure 1 Box 114 and Figure 10a-Figure 10d , the method 100 includes a block 114, in which a gate cut-off opening 230 is formed. In block 114, the metal gate structure 227 is patterned by a process including lithography and etching. In the present embodiment, block 114 includes forming a patterned hard mask 228 on the semiconductor structure 200, and the patterned hard mask 228 has a gate cut-off opening 230 defining an area where the metal gate structure 227 is to be cut. The metal gate structure 227 is then etched using the hard mask 228 as an etching mask. The operation of block 114 forms the gate cut-off opening 230 in the metal gate structure 227. The hard mask 228 may include a suitable material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The hard mask 222 is formed by depositing the hard mask, forming a patterned photoresist layer by lithography, and etching the hard mask within the opening of the patterned photoresist layer. The etching process applied to the metal gate structure 227 may include multiple etching steps with etchants for the respective gate materials and may include wet etching, dry etching, or a combination thereof.

[0057] Block 114 of method 100 may include various embodiments. Fig.10c In some of the illustrated embodiments, the gate cut-off opening 230 cuts off the metal gate structure 227, including the gate dielectric layer 224 and the gate electrode 226, so that the gate dielectric layer 224 and the gate electrode 226 are exposed in the gate cut-off opening 230. In addition, the formation of the gate cut-off opening 230 removes the first dielectric layer 216 to expose the second dielectric layer 218 in the gate cut-off opening. In these embodiments, as shown in FIG. Fig.10cAs shown, the length of the channel isolation feature 219 along the Y direction (Y1) is defined between the two gate cut-off openings 230. The present disclosure is not limited to this. In some other embodiments, the gate cut-off opening 230 does not extend across the channel isolation feature 219, and both ends of the channel isolation feature 219 are adjacent to the gate dielectric layer 224 of the metal gate structure 227. That is, in these embodiments, the gate cut-off opening 230 terminates before it reaches the channel isolation feature 219. In other embodiments, the first dielectric layer 216 is not removed and the gate cut-off opening 230 is not rectangular in shape. In these embodiments, the gate cut-off opening 230 can extend into the channel isolation feature 219, or the gate isolation feature 219 can extend into the gate cut-off opening 230.

[0058] refer to Figure 1 Block 116 and Figure 11a-Figure 11d , the method 100 includes block 116, where a dielectric material is deposited in the gate cut-off opening 230 to form a gate cut-off feature 232. In the present embodiment, the formation of the gate cut-off feature 232 includes deposition, and may further include a CMP process after the deposition. The deposition process may deposit any suitable dielectric material in the gate cut-off opening 230 using a suitable deposition technique, such as CVD, flowable chemical vapor deposition (FCVD), high density plasma CVD (HDPCVD), other suitable techniques, or a combination thereof. After forming the gate cut-off feature 232, block 116 may include a CMP process such that a top surface of the gate cut-off feature 232 is coplanar with a top surface of the metal gate structure 27 and the ILD layer 210.

[0059] refer to Figure 1 The method 100 includes block 118, where further processes are performed. These further processes may include forming interconnect structures, gate contacts, and source / drain contacts. For example, another ILD layer may be formed above the semiconductor structure 200, and a gate contact or a source / drain contact may be formed.

[0060] Reference now Figure 12-Figure 17 As previously described with respect to blocks 108 and 114 of method 100, the present disclosure discloses various embodiments regarding the formation of gate trenches 220 and gate cut-off openings 230. These various embodiments may result in various semiconductor structures 200. Referring now to Fig.12In the embodiment where the gate cut-off opening 230 is formed to remove the gate dielectric layer 224 and expose the second dielectric layer 218 of the channel isolation feature 219, the gate cut-off feature 232 is directly in contact with the gate dielectric layer 224, the gate electrode 226, the first dielectric layer 216 and the second dielectric layer 218. That is, the channel isolation feature 219 in the semiconductor structure 200 includes the second dielectric body 218, which is formed by the first dielectric layer 216 of the active region 204, the ILD layer 210 (not shown for simplicity). Fig.12 ) and the STI feature 203. The gate cutoff feature 232 has a uniform width along the Y direction and is aligned along the X direction.

[0061] Reference now Fig.13 and Fig.14 In some embodiments, the gate cut-off opening 230 does not extend beyond the channel isolation feature 219. In these embodiments, depending on whether the first dielectric layer 216 is etched when the gate trench 220 is formed, the second dielectric layer 218 of the channel isolation feature 219 may contact the gate electrode 226, such as Fig.13 As shown, the gate dielectric layer 224 may be in contact with the second dielectric layer 218, as shown. Fig.14 as displayed.

[0062] Reference now Fig.15 In some embodiments, the formation of the gate cut-off opening 230 may leave the second dielectric layer 218 of the channel isolation feature 219 substantially unetched, while only the gate dielectric layer 224 is removed. In these embodiments, the second dielectric layer 218 may be in contact with the gate cut-off feature 232, and the gate electrode 226 may be in contact with the gate cut-off feature 232. In these embodiments, the channel isolation feature 219 extends into the gate cut-off feature 232, and the length of the gate cut-off feature 232 adjacent to the channel isolation feature 219 along the Y direction may be shorter than that of the gate cut-off feature 232 not adjacent to the channel isolation feature 219. Now referring to Fig.16 In some other embodiments, the second dielectric layer 218 can be removed to expose the first dielectric layer 216. The channel isolation feature 219 still extends to the gate cut-off feature 232. In these embodiments, the gate cut-off feature 232 is directly in contact with the first dielectric layer 216 and the gate electrode 226. Fig.15 and Fig.16 As shown, when the channel isolation feature 219 extends to the gate cut-off feature 232 , the gate cut-off feature 232 is not aligned along the X-direction.

[0063] Reference now Fig.17In some alternative embodiments, only a portion of the second dielectric layer 218 of the channel isolation feature 219 is removed, and the gate cut-off feature 232 extends into the second dielectric layer 218, so that the length of the gate cut-off feature 232 adjacent to the channel isolation feature 219 along the Y direction is longer and greater than the width of the gate.

[0064] Based on the above discussion, it can be seen that the present disclosure provides advantages over conventional methods and semiconductor structures. However, it should be understood that other embodiments may provide additional advantages, and it is not necessary to disclose all advantages herein, and no specific advantages are required for all embodiments. For example, the present disclosure provides a method in which a channel isolation feature is formed before forming a metal gate, and a gate cut-off feature is formed after forming a metal gate. The method of the present disclosure avoids forming a gate cut-off opening by stacking a gate electrode, a gate dielectric layer, and a channel member, and can expand the filling window of the metal gate structure to improve component performance and production yield. In some embodiments, the method of the present disclosure can cause the gate cut-off feature within the semiconductor structure to directly contact the second dielectric layer and the gate electrode of the channel isolation feature.

[0065] The present disclosure provides a semiconductor structure. The semiconductor structure includes a first active region, a gate structure, a gate cut-off feature and a channel isolation feature. The first active region is located on a substrate and extends along a first direction. The gate structure is located on the first active region and extends along a second direction, wherein the second direction is perpendicular to the first direction. The gate cut-off feature is adjacent to one end of the gate structure. The channel isolation feature extends along the second direction and is located between the first active region and a second active region. The gate structure includes a metal electrode directly contacting the gate cut-off feature. The channel isolation feature includes a liner on a sidewall extending along the second direction and a dielectric filling layer between the sidewalls. The gate cut-off feature is adjacent to one end of the channel isolation feature, and the dielectric filling layer is in direct contact with the gate cut-off feature.

[0066] In some embodiments, the gate cutoff feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or combinations thereof.

[0067] In some embodiments, the channel isolation feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or combinations thereof.

[0068] In some embodiments, the liner includes silicon oxide, and the dielectric fill layer includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or a combination thereof.

[0069] In some embodiments, the gate cutoff feature has a uniform width along the second direction.

[0070] In some embodiments, the first active region includes a plurality of first channel members, wherein the second active region includes a plurality of second channel members, wherein the channel isolation feature isolates the first channel members from the second channel members.

[0071] In some embodiments, the first channel member is surrounded by a gate structure.

[0072] The present disclosure provides a semiconductor structure. The semiconductor structure includes a first active region, a first gate structure, a gate cut-off feature and a channel isolation feature. The first active region is located on a substrate and extends along a first direction. The first gate structure is located on the first active region and extends along a second direction, wherein the second direction is perpendicular to the first direction. The gate cut-off feature is adjacent to one end of the first gate structure. The channel isolation feature extends along the second direction and is located between a second gate structure and a third gate structure. The channel isolation feature is arranged between the first active region and a second active region extending along the first direction. The second gate structure and the third gate structure include a gate dielectric layer. The channel isolation feature includes a liner located on the sidewall and a dielectric filling layer surrounded by the sidewall. The liner of the channel isolation feature is in direct contact with the gate dielectric layer of the second and third gate structures.

[0073] In some embodiments, the gate cutoff feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon carbon oxynitride, silicon carbon nitride, silicon oxycarbide, or a combination thereof, and the channel isolation feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon carbon oxynitride, silicon carbon nitride, silicon oxycarbide, or a combination thereof.

[0074] In some embodiments, the liner includes silicon oxide, and the dielectric fill layer includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or a combination thereof.

[0075] In some embodiments, the gate cutoff feature terminates before reaching the channel isolation feature.

[0076] In some embodiments, the first active region includes a plurality of first channel members, wherein the second active region includes a plurality of second channel members, wherein the channel isolation feature isolates the first channel members from the second channel members.

[0077] In some embodiments, the first channel member is surrounded by the first gate structure.

[0078] The present disclosure provides a method for forming a semiconductor structure. The method includes: providing a semiconductor structure, wherein the semiconductor structure includes a first active region and a plurality of dummy gate structures above the first active region; forming a channel isolation feature to divide the first active region into a first section and a second section; after forming the channel isolation feature, removing the dummy gate structure; patterning the first active region to form a plurality of channel components; forming a plurality of gate structures on the semiconductor structure to surround the channel components; etching the gate structure to form a gate cut-off opening; and depositing a dielectric material in the gate cut-off opening to form a gate cut-off feature.

[0079] In some embodiments, the first active region includes a plurality of silicon layers interleaved with a plurality of germanium layers, wherein patterning of the first active region includes selectively removing the germanium layers.

[0080] In some embodiments, forming the gate structure includes: depositing a gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

[0081] In some embodiments, forming a channel isolation feature includes: etching back a second active region parallel to the first active region to form a channel isolation trench; depositing a liner in the channel isolation trench; depositing a dielectric filling layer on the liner disposed in the channel isolation trench; and planarizing a top surface of the semiconductor structure. The recess of the second active region includes the first active region recessed below the second active region.

[0082] In some embodiments, the liner includes silicon oxide, and the dielectric fill layer includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide, or a combination thereof.

[0083] In some embodiments, the dielectric filling layer is composed of a dielectric material.

[0084] In some embodiments, forming the gate structure includes: depositing a gate dielectric layer; and depositing a gate electrode on the gate dielectric layer. Etching the gate structure includes etching the liner, the dielectric filling layer, the gate dielectric layer, and the gate electrode.

[0085] Although the present disclosure has been disclosed as above with preferred embodiments, it is not intended to limit the present disclosure. Anyone skilled in the art, including those with ordinary knowledge, may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. A semiconductor structure comprising: A first active region, located on a substrate and extending along a first direction; a second active region, located on the substrate and extending along the first direction, and separated from the first active region in the first direction; A gate structure, located on the first active region and extending along a second direction, wherein the second direction is perpendicular to the first direction; a gate cutoff feature adjacent to one end of the gate structure; and a channel isolation feature extending along the second direction and located between the first active region and the second active region, The gate structure includes a metal electrode directly contacting the gate cut-off feature. The channel isolation feature includes a liner on the sidewalls extending along the second direction and a dielectric filling layer between the sidewalls. The gate cut-off feature is adjacent to one end of the channel isolation feature, and the dielectric filling layer is in direct contact with the gate cut-off feature.

2. The semiconductor structure according to claim 1, wherein: The gate cutoff feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide or a combination thereof.

3. The semiconductor structure according to claim 1, wherein: The channel isolation features include silicon nitride, silicon oxynitride, silicon oxide, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide or a combination thereof.

4. The semiconductor structure according to claim 1, wherein: The liner includes silicon oxide, and the dielectric filling layer includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide or a combination thereof.

5. The semiconductor structure according to claim 1, wherein: The gate cutoff feature has a uniform width along the second direction.

6. The semiconductor structure of claim 1, wherein: The first active region includes a plurality of first channel components, wherein the second active region includes a plurality of second channel components, wherein the channel isolation feature isolates the first channel components from the second channel components.

7. The semiconductor structure of claim 6, wherein: The first channel member is surrounded by the gate structure.

8. A semiconductor structure comprising: A first active region, located on a substrate and extending along a first direction; a second active region, located on the substrate and extending along the first direction, and separated from the first active region in the first direction; A first gate structure, located on the first active region and extending along a second direction, wherein the second direction is perpendicular to the first direction; a gate cutoff feature adjacent to an end of the first gate structure; and a channel isolation feature extending along the second direction and located between a second gate structure and a third gate structure, The channel isolation feature is disposed between the first active region and the second active region extending along the first direction. Wherein, the second gate structure and the third gate structure include a gate dielectric layer, The channel isolation feature includes a liner on the sidewall and a dielectric filling layer surrounded by the sidewall. The pad of the channel isolation feature is in direct contact with the gate dielectric layer of the second gate structure and the third gate structure.

9. The semiconductor structure of claim 8, wherein: The gate cutoff feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon nitride, silicon oxycarbide or a combination thereof, and the channel isolation feature includes silicon nitride, silicon oxynitride, silicon oxide, silicon carbon nitride, silicon carbon nitride, silicon oxycarbide or a combination thereof.

10. The semiconductor structure of claim 8, wherein: The liner includes silicon oxide, and the dielectric filling layer includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide or a combination thereof.

11. The semiconductor structure of claim 8, wherein: The gate cutoff feature terminates before reaching the channel isolation feature.

12. The semiconductor structure of claim 8, wherein: The first active region includes a plurality of first channel components, wherein the second active region includes a plurality of second channel components, wherein the channel isolation feature isolates the first channel components from the second channel components.

13. The semiconductor structure of claim 12, wherein: The first channel member is surrounded by the first gate structure.

14. A method of forming a semiconductor structure, comprising: A semiconductor structure is provided, wherein the semiconductor structure comprises a first active region and a plurality of dummy gate structures above the first active region; forming a channel isolation feature to divide the first active area into a first section and a second section; After forming the channel isolation feature, removing the dummy gate structure; patterning the first active region to form a plurality of channel members; forming a plurality of gate structures on the semiconductor structure to surround the channel member; Etching the gate structure to form a gate cut-off opening; as well as A dielectric material is deposited in the gate cut-off opening to form a gate cut-off feature.

15. The method for forming a semiconductor structure according to claim 14, wherein: The first active region includes a plurality of silicon layers interlaced with a plurality of germanium layers, wherein patterning of the first active region includes selectively removing the germanium layers.

16. The method of claim 14, wherein: Forming the above-mentioned gate structure includes: depositing a gate dielectric layer; and A gate electrode is deposited on the gate dielectric layer.

17. The method for forming a semiconductor structure according to claim 14, wherein: The above channel isolation features include: Etching back a second active region parallel to the first active region to form a channel isolation trench; Depositing a liner in the channel isolation trench; Depositing a dielectric filling layer on the liner disposed in the channel isolation trench; and planarizing a top surface of the semiconductor structure, The recessing operation of the second active region includes recessing the first active region below the second active region.

18. The method of claim 17, wherein: The liner includes silicon oxide, and the dielectric filling layer includes silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon oxycarbide or a combination thereof.

19. The method of claim 17, wherein: The dielectric filling layer is composed of dielectric material.

20. The method of claim 17, wherein: Forming the above-mentioned gate structure includes: depositing a gate dielectric layer; and depositing a gate electrode on the gate dielectric layer, The etching of the gate structure includes etching the liner, the dielectric filling layer, the gate dielectric layer and the gate electrode.

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