Dynamic random access memory device and manufacturing method thereof

Abstract

The present invention provides a dynamic random access memory element comprising a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation zones, a plurality of second isolation zones, a plurality of transistors formed between the first isolation zones and the second isolation zones, a plurality of word lines, and a plurality of capacitors formed above the first isolation zones and the second isolation zones. The semiconductor substrate defines a longitudinal direction, a transverse direction, a plurality of columns along the longitudinal direction, and a plurality of rows along the transverse direction. The first isolation zones and the second isolation zones extend along the longitudinal direction. Each transistor corresponds to one column in the columns and one row in the rows. The transistors located on one side of each first isolation zone are staggered with the transistors located on the other side of the first isolation zone.

Description

Technical Field

[0001] The present invention relates to a dynamic random access memory (DRAM) element and a method for manufacturing the DRAM element, and more particularly to a DRAM element comprising a plurality of vertical current-type fan-shaped field effect transistors (FanFET) and a method for manufacturing the DRAM element. Background Art

[0002] See also Figure 1 and Figure 2 , the drawings schematically depict the vertical current-type fan-shaped field effect transistor 1 disclosed by U.S. Patent Publication No. 2019123060A1. Figure 1 An external view of a vertical current-mode fan-shaped field effect transistor 1 . Figure 2 for Figure 1 The cross-sectional view of the vertical current-mode fan-shaped field effect transistor 1 along the AA line.

[0003] like Figure 1 and Figure 2 As shown, the vertical current-mode fan-shaped field effect transistor 1 of the prior art includes a column 10 formed of a semiconductor material, a gate dielectric layer 12 and a gate conductor 14. The column 10 formed of a semiconductor material is formed along a semiconductor substrate (not shown in FIG. 1 ). Figure 1 and Figure 2 The semiconductor substrate is defined as follows: Figure 1 The normal direction N and the longitudinal direction L are shown.

[0004] The column 10 formed of semiconductor material has a base side surface 100 perpendicular to the lateral direction T of the semiconductor substrate, a tapered side surface 101 opposite to the base side surface, a top surface 102 parallel to the lateral direction T, a bottom surface 103 opposite to the top surface 102, a front side surface 104 adjacent to the base side surface 100 and the tapered side surface 101, and a rear side surface 105 opposite to the front side surface 104. In the column 10 formed of semiconductor material, a first elongated portion 106 is sandwiched between the base side surface 100, the front side surface 104, the top surface 102, and the rear side surface 105 to form a source region. A second elongated portion 107 is sandwiched between the base side surface 100, the front side surface 104, the rear side surface 105, and the bottom surface 103 to form a drain region. A plate-shaped portion 108 is located on the base side surface 100 and between the first elongated portion 106 and the second elongated portion 107 to form a channel region. The other portions of the column 10 formed of semiconductor material form a body region. The gate dielectric layer 12 is formed to cover the base side 100 of the pillar 10 formed of a semiconductor material. The gate conductor 14 is formed to cover the gate dielectric layer 12.

[0005] Obviously, in the vertical current type fan-shaped field effect transistor 1, the column 10 formed by the semiconductor material extends along the lateral direction T of the semiconductor substrate, and the first elongated portion 106 forming the source region and the second elongated portion 107 forming the drain region are arranged oppositely at the upper and lower parts of the column 10 formed by the semiconductor material.

[0006] In order to achieve a smaller size, the DRAM element of the prior art utilizes various vertical transistors. In this way, by using vertical transistors stacked below or above the cell capacitor, the DRAM element can have a 4F 2 , where F represents the process feature size (i.e., the minimum lithography feature size). However, 4F 2 The cell size of is already the limit of these prior art dynamic random access memory devices. Summary of the invention

[0007] Therefore, a technical problem to be solved by the present invention is to provide a dynamic random access memory device including a plurality of vertical current-type fan-shaped field effect transistors and a method for manufacturing the dynamic random access memory. In particular, the dynamic random access memory device according to the present invention can have a frequency less than 4F. 2 The unit size of .

[0008] A dynamic random access memory element according to a preferred embodiment of the present invention comprises a semiconductor substrate, a plurality of bit lines, a plurality of first isolation bands, a plurality of second isolation bands, a plurality of stacking bands, a plurality of transistors, a plurality of word lines, a second insulating layer, a plurality of transfer via contacts, a third insulating layer and a plurality of capacitors. The semiconductor substrate defines a longitudinal direction, a lateral direction, a normal direction, a plurality of columns along the longitudinal direction of the semiconductor substrate and a plurality of rows along the lateral direction of the semiconductor substrate. A plurality of bit lines are formed on the semiconductor substrate. Each bit line corresponds to one of the plurality of rows and extends along the corresponding row. A plurality of first isolation bands are formed on the plurality of bit lines and extend along the longitudinal direction of the semiconductor substrate. Each first isolation band has its own first longitudinal edge and its own second longitudinal edge. A plurality of second isolation bands are formed on the plurality of bit lines and extend along the longitudinal direction of the semiconductor substrate. Each second isolation band has its own third longitudinal edge and its own fourth longitudinal edge. A plurality of first isolation bands and a plurality of second isolation bands are arranged alternately. A plurality of stacked bands are composed of a first semiconductor layer formed on a plurality of bit lines, a first insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating layer. Each stacked band corresponds to a first isolation band among a plurality of first isolation bands and a second isolation band among a plurality of second isolation bands, and is located between the corresponding first isolation band and the corresponding second isolation band. Each stacked band has a plurality of recesses. A plurality of recesses are formed at the first insulating layer and face the third longitudinal edge or the fourth longitudinal edge of the corresponding second isolation band. The recesses located on one side of each first isolation band are alternately arranged with the recesses located on the other side of the first isolation band. Each recess corresponds to a column among a plurality of columns and a row among a plurality of rows.

[0009] Each transistor corresponds to one of the depressions and includes a column formed by a semiconductor material. Each column matches the corresponding depression and extends in the lateral direction of the semiconductor substrate. Each column has its own base side parallel to the normal direction of the semiconductor substrate, its own tapered side opposite to the base side, its own first top surface perpendicular to the normal direction of the semiconductor substrate, its own bottom surface opposite to the first top surface, its own front side surface adjacent to the base side surface and the tapered side surface, and its own rear side surface opposite to the front side surface. In each column formed by semiconductor material, its own first elongated portion is sandwiched between the first top surface, the base side surface, the front side surface and the rear side surface to form its own source region. Its own second elongated portion is sandwiched between the bottom surface, the base side surface, the front side surface and the rear side surface to form its own drain region. Its own plate-like portion is located on the base side surface and between the first elongated portion and the second elongated portion to form its own channel region. The other parts of the column form its own body region. Each transistor includes its own gate oxide / dielectric multilayer structure covering the base side of the corresponding pillar formed by semiconductor material, its own gate conductor covering the gate oxide / dielectric multilayer structure, its own first sub-bit line and its own second sub-bit line. The first sub-bit line is formed at the first semiconductor layer and connected between the drain region and the bit line corresponding to the transistor. The second sub-bit line is formed at the second semiconductor layer and connected to the source region. Each word line corresponds to one of the multiple columns and connects the gate conductors arranged along the corresponding column. The second insulating layer is formed on the second semiconductor layer, the multiple first isolation bands and the multiple second isolation bands. Each transfer via contact corresponds to one of the multiple second sub-bit lines and is formed to penetrate the second insulating layer and connect the corresponding second sub-bit line. The third insulating layer is formed on the second insulating layer and the multiple transfer via contacts. Each capacitor corresponds to one of the multiple transfer via contacts and is formed to penetrate the third insulating layer and connect the corresponding transfer via contact.

[0010] In a specific embodiment, the base side of the column formed of semiconductor material can be a flat surface, a convex surface, a concave surface, etc.

[0011] In a specific embodiment, in each transistor, the combined surface formed by the first top surface of the column formed by the semiconductor material, the second top surface of the gate oxide / dielectric multilayer structure and the third top surface of the gate conductor can be in the shape of a semi-ellipse, a semi-circle, a triangle, a thumb shape or a trapezoid.

[0012] Theoretically, the cell size of the dynamic random access memory device according to the present invention is equal to 3.5 times the square of the process feature size.

[0013] Furthermore, the dynamic random access memory device according to the present invention further comprises a fourth insulating layer and a plurality of connecting lines. The fourth insulating layer is formed to cover the semiconductor substrate and the plurality of bit lines. Each connecting line corresponds to a first sub-bit line among the plurality of first sub-bit lines and a bit line among the plurality of bit lines, and is formed to penetrate the fourth insulating layer and then connect between the corresponding first sub-bit line and the corresponding bit line.

[0014] According to a preferred embodiment of the present invention, a method for manufacturing a dynamic random access memory device is firstly formed on a semiconductor substrate. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns along the longitudinal direction, and a plurality of rows along the transverse direction. Each bit line corresponds to one of the plurality of rows and extends along the corresponding row. Then, a first semiconductor layer is formed on the plurality of bit lines according to the method of the present invention. Then, a first insulating layer is formed on the first semiconductor layer according to the method of the present invention. Then, a second semiconductor layer is formed on the first insulating layer according to the method of the present invention. Then, a plurality of first grooves parallel to the longitudinal direction of the semiconductor substrate are formed according to the method of the present invention. The plurality of first grooves penetrate the first semiconductor layer, the first insulating layer, and the second semiconductor layer. Each first groove has its own first longitudinal sidewall, its own second longitudinal sidewall, and a plurality of inwardly protruding protrusions. The protrusions on the first longitudinal sidewall of each first groove are arranged alternately with the protrusions on the second longitudinal sidewall. Then, a plurality of first isolation zones are formed according to the method of the present invention. Each first isolation band fills a first trench among the plurality of first trenches, so that the plurality of stacking bands and the plurality of first isolation bands are arranged alternately. The plurality of stacking bands are composed of a first semiconductor layer, a first insulating layer and a second semiconductor layer. Then, according to the method of the present invention, a plurality of second trenches parallel to the longitudinal direction of the semiconductor substrate are formed. Each second trench is formed on a portion of a stacking band among the stacking bands and penetrates the first semiconductor layer, the first insulating layer and the second semiconductor layer. Each second trench has its own third longitudinal sidewall and its own fourth longitudinal sidewall. Then, according to the method of the present invention, the first semiconductor layer and the second semiconductor layer on the third longitudinal sidewall and the fourth longitudinal sidewall of each second trench are partially doped to form a plurality of first conductive portions on the first semiconductor layer and a plurality of second conductive portions on the second semiconductor layer. Each first conductive portion and each second conductive portion correspond to one of the plurality of protrusions. Then, according to the method of the present invention, a plurality of residual portions of the first insulating layer are removed. Each residual portion corresponds to one of the plurality of protrusions, so that a plurality of recesses are formed on the third longitudinal sidewall and the fourth longitudinal sidewall of each second trench. The depressions on one side of each first isolation zone are arranged alternately with the depressions on the other side of the first isolation zone. Each depression corresponds to one of the multiple columns and one of the multiple rows. Then, a plurality of pillars formed of semiconductor material are formed according to the method of the present invention. The plurality of pillars formed of semiconductor material are arranged according to the multiple columns and the multiple rows. Each pillar formed of semiconductor material cooperates with one of the depressions and extends along the lateral direction of the semiconductor substrate.Each pillar has its own base side parallel to the normal direction of the semiconductor substrate, its own tapered side opposite to the base side, its own first top surface perpendicular to the normal direction of the semiconductor substrate, its own bottom surface opposite to the first top surface, its own front side surface adjacent to the base side surface and the tapered side surface, and its own rear side surface opposite to the front side surface. In each pillar formed of semiconductor material, its own first elongated portion is sandwiched between the first top surface, the base side surface, the front side surface and the rear side surface to form its own source region. Its own second elongated portion is sandwiched between the bottom surface, the base side surface, the front side surface and the rear side surface to form its own drain region. Its own plate-shaped portion is located on the base side surface and between the first elongated portion and the second elongated portion to form its own channel region. The other parts of the pillar form its own body region. Each first conductive portion serves as a first sub-bit line among a plurality of first sub-bit lines. Each first sub-bit line corresponds to one of the plurality of pillars and is connected between the drain region of the corresponding pillar and the bit line corresponding to the pillar. Each second conductive portion serves as a second sub-bit line among a plurality of second sub-bit lines. Each second sub-bit line corresponds to one of a plurality of pillars and is connected to the source region of the corresponding pillar. Then, a plurality of gate oxide / dielectric multilayer structures are formed according to the method of the present invention. Each gate oxide / dielectric multilayer structure covers the base side of one of a plurality of pillars formed by semiconductor material. Then, a plurality of conductor layers are formed according to the method of the present invention. Each conductor layer covers one of the third longitudinal sidewall and the fourth longitudinal sidewall of a second trench among a plurality of second trenches. Then, the plurality of conductor layers are partially etched according to the method of the present invention to form a plurality of gate conductors and a plurality of word lines. Each gate conductor covers a gate oxide / dielectric multilayer structure among a plurality of gate oxide / dielectric multilayer structures. Each word line corresponds to one of a plurality of columns and connects the gate conductors arranged along the corresponding column. Then, a plurality of second isolation bands are formed according to the method of the present invention. Each second isolation band fills a second trench among a plurality of second trenches. Next, according to the method of the present invention, a second insulating layer is formed on the second semiconductor layer, the plurality of first isolation zones, and the plurality of second isolation zones. Next, according to the method of the present invention, a plurality of transfer via contacts are formed. Each transfer via contact corresponds to a second sub-bit line among the plurality of second sub-bit lines, and is formed to penetrate the second insulating layer and thus connect the corresponding second sub-bit line. Next, according to the method of the present invention, a third insulating layer is formed on the second insulating layer and the plurality of transfer via contacts. Finally, according to the method of the present invention, a plurality of capacitors are formed. Each capacitor corresponds to a transfer via contact among the plurality of transfer via contacts, and is formed to penetrate the third insulating layer and thus connect the corresponding transfer via contact.

[0015] Different from the prior art, the dynamic random access memory device according to the present invention comprises a plurality of vertical current-type fan-shaped field effect transistors and can have a capacitance less than 4F. 2 The unit size of .

[0016] The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An external view of a vertical current-mode field effect transistor of the prior art;

[0018] Figure 2 for Figure 1 A cross-sectional view of a vertical current-mode field effect transistor along line AA;

[0019] Figure 3 An equivalent circuit diagram of a dynamic random access memory device according to a preferred embodiment of the present invention;

[0020] Figure 4 An external view of a partial structure inside a dynamic random access memory device according to a preferred embodiment of the present invention;

[0021] Figure 5 for Figure 4 A cross-sectional view of a transistor of a dynamic random access memory element according to the present invention along line BB;

[0022] Figure 6 A top view of a dynamic random access memory device according to the present invention with the top structure or cell removed;

[0023] Figure 7 A top view of a dynamic random access memory element according to the present invention;

[0024] Figure 8 for Figure 7 A cross-sectional view of a dynamic random access memory element according to the present invention along line CC;

[0025] Fig. 9 A top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention;

[0026] Fig.10 for Fig. 9 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line DD;

[0027] Fig.11 Another top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention;

[0028] Fig.12 for Fig.11 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line EE;

[0029] Fig.13 Another top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention;

[0030] Fig.14 for Fig.13 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line FF;

[0031] Fig.15 Another top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention;

[0032] Fig.16 for Fig.15 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line GG;

[0033] Fig.17 Another top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention;

[0034] Fig.18 for Fig.17 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line HH;

[0035] Fig.19 Another top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention;

[0036] Fig. 20 for Fig.19 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line II;

[0037] Fig.21 Another top view of a semi-finished product of a dynamic random access memory element manufactured by the method according to the present invention; Fig. 22 for Fig.21 A cross-sectional view of a semi-finished product of a dynamic random access memory element along line JJ;

[0038] Fig.23 A top view of a variation of a dynamic random access memory device according to the present invention with the top structure or cell removed; Fig.24 Another variation of a DRAM device according to the present invention has a top view with the top structure or cell removed; Fig.25 Another variation of a DRAM device according to the present invention is a top view with the top structure or cell removed.

[0039] Description of Figure Numbers:

[0040] 1: Vertical current type fan-shaped field effect transistor 10: Column

[0041] 100: Basic side 101: Conical side

[0042] 102: Top surface 103: Bottom surface

[0043] 104: front side 105: back side

[0044] 106: first elongated portion 107: second elongated portion

[0045] 108: Plate-shaped portion 12: Gate dielectric layer

[0046] 14: Gate conductor 2: Dynamic random access memory element

[0047] 20: memory cell string 202: memory cell block

[0048] 21: semiconductor substrate 212: row

[0049] 214: Row 22: Bit line

[0050] 23: first isolation zone 232: first longitudinal edge

[0051] 234: Second longitudinal edge 24: Second isolation zone

[0052] 242: third longitudinal edge 244: fourth longitudinal edge

[0053] 25: stacking belt 252: recessed

[0054] 26: Transistor 260: Semiconductor Materials

[0055] 262: Column 2620: Foundation side

[0056] 2621: Conical side surface 2622: First top surface

[0057] 2623: Bottom 2624: Front side

[0058] 2625: rear side 2626: first elongated portion

[0059] 2627: Second elongated portion 2628: Plate-like portion

[0060] 264: Gate oxide / dielectric layer 266: Gate conductor

[0061] 267: first sub-bit line 268: second sub-bit line

[0062] 27: word line 28: second insulating layer

[0063] 29: Transfer through-hole contact 30: Capacitor

[0064] 302: top electrode 304: high dielectric value dielectric layer

[0065] 306: bottom electrode 31: first semiconductor layer

[0066] 312: first conductive portion 32: first insulating layer

[0067] 33: Second semiconductor layer 332: Second conductive portion

[0068] 34: Fourth insulation layer 35: Connecting wire

[0069] 36: first groove 362: first longitudinal side wall

[0070] 364: second longitudinal side wall 366: protrusion

[0071] 37: second groove 372: third longitudinal side wall

[0072] 374: fourth longitudinal side wall 38: third insulating layer

[0073] 39: Conductive pad 40: Conductor layer

[0074] BL0 to BLm-1: bit lines Q0 to Qn-1: transistors

[0075] C0 to Cn-1: capacitors W0 to Wn-1: word lines

[0076] SR: Source region DR: Drain region

[0077] CR: Channel area L: Longitudinal direction

[0078] T: Transverse direction N: Normal direction DETAILED DESCRIPTION

[0079] See also Figure 3 , Figure 3 An equivalent circuit diagram of a dynamic random access memory device 2 according to a preferred embodiment of the present invention. More specifically, Figure 3 Equivalent circuit diagram of a dynamic random access memory element 2 having a vertical channel structure.

[0080] like Figure 3As shown, the memory cell array in the dynamic random access memory device 2 according to the present invention includes a plurality of memory cell strings 20 along the lateral direction T. Each memory cell string 20 is composed of a plurality of memory cell blocks 202 connected in parallel to a corresponding one of the plurality of bit lines (BL0 to BLm-1). Each memory cell string 20 includes a corresponding one of the plurality of bit lines (BL0 to BLm-1), a plurality of transistors (Q0 to Qn-1), and a plurality of capacitors (C0 to Cn-1). Each memory cell block 202 is composed of a transistor (Q0 to Qn-1) among the plurality of transistors (Q0 to Qn-1) and a capacitor (C0 to Cn-1) among the plurality of capacitors (C0 to Cn-1). Each transistor (Q0 to Qn-1) is connected to its corresponding bit line (BL0 to BLm-1) with its drain, and is connected to one end of its corresponding capacitor (C0 to Cn-1) with its source. Each capacitor (C0 to Cn-1) has its other end grounded. Each word line (W0 to Wn-1) of the plurality of word lines (W0 to Wn-1) corresponds to one of the plurality of columns and is connected to gates of the transistors on the same column.

[0081] See also Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 , the above-mentioned figures schematically depict a transistor 2 according to a preferred embodiment of the present invention. Figure 4 An external view of a partial structure inside a dynamic random access memory device 2 according to a preferred embodiment of the present invention. Figure 5 Figure 4 FIG. 4 is a cross-sectional view of the transistor 26 of the dynamic random access memory element 2 according to the present invention along line BB. Figure 6 A top view of a dynamic random access memory device 2 according to the present invention with the top structures or cells removed. Figure 7 Top view of a dynamic random access memory element 2 according to the invention. Figure 8 for Figure 7 FIG. 2 is a cross-sectional view of a dynamic random access memory device 2 according to the present invention along line CC. The dynamic random access memory device 2 according to the present invention mainly comprises a plurality of Figure 1 and Figure 2 Also, see Fig.14 , Fig.14 A cross-sectional view of a semi-finished product of a dynamic random access memory device 2 according to the present invention during the manufacturing process.

[0082] like Figures 4 to 8 and Fig.14As shown, the dynamic random access memory device 2 according to the preferred embodiment of the present invention comprises a semiconductor substrate 21, a plurality of bit lines 22, a plurality of first isolation bands 23, a plurality of second isolation bands 24, a plurality of stacking bands 25 (such as Fig.14 As shown in FIG. 1 ), a plurality of transistors 26, a plurality of word lines 27, a second insulating layer 28, a plurality of transfer via contacts 29, a third insulating layer 38, and a plurality of capacitors 30. Figure 6 and Figure 7 In FIG. 8 , the dashed lines represent the plurality of bit lines 22 formed under the plurality of capacitors 30 and the plurality of transistors 26 .

[0083] The semiconductor substrate 21 defines a longitudinal direction L, a lateral direction T, a normal direction N, a plurality of columns 212 along the longitudinal direction L of the semiconductor substrate 21 , and a plurality of rows 214 along the lateral direction T of the semiconductor substrate 21 .

[0084] A plurality of bit lines 22 are formed on the semiconductor substrate 21 . Each bit line 22 corresponds to one of the plurality of rows 214 and extends along the corresponding row 214 .

[0085] A plurality of first isolation zones 23 are formed on a plurality of bit lines 22 and extend along the longitudinal direction L of the semiconductor substrate 21. Each of the first isolation zones 23 has its own first longitudinal edge 232 and its own second longitudinal edge 234. A plurality of second isolation zones 24 are formed on a plurality of bit lines 22 and extend along the longitudinal direction L of the semiconductor substrate 21. Each of the second isolation zones 24 has its own third longitudinal edge 242 and its own fourth longitudinal edge 244. The plurality of first isolation zones 23 and the plurality of second isolation zones 24 are arranged alternately.

[0086] Likewise Fig.14 As shown, the plurality of stacked strips 25 are composed of a first semiconductor layer 31 formed on the plurality of bit lines 22, a first insulating layer 32 formed on the first semiconductor layer 31, and a second semiconductor layer 33 formed on the first insulating layer 32. It should be emphasized that the first insulating layer 32 exists only during the manufacturing process of the dynamic random access memory device 2 according to the present invention, and after the dynamic random access memory device 2 according to the present invention is manufactured, the first insulating layer 32 is completely removed.

[0087] Each stacking strip 25 corresponds to a first isolation strip 23 among the plurality of first isolation strips 23 and a second isolation strip 24 among the plurality of second isolation strips 24. Each stacking strip 25 is located between its corresponding first isolation strip 23 and its corresponding second isolation strip 24. Each stacking strip 25 has a plurality of recesses 252. The plurality of recesses 252 are formed at the first insulating layer 32 and face the third longitudinal edge 242 or the fourth longitudinal edge 244 of the corresponding second isolation strip 24. The recesses 252 located on one side of each first isolation strip 23 are alternately arranged with the recesses 252 located on the other side of the first isolation strip 23. Each recess 252 corresponds to one column 212 among the plurality of columns 212 and one row 214 among the plurality of rows 214.

[0088] Each transistor 26 corresponds to one of the recesses 252 and includes a column 262 formed of a semiconductor material 260. Each column 262 matches the corresponding recess 252 and extends along the lateral direction T of the semiconductor substrate 21. Each column 262 has its own base side surface 2620 parallel to the normal direction N of the semiconductor substrate 21, its own tapered side surface 2621 opposite to the base side surface 2620, its own first top surface 2622 perpendicular to the normal direction N of the semiconductor substrate 21, its own bottom surface 2623 opposite to the first top surface 2622, its own front side surface 2624 adjacent to the base side surface 2620 and the tapered side surface 2621, and its own rear side surface 2625 opposite to the front side surface 2624. Each column 262 formed of the semiconductor material 260 and having its own first elongated portion 2626 is sandwiched between the first top surface 2622, the base side surface 2620, the front side surface 2624 and the rear side surface 2625 to form its own source region SR. Each column 262 formed of the semiconductor material 260 and having its own second elongated portion 2627 is sandwiched between the bottom surface 2623, the base side surface 2620, the front side surface 2624 and the rear side surface 2625 to form its own drain region DR. Each column 262 formed of the semiconductor material 260 and having its own plate-shaped portion 2628 is located on the base side surface 2620 and between the first elongated portion 2626 and the second elongated portion 2627 to form its own channel region CR. The other portions of the columns 262 form their own body regions. In fact, the semiconductor material 260 may also cover the first longitudinal edge 232 and the second longitudinal edge 234 of the first isolation zone 23.

[0089] In some specific embodiments, the semiconductor material forming the pillar 20 may be, for example, a polysilicon material. The source region SR and the drain region DR may be doped with an n-type dopant (e.g., phosphorus or arsenic) or a p-type dopant (e.g., boron). The channel region CR may be doped with a dopant of a different conductivity type from the source region SR and the drain region DR. A portion of the body region away from the channel region CR, the source region SR, and the drain region DR may be doped with a specific dopant.

[0090] Each transistor 26 further comprises a gate oxide / dielectric multilayer structure 264 covering a base side 2620 of a corresponding pillar 262 formed of a semiconductor material 260, a gate conductor 266 covering the gate oxide / dielectric multilayer structure 264, a first sub-bit line 267, and a second sub-bit line 268. The first sub-bit line 267 is formed at the first semiconductor layer 31 and connected between the drain region DR and the bit line 22 corresponding to the transistor 26. The second sub-bit line 268 is formed at the second semiconductor layer 33 and connected to the source region SR. Each word line 27 corresponds to one of the columns 212 and connects the gate conductors 266 arranged along the corresponding column 212.

[0091] The second insulating layer 28 is formed on the second semiconductor layer 33, the first isolation strips 23 and the second isolation strips 24. Each transfer via contact 29 corresponds to one of the second sub-bit lines 268 and is formed to penetrate the second insulating layer 28 and connect to the corresponding second sub-bit line 268.

[0092] The third insulating layer 38 is formed on the second insulating layer 28 and the plurality of transfer via contacts 29. Each capacitor 30 corresponds to one of the plurality of transfer via contacts 29 and is formed to penetrate the third insulating layer 38 and connect to its corresponding transfer via contact 29. The structure of the plurality of capacitors 30 can be referred to Figure 8 The examples shown are, but not limited to, Figure 8 As shown, each capacitor 30 includes its own bottom electrode 306 , its own top electrode 302 , and its own high-k dielectric layer 304 formed between its own bottom electrode 306 and its own top electrode 302 .

[0093] In one embodiment, the base side 2620 of the pillar 262 formed of the semiconductor material 260 may be a flat surface, a convex surface, a concave surface, or the like.

[0094] In a specific embodiment, in each transistor 26, the combined surface formed by the first top surface 2622 of the pillar 262 formed by the semiconductor material 260, the second top surface of the gate oxide / dielectric multilayer structure 264 and the third top surface of the gate conductor 266 can be in the shape of a semi-ellipse, a semi-circle, a triangle, a thumb shape or a trapezoid.

[0095] Furthermore, the dynamic random access memory device 2 according to the present invention further includes a fourth insulating layer 34 and a plurality of connecting lines 35. The fourth insulating layer 34 is formed to cover the semiconductor substrate 21 and the plurality of bit lines 22. Each connecting line 35 corresponds to one first sub-bit line 267 of the plurality of first sub-bit lines 267 and one bit line 22 of the plurality of bit lines 22, and is formed to penetrate the fourth insulating layer 34 and then connect between the corresponding first sub-bit line 267 and the corresponding bit line 22. The plurality of connecting lines 35 have the function of stabilizing the current density and direction.

[0096] Likewise Figure 7 As shown, each memory cell 202 is surrounded by a thick parallelogram with a side length of 2F, where F represents the process feature size. Based on the thick black parallelogram, the cell size of the dynamic random access memory device 2 according to the present invention is calculated by the following formula:

[0097] Unit size = 8 / 4F × 7 / 4F = 3.5F 2

[0098] Therefore, theoretically, the cell size of the dynamic random access memory device 2 according to the present invention is equal to 3.5 times the square of the process feature size.

[0099] See also Figures 9 to 20 The accompanying drawings schematically show a method according to a preferred embodiment of the present invention as shown in FIG. Figures 4 to 8 A dynamic random access memory element 2 is shown.

[0100] See also Fig. 9 and Fig.10 , Fig. 9 Top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig.10 for Fig. 9 A cross-sectional view of a semi-finished product of a dynamic random access memory element 2 along line DD. Fig. 9 and Fig.10 As shown, according to the method of the present invention, first, a plurality of bit lines 22 are formed on a semiconductor substrate 21. The semiconductor substrate 21 defines a longitudinal direction L, a lateral direction T, a normal direction N, a plurality of columns 212 along the longitudinal direction L, and a plurality of rows 214 along the lateral direction T. Each bit line 22 corresponds to one of the plurality of rows 214 and extends along the corresponding row 214.

[0101] See also Fig.11 and Fig.12 , Fig.11 Another top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig.12 for Fig.11 A cross-sectional view of a semi-finished product of a dynamic random access memory element 2 along line EE. Fig.11 and Fig.12 As shown, then, a fourth insulating layer 34 is formed according to the method of the present invention to cover the semiconductor substrate 21 and the bit line 22. Fig.11 and Fig.12 As shown, then, a plurality of conductive pads 39 are formed according to the method of the present invention, each conductive pad 39 corresponds to one row 214 of the plurality of rows 214 and two columns 212 of the plurality of columns 212, and is formed at its corresponding row 214 and its corresponding two columns 212, and penetrates the fourth insulating layer 34 to contact the bit lines 22 arranged along its corresponding row 214.

[0102] See also Fig.13 And refer again Fig.14 , Fig.13 Another top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig.14 for Fig.13 A cross-sectional view of a semi-finished product of a dynamic random access memory element 2 along line FF. Fig.13 and Fig.14 As shown, then, according to the method of the present invention, a first semiconductor layer 31 is formed on the plurality of bit lines 22. Then, according to the method of the present invention, a first insulating layer 32 is formed on the first semiconductor layer 31. Fig.13 and Fig.14 As shown, then, according to the method of the present invention, a second semiconductor layer 33 is formed on the first insulating layer 32. Fig.13 and Fig.14 As shown, then, according to the method of the present invention, a plurality of first trenches 36 parallel to the longitudinal direction L of the semiconductor substrate 21 are formed. The plurality of first trenches 36 penetrate the first semiconductor layer 31, the first insulating layer 32, and the second semiconductor layer 33. Each first trench 36 has its own first longitudinal sidewall 362, its own second longitudinal sidewall 364, and a plurality of inwardly protruding protrusions 366. The protrusions 366 on the first longitudinal sidewall 362 of each first trench 36 are alternately arranged with the protrusions 366 on the second longitudinal sidewall 364.

[0103] See also Fig.15 and Fig.16 , Fig.15Top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig.16 for Fig.15 A cross-sectional view of a semi-finished product of a dynamic random access memory element 2 along line GG. Fig.15 and Fig.16 As shown, then, a plurality of first isolation bands 23 are formed according to the method of the present invention. Each first isolation band 23 fills a first groove 36 among the plurality of first grooves 36, so that a plurality of stacking bands 25 and a plurality of first isolation bands 23 are arranged alternately. The plurality of stacking bands 25 are composed of a first semiconductor layer 31, a first insulating layer 32 and a second semiconductor layer 33. Each first isolation band 23 has its own first longitudinal edge 232 and its own second longitudinal edge 234.

[0104] Likewise Fig.15 and Fig.16 As shown, then, according to the method of the present invention, a plurality of second trenches 37 parallel to the longitudinal direction L of the semiconductor substrate 21 are formed. Each second trench 37 is formed on a portion of one of the stacked strips 25 and penetrates the first semiconductor layer 31, the first insulating layer 32 and the second semiconductor layer 33. Each second trench 37 has its own third longitudinal sidewall 372 and its own fourth longitudinal sidewall 374.

[0105] Likewise Fig.15 and Fig.16 As shown, then, according to the method of the present invention, the first semiconductor layer 31 and the second semiconductor layer 33 on the third longitudinal sidewall 372 and the fourth longitudinal sidewall 374 of each second trench 37 are partially doped to form a plurality of first conductive portions 312 on the first semiconductor layer 31 and a plurality of second conductive portions 332 on the second semiconductor layer 33. Each first conductive portion 312 and each second conductive portion 332 corresponds to one protrusion 366 among the plurality of protrusions 366.

[0106] Likewise Fig.15 and Fig.16 As shown, then, according to the method of the present invention, a plurality of residual portions of the first insulating layer 32 are removed. Each residual portion corresponds to one of the plurality of protrusions 366, so that a plurality of recesses 252 are formed on the third longitudinal sidewall 372 and the fourth longitudinal sidewall 374 of each second groove 37. The recesses 252 located on one side of each first isolation zone 23 are alternately arranged with the recesses 252 located on the other side of the first isolation zone 23. Each recess 252 corresponds to one of the plurality of columns 212 and one of the plurality of rows 214.

[0107] See also Fig.17 and Fig.18 , Fig.17 Another top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig.18 for Fig.17 A cross-sectional view of a semi-finished product of a dynamic random access memory element 2 along line HH. Fig.17 and Fig.18 As shown, then, a plurality of pillars 262 formed of semiconductor material 260 are formed according to the method of the present invention. The plurality of pillars 262 formed of semiconductor material 260 are arranged according to a plurality of columns 212 and a plurality of rows 214. For manufacturing convenience, the semiconductor material 260 forming the pillars 262 may also cover the first conductive portion 312 and the second conductive portion 332.

[0108] Please refer to Figure 4 and Figure 5 Each pillar 262 formed of the semiconductor material 260 matches one of the recesses 252 and extends along the lateral direction T of the semiconductor substrate 21. Each pillar 262 has its own base side surface 2620 parallel to the normal direction N of the semiconductor substrate 21, its own tapered side surface 2621 opposite to the base side surface 2620, its own first top surface 2622 perpendicular to the normal direction N of the semiconductor substrate 21, its own bottom surface 2623 opposite to the first top surface 2622, its own front side surface 2624 adjacent to the base side surface 2620 and the tapered side surface 2621, and its own rear side surface 2625 opposite to the front side surface 2624. Each pillar 262 formed of the semiconductor material 260 has its own first elongated portion 2626 sandwiched between the first top surface 2622, the base side surface 2620, the front side surface 2624, and the rear side surface 2625 to form its own source region SR. Each pillar 262 formed of the semiconductor material 260 and having its own second elongated portion 2627 is sandwiched between the bottom surface 2623, the base side surface 2620, the front side surface 2624 and the rear side surface 2625 to form its own drain region DR. Each pillar 262 formed of the semiconductor material 260 and having its own plate-shaped portion 2628 is located on the base side surface 2620 and between the first elongated portion 2626 and the second elongated portion 2627 to form its own channel region CR. The other portion of each pillar 262 formed of the semiconductor material 260 forms its own body region. In fact, the semiconductor material 260 can also cover the third longitudinal sidewalls 372 and the fourth longitudinal sidewalls 374 of the plurality of second trenches 37.

[0109] Each first conductive portion 312 serves as a first sub-bit line 267 among the plurality of first sub-bit lines 267. Each first sub-bit line 267 corresponds to one of the plurality of pillars 262, and is connected between the drain region DR of the corresponding pillar 262 and the bit line 22 corresponding to the pillar 262. Each second conductive portion 332 serves as a second sub-bit line 268 among the plurality of second sub-bit lines 268. Each second sub-bit line 268 corresponds to one of the plurality of pillars 262, and is connected to the source region SR of the corresponding pillar 262.

[0110] Likewise Fig.17 and Fig.18 As shown, then, a plurality of gate oxide / dielectric multilayer structures 264 are formed according to the method of the present invention. Each gate oxide / dielectric multilayer structure 264 covers the base side 2620 of one of the plurality of pillars 262 formed by the semiconductor material 260. For manufacturing convenience, the plurality of gate oxide / dielectric multilayer structures 264 can also be covered on the semiconductor material 260 that has covered the first conductive portion 312 and the second conductive portion 332.

[0111] Likewise Fig.17 and Fig.18 As shown, then, a plurality of conductor layers 40 are formed according to the method of the present invention. Each conductor layer 40 covers one of the third longitudinal sidewall 372 and the fourth longitudinal sidewall 374 of one of the plurality of second trenches 37. In fact, each conductor layer 40 may also be covered on one of the gate oxide / dielectric multilayer structures 264 and the semiconductor material 260.

[0112] See also Fig.19 and Fig. 20 , Fig.19 Another top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig. 20 for Fig.19 A cross-sectional view of a semi-finished product of the dynamic random access memory element 2 along line II. Fig.19 and Fig. 20 As shown, the plurality of conductor layers 40 are then partially etched according to the method of the present invention to form a plurality of gate conductors 266 and a plurality of word lines 27. Each gate conductor 266 is covered with one of the plurality of gate oxide / dielectric multilayer structures 264. Each word line 27 corresponds to one of the plurality of columns 212 and connects the gate conductors 266 arranged along the corresponding column 212. In order to increase the volume of the plurality of gate conductors 266 and the plurality of word lines 27, before forming the plurality of conductor layers 40, another semiconductor material (not shown) is formed. Fig.18 and Fig. 20 ) may be formed to cover a plurality of gate oxide / dielectric layers 264 that have been covered on the semiconductor material 260. The semiconductor material 260 has been covered on the first conductive portion 312 and the second conductive portion 332.

[0113] It should be noted that a portion of the conductive pad 39 in the second trench 37 is removed, thereby converting the conductive pad 39 into a plurality of connecting lines 35. Each connecting line 35 corresponds to a first sub-bit line 267 of the plurality of first sub-bit lines 267 and is connected between its corresponding first sub-bit line 267 and its corresponding bit line 22.

[0114] See also Fig.21 and Fig. 22 , Fig.21 Another top view of a semi-finished product of a dynamic random access memory element 2 manufactured by the method according to the invention. Fig.21 for Fig. 22 A cross-sectional view of a semi-finished product of a dynamic random access memory element 2 along line JJ. Fig.21 and Fig. 22 As shown, then, a plurality of second isolation zones 24 are formed according to the method of the present invention. Each second isolation zone 24 fills a second trench 37 among the plurality of second trenches 37.

[0115] Please refer to Figure 7 and Figure 8 Then, according to the method of the present invention, a second insulating layer 28 is formed on the second semiconductor layer 33, the plurality of first isolation strips 23 and the plurality of second isolation strips 24. Figure 7 and Figure 8 As shown, then, a plurality of transfer via contacts 29 are formed according to the method of the present invention. Each transfer via contact 29 corresponds to a second sub-bit line 268 among the plurality of second sub-bit lines 268, and is formed to penetrate the second insulating layer 28 and thus connect the corresponding second sub-bit line 268. Figure 7 and Figure 8 As shown, finally, according to the method of the present invention, a third insulating layer 38 is formed on the second insulating layer 28 and the plurality of transfer via contacts 29. In addition, according to the method of the present invention, a plurality of capacitors 30 are formed. Each capacitor 30 corresponds to a transfer via contact 29 among the plurality of transfer via contacts 29, and is formed to penetrate the third insulating layer 38 and then connect the corresponding transfer via contact 29. The plurality of capacitors 30 are isolated by the third insulating layer 38, respectively.

[0116] See also Fig.23 , Fig.24 and Fig.25 , and please refer to Figure 6 . Fig.23A top view with the top structure or cells removed of a variation of a DRAM device 2 according to a preferred embodiment of the present invention. Fig.24 Another variation of the DRAM device 2 according to the preferred embodiment of the present invention is a top view with the top structure or cells removed. Fig.25 Another variation of the DRAM device 2 according to the preferred embodiment of the present invention is a top view with the top structure or cells removed.

[0117] like Figure 6 , Fig.23 , Fig.24 and Fig.25 As shown, the dashed arrows in the figures represent the direction in which the transistors 26 arranged on the first longitudinal edge 232 of each first isolation zone 23 are mapped to the transistors 26 arranged on the second longitudinal edge 234 of the first isolation zone 23 .

[0118] Figure 6 , Fig.23 , Fig.24 and Fig.25 The dashed arrows on the adjacent first isolation zones 23 shown in FIG. 1 have different combinations of directions. That is, the transistors 26 arranged on the first longitudinal edge 232 and the second longitudinal edge 234 of the adjacent first isolation zones 23 of the dynamic random access memory element 2 according to the preferred embodiment of the present invention are symmetrical as shown in FIG. Figure 6 , Fig.23 , Fig.24 and Fig.25 The combination shown in . Fig.23 , Fig.24 and Fig.25 The DRAM element 2 shown in FIG. 1 also has Figure 6 All structural features of the dynamic random access memory element 2 are shown. Fig.23 , Fig.24 and Fig.25 With Figure 6 Components and structures marked with the same numbers have the same or similar structures and functions, and will not be described in detail here.

[0119] Through the above detailed description of the present invention, it can be clearly understood that the dynamic random access memory element 2 according to the present invention is composed of a plurality of vertical current-type fan-shaped field effect transistors and can have a capacitance less than 4F. 2 The unit size of .

[0120] Through the detailed description of the preferred embodiments above, it is hoped that the features and spirit of the present invention can be more clearly described, and the preferred embodiments disclosed above are not intended to limit the aspects of the present invention. On the contrary, its purpose is to cover various changes and arrangements with equivalents within the aspects of the claims to be applied for by the present invention. Therefore, the aspects of the claims applied for by the present invention should be interpreted in the broadest sense based on the above description so as to cover all possible changes and arrangements with equivalents.

Claims

1. A dynamic random access memory device, characterized in that: Include: a semiconductor substrate defining a longitudinal direction, a lateral direction, a normal direction, a plurality of columns along the longitudinal direction, and a plurality of rows along the lateral direction; a plurality of bit lines formed on the semiconductor substrate, each bit line corresponding to one of the plurality of rows and extending along its corresponding row; A plurality of first isolation zones formed on the plurality of bit lines and extending along the longitudinal direction, each of the first isolation zones having a respective first longitudinal edge and a respective second longitudinal edge; A plurality of second isolation zones, formed on the plurality of bit lines and extending along the longitudinal direction, each second isolation zone having a respective third longitudinal edge and a respective fourth longitudinal edge, the plurality of first isolation zones and the plurality of second isolation zones being arranged alternately; A plurality of stacked bands, composed of a first semiconductor layer formed on the plurality of bit lines, a first insulating layer formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating layer, each stacked band corresponds to a first isolation band among the plurality of first isolation bands and a second isolation band among the plurality of second isolation bands, and is located between the first isolation band corresponding to it and the second isolation band corresponding to it, each stacked band has a plurality of recesses, wherein the plurality of recesses face the third longitudinal edge or the fourth longitudinal edge of the second isolation band corresponding to it, the recesses located on one side of each first isolation band are alternately arranged with the recesses located on the other side of the first isolation band, and each recess corresponds to one of the plurality of columns and one of the plurality of rows; A plurality of transistors, each transistor corresponds to a recess in the recesses and includes a separate column formed of a semiconductor material, each column cooperates with its corresponding recess and extends along the lateral direction, each column has a separate base side surface parallel to the normal direction, a separate tapered side surface opposite to the base side surface, a separate first top surface perpendicular to the normal direction, a separate bottom surface opposite to the first top surface, a separate front side surface adjacent to the base side surface and the tapered side surface, and a separate rear side surface opposite to the front side surface, in each column, a separate first elongated portion is sandwiched between the first top surface, the base side surface, the front side surface and the rear side surface to form a separate source region, and a separate second elongated portion is sandwiched between the bottom surface, the base side surface, A separate drain region is formed between the front side and the back side, a separate plate-shaped portion is located on the base side and between the first elongated portion and the second elongated portion to form a separate channel region, and a region of the column other than the source region, the drain region and the channel region forms a separate body region, and each transistor includes a separate dielectric layer covering the base side of the column formed of the semiconductor material, a separate gate conductor covering the dielectric layer, a separate first sub-bit line and a separate second sub-bit line, wherein the separate first sub-bit line is formed at the first semiconductor layer and connected between the drain region and the bit line corresponding to the transistor, and the separate second sub-bit line is formed at the second semiconductor layer and connected to the source region; a plurality of word lines, each word line corresponding to one of the plurality of columns and connecting the gate conductors arranged along its corresponding column; A second insulating layer is formed on the second semiconductor layer, the plurality of first isolation zones and the plurality of second isolation zones; a plurality of transfer via contacts, each transfer via contact corresponding to a second sub-bit line among the plurality of second sub-bit lines and formed to penetrate the second insulating layer and thereby connect to its corresponding second sub-bit line; a third insulating layer formed on the second insulating layer and the plurality of transfer via contacts; as well as A plurality of capacitors, each capacitor corresponds to one of the plurality of transfer via contacts and is formed to penetrate the third insulating layer and further connect to its corresponding transfer via contact. 2 . The DRAM device according to claim 1 , wherein each base side surface is a flat surface, a convex surface or a concave surface.

3. The DRAM device according to claim 2 , wherein in each transistor, a combined surface formed by the first top surface of the pillar formed by the semiconductor material, the second top surface of the dielectric layer, and the third top surface of the gate conductor presents one selected from the group consisting of a semi-ellipse, a semi-circle, a triangle, a thumb shape, and a trapezoid. 4 . The DRAM device according to claim 3 , wherein a cell size of the DRAM device is equal to 3.5 times a square of a process feature size.

5. The dynamic random access memory device according to claim 3, comprising: a fourth insulating layer formed to cover the semiconductor substrate and the plurality of bit lines; and A plurality of connection lines, each connection line corresponds to a first sub-bit line among the plurality of first sub-bit lines and a bit line among the plurality of bit lines and is formed to penetrate the fourth insulating layer and then connect between the corresponding first sub-bit line and the corresponding bit line.

6. A method for manufacturing a dynamic random access memory device, characterized in that: It includes the following steps: (a) forming a plurality of bit lines on a semiconductor substrate, wherein the semiconductor substrate defines a longitudinal direction, a lateral direction, a normal direction, a plurality of columns along the longitudinal direction, and a plurality of rows along the lateral direction, each bit line corresponding to one of the plurality of rows and extending along the corresponding row; (b) forming a first semiconductor layer on the plurality of bit lines; (c) forming a first insulating layer on the first semiconductor layer; (d) forming a second semiconductor layer on the first insulating layer; (e) forming a plurality of first grooves parallel to the longitudinal direction, the plurality of first grooves penetrating the first semiconductor layer, the first insulating layer and the second semiconductor layer, wherein each first groove has a respective first longitudinal sidewall, a respective second longitudinal sidewall and a plurality of protrusions protruding inwardly, and the protrusions on the first longitudinal sidewall and the protrusions on the second longitudinal sidewall are arranged alternately; (f) forming a plurality of first isolation bands, each of which fills a first trench among the plurality of first trenches, so that a plurality of stacking bands are arranged alternately with the plurality of first isolation bands, and the plurality of stacking bands are composed of the first semiconductor layer, the first insulating layer, and the second semiconductor layer; (g) forming a plurality of second grooves parallel to the longitudinal direction, wherein each second groove is formed on a portion of one of the stacked strips and penetrates the first semiconductor layer, the first insulating layer and the second semiconductor layer, and each second groove has a respective third longitudinal sidewall and a respective fourth longitudinal sidewall; (h) partially doping the first semiconductor layer and the second semiconductor layer on the third longitudinal sidewall and the fourth longitudinal sidewall of each second trench to form a plurality of first conductive portions on the first semiconductor layer and a plurality of second conductive portions on the second semiconductor layer, wherein each first conductive portion and each second conductive portion corresponds to one of the plurality of protrusions; (i) removing a plurality of residual portions of the first insulating layer, each of the residual portions corresponding to one of the plurality of protrusions, so that a plurality of recesses are formed on the third longitudinal sidewall and the fourth longitudinal sidewall of each second groove, wherein the recesses on one side of each first isolation zone are alternately arranged with the recesses on the other side of the first isolation zone, and each recess corresponds to one of the plurality of columns and one of the plurality of rows; (j) forming a plurality of pillars formed of a semiconductor material, wherein the plurality of pillars formed of the semiconductor material are arranged according to the plurality of columns and the plurality of rows, each pillar formed of the semiconductor material cooperates with one of the recesses and extends along the lateral direction, each pillar has a respective base side surface parallel to the normal direction, a respective tapered side surface opposite to the base side surface, a respective first top surface perpendicular to the normal direction, a respective bottom surface opposite to the first top surface, a respective front side surface adjacent to the base side surface and the tapered side surface, and a respective rear side surface opposite to the front side surface, in each pillar, a respective first elongated portion is sandwiched between the first top surface, the base side surface, the front side surface, and the rear side surface to form a respective source region, and a respective first Two elongated portions are sandwiched between the bottom surface, the base side surface, the front side surface and the back side surface to form a separate drain region, a separate plate-shaped portion is located on the base side surface and between the first elongated portion and the second elongated portion to form a separate channel region, and the region of the column other than the source region, the drain region and the channel region forms a separate body region, wherein each first conductive portion serves as a first sub-bit line among a plurality of first sub-bit lines, each first sub-bit line corresponds to one of the plurality of columns and is connected between the drain region of the corresponding column and the bit line corresponding to the column, and each second conductive portion serves as a second sub-bit line among a plurality of second sub-bit lines, each second sub-bit line corresponds to one of the plurality of columns and is connected to the source region of the corresponding column; (k) forming a plurality of dielectric layers, each dielectric layer covering the base side of one of the plurality of pillars formed of the semiconductor material; (1) forming a plurality of conductor layers, each of which covers one of the third longitudinal sidewall and the fourth longitudinal sidewall of a second trench among the plurality of second trenches; (m) partially etching the plurality of conductor layers to form a plurality of gate conductors and a plurality of word lines, wherein each gate conductor is covered by one of the plurality of dielectric layers, and each word line corresponds to one of the plurality of columns and connects the gate conductors arranged along the corresponding column; (n) forming a plurality of second isolation zones, each of the second isolation zones filling a second trench among the plurality of second trenches; (o) forming a second insulating layer on the second semiconductor layer, the plurality of first isolation strips, and the plurality of second isolation strips; (p) forming a plurality of transfer via contacts, each transfer via contact corresponding to one of the plurality of second sub-bit lines and formed to penetrate the second insulating layer and thereby connect the corresponding second sub-bit line; (q) forming a third insulating layer on the second insulating layer and the plurality of transfer via contacts; as well as (r) forming a plurality of capacitors, each capacitor corresponding to one of the plurality of via contacts and formed to penetrate the third insulating layer and thereby connect to its corresponding via contact. 7 . The method for manufacturing a dynamic random access memory device according to claim 6 , wherein each base side surface is a plane, a convex surface or a concave surface.

8. The method for manufacturing a dynamic random access memory device according to claim 7, wherein a combined surface composed of the first top surface of one of the pillars formed by the semiconductor material, a second top surface of the dielectric layer covering the base side of the pillar, and a third top surface of the gate conductor covering the dielectric layer presents one selected from the group consisting of a semi-ellipse, a semi-circle, a triangle, a thumb shape and a trapezoid.

9. The method for manufacturing a dynamic random access memory device according to claim 8, comprising the following steps between step (a) and step (b): forming a fourth insulating layer to cover the semiconductor substrate and the plurality of bit lines; and forming a plurality of conducting pads, each conducting pad corresponding to one of the plurality of rows and two of the plurality of columns and formed at its corresponding row and its corresponding two columns and formed to penetrate the fourth insulating layer and thus connect the bit lines along its corresponding row, wherein in step (g), a portion of the conducting pad in the second groove is removed to change the conducting pad into a plurality of connecting lines, Each connection line corresponds to a first sub-bit line among the plurality of first sub-bit lines and a bit line among the plurality of bit lines and is connected between the corresponding first sub-bit line and the corresponding bit line.

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