Display devices

Abstract

A display device is provided, comprising a display panel and an input sensing layer. The input sensing layer includes an input sensor and a plurality of input sensing lines. The display panel includes a substrate layer, a circuit layer including a plurality of clock signal lines, a first electrode disposed between the clock signal lines and the input sensing lines and having a plurality of second holes defined therein, and a second electrode overlapping at least one of the clock signal lines in a planar view, thereby achieving uniform input sensitivity.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0049957, filed on April 29, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more specifically to display devices that provide uniform input sensitivity. Background Technology

[0004] Various display devices are being developed for multimedia devices such as televisions, mobile phones, tablets, navigation systems, and game consoles. These display devices include keyboards, mice, and other input devices. Furthermore, in recent years, display devices have incorporated input sensing layers as input devices. Summary of the Invention

[0005] An embodiment of the present invention provides a display device comprising a display panel for displaying images and an input sensing layer disposed on the display panel. The input sensing layer may be disposed on the display panel and may include an input sensor and multiple input sensing lines electrically connected to the input sensor. The display panel may include a substrate layer, a circuit layer, a light-emitting element layer, a first electrode, and a second electrode. The substrate layer may include a display area and a non-display area. The circuit layer may include a pixel circuit layer disposed in the display area of ​​the substrate layer and a driving circuit layer disposed in the non-display area of ​​the substrate layer. The driving circuit layer includes a power electrode and multiple clock signal lines and provides driving signals for driving the pixel circuit layer. The light-emitting element layer may include a pixel electrode disposed on and electrically connected to the pixel circuit layer, a light-emitting layer disposed on the pixel electrode, and a common electrode disposed on the light-emitting layer and extending from the display area toward the non-display area. The first electrode may be disposed between the multiple clock signal lines and the multiple input sensing lines, and may have multiple second holes defined therein. The second electrode may overlap with at least one of the multiple clock signal lines in a plan view.

[0006] In one embodiment, at least one of the multiple clock signal lines may include the clock signal line that is furthest from the display area, and the second electrode may completely overlap with the clock signal line that is furthest from the display area in a plan view.

[0007] In one embodiment, multiple second electrodes may be provided. In another embodiment, the multiple second electrodes may correspond one-to-one with the multiple second holes.

[0008] In one embodiment, the first electrode may be electrically connected to the power supply electrode and the common electrode.

[0009] In one embodiment, the display panel may further include a pixel defining film disposed on the pixel electrodes and exposing at least a portion of the pixel electrodes. A second electrode may be disposed on the pixel defining film such that it overlaps with the pixel defining film in a planar view.

[0010] In one embodiment, the second electrode may be spaced apart from the first electrode, and the pixel defining film is inserted between the second electrode and the first electrode.

[0011] In one embodiment, the first electrode may be disposed on the same layer as the pixel electrode. In another embodiment, the second electrode may be conductive. In yet another embodiment, the second electrode may include a transparent conductive layer. In yet another embodiment, the display panel may further include a thin-film encapsulation layer disposed on the light-emitting element layer. In yet another embodiment, the input sensing layer may be directly disposed on the thin-film encapsulation layer.

[0012] In one implementation, a first hole may be defined in the display device, passing through the display panel and the input sensing layer. The first hole may be surrounded by the display area in a plan view.

[0013] In one implementation, the plurality of second holes may be filled with insulating material.

[0014] In embodiments of the present invention, the display device may include a substrate layer, a circuit layer, a light-emitting element layer, a pixel defining film, and a second electrode. The substrate layer may have a display area and a non-display area defined thereon. The circuit layer may include a driving circuit layer and a pixel circuit layer, the driving circuit layer being disposed on the substrate layer and including a power supply electrode and multiple clock signal lines. The light-emitting element layer may be disposed on the circuit layer and may include a pixel electrode, a light-emitting layer, and a common electrode sequentially laminated thereon. The pixel defining film may be disposed on the pixel electrode and expose at least a portion of the pixel electrode. The second electrode may be disposed on the pixel defining film and may overlap with at least one of the multiple clock signal lines in a planar view.

[0015] In one embodiment, the display device may further include a first electrode electrically connected to a power supply electrode and a common electrode and overlapping at least some of a plurality of clock signal lines. The first electrode may have a plurality of second holes defined therein, and the second electrode overlaps with the plurality of second holes in a plan view.

[0016] In one embodiment, the first electrode may have a plurality of second holes defined therein, and the second electrode may overlap with the plurality of second holes on a plane. In another embodiment, a plurality of second electrodes may be provided. Each second electrode may correspond one-to-one with a plurality of second holes. In yet another embodiment, the display device may further include a thin-film encapsulation layer disposed on a common electrode.

[0017] In some embodiments, the display device may further include an input sensing layer. The input sensing layer may be directly disposed on the thin-film encapsulation layer and may include an input sensor and multiple input sensing lines electrically connected to the input sensor.

[0018] In one implementation, the second electrode may be disposed between the input sensing line and multiple clock signal lines.

[0019] In one embodiment, the second electrode may include a transparent conductive layer.

[0020] In one embodiment, the display device may further include at least one first hole that passes through the display area of ​​the substrate layer.

[0021] In one implementation, the second electrode may completely overlap with the clock signal line that is positioned furthest from the display area. Attached Figure Description

[0022] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0023] Figure 1 This is a perspective view of a display device according to an embodiment of the present invention;

[0024] Figure 2 This is a perspective view of a display device according to an embodiment of the present invention;

[0025] Figure 3 This is a perspective view of a display device according to an embodiment of the present invention;

[0026] Figure 4 This is a cross-sectional view of a display module according to an embodiment of the present invention;

[0027] Figure 5 It is along the implementation of the concept of the present invention. Figure 1 A cross-sectional view of the display module taken by line I-I';

[0028] Figure 6 This is a plan view of a display panel according to an embodiment of the present invention.

[0029] Figure 7 This is a block diagram of a gate drive circuit and a drive stage according to an embodiment of the present invention.

[0030] Figure 8 This is a plan view of the input sensing layer according to an embodiment of the present invention;

[0031] Figure 9 It is shown Figure 4 An enlarged cross-sectional view of region AA;

[0032] Figure 10A This is a schematic plan view of the first and second electrodes according to an embodiment of the present invention.

[0033] Figure 10B It is along Figure 10A A sectional view taken from line II-II';

[0034] Figure 11A This is a schematic plan view illustrating the first and second electrodes according to an embodiment of the present invention; and

[0035] Figure 11B It is along Figure 11A The sectional view taken from line III-III'. Detailed Implementation

[0036] In this disclosure, when an element (or region, layer, portion, etc.) is referred to as being on, "connected to" or "attached to" another element, it means that the element may be directly disposed on / connected to / attached to the other element, or a third element may be disposed therebetween.

[0037] The same reference numerals refer to the same elements. Furthermore, in order to effectively depict the technical content, the thickness, scale, and dimensions of the elements are exaggerated in the accompanying drawings.

[0038] The term "and / or" includes all combinations of one or more of the relevant configurations that can be defined.

[0039] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element without departing from the scope of exemplary embodiments of the inventive concept, and similarly, a second element may be referred to as a first element. Singular terms may include plural terms unless the context clearly indicates otherwise.

[0040] Furthermore, terms such as "below," "lower part," "above," and "upper part" are used to describe the relationships of the configurations shown in the accompanying drawings. These terms are used as relative concepts and are described with reference to the directions shown in the accompanying drawings.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It should also be understood that terms defined in common dictionaries may be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and they are interpreted herein as explicitly defined unless they are interpreted in an idealized or overly formal sense.

[0042] It should be understood that the terms “comprising” or “having” are intended to describe the presence of a feature, integral, step, operation, element, component or combination thereof set forth in this disclosure, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components or combinations thereof.

[0043] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0044] Figure 1 This is a perspective view of a display device DD according to an embodiment of the present invention. The display device DD according to the present invention can be used in large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as mobile phones, tablet computers, car navigation systems, game consoles, and smartwatches.

[0045] The display device DD may have a display area DD-DA and a non-display area DD-NDA defined thereon.

[0046] The display device DD can be folded along a folding axis FX, which extends along a second direction DR2 that intersects the first direction DR1. In other words, the display device DD can be referred to as a foldable display device.

[0047] The display device DD can display images through the display area DD-DA. Figure 1 The image shown illustrates a monitoring window and application icons. In the following text, the display area DD-DA located to the left of the folding axis FX may be referred to as the first display area DD-DA1, and the display area DD-DA located to the right of the folding axis FX may be referred to as the second display area DD-DA2. The first display area DD-DA1 and the second display area DD-DA2 may be adjacent to each other in the first direction DR1.

[0048] exist Figure 1 In this example, the folding axis FX is shown as passing through the center of the display device DD and extending along the second direction DR2. Furthermore, in Figure 1In this example, the areas of the first display area DD-DA1 and the second display area DD-DA2 are shown to be the same. However, the inventive concept is not limited thereto. The position of the folding axis FX can be defined as being closer to one side edge, and in this case, the areas of the first display area DD-DA1 and the second display area DD-DA2 can be different from each other.

[0049] The unfolded display device DD (i.e., the display device DD unfolded to have a flat surface) can be referred to as the first state, i.e., the unfolded state. In the first state, each of the first display area DD-DA1 and the second display area DD-DA2 of the display device DD can be parallel to the plane defined by the first direction DR1 and the second direction DR2.

[0050] In an embodiment of the present invention, a first aperture MH can be defined within the display area DD-DA. The first aperture MH can be surrounded by the display area DD-DA. An electronic module (not shown) can overlap with the first aperture MH in a plan view. The electronic module can receive external input through the first aperture MH, or provide output through the first aperture MH.

[0051] In this embodiment, when the display device DD is in the first state, the front surface (or upper surface) and rear surface (or lower surface) of each component are defined based on the orientation of the displayed image. The front and rear surfaces are opposite to each other in a third direction DR3, and the normal direction of each of the front and rear surfaces may be parallel to the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and can be changed to different directions. In the following, the first direction to the third direction refers to the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, and is given the same reference numerals as the corresponding reference numerals.

[0052] Figure 2 This is a perspective view of a display device according to an embodiment of the present invention.

[0053] Reference Figure 1 and Figure 2 The display device DD can be folded along the folding axis FX. Figure 2 The display device DD is shown when folded. (Example) Figure 2 As shown, the state in which the display device DD is fully folded can be referred to as the second state (inward folding state).

[0054] The inward folding state can be a state in which the first display area DD-DA1 and the second display area DD-DA2 are folded so that they face each other. Therefore, in the fully inward folding state, the first display area DD-DA1 and the second display area DD-DA2 cannot be seen from the outside.

[0055] When the display device DD changes from the first state (expanded state) to the second state (inward folded state), a portion of the display device DD including the second display area DD-DA2 can rotate relative to another portion of the display device DD including the first display area DD-DA1 along the first rotation direction RDa.

[0056] Figure 3 This is a perspective view of a display device according to an embodiment of the present invention.

[0057] Reference Figure 1 and Figure 3 The display device DD can be folded along the folding axis FX to expose the display area DD-DA to the outside (outward folded state). Figure 3 An outward-folding display device DD is shown. (Example) Figure 3 As shown, the state in which the display device DD is fully folded outward can be referred to as the third state.

[0058] The outward folding state can be such that the first display area DD-DA1 and the second display area DD-DA2 are folded so that they do not face each other. Therefore, in the fully outward folding state, the first display area DD-DA1 and the second display area DD-DA2 can be seen from the outside.

[0059] When the display device DD transitions from the first state to the third state (outward folding state), a portion of the display device DD, including the second display area DD-DA2, can rotate relative to another portion of the display device DD, including the first display area DD-DA1, along the second rotation direction RDb. The second rotation direction RDb can be a reference... Figure 2 The first rotational direction described is opposite to the direction of RDa.

[0060] Figure 4 This is a cross-sectional view of a display module DM according to an embodiment of the present invention. Figure 5 It is along the implementation of the concept of the present invention. Figure 1 The sectional view of the display module DM is taken by line I-I'. Figure 6 This is a plan view of a display panel DP according to an embodiment of the present invention. Figure 7 This is a block diagram of the gate drive circuit GDC and the drive stage GDSi according to an embodiment of the present invention.

[0061] Reference Figure 4 and Figure 5 The display panel DP includes a substrate layer SUB, a circuit layer DP-CL disposed on the substrate layer SUB, a light-emitting element layer DP-ED, and a thin-film encapsulation layer TFE.

[0062] In a plan view, the display panel DP includes the display area DA and the non-display area NDA. The display area DA and the non-display area NDA of the display panel DP correspond to the display device DD, respectively. Figure 1 The display area of ​​DD-DA ( Figure 1 ) and non-display area DD-NDA ( Figure 1 The display area DA and non-display area NDA of the display panel DP may not necessarily be the same as the display device DD. Figure 1 The display area of ​​DD-DA ( Figure 1 ) and non-display area DD-NDA ( Figure 1 The same applies, but may vary depending on the structure and design of the display panel (DP).

[0063] In this specification, "plan view" may refer to the view as seen from a third party to DR3.

[0064] The substrate SUB may include at least one plastic film. The substrate SUB is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate. The plastic substrate may include at least one of acrylic resin, methacrylate resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and dinaphthalene-based phenyl resin.

[0065] The DP-CL circuit layer can be disposed on the substrate SUB. The DP-CL circuit layer may include multiple insulating layers, multiple conductive layers, and semiconductor layers. The multiple conductive layers of the DP-CL circuit layer can form signal lines or pixel control circuits. The DP-CL circuit layer may include a pixel circuit layer DP-PCL disposed in the display area DA and a drive circuit layer DP-DCL disposed in the non-display area NDA.

[0066] The light-emitting element layer DP-ED can be disposed on the circuit layer DP-CL. The light-emitting element layer DP-ED includes multiple light-emitting elements ED (…). Figure 9 ).

[0067] A thin-film encapsulation layer (TFE) can be disposed on the circuit layer DP-CL and the light-emitting element layer DP-ED. The TFE can encapsulate both the circuit layer DP-CL and the light-emitting element layer DP-ED. The TFE can comprise multiple inorganic films and at least one organic film disposed between the multiple inorganic films. The inorganic films protect the light-emitting element layer DP-ED from moisture / oxygen, and the organic film protects the light-emitting element layer DP-ED from foreign substances such as dust particles.

[0068] An input sensing layer (TSL) is disposed on a thin-film encapsulation layer (TFE). The input sensing layer (TSL) may be directly disposed on the thin-film encapsulation layer (TFE). However, embodiments of the present invention are not limited thereto. A protective layer may be disposed on the thin-film encapsulation layer (TFE), and the input sensing layer (TSL) may be directly disposed on the protective layer. The protective layer may be an inorganic layer or an organic layer. The inorganic layer may include at least one of silicon nitride, silicon oxynitride, and silicon oxide. The organic layer may include a polymer. However, this is merely exemplary, and embodiments of the present invention are not limited thereto. Although the protective layer is described as a separate component, the protective layer may be a component included within the thin-film encapsulation layer (TFE).

[0069] The input sensing layer TSL comprises an input sensor TSP and an input sensing line TL. The input sensor TSP and input sensing line TL can have a single-layer or multi-layer structure. The input sensor TSP and input sensing line TL may comprise transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, or graphene. The input sensor TSP and input sensing line TL may comprise metal layers, for example, formed of molybdenum, silver, titanium, copper, aluminum, or alloys thereof. The input sensor TSP and input sensing line TL may have the same or different layer structures. Details of the input sensing layer TSL will be described later.

[0070] Figure 5 This is a cross-sectional view of the region corresponding to the area where the first hole MH is located. (Reference) Figure 5 The first aperture MH can pass through the display panel DP and the input sensing layer TSL. The first aperture MH can be defined as the area where all components of the display panel DP and the input sensing layer TSL are removed.

[0071] In this embodiment, the first hole MH is shown as a cylindrical shape with a height in the third direction DR3, but it is not limited to this. The first hole MH can be set into various shapes such as a polygonal cylinder, an elliptical cylinder, a cone, etc., but is not limited to any one embodiment.

[0072] An electronic module (not shown) may be disposed below the display panel DP, or it may be disposed within the first aperture MH. The electronic module may be a module with dimensions that can be accommodated within the first aperture MH, or it may be a module with dimensions at least similar to those of the first aperture MH. For example, the electronic module (not shown) may be a camera.

[0073] Reference Figure 6 The display panel DP includes multiple pixels PX. The area where the multiple pixels PX are set is defined as the display area DA. In this embodiment, the non-display area NDA can be set along the edge of the display area DA.

[0074] The display panel DP includes gate lines GL, data lines DL, light-emitting lines EL, control signal lines SL-D, initialization voltage lines SL-Vint, voltage lines SL-VDD, power electrodes E-VSS, and pads PD.

[0075] Gate lines GL are connected to corresponding pixels PX in a plurality of pixels PX, and data lines DL are also connected to corresponding pixels PX in a plurality of pixels PX. Each of the light-emitting lines EL can be arranged side-by-side to extend parallel to the corresponding gate line GL in the gate lines GL. Control signal lines SL-D can provide control signals to the gate drive circuit GDC. Initialization voltage line SL-Vint can provide an initialization voltage to the plurality of pixels PX. Voltage line SL-VDD is connected to the plurality of pixels PX and can provide a first voltage to the plurality of pixels PX. Voltage line SL-VDD may include multiple lines extending in a first direction DR1 and multiple lines extending in a second direction DR2. Power supply electrodes E-VSS are disposed in the non-display area NDA and can be configured to surround the three side surfaces of the display area DA. Power supply electrodes E-VSS can provide a common voltage (e.g., a second voltage) to the plurality of pixels PX. The common voltage can be a voltage having a level lower than the first voltage.

[0076] On one side of the non-display area NDA, the gate drive circuit GDC to which the gate line GL and the light-emitting line EL are connected can be set.

[0077] Pad PD can be connected to the ends of data line DL, control signal line SL-D, initialization voltage line SL-Vint, and voltage line SL-VDD.

[0078] refer to Figure 4 and Figure 7 The DP-CL circuit layer may include multiple insulating layers, multiple conductive layers, and semiconductor layers. The multiple conductive layers of the DP-CL circuit layer can constitute control circuitry for signal lines or pixels. The DP-CL circuit layer may include a pixel circuit layer DP-PCL disposed in the display area DA and a driving circuit layer DP-DCL disposed in the non-display area NDA. The pixel circuit layer DP-PCL may include reference... Figure 6 The gate line GL, data line DL, light emission line EL, initialization voltage line SL-Vint, voltage line SL-VDD, and pixel PX are described.

[0079] The driving circuit layer DP-DCL may include power supply electrodes E-VSS, gate drive circuit GDC, and control signal line SL-D. The control signal line SL-D may include... Figure 7The diagram shows a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, a fourth clock signal line CL4, a first voltage line VL1, a second voltage line VH1, a third voltage line VL2, a fourth voltage line VH2, a first start signal line EF1, and a second start signal line EF2. In this assembly, the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, and the fourth clock signal line CL4 can be collectively referred to as clock signal lines.

[0080] exist Figure 7 The diagram exemplarily illustrates a drive stage GDSi, which is connected to the i-th gate line GLi and the i-th light-emitting line ELi, among multiple drive stages of a gate drive circuit GDC.

[0081] The driver stage GDSi may include an emission control stage EC-Ci and a gate driver stage GC-Ci. Emission control signals CLK1, CLK2, VGL, VGH, and EMFLM can be provided to the emission control stage EC-Ci via a first clock signal line CL1, a second clock signal line CL2, a first voltage line VL1, a second voltage line VH1, and a first start signal line EF1. Gate control signals CLK3, CLK4, VGL1, VGH1, and FLM can be provided to the gate driver stage GC-Ci via a third clock signal line CL3, a fourth clock signal line CL4, a third voltage line VL2, a fourth voltage line VH2, and a second start signal line EF2.

[0082] In this embodiment, an exemplary driving stage GDSi is shown, comprising a light-emitting control stage EC-Ci and a gate driving stage GC-Ci. However, embodiments of the present invention are not limited thereto. For example, the light-emitting control stage EC-Ci and the gate driving stage GC-Ci may be included in different driving stages.

[0083] The light control level EC-Ci may include a first clock terminal CK1, a second clock terminal CK2, a first voltage input terminal VPL1, a second voltage input terminal VPH1, an input terminal IN, a carry terminal CR, and an output terminal OUT1.

[0084] The first clock terminal CK1 receives the first clock signal CLK1, and the second clock terminal CK2 receives the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 can be signals with different phases. The second clock signal CLK2 can be a signal with the phase out of phase with the first clock signal CLK1, or it can be a signal with a phase delay.

[0085] The first voltage input terminal VPL1 receives a first voltage VGL, and the second voltage input terminal VPH1 receives a second voltage VGH. The voltage level of the first voltage VGL may be lower than the voltage level of the second voltage VGH.

[0086] The IN input terminal can receive signals from the previous light control stage (e.g., EC-C). i-1 (not shown) is the carry signal, and the carry terminal CR can output the carry signal to the next light control stage (e.g., EC-C). i+1 (Not shown). Output terminal OUT1 can provide the light control signal generated from the light control stage EC-Ci to the i-th light-emitting line ELi.

[0087] The start signal EMFLM can be input to the input terminal IN of the first light emission control stage (e.g., EC-C1 (not shown)) in the light emission control stage.

[0088] The gate driver stage GC-Ci may include a third clock terminal CK3, a fourth clock terminal CK4, a third voltage input terminal VPL2, a fourth voltage input terminal VPH2, an input terminal IN, a carry terminal CR, and an output terminal OUT2.

[0089] The third clock terminal CK3 receives the third clock signal CLK3, and the fourth clock terminal CK4 receives the fourth clock signal CLK4. The third clock signal CLK3 and the fourth clock signal CLK4 can be signals with different phases. The fourth clock signal CLK4 can be a signal with the phase out of phase with the third clock signal CLK3, or it can be a signal with a phase delay.

[0090] The third voltage input terminal VPL2 receives the third voltage VGL1, and the fourth voltage input terminal VPH2 receives the fourth voltage VGH1. The voltage level of the third voltage VGL1 may be lower than the voltage level of the fourth voltage VGH1.

[0091] The input terminal IN can receive data from the previous gate drive stage (e.g., GC-C). i-1 (not shown) is the carry signal, and the carry terminal CR can output the carry signal to the next gate drive stage (e.g., GC-C). i+1 (Not shown). Output terminal OUT2 can provide the gate signal generated from gate driver stage GC-Ci to gate line i.

[0092] The start signal FLM can be input to the input terminal IN of the first gate drive stage (e.g., GC-C1 (not shown)) in the gate drive stage.

[0093] In embodiments of the present invention, any one of the following terminals of the light emission control stage EC-Ci—the first clock terminal CK1, the second clock terminal CK2, the first voltage input terminal VPL1, the second voltage input terminal VPH1, the input terminal IN, the carry terminal CR, and the output terminal OUT1—can be omitted, or other terminals may be included. For example, the carry terminal CR can be omitted.

[0094] In embodiments of the present invention, any one of the following terminals of the gate drive stage GC-Ci—the third clock terminal CK3, the fourth clock terminal CK4, the third voltage input terminal VPL2, the fourth voltage input terminal VPH2, the input terminal IN, the carry terminal CR, and the output terminal OUT2—may be omitted, or other terminals may be included. For example, the carry terminal CR may be omitted.

[0095] In addition, Figure 7 The diagram exemplarily illustrates the input terminal IN of the light-emitting control stage EC-Ci and the gate drive stage GC-Ci, which are connected to each of the carry terminals of the preceding stage. However, embodiments of the present invention are not limited thereto. The connections between the drive stages may vary.

[0096] Figure 8 This is a plan view of the input sensing layer TSL according to an embodiment of the present invention.

[0097] like Figure 8 As shown, the input sensing layer TSL may include an input sensor TSP (as shown in the diagram). Figure 4 ) and multiple input sensing lines TL ( Figure 4 The input sensing layer TSL can sense external input using either mutual capacitance or self-capacitance methods. The input sensor TSP may include first touch electrodes TE1-1 to TE1-5 and second touch electrodes TE2-1 to TE2-4. Input sensing line TL( Figure 4 It may include first input sensing lines TL1-1 to TL1-5 electrically connected to first touch electrodes TE1-1 to TE1-5 and second input sensing lines TL2-1 to TL2-4 electrically connected to second touch electrodes TE2-1 to TE2-4. The first input sensing lines TL1-1 to TL1-5 and the second input sensing lines TL2-1 to TL2-4 may be electrically connected to sensing signal pads TS-PD.

[0098] The first touch electrodes TE1-1 to TE1-5 and the second touch electrodes TE2-1 to TE2-4 intersect each other. The first touch electrodes TE1-1 to TE1-5 are arranged on the second direction DR2, and the shape of each of the first touch electrodes TE1-1 to TE1-5 extends in the first direction DR1. The second touch electrodes TE2-1 to TE2-4 are arranged on the first direction DR1, and the shape of each of the second touch electrodes TE2-1 to TE2-4 extends in the second direction DR2.

[0099] Each of the first touch electrodes TE1-1 to TE1-5 includes a first sensor SP1 and a first connecting line CP1. Each of the second touch electrodes TE2-1 to TE2-4 includes a second sensor SP2 and a second connecting line CP2. Of the five first sensors SP1, the two first sensors SP1 located at both ends may have a smaller size than the first sensor SP1 located in the center; for example, they may have half the size of the first sensor SP1 located in the center. Of the six second sensors SP2, the two second sensors SP2 located at both ends may have a smaller size than the second sensor SP2 located in the center; for example, they may have half the size of the second sensor SP2 located in the center.

[0100] exist Figure 8 The diagram illustrates first touch electrodes TE1-1 to TE1-5 and second touch electrodes TE2-1 to TE2-4 according to an embodiment. However, their shapes are not limited to those shown. For example, in embodiments of the present invention, the first touch electrodes TE1-1 to TE1-5 and the second touch electrodes TE2-1 to TE2-4 may have shapes in which the sensor and the connecting lines are indistinguishable from each other.

[0101] The first sensor SP1 is arranged along the first direction DR1, and the second sensor SP2 is arranged along the second direction DR2. Each of the first connecting lines CP1 connects adjacent first sensors SP1, and each of the second connecting lines CP2 connects adjacent second sensors SP2.

[0102] The first input sensing lines TL1-1 to TL1-5 are respectively connected to one end of the first touch electrodes TE1-1 to TE1-5. The second input sensing lines TL2-1 to TL2-4 are connected to both ends of the second touch electrodes TE2-1 to TE2-4. In an embodiment of the present invention, the first input sensing lines TL1-1 to TL1-5 may also be connected to both ends of the first touch electrodes TE1-1 to TE1-5. In an embodiment of the present invention, the second input sensing lines TL2-1 to TL2-4 may be connected to only one end of the second touch electrodes TE2-1 to TE2-4.

[0103] Figure 9 It is shown Figure 4 An enlarged cross-sectional view of region AA.

[0104] refer to Figure 9 A buffer layer BFL can be disposed on the substrate SUB. The buffer layer BFL improves the adhesion between the substrate SUB and the conductive or semiconductor pattern. The buffer layer BFL may include an inorganic layer. Although not shown separately, a barrier layer for preventing the ingress of foreign materials may also be disposed on the upper surface of the substrate SUB. The buffer layer BFL and the barrier layer may be selectively provided or omitted.

[0105] Pixel circuit layer DP-PCL ( Figure 4 It can include multiple transistors. Figure 9 The diagram illustrates one of a plurality of transistors, namely transistor TR. Transistor TR may include a semiconductor pattern OP, a control electrode GE, an input electrode IE, and an output electrode OE. The semiconductor pattern OP may be disposed on a buffer layer BFL. The semiconductor pattern OP may include at least one of amorphous silicon, polycrystalline silicon, and metal oxide.

[0106] A first insulating layer 10 can be disposed on the semiconductor pattern OP. Figure 9 In this embodiment, the first insulating layer 10 is exemplarily shown as being provided in the form of a layer covering the semiconductor pattern OP. However, embodiments of the present invention are not limited thereto.

[0107] The first insulating layer 10 may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a combination thereof.

[0108] On the first insulating layer 10, a control electrode GE of the transistor TR can be disposed. The control electrode GE can be configured to be aligned with the gate line GL. Figure 6 It is manufactured using the same photolithography process as the other two.

[0109] A second insulating layer 20 may be disposed on the first insulating layer 10 and the control electrode GE, covering the control electrode GE. The second insulating layer 20 may provide a flat surface. The second insulating layer 20 may include organic and / or inorganic materials.

[0110] The input electrode IE and output electrode OE of the transistor TR can be disposed on the second insulating layer 20. The input electrode IE and the output electrode OE are connected to the semiconductor pattern OP through a first through-hole CH1 and a second through-hole CH2 passing through the first insulating layer 10 and the second insulating layer 20, respectively.

[0111] Meanwhile, in another embodiment of the present invention, the transistor TR can be converted into a bottom gate structure and implemented.

[0112] A reference can be set on the second insulating layer 20. Figure 7 The power supply electrode E-VSS and multiple signal lines are described. Specifically, the power supply electrode E-VSS, the first clock signal line CL1, the second clock signal line CL2, the third clock signal line CL3, the fourth clock signal line CL4, the first voltage line VL1, the second voltage line VH1, the third voltage line VL2, the fourth voltage line VH2, the first start signal line EF1, and the second start signal line EF2 can be provided on the second insulating layer 20.

[0113] A third insulating layer 30 may be provided on the second insulating layer 20 to cover multiple signal lines CL1, CL2, CL3, CL4, VL1, VH1, VL2, VH2, EF1 and EF2, the input electrode IE, and the output electrode OE. The third insulating layer 30 may cover a portion of the power supply electrodes E-VSS. The third insulating layer 30 includes an organic layer and / or an inorganic layer. Specifically, the third insulating layer 30 may include an organic material to provide a flat surface.

[0114] Depending on the pixel's circuit structure, any one of the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 can be omitted. Each of the second insulating layer 20 and the third insulating layer 30 can be defined as an intermediate layer. The intermediate layer is disposed between the conductive patterns to insulate the conductive patterns.

[0115] A pixel defining film (PDL) and a light-emitting element (ED) can be disposed on the third insulating layer 30. The light-emitting element ED can be disposed in the display area DA. The light-emitting element ED may include a pixel electrode (PE), a light-emitting layer (EML), and a common electrode (CE) laminated sequentially.

[0116] A pixel electrode PE can be disposed on the third insulating layer 30. The pixel electrode PE can be electrically connected to the pixel circuit layer DP-PCL. For example, the pixel electrode PE can be connected to the output electrode OE through a third via CH3 passing through the third insulating layer 30.

[0117] A pixel-defining film (PDL) may be disposed on a third insulating layer 30. The PDL covers at least a portion of the pixel electrode PE and may expose another portion of the pixel electrode PE. A light-emitting layer (EML) may be disposed on the pixel electrode PE. The EML may include an organic light-emitting material. However, embodiments of the present invention are not limited thereto. The EML may include inorganic materials as light-emitting materials. For example, quantum dots may be included as light-emitting materials.

[0118] A common electrode CE can be disposed on the light-emitting layer EML. The common electrode CE can be electrically connected to the power supply electrode E-VSS. The common electrode CE can receive power supply voltage from the power supply electrode E-VSS. The common electrode CE can extend from the display area DA towards the non-display area NDA. The common electrode CE can be disposed between the input sensing line TL and multiple clock signal lines CL1, CL2, CL3, and CL4 (hereinafter, CL). The portion of the common electrode CE extending towards the non-display area NDA can be disposed on the pixel defining film PDL.

[0119] Although not shown, at least one of a hole injection layer (not shown), a hole transport layer (not shown), and an electron blocking layer (not shown) may be disposed between the pixel electrode PE and the light-emitting layer EML. At least one of an electron injection layer (not shown), an electron transport layer (not shown), and a hole blocking layer (not shown) may be disposed between the light-emitting layer EML and the common electrode CE. Holes and electrons injected from the pixel electrode PE and the common electrode CE of the light-emitting element ED respectively will form excitons, and when the excitons fall into the ground state, they can emit light.

[0120] A thin-film encapsulation layer (TFE) can be disposed on the light-emitting element (ED). The TFE layer can be directly disposed on the ED. Figure 9 In the diagram, the thin-film encapsulation layer TFE is shown as being directly disposed on the common electrode CE. However, embodiments of the present invention are not limited thereto. For example, the light-emitting element ED may also include a capping layer (not shown) disposed on the common electrode CE. The capping layer (not shown) may be an optical functional layer for controlling the refractive index of light emitted from the light-emitting layer EML or for controlling the resonant distance of the light. In this case, the thin-film encapsulation layer TFE may be directly disposed on the capping layer (not shown).

[0121] The thin-film encapsulation layer TFE can have a multilayer structure comprising a first inorganic thin film IOL1, a first organic thin film OL1, and a second inorganic thin film IOL2. The first inorganic thin film IOL1, the first organic thin film OL1, and the second inorganic thin film IOL2 can each independently have a single-layer structure or a multilayer structure. However, embodiments of the present invention are not limited thereto. The thin-film encapsulation layer TFE may also comprise organic and inorganic thin films.

[0122] The input sensing layer TSL can be disposed on the thin-film encapsulation layer TFE. The input sensing layer TSL can also be directly disposed on the thin-film encapsulation layer TFE. The input sensing layer TSL may include a first input insulating layer TS-IL1 disposed below the input sensing line TL and a second input insulating layer TS-IL2 covering the input sensing line TL. Although not shown, first touch electrodes TE1-1 to TE1-5 (see [reference needed]) can be disposed below the first input insulating layer TS-IL1. Figure 8) and the second touch electrodes TE2-1 to TE2-4 (see Figure 8 Some components of each of ). For example, below the first input insulation layer TS-IL1, the first connection line CP1 (see Figure 8 Furthermore, a second connecting line CP2 can be provided between the first input insulation layer TS-IL1 and the second input insulation layer TS-IL2 (see...). Figure 8 ), first sensor SP1 and second sensor SP2.

[0123] In the non-display area NDA, a first dam portion DM1 and a second dam portion DM2 can be provided. The first dam portion DM1 and the second dam portion DM2 can be arranged in a plan view to surround the display area DA. When organic monomers are printed to form the first organic film OL1 of the thin-film encapsulation layer TFE, organic monomers may overflow. In this case, the first dam portion DM1 and the second dam portion DM2 can prevent organic monomer overflow.

[0124] The first dam portion DM1 can be disposed on the power supply electrode E-VSS. The first dam portion DM1 can be formed by a single layer, and the first dam portion DM1 can be formed simultaneously with the pixel defining film PDL.

[0125] The second dam section DM2 can be located outside the first dam section DM1. For example, the distance between the first dam section DM1 and the display area DA can be smaller than the distance between the second dam section DM2 and the display area DA.

[0126] The second dam portion DM2 may cover a portion of the power supply electrode E-VSS. The second dam portion DM2 may be formed of multiple layers, and may include a first layer DM2-1 and a second layer DM2-2. The first layer DM2-1 may be formed simultaneously with the third insulating layer 30, and the second layer DM2-2 may be formed simultaneously with the pixel defining film PDL.

[0127] The common electrode CE and the power supply electrode E-VSS can be electrically connected to each other via the first electrode CNE. That is, the first electrode CNE can serve as a connecting electrode for electrically connecting the common electrode CE and the power supply electrode E-VSS. The first electrode CNE can be configured to overlap with the non-display area NDA. The first electrode CNE can be disposed between the power supply electrode E-VSS and the first dam portion DM1. The first electrode CNE can be directly disposed on the power supply electrode E-VSS. The first electrode CNE can be configured to extend towards the display area DA between the third insulating layer 30 and the pixel defining film PDL. The first electrode CNE can be disposed on the same layer as the pixel electrode PE. For example, the first electrode CNE and the pixel electrode PE can be disposed on the third insulating layer 30. The first electrode CNE and the pixel electrode PE can be formed using the same process and can be formed from the same material.

[0128] The first electrode CNE may have at least one second hole CNE-H. For example, in the first electrode CNE, at least one second hole CNE-H may be defined in the portion overlapping with the pixel defining film PDL. Multiple second holes CNE-H may be provided. The second holes CNE-H may be filled with an insulating material, such as the pixel defining film PDL.

[0129] In this embodiment, gases generated during a process can be vented to the outside through the second hole CNE-H. For example, hydrogen gas may be generated in the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 during this process. When the hydrogen gas is not vented, it can be absorbed into the semiconductor layer of the gate drive circuit GDC. Hydrogen gas acts as a carrier and may cause defects in the gate drive circuit GDC. However, in this embodiment, the hydrogen gas can be vented to the outside through the second hole CNE-H, which serves as an exhaust channel.

[0130] The first electrode CNE can be supplied with a common voltage. Therefore, noise generated between the clock signal line CL and the input sensing line TL can be blocked by the first electrode CNE. However, some of the second holes CNE-H may overlap with at least some of the clock signal lines CL in a planar view. Therefore, the clock signal applied to the clock signal line CL is not shielded, thus generating noise in the signal applied to the input sensing line TL. Specifically, in the case of medium-sized display devices such as foldable display devices, compared to small display devices such as mobile phones, the width of the input sensing line TL is large, and therefore the input sensing line TL is greatly affected by the clock signal.

[0131] According to an embodiment of the present invention, the common electrode CE can cover the area where the input sensing line TL and the clock signal line CL overlap in a planar view. The common electrode CE can prevent noise from being generated in the signal applied to the input sensing line TL due to the clock signal applied to the clock signal line CL, and therefore can prevent changes in input sensitivity due to noise.

[0132] Simultaneously, a mask can be used to deposit the common electrode CE. During the formation of the common electrode CE, because the mask and the display panel DP are spaced apart, a shadowing phenomenon occurs, making it possible to deposit a thin outer portion of the common electrode CE, i.e., the portion of the common electrode CE furthest from the display area DA. Due to the thin deposition of the common electrode CE, the signal supplied to the clock signal line CL may not be sufficiently shielded from noise caused by the clock signal line CL. In this case, noise may be generated in the input sensing line TL due to the clock signal applied to the clock signal line CL, and the input sensitivity may be uneven.

[0133] The display panel DP according to an embodiment of the present invention includes a second electrode SE. The second electrode SE may be disposed above or below the common electrode CE. The second electrode SE may directly contact the common electrode CE. In a plan view, the second electrode SE may completely overlap with at least some of the clock signal lines CL.

[0134] The second electrode SE can be disposed on a portion susceptible to noise caused by the clock signal line CL. For example, the second electrode SE can overlap with the clock signal line CL that overlaps with the second hole CNE-H in the plan view. Furthermore, the thickness of the common electrode CE disposed on the first clock signal line CL1, which is furthest from the display area DA, can be less than the thickness of the common electrode CE disposed on the other clock signal lines CL2, CL3, and CL4. In this case, the second electrode SE can overlap at least with the first clock signal line CL1, which is furthest from the display area DA, in the plan view.

[0135] Because the second electrode SE is positioned to overlap with the clock signal line CL, the clock signal applied to the clock signal line CL can be blocked by the second electrode SE, thereby preventing noise from being generated in the input sensing line TL. In other words, the second electrode SE can be used as a shielding electrode to block noise caused by the clock signal line CL.

[0136] The second electrode SE may be conductive. For example, the second electrode SE may comprise at least one of a metal, a transparent conductive compound, and a conductive polymer. More preferably, the second electrode SE may be made of a transparent conductive layer such as indium zinc oxide (IZO). Because the second electrode SE is conductive, the clock signal is effectively blocked, thereby effectively preventing noise from being generated in the input sensing line TL. Therefore, the input sensitivity of the input sensing layer TSL can become uniform.

[0137] The second electrode SE can be disposed on the pixel defining film PDL. For example, the second electrode SE can be disposed spaced apart from the first electrode CNE, and the pixel defining film PDL is inserted between the second electrode SE and the first electrode CNE. Since the second electrode SE is disposed on the pixel defining film PDL, the gas discharged from the second hole CNE-H can be smoothly discharged to the outside without being blocked by the second electrode SE.

[0138] As described above, the input sensing layer TSL can be directly disposed on the thin-film encapsulation layer TFE. In this case, the input sensing line TL and the clock signal line CL are positioned close to each other. Therefore, the input sensing layer TSL is more affected by the clock signal and noise can be generated more frequently in the input sensing layer TSL. However, in the embodiment, since the display panel DP includes a second electrode SE, the noise is blocked, and uniform input sensitivity can be achieved.

[0139] Figure 10A This is a schematic plan view of the first electrode CNE and the second electrode SE according to an embodiment of the present invention. Figure 10B It is along Figure 10A The sectional view taken from line II-II'. Figure 11A This is a schematic plan view of the first electrode CNE and the second electrode SE according to an embodiment of the present invention. Figure 11B It is along Figure 11A The sectional view taken from line III-III'.

[0140] exist Figure 10A The diagram schematically illustrates a first electrode CNE and a second electrode SE disposed on the first electrode CNE. (As shown...) Figure 10A and Figure 10B As shown, multiple second electrodes SE can be configured. Each of the multiple second electrodes SE can correspond one-to-one with each of the multiple second holes CNE-H. That is, each of the multiple second electrodes SE can completely cover each of the multiple second holes CNE-H. Therefore, signals not shielded by the second holes CNE-H can be blocked by the second electrodes SE.

[0141] exist Figure 11A The diagram schematically illustrates a first electrode CNE and a second electrode SE disposed on the first electrode CNE. (As shown...) Figure 11A and Figure 11B As shown, the second electrode SE can be configured as a single unit. The second electrode SE can be integrated to cover multiple second holes CNE-H.

[0142] The display device DD according to the embodiment (see Figure 1 The device includes a second electrode SE that overlaps with at least some of the clock signal lines CL in the planar diagram. The second electrode SE prevents noise from being generated in the input sensing line TL due to the clock signal applied to the clock signal lines CL, and therefore prevents variations in touch sensitivity caused by noise. Thus, the display device DD can achieve uniform input sensitivity.

[0143] According to an embodiment of the present invention, the display device may include a second electrode. The second electrode can prevent noise from being generated in the input sensing line, and therefore, can provide an input sensing layer with uniform input sensitivity.

[0144] Although the inventive concept has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes in form and detail may be made to the embodiments thereof without departing from the spirit and scope of the inventive concept as set forth in the appended claims. Furthermore, the embodiments disclosed herein are not intended to limit the technical spirit of the inventive concept, and all technical concepts falling within the scope of the appended claims and their equivalents should be interpreted as including within the scope of the inventive concept.

Claims

1. A display device, including: The display panel is configured to display images. as well as An input sensing layer is disposed on the display panel and includes an input sensor and multiple input sensing lines electrically connected to the input sensor, wherein... The display panel includes: The base layer includes both display and non-display areas; The circuit layer includes a pixel circuit layer disposed in the display area of ​​the substrate layer and a driving circuit layer disposed in the non-display area of ​​the substrate layer, wherein the driving circuit layer includes power supply electrodes and multiple clock signal lines and provides driving signals configured to drive the pixel circuit layer; The light-emitting element layer includes a pixel electrode disposed on the pixel circuit layer and electrically connected to the pixel circuit layer, a light-emitting layer disposed on the pixel electrode, and a common electrode disposed on the light-emitting layer and extending from the display area toward the non-display area; A first electrode is disposed between the plurality of clock signal lines and the plurality of input sensing lines and has a plurality of second holes defined within the first electrode; and The second electrode is disposed on the first electrode and overlaps with the common electrode and the clock signal line that overlaps with the plurality of second holes in the plan view.

2. The display device according to claim 1, wherein, The at least one of the plurality of clock signal lines includes a clock signal line that is positioned furthest from the display area, and the second electrode overlaps with the clock signal line that is positioned furthest from the display area in the plan view.

3. The display device according to claim 2, wherein, The second electrode is configured as a plurality of second electrodes, and the plurality of second electrodes cover the plurality of second holes in a one-to-one correspondence.

4. The display device according to claim 1, wherein, The first electrode is electrically connected to the power supply electrode and the common electrode.

5. The display device according to claim 1, wherein, The display panel further includes a pixel defining film disposed on the pixel electrode and exposing at least a portion of the pixel electrode, and the second electrode is disposed on the pixel defining film.

6. The display device according to claim 5, wherein, The second electrode is spaced apart from the first electrode, and the pixel defining film is inserted between the first electrode and the second electrode.

7. The display device according to claim 1, wherein, The first electrode is disposed on the same layer as the pixel electrode.

8. The display device according to claim 1, wherein, The second electrode is conductive.

9. The display device according to claim 1, wherein, The second electrode includes a transparent conductive layer.

10. The display device according to claim 1, wherein, The display panel further includes a thin-film encapsulation layer disposed on the light-emitting element layer, and the input sensing layer is directly disposed on the thin-film encapsulation layer.

11. The display device according to claim 1, wherein, A first hole is defined through the display panel and the input sensing layer, and the first hole is surrounded by the display area in the plan view.

12. The display device according to claim 1, wherein, The plurality of second holes are filled with insulating material.

Images