Circuit for approximate floating point fusion dot product operation

Abstract

The invention discloses a circuit for approximate floating point fusion dot product operation. The circuit comprises an extraction module used for extracting sign bits, mantissa bits and exponent bits from four single-precision floating point numbers; the symbol integration module is used for integrating symbol bits and correcting mantissa bits; the index comparison module is used for calculating two groups of dot product effective indexes according to the index bits and generating three control quantities; the first multiplication module is used for generating a first group of approximate partial products according to a correction mantissa digit corresponding to a first control quantity larger value; the second multiplication module is used for generating a second group of approximate partial products according to the correction mantissa digit corresponding to the smaller value of the first control quantity, and performing arithmetic displacement and adding symbol compensation bits according to the size of the second control quantity; the fusion compression module is used for performing fusion compression on the first group of approximate partial products, the second group of approximate partial products after arithmetic shift and the symbol compensation bits to obtain a sum sequence and a carry sequence; and the result output module is used for generating a dot product operation result in combination with the third control quantity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of approximate circuit design, in particular, to a circuit for approximate floating point fused dot product operation. BACKGROUND

[0002] Compared with fixed point numbers, floating point numbers have a wider data representation range, so floating point number operations are widely used in fields such as digital signal processing, image recognition, deep learning and other fields with high data range requirements. However, floating point number operations require complex processing steps such as scaling, normalization and rounding, which significantly increases the hardware resource overhead and operation delay of floating point number operations. An effective optimization strategy is to disassemble the floating point number operation steps and fuse multiple floating point number operations to reduce redundant calculations and improve the overall performance of the floating point number operation unit. For example, a floating point fused dot product operation unit facing multiple multiply-add operation scenarios.

[0003] There is little research on floating point fused dot product operation units. Current floating point fused dot product operation units mainly optimize the normalization, exponent comparison or mantissa alignment logic in floating point multiplication operations, or improve data throughput through pipeline design. However, this has the following problems: (1) The implementation of the pipeline structure requires additional register cascading, which not only increases the hardware area and power consumption overhead, but also results in a large total delay for completing a single floating point fusion operation, making it difficult to meet the real-time signal processing, low-latency inference and other time response requirements of strict scenarios; (2) Existing designs often compress each group of partial products independently, resulting in high circuit complexity and large area. SUMMARY

[0004] To solve the problems in the prior art, the present application provides a circuit for approximate floating point fused dot product operation, which has the characteristics of small area, low complexity, low power consumption and low delay.

[0005] To achieve the above technical purposes, the present application adopts the following technical solutions: a circuit for approximate floating point fused dot product operation, comprising: an extraction module, a symbol integration module, an exponent comparison module, a first multiplication module, a second multiplication module, a fusion compression module and a result output module; The extraction module is used to extract the sign bit, mantissa bit and exponent bit from four single-precision floating point numbers conforming to the IEEE754 standard, respectively; The symbol integration module is used to integrate the extracted sign bits and correct the mantissa bits using the integrated sign bits to obtain corrected mantissa bits; The exponent comparison module is used to calculate two groups of dot product effective exponents according to the exponent bits, and generate a comparison result of the two groups of dot product effective exponents, a difference value of the two groups of dot product effective exponents and a larger value of the two groups of dot product effective exponents. The first multiplication module is configured to generate a first group of approximate partial products according to the modified mantissa bits corresponding to the group of dot products with larger effective exponent in the comparison result of the two groups of effective exponents of dot products; The second multiplication module is configured to generate a second group of approximate partial products according to the modified mantissa bits corresponding to the group of dot products with smaller effective exponent in the comparison result of the two groups of effective exponents of dot products, and to perform arithmetic shift and add sign compensation bits according to the size of the difference between the two groups of effective exponents of dot products; The fusion compression module is configured to fuse and compress the first group of approximate partial products, the second group of approximate partial products after arithmetic shift, and the sign compensation bits to obtain two sequences of and and a sequence of carry. The result output module is configured to combine the sequence of and the sequence of carry with the larger value in the two groups of effective exponents of dot products to generate a dot product operation result.

[0006] Further, the sign integration module includes a first sign integration unit and a second sign integration unit. The first sign integration unit is configured to integrate the extracted first sign bit and the second sign bit to obtain a first integrated sign bit , and to correct the second mantissa bit according to the first integrated sign bit . The second sign integration unit is configured to integrate the operator and the extracted third sign bit , the fourth sign bit to obtain a second integrated sign bit , and to correct the fourth mantissa bit according to the second integrated sign bit . , wherein represents an exclusive OR operation, represents an addition operation, =1 represents a subtraction operation.

[0007] Further, the first sign integration unit includes a first leading 1 expansion unit, a first bit inversion unit, a first exclusive OR gate, and a first selector. The first leading 1 expansion unit is configured to perform leading 1 expansion on the first mantissa bit and the second mantissa bit respectively, that is, to add three bits of 001 in front of the highest bit of the first mantissa bit and the second mantissa bit to obtain the modified first mantissa bit and the leading 1 expanded second mantissa bit. The first exclusive OR gate is configured to perform exclusive OR operation on the first sign bit and the second sign bit to obtain the first integrated sign bit . The first bit inversion unit is configured to add and invert all bits except the first integrated sign bit to obtain the bit-inverted second mantissa bits; The first selector is configured to select the corrected second mantissa bits from the leading 1 extended second mantissa bits and the bit-inverted second mantissa bits .

[0008] Further, the second integrated unit comprises a second leading 1 extension unit, a second bit inversion unit, a second XOR gate, a third XOR gate and a second selector. The second leading 1 extension unit is configured to perform leading 1 extension on the third mantissa bits and the fourth mantissa bits respectively, to add three bits 001 in front of the highest bits of the third mantissa bits and the fourth mantissa bits to obtain the corrected third mantissa bits and the leading 1 extended fourth mantissa bits. The second XOR gate is configured to perform XOR operation on the third sign bit and the fourth sign bit to obtain the third integrated sign bit. The third XOR gate is configured to perform XOR operation on the third integrated sign bit and the operator to obtain the second integrated sign bit . The second bit inversion unit is configured to add and invert all bits except the second integrated sign bit to obtain the bit-inverted fourth mantissa bits. The second selector is configured to select the corrected fourth mantissa bits from the leading 1 extended fourth mantissa bits and the bit-inverted fourth mantissa bits .

[0009] Further, the calculation process of the two sets of dot product effective exponents is as follows:

[0010]

[0011] wherein, represents the first dot product effective exponent, represents the first exponent bit, represents the second exponent bit, represents the second dot product effective exponent, represents the third exponent bit, represents the fourth exponent bit.

[0012] Furthermore, the first multiplication module includes: a first data exchange module, a first Booth encoding module, and a first approximate partial product generation module; The first data exchange module includes a third selector and a fourth selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa of one set of dot products is input into the third selector for selection, and the corrected mantissa of the other set of dot products is input into the fourth selector for selection, so as to obtain the corrected mantissa of the dot product with the larger effective exponent. The Booth encoding module is used to encode the selection result of the fourth selector to obtain the first Booth encoding; The first approximate partial product generation module is used to generate a first set of approximate partial products based on the selection result of the third selector and the first Booth encoding.

[0013] Furthermore, the second bit multiplication calculation module includes: a second data exchange module, a second Booth encoding module, a second approximate partial product generation module, and a partial product shifting module; The second data exchange module includes a fifth selector, a sixth selector, and a seventh selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa bits corresponding to one set of dot products are input into the fifth selector for selection, and the corrected mantissa bits corresponding to the other set of dot products are input into the sixth selector for selection, so as to obtain the corrected mantissa bits corresponding to the dot product with the smaller effective exponent; the seventh selector is used to select the integrated sign bit from the first integrated sign bit and the second integrated sign bit. The Booth encoding module is used to encode the selection result of the sixth selector to obtain the second Booth encoding; The second approximate partial product generation module is used to generate a second set of approximate partial products based on the selection result of the fifth selector and the second Booth encoding; The partial product shift module is used to perform an arithmetic right shift on the entire column of the second set of approximate partial products by the difference between the effective exponents of the two sets of dot products, to obtain aligned approximate partial products. The most significant bit of the aligned approximate partial product is then placed to the left of the column based on the integrated sign bit, and a sign compensation bit is added.

[0014] Furthermore, if the sign bit is integrated Add two sets of 1s representing the difference of the significant exponents of the dot product to the left of the most significant bit of the aligned approximate partial product, and add 0s to all remaining bits; if Add 0s to the left of the most significant bit of the aligned approximate partial product.

[0015] Furthermore, the result output module includes: a mantissa addition module, a regularization module, and an exponent adjustment module; The mantissa addition module is used to calculate the sum of the sum sequence and the carry sequence, and uses the highest bit of the sum as the output sign bit; The regularization module is used to determine whether to perform bitwise inversion based on the highest bit of the summation result. If the highest bit is 1, all bits of the summation result except the sign bit are inverted. If the highest bit is 0, the summation result remains unchanged. Then, a leading 1 is detected, and the mantissa and exponent adjustment signals are output. The index adjustment module is used to adjust the index signal. and the larger of the two sets of effective exponents of the dot product Calculate the output exponent bits ; The output sign bit, output mantissa bit, and output exponent bit are used together as the result of the dot product operation.

[0016] Furthermore, the output process of the exponential adjustment signal is as follows: i: If the 24th bit of the sum is 1, the exponential adjustment signal is 0; otherwise, check if the 23rd bit of the sum is 1. ii: If yes, increment the exponential adjustment signal by 1; otherwise, continue to check if the next bit is 1. iii: Repeat step ii until it is determined whether the first digit of the sum is 1. If it is, the exponent adjustment signal is 22; otherwise, the exponent adjustment signal is 23.

[0017] Compared with the prior art, the present invention has the following beneficial effects: (1) The circuit of the approximate floating-point fused dot product operation of the present invention integrates the sign bit in the single-precision floating-point number through the sign integration module, and uses the integrated sign bit to correct the mantissa bit, ensuring that the two sets of dot products always perform addition operation, avoiding additional sign judgment and subtraction operation logic, and reducing hardware overhead. (2) The circuit of the approximate floating-point fused dot product operation of the present invention generates two sets of dot product effective exponents based on the comparison results of the two sets of dot product effective exponents, and remaps the inputs of the first multiplication module and the second multiplication module. The difference between the two sets of dot product effective exponents is directly applied to the arithmetic shift of the approximate partial product, avoiding the large bit width shifter from becoming the critical path. This can effectively reduce the area of ​​the shift unit and the logic depth, and at the same time realize the close coordination between the exponent alignment and the data flow inside the multiplier. In addition, the Booth encoding module is used in the multiplication stage and approximate calculation is introduced to generate the approximate partial product to reduce the multiplication overhead. (3) The circuit for approximate floating-point fused dot product operation of the present invention fuses and compresses the first group of approximate partial products, the second group of approximate partial products with arithmetic shift, and the sign compensation bits, thereby improving the efficiency of the fusion compression module, avoiding two independent compressions and carry propagation between multi-level groups, and effectively reducing circuit area and delay. In addition, during the approximate partial product shifting stage, a small amount of compensation "1" is injected according to the product sign. Without explicitly saving the complete sign extension, the result of the approximate partial product compression is equivalent to performing an arithmetic right shift on the high bits, thereby completing the sign correction with a small hardware overhead. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit for approximate floating-point fused dot product operation according to the present invention; Figure 2 This is a schematic diagram of the symbol integration module in this invention; Figure 3 This is a schematic diagram of the first multiplication module and the second multiplication module in this invention. Detailed Implementation

[0019] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.

[0020] like Figure 1 This is a schematic diagram of the circuit for approximate floating-point fused dot product operation of the present invention. The circuit includes: an extraction module, a sign integration module, an exponent comparison module, a first multiplication module, a second multiplication module, a fusion compression module, and a result output module. The extraction module is used to extract data from four single-precision floating-point numbers conforming to the IEEE 754 standard. Extracting the sign bit mantissa and exponent The four single-precision floating-point numbers that conform to the IEEE 754 standard are all represented by 32 bits of binary. Taking A[31:0] as an example, the highest bit A

[31] is the sign bit. When A

[31] =1, it represents a negative number, and when A

[31] =0, it represents a positive number. A[30:23] is the exponent bit, and A[22:0] is the mantissa bit.

[0021] The sign integration module integrates the extracted sign bits and uses the integrated sign bits to correct the mantissa bits, obtaining the corrected mantissa bits. By integrating the sign bits in single-precision floating-point numbers and using the integrated sign bits to correct the mantissa bits, the module ensures that the two sets of dot products always perform addition operations, avoiding additional sign judgment and subtraction logic and reducing hardware overhead. Figure 2 The symbol integration module includes a first symbol integration unit and a second symbol integration unit; The first integration unit is used to extract the first symbol bit. Second sign bit The first integrated symbol bit is obtained by integration. According to the first integrated symbol bit Correct the second last digit; The second symbol integration unit is used to integrate operators and the extracted third sign bit Fourth sign bit The integration process yields the second integrated symbol bit. According to the second integrated symbol bit Correct the fourth last digit; in, This represents the XOR operation. , indicates addition. =1 indicates a subtraction operation.

[0022] In one technical solution of the present invention, the first conformance integration unit includes: a first preamble 1 extension unit, a first bit-inverting unit, a first XOR gate, and a first selector; The first leading 1 extension unit is used to respectively convert the first mantissa digits Second last digit A leading 1 expansion is performed. Considering that the subsequent Booth algorithm requires the bit width of both multipliers to be even, the first mantissa is... Second last digit Add three 001 bits before the highest bit to obtain the corrected first mantissa. The second mantissa, extended by the leading 1; The first XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain the first integrated sign bit. ; The first bitwise inversion unit is used to add a bit before the most significant bit of the second mantissa. And except for the first integrated symbol bit Invert all the bits outside the first digit to get the second bitwise reversed digit. The first selector is used to select from the second mantissa extended with leading 1s and the second mantissa bitwise reversed to obtain the corrected second mantissa. The first mantissa digit of the correction was preserved through sign integration. Since the number is always positive, we only need to add bitwise inversion logic to the second mantissa, which reduces the circuit area and power consumption.

[0023] In one technical solution of the present invention, the second conformance integration unit includes: a second preamble 1 extension unit, a second bit-inverting unit, a second XOR gate, a third XOR gate, and a second selector; The second preamble 1 extension unit is used to respectively convert the third mantissa digit and the fourth last digit A leading 1 extension is performed. Considering that the subsequent Booth algorithm requires the bit width of both multipliers to be even, the extension is done in the third mantissa. and the fourth last digit Add three 001 bits before the highest bit to obtain the corrected third mantissa. The fourth digit extended from the leading 1; The second XOR gate is used to perform an XOR operation on the third and fourth sign bits to obtain the third integrated sign bit. The third XOR gate is used to perform an XOR operation between the third integrated sign bit and the operator to obtain the second integrated sign bit. ; The second bitwise inversion unit is used to add a bit before the most significant bit of the fourth mantissa. And except for the second integration sign bit Invert all the bits except the first one to get the fourth bit of the reversed digits; The second selector is used to select from the fourth mantissa extended by leading 1 and the fourth mantissa bit-inverted to obtain the corrected fourth mantissa. By integrating the operators representing addition and subtraction into the sign bit of the fourth mantissa, the bitwise NOT logic is reduced while ensuring that the two sets of dot products are always added, thus reducing the circuit's computational complexity and resource overhead.

[0024] The exponent comparison module is used to calculate two sets of effective exponents for the dot product based on the exponent digits, and then uses these two sets of effective exponents to generate a comparison result of the two sets of effective exponents. The difference between the two sets of effective exponents of the dot product and the larger of the two sets of effective exponents of the dot product , specifically, when hour, , , ;when hour, , , It is used for subsequent data exchange, approximate partial product shifting, and exponential adjustment.

[0025] The calculation process for the two sets of effective exponents of the dot product is as follows:

[0026]

[0027] in, This represents the effective exponent of the first point product. Indicates the first exponent. Indicates the second exponent. This represents the effective exponent of the second point product. Indicates the third exponent. This indicates the fourth exponent.

[0028] The first multiplication module is used to generate the first set of approximate partial products based on the corrected mantissa of the set of dot products with the larger effective exponent; for example... Figure 3 The first multiplication module includes: a first data exchange module, a first Booth encoding module, and a first approximate partial product generation module; The first data exchange module includes a third selector and a fourth selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa of one set of dot products is input into the third selector for selection, and the corrected mantissa of the other set of dot products is input into the fourth selector for selection, so as to obtain the corrected mantissa of the dot product with the larger effective exponent. To reduce the resource overhead of mantissa multiplication, a Booth encoding module is introduced to encode the selection result of the fourth selector, resulting in the first Booth encoding. The first approximate partial product generation module is used to generate the first set of approximate partial products based on the selection result of the third selector and the first Booth encoding. The low-weight partial products are truncated, and only the high-weight partial product columns are generated when generating approximate partial products to reduce multiplication overhead. The specific degree of truncation can be determined according to different precision requirements.

[0029] The second multiplication module generates a second set of approximate partial products based on the smaller of the two sets of effective exponents, using the corrected mantissa bits corresponding to the two sets of dot products. It then performs arithmetic shifts and adds sign compensation bits based on the difference between the two sets of effective exponents. Figure 3 The second bit multiplication calculation module includes: a second data exchange module, a second Booth encoding module, a second approximate partial product generation module, and a partial product shifting module; The second data exchange module includes a fifth selector, a sixth selector, and a seventh selector. Based on the comparison results of the two sets of dot product effective exponents, the corrected mantissa bits corresponding to one set of dot products are input into the fifth selector for selection, and the corrected mantissa bits corresponding to the other set of dot products are input into the sixth selector for selection, thus obtaining the corrected mantissa bits corresponding to the dot product with the smaller effective exponent. The seventh selector is used to select the integrated sign bit from the first integrated sign bit and the second integrated sign bit. Through the second data exchange module, the operand with the smaller effective exponent is always connected to the second multiplication module, achieving close coordination between exponent alignment and the internal data flow of the multiplier.

[0030] The Booth encoding module is used to encode the selection result of the sixth selector to obtain the second Booth encoding; The second approximate partial product generation module is used to generate a second set of approximate partial products based on the selection result of the fifth selector and the second Booth encoding. The partial product shift module is used to perform the difference between the effective exponents of the two sets of dot products on an entire column of the second set of approximate partial products. The size is arithmetically shifted right to obtain an aligned approximate partial product. The most significant bit of the aligned approximate partial product is then placed to the left, and a sign compensation bit is added based on the consolidated sign bit. If the consolidated sign bit... Add two sets of 1s representing the difference of the significant exponents of the dot product to the left of the most significant bit of the aligned approximate partial product, and add 0s to all remaining bits; if By adding zeros to the left of the most significant bit column of the aligned approximate partial product, and ensuring that the total number of bits for sign compensation is consistent with the number of bits in the second group of approximate partial products, the area and logic depth of the shifter are reduced, while sign correction is accomplished with less hardware overhead.

[0031] This invention generates two sets of effective exponents based on the comparison results of the two sets of effective exponents of the dot product, and remaps the inputs of the first and second multiplication modules. The difference between the two sets of effective exponents of the dot product is directly applied to the arithmetic shift of the approximate partial product, avoiding the large bit-width shifter from becoming the critical path. This effectively reduces the area of ​​the shift unit and the logic depth, while achieving close coordination between the exponent alignment and the data flow inside the multiplier. In addition, a Booth encoding module is used in the multiplication stage and approximate calculation is introduced to generate an approximate partial product to reduce the multiplication overhead.

[0032] The fusion compression module is used to fuse and compress the first set of approximate partial products, the second set of approximate partial products after arithmetic shift, and the sign compensation bits in the same compression tree, resulting in two rows denoted as sum sequences. and carry sequence The fusion compression module uses 4:2 and 3:2 compressors, and the overall size of the fusion compression module is determined by the size of the approximate partial product matrix. By fusing the first set of approximate partial products, the arithmetically shifted second set of approximate partial products, and the sign compensation bits, the efficiency of individual compressors in the fusion compression module is improved. This avoids two independent compression sets and carry propagation between multiple groups, effectively reducing circuit area and delay. Furthermore, during the shifting stage of the second set of approximate partial products, a small amount of compensation "1" is injected according to the product sign. Without explicitly preserving the complete sign extension, the result of partial approximate product compression is equivalent to performing an arithmetic right shift on the complete product in the high bits, thus completing the sign correction with minimal hardware overhead.

[0033] The result output module combines the sum sequence and the carry sequence with the larger of the two sets of effective exponents of the dot product to generate the dot product result. The result output module includes: a mantissa addition module, a regularization module, and an exponent adjustment module. The mantissa addition module uses a carry-lookahead adder and a carry-select adder to form a CLA-based CSA, which is used to calculate the sum of the sum sequence and the carry sequence, and uses the highest bit of the sum as the output sign bit; The regularization module is used to determine whether to perform bitwise inversion based on the highest bit of the summation result. If the highest bit is 1, all bits of the summation result except the sign bit are inverted. If the highest bit is 0, the summation result remains unchanged. Then, a leading 1 detection is performed, and the mantissa and exponent adjustment signals are output. The exponential adjustment module is used to adjust the exponential signal. and the larger of the two sets of effective exponents of the dot product Calculate the output exponent bits ; The output sign bit, output mantissa bit, and output exponent bit are used together as the result of the dot product operation.

[0034] In one technical solution of the present invention, the output process of the exponential adjustment signal is as follows: i: If the 24th bit of the sum is 1, the exponential adjustment signal is 0; otherwise, check if the 23rd bit of the sum is 1. ii: If yes, increment the exponential adjustment signal by 1; otherwise, continue to check if the next bit is 1. iii: Repeat step ii until it is determined whether the first digit of the sum is 1. If it is, the exponent adjustment signal is 22; otherwise, the exponent adjustment signal is 23.

[0035] By statistically analyzing the dot product calculation results of this invention, when generating partial products with 27 columns of height, the accuracy of the calculation results of this invention can reach: the average relative error is [value missing]. The normalized mean error is Meanwhile, the signal quantization noise ratio of this invention is 112.25dB, which meets the accuracy requirements of most word signal processing.

[0036] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A circuit for approximate floating-point fused dot product operation, characterized in that, include: The module includes an extraction module, a symbol integration module, an exponent comparison module, a first multiplication module, a second multiplication module, a fusion compression module, and a result output module. The extraction module is used to extract the sign bit, mantissa bit, and exponent bit from four single-precision floating-point numbers conforming to the IEEE 754 standard, respectively. The symbol integration module is used to integrate the extracted sign bits and use the integrated sign bits to correct the mantissa bits to obtain the corrected mantissa bits. The index comparison module is used to calculate two sets of dot product effective indices based on the index digits, and to generate a comparison result of the two sets of dot product effective indices, the difference between the two sets of dot product effective indices, and the larger value of the two sets of dot product effective indices using the two sets of dot product effective indices. The first multiplication module is used to generate a first set of approximate partial products based on the corrected mantissa of the set of dot products with the larger effective exponent in the comparison results of the two sets of dot products. The second multiplication module is used to generate a second set of approximate partial products based on the correction mantissa of the smaller set of dot products in the comparison results of the two sets of dot product effective exponents, and to perform arithmetic shift and add sign compensation bits according to the difference between the two sets of dot product effective exponents. The fusion compression module is used to fuse and compress the first group of approximate partial products, the second group of approximate partial products after arithmetic shift, and the sign compensation bit to obtain two rows, which are denoted as the sum sequence and the carry sequence, respectively. The result output module is used to combine the sum sequence and the carry sequence with the larger of the two sets of effective exponents of the dot product to generate the dot product result.

2. The circuit for approximate floating-point fused dot product operation according to claim 1, characterized in that, The symbol integration module includes a first symbol integration unit and a second symbol integration unit; The first conformance integration unit is used to extract the first sign bit Second sign bit The first integrated symbol bit is obtained by integration. According to the first integrated symbol bit Correct the second last digit; The second symbol integration unit is used to integrate operators and the extracted third sign bit Fourth sign bit The integration process yields the second integrated symbol bit. According to the second integrated symbol bit Correct the fourth last digit; in, This represents the XOR operation. , indicates addition. =1 indicates a subtraction operation.

3. The circuit for approximate floating-point fused dot product operation according to claim 2, characterized in that, The first conformance integration unit includes: a first preamble 1 extension unit, a first bit-inverting unit, a first XOR gate, and a first selector; The first leading 1 extension unit is used to respectively extend the first mantissa digits Second last digit Perform leading 1 expansion on the first mantissa. Second last digit Add three 001 bits before the highest bit to obtain the corrected first mantissa. The second mantissa, extended by the leading 1; The first XOR gate is used to perform an XOR operation on the first sign bit and the second sign bit to obtain the first integrated sign bit. ; The first bit-inverting unit is used to add a bit before the most significant bit of the second mantissa. And except for the first integrated symbol bit Invert all the bits outside the first digit to get the second bitwise reversed digit. The first selector is used to select from the second mantissa extended with leading 1 and the second mantissa bitwise inverted to obtain the corrected second mantissa. .

4. The circuit for approximate floating-point fused dot product operation according to claim 2, characterized in that, The second conformal integration unit includes: a second preamble 1 extension unit, a second bit-inverting unit, a second XOR gate, a third XOR gate, and a second selector; The second leading 1 extension unit is used to respectively extend the third mantissa digits and the fourth last digit Perform leading 1 expansion on the third mantissa. and the fourth last digit Add three 001 bits before the highest bit to obtain the corrected third mantissa. The fourth digit extended from the leading 1; The second XOR gate is used to perform an XOR operation on the third sign bit and the fourth sign bit to obtain the third integrated sign bit; The third XOR gate is used to perform an XOR operation on the third integrated sign bit and the operator to obtain the second integrated sign bit. ; The second bitwise inversion unit is used to add a bit before the most significant bit of the fourth mantissa. And except for the second integration sign bit Invert all the bits except the first one to get the fourth bit of the reversed digits; The second selector is used to select from the fourth mantissa extended with leading 1s and the fourth mantissa bitwise reversed to obtain the corrected fourth mantissa. .

5. The circuit for approximate floating-point fused dot product operation according to claim 1, characterized in that, The calculation process for the two sets of effective exponents of the dot product is as follows: in, This represents the effective exponent of the first point product. Indicates the first exponent. Indicates the second exponent. This represents the effective exponent of the second point product. Indicates the third exponent. This indicates the fourth exponent.

6. The circuit for approximate floating-point fused dot product operation according to claim 1, characterized in that, The first multiplication module includes: a first data exchange module, a first Booth encoding module, and a first approximate partial product generation module; The first data exchange module includes a third selector and a fourth selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa of one set of dot products is input into the third selector for selection, and the corrected mantissa of the other set of dot products is input into the fourth selector for selection, so as to obtain the corrected mantissa of the dot product with the larger effective exponent. The Booth encoding module is used to encode the selection result of the fourth selector to obtain the first Booth encoding; The first approximate partial product generation module is used to generate a first set of approximate partial products based on the selection result of the third selector and the first Booth encoding.

7. The circuit for approximate floating-point fused dot product operation according to claim 2, characterized in that, The second bit multiplication calculation module includes: a second data exchange module, a second Booth encoding module, a second approximate partial product generation module, and a partial product shifting module; The second data exchange module includes a fifth selector, a sixth selector, and a seventh selector. Based on the comparison results of the effective exponents of the two sets of dot products, the corrected mantissa bits corresponding to one set of dot products are input into the fifth selector for selection, and the corrected mantissa bits corresponding to the other set of dot products are input into the sixth selector for selection, so as to obtain the corrected mantissa bits corresponding to the dot product with the smaller effective exponent; the seventh selector is used to select the integrated sign bit from the first integrated sign bit and the second integrated sign bit. The Booth encoding module is used to encode the selection result of the sixth selector to obtain the second Booth encoding; The second approximate partial product generation module is used to generate a second set of approximate partial products based on the selection result of the fifth selector and the second Booth encoding; The partial product shift module is used to perform an arithmetic right shift on the entire column of the second set of approximate partial products by the difference between the effective exponents of the two sets of dot products, to obtain aligned approximate partial products. The most significant bit of the aligned approximate partial product is then placed to the left of the column based on the integrated sign bit, and a sign compensation bit is added.

8. The circuit for approximate floating-point fused dot product operation according to claim 7, characterized in that, If the sign bit is integrated Add two sets of 1s representing the difference of the significant exponents of the dot product to the left of the most significant bit of the aligned approximate partial product, and add 0s to all remaining bits; if Add 0s to the left of the most significant bit of the aligned approximate partial product.

9. The circuit for approximate floating-point fused dot product operation according to claim 1, characterized in that, The result output module includes: a mantissa addition module, a regularization module, and an exponent adjustment module; The mantissa addition module is used to calculate the sum of the sum sequence and the carry sequence, and uses the highest bit of the sum as the output sign bit; The regularization module is used to determine whether to perform bitwise inversion based on the highest bit of the summation result. If the highest bit is 1, the summation result is inverted bitwise except for the sign bit. If the highest bit is 0, the summation result remains unchanged. Then, a leading 1 detection is performed, and the mantissa and exponent adjustment signals are output. The index adjustment module is used to adjust the index signal. and the larger of the two sets of effective exponents of the dot product Calculate the output exponent bits ; The output sign bit, output mantissa bit, and output exponent bit are used together as the result of the dot product operation.

10. The circuit for approximate floating-point fused dot product operation according to claim 9, characterized in that, The output process of the exponential adjustment signal is as follows: i: If the 24th bit of the sum is 1, the exponential adjustment signal is 0; otherwise, check if the 23rd bit of the sum is 1. ii: If yes, increment the exponential adjustment signal by 1; otherwise, continue to check if the next bit is 1. iii: Repeat step ii until it is determined whether the first digit of the sum is 1. If it is, the exponent adjustment signal is 22; otherwise, the exponent adjustment signal is 23.

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