Optical control module, mask, and method including optical control module and mask

Abstract

The present disclosure relates to an optical control module, a mask, and a method including an optical control module and a mask. An optical control module, a mask, and a method including an optical control module and a mask for patterning an integrated circuit device. The method includes exposing an initial mask exposure field and a subsequent mask exposure field on the surface of a semiconductor substrate via a mask. The initial mask exposure field and the subsequent mask exposure field pattern corresponding array areas and edge areas on the semiconductor substrate. The initial mask exposure field partially overlaps with the subsequent mask exposure field, so that the initial optical control module (OCM) patterned during the exposure of the initial mask exposure field and the subsequent OCM patterned during the exposure of the subsequent mask exposure field are both positioned within a single control module die. The mask includes a mask that can be used during the method or can form the integrated circuit device. The integrated circuit device includes an integrated circuit device formed using the method or the mask.

Description

Technical Field

[0001] The present disclosure relates generally to photolithography, and more particularly to an optical control module for aligning adjacent reticle exposure fields during patterning of integrated circuit devices. Background Art

[0002] Multiple integrated circuit devices are typically fabricated on a single semiconductor substrate. The fabrication process includes patterning individual layers of the integrated circuit device on the semiconductor substrate using photolithography techniques. Such photolithography techniques utilize separate masks that include patterning information about the individual layers to pattern each individual layer of the integrated circuit device. In practice, the mask is only used to pattern a portion of the multiple integrated circuit devices, which may be confined within a mask field of the mask, for example. In order to pattern all of the integrated circuit devices to be fabricated on the semiconductor substrate, the mask field is stepped across the surface of the semiconductor substrate, thereby patterning repeated instances of the mask exposure field on the surface of the semiconductor substrate.

[0003] An optical control module (OCM) is used to align adjacent reticle exposure fields. A lithography system can utilize the OCM as a reference structure during a patterning process, thereby allowing adjacent reticle exposure fields to be aligned in a regular grid or pattern on the surface of a semiconductor substrate.

[0004] Historically, OCMs were positioned within the scribe lines that separated adjacent integrated circuit devices. Such an approach is effective for wide scribe lines, such as may be used when singulating integrated circuit devices via mechanical sawing techniques. However, the semiconductor industry is moving toward narrower scribe lines in order to increase the density of integrated circuit devices on a semiconductor substrate. In these systems, laser scribing techniques are used to singulate integrated circuit devices, and the presence of OCMs within the scribe lines may generally be detrimental to such laser scribing techniques.

[0005] More recently, the four corner dies of a given reticle exposure field each include a corresponding OCM. Such a configuration allows structureless scribing, thereby allowing laser scribing techniques. However, within each reticle exposure field, four dies must be sacrificed as OCMs, thereby reducing the total number of marketable integrated circuit devices that can be patterned on a semiconductor substrate. Summary of the invention

[0006] According to a first aspect of the present invention, there is provided a method for manufacturing an integrated circuit device, the method comprising:

[0007] The mask and the semiconductor substrate are positioned relative to each other, wherein

[0008] (i) the mask includes an array region and an edge region;

[0009] (ii) the array region includes a pattern representing device layers of a plurality of integrated circuit devices and arranged in a two-dimensional grid, the two-dimensional grid including scribe lines separating adjacent device layers of adjacent integrated circuit devices of the plurality of integrated circuit devices;

[0010] (iii) the array region further comprises a control module die, the control module die comprising a patterning of a first optical control module (OCM) representing the device layer; and

[0011] (iv) the edge region is outside the array region and includes a pattern representing a second OCM of the device layer, a pattern representing a third OCM of the device layer, and a pattern representing a fourth OCM of the device layer;

[0012] exposing an initial mask exposure field on a surface of the semiconductor substrate via the mask to pattern an initial array region and an initial edge region on the semiconductor substrate; and

[0013] Exposing subsequent mask exposure fields on the surface of the semiconductor substrate via the mask to pattern subsequent array regions and subsequent edge regions on the semiconductor substrate, wherein the subsequent mask exposure fields partially overlap with the initial mask exposure fields, so that an initial OCM patterned during the exposure of the initial mask exposure fields and a subsequent OCM patterned during the exposure of the subsequent mask exposure fields are both positioned within a single control module die.

[0014] In one or more embodiments, exposing the initial mask exposure field and exposing the subsequent mask exposure field include directing electromagnetic radiation through the mask and incident on a photoresist layer coating the surface of the semiconductor substrate to selectively expose the photoresist layer to the electromagnetic radiation.

[0015] In one or more embodiments, (i) prior to said positioning, said method further comprises coating said surface of said semiconductor substrate with a photoresist layer; and

[0016] (ii) after said exposing said initial reticle exposure field and said exposing said subsequent reticle exposure field, said method further comprises developing said photoresist layer to form a photoresist pattern on said surface of said semiconductor substrate.

[0017] In one or more embodiments, the mask is a first mask including a first array region and a first edge region, wherein the photoresist layer is a first photoresist layer, and further wherein the method includes:

[0018] (i) defining the device layer of the plurality of integrated circuit devices on the semiconductor substrate;

[0019] (ii) removing the photoresist pattern from the semiconductor substrate;

[0020] (iii) coating the surface of the semiconductor substrate with a second photoresist layer; and

[0021] (iv) repeating said positioning, said exposing said initial reticle exposure field, and said exposing said subsequent reticle exposure field with a second reticle including a second array region and a second edge region.

[0022] In one or more embodiments, the repeating comprises:

[0023] (i) during said repeating said exposing said initial reticle exposure field, aligning said first OCM, said second OCM, said third OCM and said fourth OCM of said initial reticle exposure field exposed via said second reticle with said first OCM, said second OCM, said third OCM and said fourth OCM of said initial reticle exposure field exposed via said first reticle to provide inter-layer alignment of said initial reticle exposure field; and

[0024] (ii) during the repeating of exposing the subsequent mask exposure field, the first OCM, the second OCM, the third OCM and the fourth OCM of the subsequent mask exposure field exposed through the second mask are aligned with the first OCM, the second OCM, the third OCM and the fourth OCM of the subsequent mask exposure field exposed through the first mask to provide inter-layer alignment of the subsequent mask exposure fields.

[0025] In one or more embodiments, the method further includes exposing a third mask exposure field on the surface of the semiconductor substrate via the mask to pattern a third array area and a third edge area on the semiconductor substrate, wherein the third mask exposure field partially overlaps with the initial mask exposure field and the subsequent mask exposure field, so that the third OCM patterned during the exposure of the third mask exposure field is positioned within the single control module die, and the single control module die also includes the initial OCM patterned during the exposure of the initial mask exposure field and the subsequent OCM patterned during the exposure of the subsequent mask exposure field.

[0026] In one or more embodiments, the method further includes exposing a fourth mask exposure field on the surface of the semiconductor substrate via the mask to pattern a fourth array region and a fourth edge region on the semiconductor substrate, wherein the fourth mask exposure field partially overlaps with the initial mask exposure field, the subsequent mask exposure field, and the third mask exposure field, so that the fourth OCM patterned during the exposure of the fourth mask exposure field is positioned within the single control module die, and the single control module die also includes the initial OCM patterned during the exposure of the initial mask exposure field, the subsequent OCM patterned during the exposure of the subsequent mask exposure field, and the third OCM patterned during the exposure of the third mask exposure field.

[0027] In one or more embodiments, the control module die further includes patterning representing at least one process control module (PCM), and further wherein the single control module die includes a corresponding PCM, and the corresponding PCM is patterned only during one of the exposing the initial mask exposure field, the exposing the subsequent mask exposure field, the exposing the third mask exposure field, and the exposing the fourth mask exposure field.

[0028] In one or more embodiments, (i) two of the second OCM patterned during the exposing the initial mask exposure field, the third OCM patterned during the exposing the initial mask exposure field, and the fourth OCM patterned during the exposing the initial mask exposure field are outside the second mask exposure field; and

[0029] (ii) two of the first OCM patterned during the exposing the subsequent reticle exposure field, the third OCM patterned during the exposing the subsequent reticle exposure field, and the fourth OCM patterned during the exposing the subsequent reticle exposure field are outside the first reticle exposure field.

[0030] In one or more embodiments, the method further includes dividing the semiconductor substrate into a plurality of different integrated circuit devices.

[0031] In one or more embodiments, the method further includes packaging the plurality of different integrated circuit devices to define a plurality of different packaged electronic devices.

[0032] According to a second aspect of the present invention, there is provided a mask, the mask being configured to be used in a lithography system to pattern device layers of a corresponding plurality of integrated circuit devices on a semiconductor substrate, the mask comprising:

[0033] an array region, the array region comprising a pattern representing the device layer, wherein

[0034] (i) within the array region, the patterning representing the device layers is arranged in a two-dimensional grid, the two-dimensional grid including scribe lines separating adjacent device layers of adjacent integrated circuit devices of the plurality of integrated circuit devices; and

[0035] (ii) the array region includes a control module die, the control module die including patterning representing a first optical control module (OCM); and

[0036] an edge region outside the array region and extending along at least two adjacent sides of the array region, wherein the edge region includes

[0037] (i) represents the patterning of the second OCM;

[0038] (ii) represents patterning of a third OCM; and

[0039] (iii) shows the patterning of the fourth OCM.

[0040] In one or more embodiments, the array region further includes a pattern representing a process control module (PCM).

[0041] In one or more embodiments, the first OCM, the second OCM, the third OCM and the fourth OCM are arranged relative to each other on the mask so that when four adjacent mask exposure fields of the mask are patterned on the semiconductor substrate using the lithography system, the initial OCM formed by the initial exposure, the subsequent OCM formed by the subsequent exposure, the third OCM formed by the third exposure, and the fourth OCM formed by the fourth exposure are positioned within a single control module die.

[0042] In one or more embodiments, the array area is a rectangular array area forming four corners, wherein:

[0043] (i) the first OCM is within the rectangular array area and close to a first corner of the four corners;

[0044] (ii) the second OCM is outside the rectangular array area and close to a second corner of the four corners;

[0045] (iii) the third OCM is outside the rectangular array area and close to a third corner of the four corners; and

[0046] (iv) The fourth OCM is outside the rectangular array area and close to a fourth corner of the four corners.

[0047] In one or more embodiments, the array area is a rectangular array area forming four corners, wherein each of the first OCM, the second OCM, the third OCM and the fourth OCM is close to a corresponding corner of the four corners, and further wherein the distance between each OCM and the corresponding corner is different for each OCM.

[0048] In one or more embodiments, the first OCM, the second OCM, the third OCM, and the fourth OCM are all positioned outside the scribe line.

[0049] According to a third aspect of the present invention, there is provided a semiconductor substrate, comprising:

[0050] a plurality of integrated circuit devices arranged in a die array on a surface of the semiconductor substrate;

[0051] a plurality of scribe lines separating adjacent integrated circuit devices of the plurality of integrated circuit devices; and

[0052] a plurality of control module dies, the plurality of control module dies being spaced apart within the die array, wherein

[0053] (i) each of the plurality of control module dies comprises a first optical control module (OCM), a second OCM, a third OCM, and a fourth OCM;

[0054] (ii) the array of dies forms a repeating pattern formed by a plurality of partially overlapping reticle exposure fields; and

[0055] (iii) each of the plurality of partially overlapping reticle exposure fields includes a respective first OCM, a respective second OCM, a respective third OCM, and a respective fourth OCM positioned within a different one of the plurality of control module dies.

[0056] In one or more embodiments, the multiple partially overlapping mask exposure fields include a first rectangular mask exposure field, a second rectangular mask exposure field partially overlapping the first rectangular mask exposure field, a third rectangular mask exposure field partially overlapping the first rectangular mask exposure field and the second rectangular mask exposure field, and a fourth rectangular mask exposure field partially overlapping the first rectangular mask exposure field, the second rectangular mask exposure field, and the third rectangular mask exposure field.

[0057] In one or more embodiments, the first rectangular mask exposure field, the second rectangular mask exposure field, the third rectangular mask exposure field and the fourth rectangular mask exposure field all overlap within an overlapping region forming the first OCM, the second OCM, the third OCM and the fourth OCM.

[0058] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like references indicate similar elements. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0060] Figure 1 is a schematic diagram of an example of a semiconductor substrate that may include a plurality of optical control modules according to the present disclosure.

[0061] Figure 2 FIG. 4 is a schematic diagram of an example in which four adjacent mask exposure fields can be formed on a semiconductor substrate according to the present disclosure.

[0062] Figure 3 is a schematic diagram of an example of a mask that can be used to pattern a semiconductor substrate according to the present disclosure.

[0063] Figure 4 is a schematic diagram of an example of relative orientation between multiple optical control modules according to the present disclosure.

[0064] Figure 5 is a schematic diagram of an example of relative orientation between multiple optical control modules according to the present disclosure.

[0065] Figure 6 is a schematic diagram of an example of relative orientation between multiple optical control modules according to the present disclosure.

[0066] Figure 7 is a flow chart depicting a method of forming a plurality of integrated circuit devices on a surface of a semiconductor substrate according to the present disclosure.

[0067] Figure 8 yes Figure 7 A schematic diagram of an example of a portion of a method.

[0068] Fig. 9 yes Figure 7 A schematic diagram of an example of a portion of a method.

[0069] Fig.10 yes Figure 7 A schematic diagram of an example of a portion of a method.

[0070] Fig.11 yes Figure 7 A schematic diagram of an example of a portion of a method. DETAILED DESCRIPTION

[0071] A semiconductor substrate or mask according to the present disclosure includes an optical control module (OCM) arranged within a given mask exposure field so that when four adjacent mask exposure fields are patterned on the surface of the semiconductor substrate, the corresponding OCM formed by each of the four adjacent mask exposure fields is positioned within a single control module die. In some embodiments, the four adjacent mask exposure fields overlap each other so that the corresponding OCM from each mask exposure field is positioned within a single control module die. In some embodiments, the mask according to the present disclosure may include only a single circuit die or circuit die position including an OCM, and the other OCMs patterned by the mask are positioned outside the die array defined by the mask. Such a semiconductor substrate or mask and a method of forming a semiconductor substrate or using a mask can increase the total number of integrated circuit devices formed on a given semiconductor substrate. This can reduce the process overhead experienced during the manufacture of the integrated circuit device or can reduce the manufacturing cost. This is particularly true when compared to a conventional semiconductor substrate or mask in which the four dies or die positions of each mask exposure field include an OCM.

[0072] Figure 1 is a schematic diagram of an example of a semiconductor substrate 10 that may include a plurality of optical control modules 60 according to the present disclosure. Figure 2 is a more detailed but still schematic illustration of an example of four adjacent mask exposure fields 70 that may be formed on a semiconductor substrate 10 according to the present disclosure. Figure 1-Figure 2 As shown, the semiconductor substrate 10 includes a plurality of integrated circuit devices 22 arranged into a die array 20 on a surface 12 of the semiconductor substrate. The semiconductor substrate 10 also includes a plurality of scribe lines 30, and the scribe lines 30 separate adjacent integrated circuit devices 22. The semiconductor substrate 10 further includes a plurality of control module dies 40 spaced apart within the die array 20. The control module dies 40 include an optical control module (OCM) 60, and may also include a process control module (PCM) 50.

[0073] like Figure 2 As shown in the central control module die 40, each control module die includes a first OCM 61, a second OCM 62, a third OCM 63 and a fourth OCM 64. Figure 2 As shown in , the die array 20 forms a repeating pattern formed by a plurality of partially overlapping mask exposure fields 70. It should be understood that the integrated circuit device 22 includes a plurality of individual device layers; and in this context, Figure 2The reticle exposure field 70 shown in FIG. 7 may be a reticle exposure field associated with or used to form a single device layer of an integrated circuit device.

[0074] exist Figure 2 In the example of , mask exposure field 70 includes first or initial mask exposure field 71, second or subsequent mask exposure field 72, third mask exposure field 73, or fourth mask exposure field 74. First mask exposure field 71 may also be referred to herein as or may be first rectangular mask exposure field 71, and second mask exposure field 72 may also be referred to herein as or may be second rectangular mask exposure field 72. Similarly, third mask exposure field 73 may also be referred to herein as or may be third rectangular mask exposure field 73, and fourth mask exposure field 74 may also be referred to herein as or may be fourth rectangular mask exposure field 74.

[0075] As shown, first reticle exposure field 71 partially overlaps with second reticle exposure field 72 along one side, and partially overlaps with third reticle exposure field 73 along an adjacent side. Similarly, second reticle exposure field 72 partially overlaps with first reticle exposure field 71 along one side, and partially overlaps with fourth reticle exposure field 74 along an adjacent side. In addition, third reticle exposure field 73 partially overlaps with first reticle exposure field 71 along one side, and partially overlaps with fourth reticle exposure field 74 along an adjacent side. Similarly, fourth reticle exposure field 74 partially overlaps with second reticle exposure field 72 along one side, and partially overlaps with third reticle exposure field 73 along an adjacent side. In addition, first reticle exposure field 71, second reticle exposure field 72, third reticle exposure field 73, and fourth reticle exposure field 74 all overlap with each other within overlap region 76.

[0076] For simplicity, Figure 2 Only four mask exposure fields 70 are shown. On a patterned or fully patterned semiconductor substrate 10, Figure 2 The reticle exposure field 70 shown in FIG. 7 may be at least partially or even completely surrounded by other similar or identical reticle exposure fields 70 .

[0077] exist Figure 2 In the figure, the structure formed by the first mask exposure field 71 (e.g., integrated circuit device 22, PCM 50, or OCM 60) is shown without shading, while the structure formed by the second mask exposure field 72 is shown with dashed shading. In addition, the structure formed by the third mask exposure field 73 is shown with horizontal line shading, and the structure formed by the fourth mask exposure field 74 is shown with horizontal dashed shading.

[0078] Continue to refer Figure 2, each mask exposure field 70 includes a corresponding first OCM 61, a corresponding second OCM 62, a corresponding third OCM 63, and a corresponding fourth OCM 64. The corresponding first OCM, the corresponding second OCM, the corresponding third OCM, and the corresponding fourth OCM formed by a given mask exposure field 70 are positioned in different control module dies 40, so that a given control module die 40 includes four optical control modules 60, and each optical control module 60 within a given control module die 40 is formed by a different mask exposure field 70.

[0079] Reference Figure 2 In the central control module die 41 shown in the specific example of FIG. 4 , the first OCM 61 shown with dashed filling can be formed by the second mask exposure field 72; the second OCM 62 shown with horizontal dashed shading can be formed by the fourth mask exposure field 74. Similarly, the third OCM 63 shown with horizontal shading can be formed by the third mask exposure field 73; and the fourth OCM 64 shown without shading can be formed by the first mask exposure field 71.

[0080] As shown and discussed, the reticle exposure fields 70 overlap each other within the overlap region 76, thereby allowing the respective first OCM, second OCM, third OCM, and fourth OCM patterned by different reticle exposure fields to be positioned on the same control module die (i.e., Figure 2 As shown in the figure, each mask exposure field 70 also includes a non-overlapping area 78 that does not overlap with other mask exposure fields 70.

[0081] The above-described relative configuration or relative orientation of OCM 60 within a given reticle exposure field 70, and the overlap between adjacent reticle exposure fields 70, can allow reticle exposure fields 70 to be aligned or relatively aligned with each other without utilizing or sacrificing four integrated circuit device locations within die array 20 as control module die 40. Utilizing the above-described relative configuration or relative orientation, OCM 60 can allow each reticle exposure field 70 to include four different OCMs 60 (e.g., first OCM 61, second OCM 62, third OCM 63, and fourth OCM 64) adjacent to the four corners of the reticle exposure field without incorporating all four OCMs into separate or dedicated integrated circuit device locations within the die array.

[0082] Therefore, compared with the semiconductor substrate of the prior art that uses the four corner die positions of the corresponding die array as the control module die, the semiconductor substrate 10 according to some embodiments of the present disclosure can produce a greater number of integrated circuit devices 22. Additionally or alternatively, since all OCMs 60 are outside the scribe lines 30, outside the scribe lines 30, or not positioned within the scribe lines 30, the semiconductor substrate 10 according to some embodiments of the present disclosure can be, can be more accurately, or can be more easily separated using die separation technology compared to the semiconductor substrate of the prior art that positions the corresponding optical control module within the corresponding scribe lines. This is especially true when using laser scribing die separation technology, because such die separation technology may be sensitive to optical reflective structures within the scribe lines.

[0083] The optical control module 60 may include any suitable structure that may be used to orient or align the reticle exposure fields 70 with the semiconductor substrate 10, or to orient or align the reticle exposure fields 70 with each other during the formation or patterning of the integrated circuit device 22 on the semiconductor substrate 10. For example, the optical control module 60 may include a structure that may be used to automatically align the reticle during the process of manufacturing the integrated circuit device 22 on the semiconductor substrate 10.

[0084] An example of an optical control module 60 includes a rectangular interference field that can be detected by the naked eye or by a computer-aided detection device and is used for mask adjustment or layer thickness testing. As a more specific example, the optical control module 60 may include a square, rectangular or cross-shaped field that can be automatically detected by a stepper using a mask. These fields may also be referred to as interference fields in this article. As an example, automatic alignment using an optical control module can be achieved by passing a low-energy laser beam through the alignment marks on the mask and reflecting them away from the corresponding alignment marks on the wafer substrate (i.e., the optical control module). The optical control module may have a three-dimensional structure so that it can be used for each exposure step during the manufacture of the integrated circuit device 22. Such a three-dimensional structure can allow or facilitate interlayer alignment between individual or vertically stacked layers of the integrated circuit device.

[0085] As discussed, the control module die 40 may include the PCM 50. The PCM 50 may be formed or defined by a single reticle exposure field 70. As an example, and as discussed, the first reticle exposure field 71 may be formed in Figure 2 The PCM 50 is not shown in the shadow, and the second mask exposure field 72 can be formed in Figure 2 The PCM 50 shown by the dashed line in FIG. 1 , the third mask exposure field 73 may be formed at Figure 2 The PCM 50 shown with horizontal line hatching in FIG. 1 and the fourth mask exposure field 74 may be formed in Figure 25 . In one embodiment, each reticle exposure field 70 may form a corresponding PCM 50 of a corresponding control module die 40 or a corresponding PCM 50 of a single corresponding control module die 40. In another embodiment, the entirety of a given PCM 50 may be formed by a single reticle exposure field 70. However, other embodiments may not include these features.

[0086] PCM 50 may include any suitable structure that may be used to monitor the manufacturing process of integrated circuit device 22. Examples of PCM 50 include: an electrical test structure that indicates one or more electrical properties indicative of the manufacturing process of integrated circuit device 22; a film property test structure that indicates one or more film properties indicative of the manufacturing process of integrated circuit device 22; or a lithography test structure that indicates one or more lithography properties indicative of the manufacturing process of integrated circuit device 22. More specific examples of PCM 50 include an electrical test circuit, a film thickness test region, a film quality test region, or a critical dimension test region.

[0087] Integrated circuit device 22 may include any suitable structure that may be formed on semiconductor substrate 10. Additionally or alternatively, integrated circuit device 22 may include any suitable structure that may be segmented or separated via cutting semiconductor substrate 10 along scribe lines 30 to produce individual chips or dies that may include processors, memories, transistors, optoelectronic devices, logic elements, circuit elements, digital electronic devices, analog electronic devices, or any other suitable semiconductor-based devices.

[0088] The semiconductor substrate 10 may include any suitable semiconductor substrate. Examples of the semiconductor substrate 10 include a silicon substrate, a germanium arsenide substrate, a gallium nitride, or a III-V semiconductor substrate.

[0089] Figure 3 According to the present disclosure, it is possible to pattern a semiconductor substrate (e.g. Figure 1-Figure 2 Schematic diagram of an example of a mask 100 for a semiconductor substrate 10). The mask 100 can be used with or within a lithography system 98 to pattern a plurality of integrated circuit devices on a semiconductor substrate, such as Figure 1-Figure 2 An integrated circuit device 22. Figure 3 Reticle 100 is shown within a field of view 190 of lens 180 of lithography system 98 .

[0090] The mask 100 includes an array region 110 and an edge region 140. The array region 110 includes a pattern 112 of a device layer 118 representing a plurality of integrated circuit devices. Within the array region 110, the pattern 112 is arranged into a two-dimensional grid 114, which includes scribe lines 116 separating adjacent device layers 118. The scribe lines 116 may be horizontal or vertical. The two-dimensional grid may also be referred to herein as a lattice field, an array, or a plurality of rows and columns. The horizontal scribe lines may be equidistant from one another and may extend parallel to the rows. Similarly, the vertical scribe lines may be equidistant from one another and may extend parallel to the columns. The array region also includes a pattern representing a control module die 120, which may also be referred to herein as a control module die 120. The control module die 120 includes a pattern representing a first optical control module (OCM) 160, as shown at 161. Examples of optical control modules are disclosed herein.

[0091] Edge region 140 is outside of array region 110, such that edge region 140 is outside or external to device layer 118 and is also outside or external to scribe line 116. Edge region 140 extends along at least two adjacent sides of array region 110 and includes patterning representing second OCM 160 as shown at 162, patterning representing third OCM 160 as shown at 163, and patterning representing fourth OCM 160 as shown at 164.

[0092] As discussed in greater detail herein, the patterns representing OCM 160 are arranged or have relative spacing such that when four adjacent reticle exposure fields 102 are patterned on the surface of the substrate, the first OCM, the second OCM, the third OCM, and the fourth OCM are all patterned within a corresponding or single control module die. Even if reticle 100 or a single reticle exposure field formed therefrom only includes a pattern representing a single OCM 160 within a pattern representing a control module die 120, as shown in FIG. Figure 3 . The patterning representing the first OCM, the patterning representing the second OCM, the patterning representing the third OCM, and the patterning representing the fourth OCM can be arranged on the mask 100 and relative to each other so that the first OCM formed by the first exposure, the second OCM formed by the second exposure, the third OCM formed by the third exposure, and the fourth OCM formed by the fourth exposure are all positioned within a single control module die. Such a configuration can reduce the total portion of die locations within the two-dimensional grid 114 that includes the patterning representing the control module die 120, thereby increasing the number of integrated circuit devices that can be formed on a given substrate, as described herein.

[0093] The array area 110 may be a rectangular array area 110 that forms or defines four corners 111. In such a configuration, each OCM 160 may be close to a corresponding corner 111 of the array area. However, the distance or average distance between each OCM 160 and the corresponding corner may be different for each OCM. Such a configuration may allow or facilitate relative orientation of four OCMs 160 within a single control module die 120 when patterning four adjacent reticle exposure fields on a semiconductor substrate, as discussed herein.

[0094] As a specific example, and with continued reference to Figure 3 , indicating that the patterning of the first OCM 161 may be within the rectangular array area and near the first corner 111 of the four corners. In contrast, indicating that the patterning of the second OCM 162 may be outside the rectangular array area and near the second corner 111 of the four corners; indicating that the patterning of the third OCM 163 may be outside the rectangular array area and near the third corner 111 of the four corners; and indicating that the patterning of the fourth OCM 164 may be outside the rectangular array area and near the fourth corner 111 of the four corners. The first corner, the second corner, the third corner, and the fourth corner are different corners of the rectangular array area.

[0095] In the context of the spatial relationship between OCMs 160 or between OCMs 160 and corresponding corners 111, the term "close to" may refer to the relative distance between a given OCM 160 and the corresponding corner 111 when compared to the distance between the given OCM and another corner 111. As a more specific example, device layer 118 may have a maximum dimension 119, and each OCM 160 may be closer to the corresponding corner 111 than the maximum dimension 119, but may be closer to the other corners 111 than the maximum dimension.

[0096] like Figure 3 As shown in , the array area 110 may include a pattern representing a process control module (PCM) 150. As shown, the pattern representing the process control module 150 may be positioned within the control module die 120. Additionally, one or more other locations or die locations within the two-dimensional grid 114 may include a pattern representing the process control module 150. Examples of process control modules are disclosed.

[0097] As used herein, the phrase "represented patterning" may refer to a pattern, structure, template, or mark that may be defined by a combination of optically opaque areas and optically transparent areas on the mask 100. When the mask is used within a lithography system, or when electromagnetic radiation is irradiated onto a substrate through the mask, the patterning projects an image of the device layer 118, an image of the control module die 120, an image of the PCM 150, and an image of the OCM 160 onto the substrate. Such a patterning may also be referred to herein as a corresponding patterning or a defined patterning.

[0098] Figure 4-Figure 6 is a schematic diagram of an example of relative orientation between a plurality of OCMs 60 that may be formed on a semiconductor substrate 10 according to the present disclosure. Figure 4-Figure 6 Shown can be incorporated into Figure 1-Figure 2 The relative arrangement of the OCM 60 in the semiconductor substrate 10 is changed. Figure 4-Figure 6 The OCM 60 is shown in the case of being patterned on the semiconductor substrate 10, but those skilled in the art will understand that Figure 3 Similar relative orientations of the patterning of OCM 160 on mask 100 are also within the scope of the present disclosure. Figure 4-Figure 6 The examples of are merely examples, and any relative arrangement of four OCMs 60 within a single control module die 40, wherein each OCM 60 is formed by a different reticle exposure field, is also within the scope of the present disclosure.

[0099] like Figure 4 As shown in FIG. 1 , OCMs 60 may be arranged adjacent to or in contact with each other and arranged in a row. Figure 5 As shown in , the OCMs 60 may be arranged adjacent to or in contact with each other and arranged in a rectangle or square, wherein each OCM 60 forms a respective corner or quadrant of the rectangle or square. Figure 6 As shown in , the OCMs 60 may be spaced apart from one another, or may define respective corners of the control module die 40 .

[0100] Figure 7 is a flow chart depicting a method 200 of fabricating an integrated circuit device according to the present disclosure. Figure 8-Figure 11 yes Figure 72 is a schematic diagram of an example of a portion of a method of . Method 200 may include coating a surface of a semiconductor substrate with a photoresist layer at 210, and includes positioning a mask and a semiconductor substrate at 220. Method 200 also includes exposing an initial mask exposure field at 230, and may include repositioning the mask and the semiconductor substrate at 240. Method 200 additionally includes exposing subsequent mask exposure fields at 250, and may include exposing a third mask exposure field at 260, exposing a fourth mask exposure field at 270, or developing the photoresist layer at 280. Method 200 may also include performing additional processing at 290 or repeating at least a portion of the method at 295.

[0101] Coating the surface of the semiconductor substrate with a photoresist layer at 210 may include coating the surface of the semiconductor substrate with any suitable photoresist layer in any suitable manner. As an example, coating at 210 may include spin coating the surface of the semiconductor substrate with the photoresist layer. Examples of photoresist layers include negative photoresist layers and positive photoresist layers. Coating at 210 may be performed at any suitable timing or sequence during method 200. As an example, coating at 210 may be performed before positioning at 220 or before exposure at 230. Reference is made herein to Figure 1-Figure 2 and Figure 4-Figure 6 An example of a semiconductor substrate is disclosed in the semiconductor substrate 10 .

[0102] Positioning the reticle and the semiconductor substrate at 220 may include positioning or locating the reticle and the semiconductor substrate relative to each other so that during exposure at 230, the initial reticle exposure field is positioned at a predetermined or desired location on the surface of the semiconductor substrate. Positioning at 220 may be performed with, via, or utilizing a lithography system such as a stepper, and may include moving the reticle relative to the semiconductor substrate or moving the semiconductor substrate relative to the reticle. Figure 3 An example of a mask is disclosed in the mask 100 .

[0103] Exposing the initial mask exposure field at 230 may include exposing the initial mask exposure field on the surface of the semiconductor substrate via the mask. As discussed herein, the mask may include an array region and an edge region. The array region may include patterning representing device layers of a plurality of integrated circuit devices and arranged into a two-dimensional grid, the two-dimensional grid including scribe lines separating adjacent device layers of adjacent integrated circuit devices of the plurality of integrated circuit devices. The array region may also include a control module die including patterning of a first optical control module (OCM) representing a device layer. As also discussed herein, the edge region is outside the array region and includes patterning of a second OCM representing a device layer, patterning of a third OCM representing a device layer, and patterning of a fourth OCM representing a device layer. With this in mind, the exposure at 230 may include exposing on the semiconductor substrate to pattern, form, or define an initial array region and an initial edge region. In this document, reference is made to Figure 3 The reticle 100 discloses examples of array regions and edge regions.

[0104] Figure 8 2 shows the exposure at 230. As shown therein, the initial mask exposure field 70 or the first mask exposure field 70 indicated at 71 and shown in dashed lines can expose, form or define the corresponding array region 80 and the corresponding edge region 90 on the surface of the semiconductor substrate 10. The exposure at 230 may also be referred to herein as the initial exposure.

[0105] Repositioning the reticle and the semiconductor substrate at 240 may include repositioning so that a subsequent reticle exposure field exposed during the exposure at 250 is positioned at a predetermined or desired location on the surface of the semiconductor substrate adjacent to the initial reticle exposure field. The repositioning at 240 may be performed with, via, or using a photolithography system, and may include moving the reticle relative to the semiconductor substrate or moving the semiconductor substrate relative to the reticle. Additionally or alternatively, the repositioning at 240 may include aligning the subsequent reticle exposure field with the initial reticle exposure field using the first OCM, the second OCM, the third OCM, or the fourth OCM patterned during the exposure at 230.

[0106] Exposing the subsequent reticle exposure fields at 250 may include exposing the subsequent reticle exposure fields on the surface of the semiconductor substrate via the reticle. This may include exposing on the semiconductor substrate to pattern, form, or define subsequent array regions and subsequent edge regions. The exposing at 250 may include exposing such that the subsequent reticle exposure fields partially overlap the initial reticle exposure fields, or such that the initial OCM patterned during the exposure of the initial reticle exposure fields and the subsequent OCM patterned during the exposure of the subsequent reticle exposure fields are both positioned within the same control module die or within a single control module die.

[0107] As discussed, the exposure at 250 includes exposing such that a subsequent reticle exposure field overlaps or at least partially overlaps with an initial reticle exposure field. As an example, at least one or even two of a first OCM patterned during the exposure of the initial reticle exposure field, a second OCM patterned during the exposure of the initial reticle exposure field, a third OCM patterned during the exposure of the initial reticle exposure field, and a fourth OCM patterned during the exposure of the initial reticle exposure field can be at least partially or even completely positioned within the subsequent reticle exposure field. Similarly, at least one or even two of a first OCM patterned during the exposure of the subsequent reticle exposure field, a second OCM patterned during the exposure of the subsequent reticle exposure field, a third OCM patterned during the exposure of the subsequent reticle exposure field, and a fourth OCM patterned during the exposure of the subsequent reticle exposure field can be at least partially or even completely positioned within the initial reticle exposure field.

[0108] Additionally or alternatively, at least one or even two of the first OCM patterned during the exposure of the initial mask exposure field, the second OCM patterned during the exposure of the initial mask exposure field, the third OCM patterned during the exposure of the initial mask exposure field, and the fourth OCM patterned during the exposure of the initial mask exposure field can be at least partially or even completely positioned outside the subsequent mask exposure field. Similarly, at least one or even two of the first OCM patterned during the exposure of the subsequent mask exposure field, the second OCM patterned during the exposure of the subsequent mask exposure field, the third OCM patterned during the exposure of the subsequent mask exposure field, and the fourth OCM patterned during the exposure of the subsequent mask exposure field can be at least partially or even completely positioned outside the initial mask exposure field.

[0109] Fig. 9, the exposure at 250 is shown. As shown therein, the subsequent reticle exposure field 70 or second reticle exposure field 70 indicated at 72 and shown in dashed lines can expose, form or define a corresponding array region 80 and a corresponding edge region 90 on the surface of the semiconductor substrate 10. Also as shown therein, the initial OCM 60 indicated at 91 and patterned during the exposure at 230 is within a single control module die 40, which also includes a subsequent OCM 60 indicated at 92 and patterned during the exposure at 250. The exposure at 250 may also be referred to herein as a subsequent exposure.

[0110] After the exposure at 250 and before the exposure at 260, method 200 may include repeating the repositioning at 240. This may include repeating such that the third reticle exposure field exposed during the exposure at 260 is positioned at a predetermined or desired location on the surface of the semiconductor substrate adjacent to a subsequent reticle exposure field, adjacent to an initial reticle exposure field, or partially overlapping the initial reticle exposure field and a subsequent reticle exposure field.

[0111] Exposing the third reticle exposure field at 260 may include exposing the third reticle exposure field to the surface of the semiconductor substrate via the reticle. This may include exposing on the semiconductor substrate to pattern, form or define a third array region and a third edge region. The exposing at 260 may include exposing so that the third reticle exposure field partially overlaps with the initial reticle exposure field and the subsequent reticle exposure field. Additionally or alternatively, the exposing at 260 may include exposing so that the initial OCM patterned during the exposure of the initial reticle exposure field, the subsequent OCM patterned during the exposure of the subsequent reticle exposure field, and the third OCM patterned during the exposure of the third reticle exposure field are all positioned within the same control module die or within a single control module die.

[0112] Fig.10 , the exposure at 260 is shown. As shown therein, the third mask exposure field 70 indicated at 73 and shown in dashed lines can expose, form or define a corresponding array region 80 and a corresponding edge region 90 on the surface of the semiconductor substrate 10. Also as shown therein, the third OCM 60 indicated at 93 and patterned during the exposure at 260 is within a single control module die that also includes an initial OCM 91 and a subsequent OCM 92. The exposure at 260 may also be referred to herein as a third exposure.

[0113] After the exposure at 260 and before the exposure at 270, method 200 may include repeating the repositioning at 240. This may include repeating such that the fourth reticle exposure field exposed during the exposure at 270 is positioned at a predetermined or desired location on the surface of the semiconductor substrate adjacent to a subsequent reticle exposure field, adjacent to an initial reticle exposure field, adjacent to a third reticle exposure field, or partially overlapping the initial reticle exposure field, the subsequent reticle exposure field, and the third reticle exposure field.

[0114] Exposing the fourth reticle exposure field at 270 may include exposing the fourth reticle exposure field to the surface of the semiconductor substrate via the reticle. This may include exposing on the semiconductor substrate to pattern, form or define a fourth array region and a fourth edge region. The exposing at 270 may include exposing so that the fourth reticle exposure field partially overlaps with the initial reticle exposure field, the subsequent reticle exposure field, and the third reticle exposure field. Additionally or alternatively, the exposing at 270 may include exposing so that the initial OCM patterned during the exposure of the initial reticle exposure field, the subsequent OCM patterned during the exposure of the subsequent reticle exposure field, the third OCM patterned during the exposure of the third reticle exposure field, and the fourth OCM patterned during the exposure of the fourth reticle exposure field are all positioned within the same control module die or within a single control module die.

[0115] Fig.11 , the exposure at 270 is shown. As shown therein, the fourth mask exposure field 70 indicated at 74 and shown in dashed lines can expose, form or define a corresponding array region 80 and a corresponding edge region 90 on the surface of the semiconductor substrate 10. Also as shown therein, the fourth OCM 60 indicated at 94 and patterned during the exposure at 270 is within a single control module die that also includes an initial OCM 91, a subsequent OCM 92, and a third OCM 93. The exposure at 280 may also be referred to herein as a fourth exposure.

[0116] like Figure 8-Figure 11 As shown, the control module die of the mask may also include patterning representing at least one process control module (PCM). Under these conditions, a single control module die may also include a corresponding PCM, such as Figure 8-Figure 11 50. The corresponding PCM included in the single control module die may be patterned during only one of the exposure at 230, the exposure at 250, the exposure at 260, and the exposure at 270.

[0117] The method 200 disclosed herein is performed with exposing an initial reticle exposure field at 230, exposing a subsequent reticle exposure field at 250, exposing a third reticle exposure field at 260, and exposing a fourth reticle exposure field at 270. The adjectives initial, subsequent, third, and fourth are used for convenience, and the exposing at 230, the exposing at 250, the exposing at 260, and the exposing at 270 may be performed in any suitable order or sequence within the scope of embodiments of the present invention.

[0118] Developing the photoresist layer at 280 may include developing to form or define a photoresist pattern on the surface of the semiconductor substrate. Developing at 280 may include removing or dissolving regions of the photoresist layer to form a pattern, wherein the regions of the photoresist layer are defined based on the exposure at 230, the exposure at 250, the exposure at 260, or the exposure at 270.

[0119] Performing additional processing at 290 may include performing any suitable additional or conventional processing of or on the semiconductor substrate to form, define, or fabricate an integrated circuit device. As an example, the mask may be a first mask including a first array region and a first edge region, and the photoresist layer may be a first photoresist layer. In this example, and after development at 280, performing at 290 may include defining a device layer of a plurality of integrated circuit devices on the semiconductor substrate. As an example, the device layer may be defined by etching or implanting the semiconductor substrate using the first photoresist layer as a mask or template.

[0120] The performing at 290 may also include removing the photoresist pattern from the semiconductor substrate. The photoresist pattern may be removed from the semiconductor substrate after defining the device layer, for example, by dissolving or burning away the photoresist pattern.

[0121] Repeating at least a portion of method 200 at 295 may include repeating any suitable portion of method 200 in any suitable order. As an example, after performing at 290, repeating at 295 may include repeating coating at 210 to coat the surface of the semiconductor substrate with a second photoresist layer.

[0122] As another example, the repeating at 295 may include repeating the positioning at 220, repeating the exposing at 230, and repeating the exposing at 250 with or using a second reticle including a second array region and a second edge region. The second reticle may be different from the first reticle. The second reticle may include a corresponding first OCM, a corresponding second OCM, a corresponding third OCM, and a corresponding fourth OCM.

[0123] During the exposure at repeat 250, the repeat at 295 may include aligning the first OCM, the second OCM, the third OCM, and the fourth OCM of the subsequent reticle exposure field exposed via the second reticle with the first OCM, the second OCM, the third OCM, and the fourth OCM of the subsequent reticle exposure field exposed via the first reticle. Such an approach may provide inter-layer alignment between the subsequent reticle exposure fields defined by the first reticle and the subsequent reticle exposure fields defined by the second reticle.

[0124] The execution at 290 and the repetition at 295 may be performed any suitable number of times to form or define any suitable number of layers of the plurality of integrated circuit devices. After forming all or all desired layers of the plurality of integrated circuit devices, the execution at 290 may further include segmenting the plurality of integrated circuit devices, for example, to define a plurality of different integrated circuit devices. This may include dicing the substrate using die separation techniques, examples of which are disclosed herein.

[0125] After segmentation, execution at 290 may include packaging the plurality of different integrated circuit devices to form a plurality of different packaged integrated circuit devices, or implementing one or more of the plurality of packaged integrated circuit devices into an electronic system. Examples of integrated circuit devices include processors, digital devices, analog devices, memory devices, sensors, programmable logic devices, or discrete devices.

[0126] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the appended claims. For example, and as discussed, OCM 60 may have any suitable location within control module die 40. As another example, the first, second, third, and fourth labels of OCM 60 defined by a given mask exposure field 70 are used arbitrarily and are not intended to represent a specific order or sequence of OCM 60. Similarly, the initial, subsequent, third, and fourth labels for mask exposure fields 70 are used arbitrarily and are not intended to represent a specific order or sequence of defining or locating mask exposure fields. Therefore, the description and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems described herein with respect to specific embodiments are not intended to be construed as key, required, or essential features or elements of any claim.

[0127] Unless otherwise specified, terms such as "first," "second," "third," and "fourth" are used to arbitrarily distinguish the elements these terms describe. Therefore, these terms are not necessarily intended to indicate temporal, spatial, or other priorities of these elements.

[0128] As used herein, the terms "suitable for" and "configured" mean that an element, component, or other subject matter is designed or intended to perform a given function. Therefore, the use of the terms "suitable for" and "configured" should not be interpreted as meaning that a given element, component, or other subject matter is only "capable of" performing a given function, but rather that the element, component, or other subject matter is specifically selected, created, implemented, used, programmed, or designed for the purpose of performing the function. Within the scope of embodiments of the present invention, an element, component, or other described subject matter described as being suitable for performing a particular function may additionally or alternatively be described as being configured to perform that function, and vice versa.

[0129] As used herein, the phrase "for example," the phrase "as an example," and / or simply the term "example," when used with reference to one or more components, features, details, structures, embodiments, and / or methods according to the present disclosure, is intended to convey that the described components, features, details, structures, embodiments, and / or methods are illustrative, non-exclusive examples of components, features, details, structures, embodiments, and / or methods according to the present disclosure. Thus, the described components, features, details, structures, embodiments, and / or methods are not intended to be limiting, requiring, or exclusive / exhaustive; and other components, features, details, structures, embodiments, and / or methods, including components, features, details, structures, embodiments, and / or methods that are similar and / or equivalent in structure and / or function, are also within the scope of embodiments of the present invention.

[0130] The following are various embodiments of the present invention.

[0131] In a first embodiment, a method for manufacturing an integrated circuit device is provided. The method includes positioning a mask and a semiconductor substrate relative to each other. The mask includes an array region and an edge region. The array region includes patterning of device layers representing multiple integrated circuit devices. The array region is arranged into a two-dimensional grid, and the two-dimensional grid includes scribe lines that separate adjacent device layers of adjacent integrated circuit devices of the multiple integrated circuit devices. The array region includes a control module die, and the control module die includes patterning of a first optical control module (OCM) representing a device layer. The edge region is outside the array region. The edge region includes patterning of a second OCM representing a device layer, patterning of a third OCM representing a device layer, and patterning of a fourth OCM representing a device layer.

[0132] The method includes exposing an initial mask exposure field on a surface of a semiconductor substrate via a mask to pattern an initial array region and an initial edge region on the semiconductor substrate. The method includes exposing a subsequent mask exposure field on the surface of the semiconductor substrate via a mask to pattern a subsequent array region and a subsequent edge region on the semiconductor substrate. The subsequent mask exposure field partially overlaps the initial mask exposure field so that the initial OCM patterned during the exposure of the initial mask exposure field and the subsequent OCM patterned during the exposure of the subsequent mask exposure field are both positioned within a single control module die.

[0133] Exposing the initial reticle exposure field and exposing the subsequent reticle exposure field may include directing electromagnetic radiation, such as light, through the reticle and incident on a photoresist layer that may coat the surface of the semiconductor substrate to selectively expose the photoresist layer to the electromagnetic radiation. The method may include coating the surface of the semiconductor substrate with the photoresist layer before positioning the reticle and the semiconductor substrate relative to each other. The method may include developing the photoresist layer to form a photoresist pattern on the surface of the semiconductor substrate after exposing the initial reticle exposure field and exposing the subsequent reticle exposure field.

[0134] The reticle may be a first reticle, the array region may be a first array region, the edge region may be a first edge region, and the photoresist layer may be a first photoresist layer. The method may include defining a device layer of a plurality of integrated circuit devices on a semiconductor substrate. The method may include removing a photoresist pattern from the semiconductor substrate. The method may include coating a surface of the semiconductor substrate with a second photoresist layer. The method may include positioning a second reticle and the semiconductor substrate relative to each other. The method may include exposing an initial reticle field via the second reticle. The method may include exposing a subsequent reticle exposure field via the second reticle. The second reticle may include a second array region and a second edge region.

[0135] The method may include aligning the first OCM, second OCM, third OCM, and fourth OCM of an initial reticle exposure field exposed via the second reticle with the first OCM, second OCM, third OCM, and fourth OCM of the initial reticle exposure field exposed via the first reticle to provide inter-layer alignment of the initial reticle exposure field. The method may include aligning the first OCM, second OCM, third OCM, and fourth OCM of a subsequent reticle exposure field exposed via the second reticle with the first OCM, second OCM, third OCM, and fourth OCM of a subsequent reticle exposure field exposed via the first reticle to provide inter-layer alignment of the subsequent reticle exposure field.

[0136] The method may include exposing a third reticle exposure field on a surface of a semiconductor substrate via a reticle. Exposure of the third reticle exposure field may pattern a third array region and a third edge region on the semiconductor substrate. The third reticle exposure field may partially overlap with the initial reticle exposure field and the subsequent reticle exposure field. A third OCM may be patterned during exposure of the third reticle exposure field. The third OCM may be positioned within a single control module die that also includes an initial OCM patterned during exposure of the initial reticle exposure field and a subsequent OCM patterned during exposure of the subsequent reticle exposure field.

[0137] The method may include exposing a fourth reticle exposure field on a surface of a semiconductor substrate via a reticle. Exposure of the fourth reticle exposure field may pattern a fourth array region and a fourth edge region on the semiconductor substrate. The fourth reticle exposure field may overlap partially with the initial reticle exposure field, the subsequent reticle exposure field, and the third reticle exposure field. A fourth OCM may be patterned during exposure of the fourth reticle exposure field. The fourth OCM may be positioned within a single control module die, the single control module die also including an initial OCM patterned during exposure of the initial reticle exposure field, a subsequent OCM patterned during exposure of the subsequent reticle exposure field, and a third OCM patterned during exposure of the third reticle exposure field.

[0138] The control module die may include patterning representing at least one process control module (PCM). A single control module die may include a corresponding PCM. The corresponding PCM may be patterned during exposure of an initial reticle exposure field, during exposure of a subsequent reticle exposure field, during exposure of a third reticle exposure field, or during exposure of a fourth reticle exposure field.

[0139] Two of the following may be outside the second reticle exposure field: (1) a second OCM that may be patterned during exposure of an initial reticle exposure field, (2) a third OCM that may be patterned during exposure of an initial reticle exposure field, and (3) a fourth OCM that may be patterned during exposure of an initial reticle exposure field. Two of the following may be outside the first reticle exposure field: (1) a first OCM that may be patterned during exposure of a subsequent reticle exposure field, (2) a third OCM that may be patterned during exposure of a subsequent reticle exposure field, and (3) a fourth OCM that may be patterned during exposure of a subsequent reticle exposure field.

[0140] The method may include singulating the semiconductor substrate into a plurality of different integrated circuit devices. The method may include packaging the plurality of different integrated circuit devices to define a plurality of different packaged electronic devices.

[0141] In a second embodiment, a mask is provided. The mask is configured to be used in a lithography system to pattern device layers of a corresponding plurality of integrated circuit devices on a semiconductor substrate. The mask includes an array region. The array region includes patterning representing the device layers. Within the array region, the patterning representing the device layers is arranged into a two-dimensional grid. The two-dimensional grid includes scribe lines. The scribe lines separate adjacent device layers of adjacent integrated circuit devices of the plurality of integrated circuit devices. The array region includes a control module die. The control module die includes patterning representing a first optical control module (OCM).

[0142] The mask includes an edge region outside the array region. The edge region extends along at least two adjacent sides of the array region. The edge region includes a pattern representing the second OCM, a pattern representing the third OCM, and a pattern representing the fourth OCM.

[0143] The array area may additionally include patterning representing a process control module (PCM).

[0144] The first OCM, the second OCM, the third OCM and the fourth OCM can be arranged on the mask and opposite to each other, so that when four adjacent mask exposure fields of the mask are patterned on the semiconductor substrate using a lithography system, the initial OCM formed by the initial exposure, the subsequent OCM formed by the subsequent exposure, the third OCM formed by the third exposure, and the fourth OCM formed by the fourth exposure can be positioned within a single control module die.

[0145] The array area may be a rectangular array area forming four corners. The first OCM may be within the rectangular array area and close to a first corner of the four corners. The second OCM may be outside the rectangular array area and close to a second corner of the four corners. The third OCM may be outside the rectangular array area and close to a third corner of the four corners. The fourth OCM may be outside the rectangular array area and close to a fourth corner of the four corners. Each of the first OCM, the second OCM, the third OCM, and the fourth OCM may be close to a corresponding corner of the four corners. The distance between each OCM and the corresponding corner may be different for each OCM.

[0146] The first OCM, the second OCM, the third OCM, and the fourth OCM may all be positioned outside the scribe line.

[0147] In a third embodiment, a semiconductor substrate is provided. The semiconductor substrate includes a plurality of integrated circuit devices. The plurality of integrated circuit devices are arranged in a die array on a surface of the semiconductor substrate. The semiconductor substrate includes a plurality of scribe lines. The plurality of scribe lines separate adjacent integrated circuit devices of the plurality of integrated circuit devices.

[0148] The semiconductor substrate includes a plurality of control module dies. The plurality of control module dies are spaced apart in the die array. Each of the plurality of control module dies includes a first optical control module (OCM), a second OCM, a third OCM, and a fourth OCM.

[0149] The die array forms a repeating pattern formed by a plurality of partially overlapping reticle exposure fields. Each reticle exposure field in the plurality of partially overlapping reticle exposure fields includes a corresponding first OCM, a corresponding second OCM, a corresponding third OCM, and a corresponding fourth OCM. Each corresponding OCM is positioned within a different control module die of the plurality of control module dies.

[0150] The plurality of partially overlapping mask exposure fields may include a first rectangular mask exposure field, a second rectangular mask exposure field, a third rectangular mask exposure field, and a fourth rectangular mask exposure field. The second rectangular mask exposure field may partially overlap with the first rectangular mask exposure field. The third rectangular mask exposure field may partially overlap with the first rectangular mask exposure field and the second rectangular mask exposure field. The fourth rectangular mask exposure field may partially overlap with the first rectangular mask exposure field, the second rectangular mask exposure field, and the third rectangular mask exposure field.

[0151] The first rectangular mask exposure field, the second rectangular mask exposure field, the third rectangular mask exposure field and the fourth rectangular mask exposure field may all overlap in the overlap region, and the overlap region may form a first OCM, a second OCM, a third OCM and a fourth OCM.

Claims

1. A method for manufacturing an integrated circuit device, characterized in that The method comprises: The mask and the semiconductor substrate are positioned relative to each other, wherein (i) the mask includes an array region and an edge region; (ii) the array region includes a pattern representing device layers of a plurality of integrated circuit devices and arranged in a two-dimensional grid, the two-dimensional grid including scribe lines separating adjacent device layers of adjacent integrated circuit devices of the plurality of integrated circuit devices; (iii) the array region further comprises a control module die, the control module die comprising a patterning of a first optical control module representing the device layer; and (iv) the edge region is outside the array region and includes a patterning of a second optical control module representing the device layer, a patterning of a third optical control module representing the device layer, and a patterning of a fourth optical control module representing the device layer; exposing an initial mask exposure field on a surface of the semiconductor substrate via the mask to pattern an initial array region and an initial edge region on the semiconductor substrate; and Exposing subsequent mask exposure fields on the surface of the semiconductor substrate via the mask to pattern subsequent array regions and subsequent edge regions on the semiconductor substrate, wherein the subsequent mask exposure fields partially overlap with the initial mask exposure fields, so that initial optical control modules patterned during the exposure of the initial mask exposure fields and subsequent optical control modules patterned during the exposure of the subsequent mask exposure fields are both positioned within a single control module die.

2. The method according to claim 1, characterized in that The exposing the initial reticle exposure field and the exposing the subsequent reticle exposure field include directing electromagnetic radiation through the reticle and incident upon a photoresist layer coating the surface of the semiconductor substrate to selectively expose the photoresist layer to the electromagnetic radiation.

3. The method according to claim 1, characterized in that: (i) prior to said positioning, said method further comprises coating said surface of said semiconductor substrate with a photoresist layer; and (ii) after said exposing said initial reticle exposure field and said exposing said subsequent reticle exposure field, said method further comprises developing said photoresist layer to form a photoresist pattern on said surface of said semiconductor substrate.

4. The method according to claim 3, characterized in that The reticle is a first reticle including a first array region and a first edge region, wherein the photoresist layer is a first photoresist layer, and further wherein the method comprises: (i) defining the device layer of the plurality of integrated circuit devices on the semiconductor substrate; (ii) removing the photoresist pattern from the semiconductor substrate; (iii) coating the surface of the semiconductor substrate with a second photoresist layer; and (iv) repeating said positioning, said exposing said initial reticle exposure field, and said exposing said subsequent reticle exposure field with a second reticle including a second array region and a second edge region.

5. The method according to claim 4, characterized in that The repetition includes: (i) during the repeating of exposing the initial reticle exposure field, aligning the first optical control module, the second optical control module, the third optical control module, and the fourth optical control module of the initial reticle exposure field exposed via the second reticle with the first optical control module, the second optical control module, the third optical control module, and the fourth optical control module of the initial reticle exposure field exposed via the first reticle to provide inter-layer alignment of the initial reticle exposure field; and (ii) during the repeating of exposing the subsequent reticle exposure field, aligning the first optical control module, the second optical control module, the third optical control module and the fourth optical control module of the subsequent reticle exposure field exposed via the second reticle with the first optical control module, the second optical control module, the third optical control module and the fourth optical control module of the subsequent reticle exposure field exposed via the first reticle to provide inter-layer alignment of the subsequent reticle exposure field.

6. The method according to claim 1, characterized in that The method further includes exposing a third mask exposure field on the surface of the semiconductor substrate via the mask to pattern a third array region and a third edge region on the semiconductor substrate, wherein the third mask exposure field partially overlaps with the initial mask exposure field and the subsequent mask exposure field, so that a third optical control module patterned during the exposure of the third mask exposure field is positioned within the single control module die, and the single control module die also includes the initial optical control module patterned during the exposure of the initial mask exposure field and the subsequent optical control module patterned during the exposure of the subsequent mask exposure field.

7. The method according to claim 1, characterized in that: (i) two of a second optical control module patterned during the exposure of the initial mask exposure field, a third optical control module patterned during the exposure of the initial mask exposure field, and a fourth optical control module patterned during the exposure of the initial mask exposure field are outside the second mask exposure field; and (ii) two of the first optical control module patterned during the exposure of the subsequent mask exposure field, the third optical control module patterned during the exposure of the subsequent mask exposure field, and the fourth optical control module patterned during the exposure of the subsequent mask exposure field are outside the first mask exposure field.

8. The method according to claim 1, characterized in that The method additionally includes singulating the semiconductor substrate into a plurality of different integrated circuit devices.

9. A mask configured to be used in a lithography system to pattern device layers of a corresponding plurality of integrated circuit devices on a semiconductor substrate, characterized in that: The mask plate comprises: an array region, the array region comprising a pattern representing the device layer, wherein (i) within the array region, the patterning representing the device layers is arranged in a two-dimensional grid, the two-dimensional grid including scribe lines separating adjacent device layers of adjacent integrated circuit devices of the plurality of integrated circuit devices; and (ii) the array region includes a control module die, the control module die including a pattern representing a first optical control module; and an edge region outside the array region and extending along at least two adjacent sides of the array region, wherein the edge region includes (i) represents the patterning of the second optical control module; (ii) represents patterning of a third optical control module; and (iii) represents the patterning of the fourth optical control module.

10. A semiconductor substrate, characterized in that: include: a plurality of integrated circuit devices arranged in a die array on a surface of the semiconductor substrate; a plurality of scribe lines separating adjacent integrated circuit devices of the plurality of integrated circuit devices; as well as a plurality of control module dies, the plurality of control module dies being spaced apart within the die array, wherein (i) each of the plurality of control module dies comprises a first optical control module, a second optical control module, a third optical control module and a fourth optical control module; (ii) the die array forms a repeating pattern formed by a plurality of partially overlapping reticle exposure fields; and (iii) each of the plurality of partially overlapping reticle exposure fields includes a respective first optical control module, a respective second optical control module, a respective third optical control module, and a respective fourth optical control module positioned within a different control module die of the plurality of control module dies.

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