Semiconductor device package and method of manufacturing the same

Abstract

At least some embodiments of the present disclosure are directed to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and a second surface opposite the first surface, an encapsulation, and an antenna. The encapsulation is disposed on the first surface of the carrier. The antenna is disposed on the encapsulation. The antenna includes a seed layer and a conductive layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package including an antenna comprising a seed layer and a conductive layer. Background Technology

[0002] The antenna is formed and mounted on the upper surface of the molding material of the IC package through an electroplating process. During the electroplating process, the back side of the substrate is protected by an adhesive layer to prevent conductive material from being plated onto the back side of the substrate. However, adhesive residue remains on the back side of the substrate after the removal process.

[0003] The substrate can be replaced by a metal frame. However, the metal frame is prone to deformation during heating operations.

[0004] A shielding layer can be included in a semiconductor package to protect the integrated circuit within the package from electromagnetic interference (EMI). It may include an antenna instead of a shielding layer. In another case, it may include both an antenna and a shielding layer. The thickness of the shielding layer depends on whether it is intended to block high-frequency or low-frequency EMI signals. High frequency refers to 0.5 GHz to 6 GHz, and low frequency refers to 10 MHz to 100 MHz. For example, to achieve a shielding effect, due to the tunneling effect of low-frequency signals, a shielding layer used to block relatively low-frequency EMI is thicker than one used to block relatively high-frequency EMI. However, forming a shielding layer with greater thickness through sputtering operations leads to higher costs and longer manufacturing times, resulting in lower yields. Summary of the Invention

[0005] In some embodiments, according to one aspect of this disclosure, a semiconductor device package includes a carrier, an encapsulation body, and an antenna, the carrier having a first surface and a second surface opposite to the first surface. The encapsulation body is disposed on the first surface of the carrier. The antenna is disposed on the encapsulation body. The antenna includes a seed layer and a conductive layer.

[0006] In some embodiments, according to one aspect of this disclosure, a semiconductor device package includes a carrier, an encapsulation body, and an antenna, the carrier having a first surface and a second surface opposite to the first surface. The carrier includes a first layer adjacent to the first surface and a second layer adjacent to the second surface. The second layer comprises a double layer. The encapsulation body is disposed on the first surface of the carrier. The antenna is disposed on the encapsulation body. The antenna includes a seed layer and a conductive layer. The material of one of the seed layer and the conductive layer of the antenna is the same as the material of one of the double layers of the second layer.

[0007] In some embodiments, according to another aspect of this disclosure, a method for manufacturing a semiconductor device package is disclosed. The method includes: providing a carrier including a first patterned layer adjacent to a first surface of the carrier; encapsulating the carrier with an encapsulation body; forming a trench in the encapsulation body; forming a conductive layer in the trench and on the carrier; and after forming the conductive layer in the trench and on the carrier, forming a second patterned layer adjacent to a second surface of the carrier, the second surface being opposite to the first surface. Attached Figure Description

[0008] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that different features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0009] Figure 1A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0010] Figure 1B A perspective view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0011] Figure 1C A top view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0012] Figure 1D A top view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0013] Figure 2A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0014] Figure 2B A perspective view illustrating a semiconductor device package according to some embodiments of the present disclosure.

[0015] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0016] Figure 4 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0017] Figures 5A to 5H This describes intermediate operations of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0018] Figures 6A to 6H This describes intermediate operations of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0019] Figure 7A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0020] Figure 8 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0021] Figure 9A A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0022] Figure 9B A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown.

[0023] Figures 10A to 10H This describes intermediate operations of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0024] Figures 11A to 11I This describes intermediate operations of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure.

[0025] Figures 12A to 12J This describes intermediate operations of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure. Detailed Implementation

[0026] The same or similar components are indicated using common reference numerals throughout the drawings and detailed descriptions.

[0027] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are merely examples and are not intended to be limiting. In this disclosure, references to the formation of a first feature on or over a second feature in the following description may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0028] Embodiments of this disclosure are discussed in detail below. However, it should be understood that this disclosure provides several applicable concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0029] Figure 1A This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. The semiconductor device package 1 includes a carrier 10, semiconductor devices 11 and 12, an encapsulation 13, an antenna 14, and a shielding layer 15.

[0030] In some embodiments, the carrier 10 has an upper surface 10t and a lower surface 10b opposite to the upper surface 10t. The carrier 10 has a side surface 10l between the upper surface 10t and the lower surface 10b. The carrier 10 has a layer 102 adjacent to the upper surface 10t and a layer 101 adjacent to the lower surface 10b. In some embodiments, layer 102 may be a conductive layer 102, and layer 101 may be a conductive layer 101. In some embodiments, the carrier 10 may include a lead frame or a quad flat no-lead (QFN) structure. In some embodiments, layer 102 adjacent to the upper surface 10t may include a lead frame or a quad flat no-lead (QFN) structure. During plating operations, the organic carrier counterpart may require additional adhesive or a protective layer on its back surface to prevent the plating of solder bumps or solder balls located on the back surface during the aforementioned operations. Residual adhesive may be carried over to subsequent operations if the adhesive or protective layer is not completely removed from the back side of the organic carrier counterpart. On the other hand, the application of adhesive to the back of the QFN structure can be omitted during the plating operation, thus effectively avoiding the problem of residual adhesive. In some embodiments, the material capacity of conductive layer 101 may differ from that of conductive layer 102. For example, the conductive material in conductive layer 102, such as copper (Cu), may be present in greater quantity than the same conductive material in conductive layer 101. Conductive layers 101 and 102 may be patterned to form two patterned conductive layers. Figure 1A As shown, conductive layer 101 is in contact with conductive layer 102. The boundary between conductive layer 101 and conductive layer 102 can be identified. In some embodiments, conductive layer 101 may comprise a copper (Cu) alloy or other suitable material. Conductive layer 102 may comprise Cu or other suitable material.

[0031] like Figure 1A As illustrated, the carrier 10 may include a recess 104 adjacent to the periphery of the lower surface 10b of the carrier 10. The recess 104 provides space for solder (e.g., SnPb) to bleed out. The carrier 10 can be securely bonded to a printed circuit board (PCB). The recess 104 of the carrier 10 can serve as a wettable side for electronic devices used in automotive applications.

[0032] Semiconductor device 11 is disposed on the upper surface 10t of carrier 10. Semiconductor device 11 can be bonded to carrier 10 via conductive wire 112. Adhesive 111 is disposed between carrier 10 and semiconductor device 11. In some embodiments, semiconductor device 11 can be bonded to carrier 10 in a flip-chip manner. Semiconductor device 11 may include application-specific integrated circuit (ASIC), controller, processor or other electronic components or semiconductor devices.

[0033] Similarly, semiconductor device 12 can be wire-bonded to carrier 10 via conductive wire 122. Adhesive 121 is disposed between carrier 10 and semiconductor device 12. The configuration of semiconductor device 12 is similar to that of semiconductor device 11. Semiconductor device 12 may be substantially the same as or different from semiconductor device 11.

[0034] Encapsulation 13 is disposed on the upper surface 10t of carrier 10. Encapsulation 13 encapsulates carrier 10. Encapsulation 13 encapsulates the upper surface 10t of carrier 10. Encapsulation 13 encapsulates semiconductor devices 11 and 12. Encapsulation 13 has an upper surface 13t and a side surface 13l substantially perpendicular to the upper surface 13t. Encapsulation 13 has grooves to accommodate antenna 14. Encapsulation 13 has further additional grooves to accommodate shielding layer 15. Encapsulation 13 can be exposed through openings in carrier 10. Encapsulation 13 can be exposed through the lower surface 10b of carrier 10.

[0035] Antenna 14 is mounted on the upper surface 13t of encapsulation body 13. Antenna 14 is positioned within a groove of encapsulation body 13. Antenna 14 is embedded within encapsulation body 13. Antenna 14 has an upper surface 14t exposed from encapsulation body 13. The upper surface 14t of antenna 14 is coplanar with the upper surface 13t of encapsulation body 13. Antenna 14 is encapsulated by encapsulation body 13 at least laterally.

[0036] Antenna 14 has a seed layer 141 and a conductive layer 142. The seed layer 141 may contain Ti, TiCu, or other suitable materials. The seed layer 141 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 141 may contain a material with high magnetic permeability. The conductive layer 142 may contain Cu or other suitable materials. The conductive layer 142 can be separated from or spaced apart from the encapsulation 13 by the seed layer 141. The conductive layer 142 is surrounded by the seed layer 141 from the sidewalls and bottom. In some embodiments, the appearance or shape of the antenna can be varied depending on the application.

[0037] A shielding layer 15 may be disposed on the upper surface 10t of the carrier 10. The shielding layer 15 is disposed in an additional groove of the encapsulation body 13. The shielding layer 15 is encapsulated by the encapsulation body 13. The shielding layer 15 has an upper surface 15t and a side surface 15s substantially perpendicular to the upper surface 15t. The upper surface 15t of the shielding layer 15 is coplanar with the upper surface 13t of the encapsulation body 13 and is exposed from the encapsulation body 13. The side surface 15s of the shielding layer 15 is coplanar with the side surface 10l of the carrier 10. The shielding layer 15 contacts the side surface 13l of the encapsulation body 13. The shielding layer 15 may surround the antenna pattern of each compartment. Figure 1A As shown, semiconductor device 11 is located in the left compartment defined by shielding layer 15, while semiconductor device 12 is located in the right compartment defined by shielding layer 15. Shielding layer 15 surrounds envelope 13. Shielding layer 15 is separated from or spaced from antenna 14 by envelope 13.

[0038] The shielding layer 15 includes a seed layer 151 and a conductive layer 152. The seed layer 151 may contain Ti, TiCu, or other suitable materials. The seed layer 151 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 151 may contain a material with high magnetic permeability. The conductive layer 152 may contain Cu or other suitable materials. The conductive layer 152 is separated from or spaced apart from the encapsulation body 13 by the seed layer 151.

[0039] Figure 1B This is a cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure. A shielding layer 15 surrounds a carrier 10. The shielding layer 15 surrounds semiconductor devices 11 and 12. Figure 1B (Not shown in the text). Shielding layer 15 surrounds envelope 13. Shielding layer 15 surrounds antenna 14. Shielding layer 15 surrounds antenna 14 in a manner that protects against electromagnetic interference (EMI) from a wider frequency range, including low-frequency EMI. Of course, lower-frequency EMI has a longer wavelength than its higher-frequency counterparts and therefore may require a thicker shielding layer to effectively filter out low-frequency EMI. The thickness of shielding layer 15 can be controlled by the manufacturing operations provided in this disclosure. A suitable thickness of shielding layer 15 can be achieved by an electroplating operation, as described in some embodiments of this disclosure. Various sputtering operations can also be applied to form shielding layer 15. In some embodiments, electroplating may have yield and cost benefits for both operations.

[0040] The side surface of one terminal of the shielding layer 15 may be substantially coplanar with the side surface of one terminal of the encapsulation 13. The side surface of one terminal of the shielding layer 15 may be substantially coplanar with the side surface of one terminal of the antenna 14.

[0041] Figure 1C This is a top view of a semiconductor device package 1' according to some embodiments of the present disclosure. The semiconductor device package 1' is similar to... Figure 1B The semiconductor device package 1 in the package differs in that the appearance or shape of the antenna 14' is different from that of the antenna 14, and the surface of the antenna 14' is surrounded by a capsule 13 to form various sides, for example.

[0042] Figure 1D This is a cross-sectional view of a semiconductor device package 1” according to some embodiments of the present disclosure. The semiconductor device package 1” is similar to Figure 1CThe semiconductor device package 1 differs in that the pattern of antenna 14” or antenna 14”' is different from that of antenna 14”, and shielding layers 15’ and 15” are embedded in the package 13 from each side, for example. Shielding layer 15’ surrounds antenna 14”. Shielding layer 15” surrounds antenna 14”'. In some embodiments, the pattern of antenna 14” is different from that of antenna 14”'. That is, two different antennas or antenna patterns are implemented in two adjacent compartments or any two compartments of the semiconductor device package. In some embodiments, one compartment with an antenna and another compartment without an antenna may be implemented. More than two compartments may be implemented. The compartments may have different shapes to match the design, such as triangular, curved, trapezoidal, or other irregular shapes, etc.

[0043] In addition to the configuration of shielding layers 15, 15', and 15" respectively, the shielding layers can completely cover the underlying semiconductor die from a top view perspective. In other words, the shielding layers can cover one of the compartments from a top view perspective. This is because the shielding layers can... Figure 1A and Figure 1B The side electrical connection illustrated in the example is to the carrier 10, so the shielding layer can also act as a heat sink or heat fin when it completely covers the corresponding compartment. In some other embodiments, the shielding layer may have a fence or mesh configuration from a top view. A fence or mesh configuration can have manufacturing advantages when performing grinding or planarization operations to remove excess shielding material from the top of the compartment.

[0044] Figure 2A This is a cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure. The semiconductor device package 2 may be similar to... Figure 1A The semiconductor device package 1 differs in that the shielding layer 25 can be laterally surrounded by the encapsulation body 13. In other words, the shielding layer 25 is embedded in the encapsulation body 13. In some embodiments, the side 13l of the encapsulation body 13 can be substantially coplanar with the side 10l of the carrier 10. The shielding layer 25 can be encapsulated by the encapsulation body 13. In some embodiments, the encapsulation body 13 can cover the side 10l of the carrier 10. Figure 2A (Not shown in the text). For example... Figure 2A As shown, the two compartments can then be separated or sawn using a laser sawing operation. When performing the laser sawing operation, the laser can be focused onto the encapsulation 13 between adjacent shielding layers 25, and after the operation, the shielding layers 25 in the individually separated packages can be laterally covered by the encapsulation 13. In some other embodiments, roller blades can be implemented to perform the aforementioned separation or sawing operation individually or in combination with laser blades. In some embodiments, the lateral spacing between adjacent shielding layers 25 can be designed to suit the dimensions of the laser blades and / or roller blades.

[0045] The shielding layer 25 comprises a seed layer 251 and a conductive layer 252. The seed layer 251 may contain Ti, TiCu, or other suitable materials. The seed layer 251 may contain magnetic materials, such as Ni, Fe, or stainless steel. The seed layer 251 may contain materials with high magnetic permeability. The conductive layer 252 may contain Cu or other suitable materials. The conductive layer 252 is separated from the encapsulation 13 by the seed layer 251. The conductive layer 252 is surrounded by the seed layer 251.

[0046] Figure 2B This is a perspective view of a semiconductor device package 2 according to some embodiments of the present disclosure. A shielding layer 25 surrounds semiconductor devices 11 and 12. Figure 2B (Not shown in the image). Shielding layer 25 surrounds antenna 14. Encapsulation body 13 surrounds shielding layer 25. Shielding layer 25 can surround the antenna pattern of each compartment. (e.g.) Figure 2A As shown, semiconductor device 11 is located in the left compartment defined by shielding layer 25, while semiconductor device 12 is located in the right compartment defined by shielding layer 25. Shielding layer 25 surrounds envelope 13. Shielding layer 25 is separated from or spaced from antenna 14 by envelope 13.

[0047] Figure 3 This is a cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure. The semiconductor device package 3 is similar to... Figure 1A The semiconductor device package 1 differs in that the upper surface 34t of the antenna 34 and the upper surface 35t of the shielding layer 35 are lower than the upper surface 13t of the package 13. The side surface of the shielding layer 35 is substantially coplanar with the side surface 13l of the package 13. This configuration of the antenna 34 and the shielding layer 35 allows the upper surface 34t of the antenna 34 to be recessed from the upper surface 13t of the package 13, and further prevents the upper surface 34t of the antenna 34 from being scratched during manufacturing operations, operational operations, or operations for attaching the semiconductor device package 3 to a PCB.

[0048] Antenna 34 has a seed layer 341 and a conductive layer 342. The seed layer 341 may contain Ti, TiCu, or other suitable materials. The seed layer 341 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 341 may contain a material with high magnetic permeability. The conductive layer 342 may contain Cu or other suitable materials. The conductive layer 342 is separated from the encapsulation 13 by the seed layer 341. The conductive layer 342 is surrounded by the seed layer 341. In some embodiments, the antenna pattern may be varied based on a specific application.

[0049] The shielding layer 35 comprises a seed layer 351 and a conductive layer 352. The seed layer 351 may contain Ti, TiCu, or other suitable materials. The seed layer 351 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 351 may contain a material with high magnetic permeability. The conductive layer 352 may contain Cu or other suitable materials. The conductive layer 352 can be separated from the encapsulation body 13 through the seed layer 351.

[0050] Figure 4 This is a cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure. The semiconductor device package 4 is similar to... Figure 1A The semiconductor device package 1 in the example differs in that the carrier 40 can be a three-layer structure, the antenna 44 can be a three-layer structure, and the shielding layer 45 can be a three-layer structure.

[0051] The carrier 40 has an upper surface 40t and a lower surface 40b opposite to the upper surface 40t. The carrier 40 has a side surface 40l between the upper surface 40t and the lower surface 40b. The carrier 40 may have a conductive layer 401 near the upper surface 40t, a conductive layer 402 near the lower surface 40b, and a seed layer 403 between the conductive layers 401 and 402. In some embodiments, the conductive layers 402 and 403 form a double layer in contact with the conductive layer 401. In some embodiments, the conductive layers 401 and 402 and the seed layer 403 form a triple layer. The materials of the conductive layers 401 and 402 and the seed layer 403 may be different from each other. The conductive layer 401 is in contact with the seed layer 403. The seed layer 403 is in contact with the conductive layer 402. In some embodiments, the conductive layer 401 may contain a copper (Cu) alloy or other suitable material. The conductive layer 402 may contain Cu or other suitable material. The seed layer 403 may contain Ti, TiCu, or other suitable material. The seed layer 403 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 403 may contain a material with high magnetic permeability. The carrier 40 may be, for example, a lead frame. The carrier 40 may contain a quad flat no-lead (QFN) structure. The conductive material in the conductive layer 402, such as copper (Cu), may be present in greater quantity than the conductive material in the conductive layer 401. For example, the conductive layer 401 may be a QFN structure containing a Cu alloy, and the conductive layer 401 may be a Cu layer formed by electroplating and / or sputtering operations.

[0052] The carrier 40 may have a groove 404 adjacent to the periphery of its lower surface 40b. The groove 404 provides space for solder (e.g., SnPb) to bleed out. The carrier 40 may be securely bonded to a printed circuit board (PCB). The groove 404 may serve as a wettable side for vehicle electronics. In some embodiments, the periphery of the solder can be observed when inspecting the semiconductor device package 4 from a top view perspective as the solder wets the groove 404 of the carrier 40 and bonds the carrier 40 to the PCB.

[0053] Antenna 44 is mounted on the upper surface 13t of the enclosure 13. Antenna 44 is positioned within a groove of the enclosure 13. Antenna 44 is embedded within the enclosure 13. Antenna 44 has an upper surface 44t. The upper surface 44t of antenna 44 is coplanar with the upper surface 13t of the enclosure 13. Antenna 44 is enclosed by the enclosure 13. Antenna 44 is exposed from the enclosure 13.

[0054] Antenna 44 includes a seed layer 441, a conductive layer 442, and a protective layer 443. The seed layer 441 may contain Ti, TiCu, or other suitable materials. The seed layer 441 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 441 may contain a material with high magnetic permeability. The conductive layer 442 may contain Cu or other suitable materials. The conductive layer 442 is separated from or spaced apart from the encapsulation 13 by the seed layer 441. The conductive layer 442 is surrounded by the seed layer 441 from the sides and bottom. The protective layer 443 covers the seed layer 441 and the conductive layer 442. The protective layer 443 is adjacent to the upper surface 44t of antenna 44. The protective layer 443 may be an insulating layer or a conductive layer. The protective layer 443 prevents the conductive layer 442 from oxidizing or being scratched during subsequent manufacturing or operating processes. In some embodiments, the protective layer 443 may contain an insulating material such as a solder resist, a conductive material such as a surface-finishing or corrosion-resistant material, or other suitable materials. In some embodiments, the protective layer 443 may comprise Ni, Au, Pd, their respective alloys, or other suitable materials. In some embodiments, the antenna pattern may be varied depending on the specific application.

[0055] A shielding layer 45 is disposed on the upper surface 40t of the carrier 40. The shielding layer 45 is disposed in an additional groove of the encapsulation body 13. The shielding layer 45 is encapsulated by the encapsulation body 13. The shielding layer 45 has an upper surface 45t and a side surface 45s substantially perpendicular to the upper surface 45t. The upper surface 45t of the shielding layer 45 is coplanar with the upper surface 13t of the encapsulation body 13. The side surface 45s of the shielding layer 45 is coplanar with the side surface 40l of the carrier 40. The shielding layer 45 is in contact with the side surface 13l of the encapsulation body 13. The shielding layer 45 surrounds the antenna 44. The shielding layer 45 surrounds the encapsulation body 13. The shielding layer 45 is separated from the antenna 44 by the encapsulation body 13.

[0056] The shielding layer 45 includes a seed layer 451, a conductive layer 452, and a protective layer 453. The seed layer 451 may contain Ti, TiCu, or other suitable materials. The seed layer 451 may contain magnetic materials, such as Ni, Fe, or stainless steel. The seed layer 451 may contain materials with high magnetic permeability. The conductive layer 452 may contain Cu or other suitable materials. The conductive layer 452 is separated from or spaced apart from the encapsulation 13 by the seed layer 451. The protective layer 453 covers the seed layer 451 and the conductive layer 452. The protective layer 453 is adjacent to the upper surface 45t of the shielding layer 45. The protective layer 453 may be an insulating layer or a conductive layer. The protective layer 453 prevents the conductive layer 452 from oxidation or scratching during subsequent manufacturing or operating processes. In some embodiments, the protective layer 453 may contain insulating materials such as solder resist, conductive materials such as surface finishing or corrosion-resistant materials, or other suitable materials. In some embodiments, the protective layer 453 comprises Ni, Au, Pd, their respective alloys or other suitable materials.

[0057] In some embodiments, with appropriate manufacturing adjustments, the upper surface 13t of the envelope 13 may be higher than the upper surface 44t of the antenna 44 and the upper surface 45t of the shielding layer 45.

[0058] Figures 5A to 5H Some embodiments of a method for manufacturing a semiconductor device package 1 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly. The operation of the method for manufacturing the semiconductor device package 1 can be similarly applied to... Figure 1B , 1C 1D, 3D and 4D semiconductor device packages.

[0059] refer to Figure 5A The method of manufacturing semiconductor device package 1 includes providing a carrier 10'. The carrier 10' may be a pre-formed lead frame, such as a quad flat no-lead (QFN) structure. The carrier 10' comprises a Cu alloy.

[0060] refer to Figure 5B A semi-etching operation is performed on the carrier 10' to form a suitable number of recesses for accommodating semiconductor devices, such as semiconductor devices 11 and 12. Semiconductor devices 11 and 12 can be disposed on the upper surface 10"t of the etched carrier 10" using adhesives 111 and 121, respectively. Through the semi-etching operation, the etched carrier 10" may include a patterned surface at the upper surface 10"t, a patterned surface, or hereinafter referred to as a patterned layer or a patterned conductive layer.

[0061] refer to Figure 5CSemiconductor devices 11 and 12 are bonded to the etched carrier 10” via conductive lines 112 and 122, respectively. Encapsulation 13 may be disposed on the upper surface 10”t of the etched carrier 10”. Encapsulation 13 encapsulates semiconductor devices 11 and 12. In some other embodiments, semiconductor devices 11 and 12 may be bonded to the carrier 10” in a flip-chip manner.

[0062] refer to Figure 5D Grooves 13a and 13b are formed in the capsule 13 by laser removal operations (e.g., laser ablation) or any other suitable operation. Figure 5D For example, trench 13b is formed between a compartment housing semiconductor device 11 and a compartment housing semiconductor device 12. The widths of trenches 13a and 13b can be controlled by a laser removal operation. As illustrated, the depth of trench 13b may differ from the depth of trench 13a. The width of trench 13b may also differ from the width of trench 13a. In some embodiments, when trench 13a is positioned close to the upper surface 13t of the encapsulation, the depth of trench 13b allows the upper surface 10”t of the etched carrier 10” to be exposed from the encapsulation 13. In some embodiments, the depth of trench 13b is greater than the depth of trench 13a. In some embodiments, trench 13b may subsequently be formed with a shielding layer and trench 13a may subsequently be formed with an antenna structure.

[0063] Trench 13a and 13b are formed on the upper surface of the encapsulation 13. Trench 13a may protrude above semiconductor devices 11 and 12. Trench 13b may be positioned between semiconductor devices 11 and 12.

[0064] refer to Figure 5EA seed layer 51 can be formed on the outer surface of the encapsulation 13. The seed layer 51 can be formed on a portion of the encapsulation 13 exposed by the etched carrier 10”. The seed layer 51 can be formed in trenches 13a and 13b of the encapsulation 13. The seed layer 51 can be formed by a sputtering operation. The seed layer 51 can contain Ti, TiCu or other suitable materials. The seed layer 51 can contain magnetic materials, such as Ni, Fe or stainless steel. The seed layer 51 can contain materials with high magnetic permeability. A conductive layer 52 is then formed on the seed layer 51 by a plating operation (e.g., electroplating or electroless plating) or other suitable operation. The conductive layer 52 is formed in trenches 13a and 13b. Simultaneously, the conductive layer 52 can be formed on the back side of the etched carrier 10”, such that the etched carrier 10” together with the newly deposited conductive layer 52 forms a composite carrier 10”'. The original carrier 10' may contain a conductive material such as copper; therefore, for plating operations, forming the conductive layer 52 on the original carrier 10' of this disclosure is more advantageous than forming it on an organic carrier counterpart. For example, the conductive layer 52 formed on the etched carrier 10" may have better thickness uniformity than the conductive layer formed on the organic carrier counterpart. In addition, the yield of forming the conductive layer 52 on the etched carrier 10" may be greater than the yield on the organic carrier counterpart.

[0065] The boundary between the etched carrier 10” and the conductive layer 52 can be observed. The conductive layer 52 comprises Cu or other suitable material. In some embodiments, a seed layer 51 can be formed by a sputtering operation. A sputtered seed layer can be selectively formed on the front side of the etched carrier 10” and the encapsulation 13. Figure 5E For example, carrier 10”' can have a double-layer structure.

[0066] In some other embodiments, the seed layer 51 can be formed by electroplating, electroless plating, or other suitable operations. In such cases, the seed layer 51 will be formed on both the front side (e.g., the side having semiconductor devices 11, 12, and encapsulation 13) and the rear side of the etched carrier 10”. Therefore, after forming the seed layer and the conductive layer 52, the carrier 10”’ can have a three-layer structure ( Figure 5E (Not shown in the text), such as Figure 4 Examples are provided below.

[0067] refer to Figure 5F A portion of the seed layer 51 and conductive layer 52 are removed through a grinding operation to form the antenna 14 and shielding layer 15. The antenna 14 comprises a seed layer 141 and a conductive layer 142. The shielding layer 15 comprises a seed layer 151 and a conductive layer 152. After the grinding operation, the antenna 14, shielding layer 15, and the upper surface of the encapsulation body 13 are substantially coplanar, as shown below. Figure 5F For example, antenna 14 and shielding layer 15 are formed simultaneously.

[0068] In some embodiments, the upper surfaces of the antenna 14 and shielding layer 15 may be recessed from the upper surface of the envelope 13 after polishing due to a flash etching operation following the polishing operation. The recesses in the antenna 14 and shielding layer 15 may appear as recessed structures due to the flash etching operation. In this case, the upper surface of the etched antenna or the etched shielding layer may be lower than the upper surface of the envelope 13. This configuration of the antenna and shielding layer can help avoid scratches during subsequent manufacturing or processing.

[0069] In some embodiments, a protective layer of conductive or insulating material can be formed on the upper surface of the antenna 14 and the upper surface of the shielding layer 15 by electroplating, spraying, or other suitable operations. Figure 5F (Not shown in the image). The protective layer may contain Ni, Au, Pd, their alloys, or other suitable materials. The protective layer, having a dielectric or insulating material, can be formed on the antenna 14 and shielding layer 15 by a spraying operation. The protective layer may contain a solder resist or other suitable materials.

[0070] refer to Figure 5G A half-etch operation is performed on the carrier 10”', for example, on the rear side of the carrier 10”', to pattern the rear side of the carrier 10”'. After the rear half-etch operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. The rear half-etch operation of the carrier 10”' can be performed after the formation of the antenna 14 and the shielding layer 15. The back surface morphology or pattern of the carrier 10 can be controlled during the rear half-etch operation. The carrier 10 includes a conductive layer 101 adjacent to the semiconductor devices 11, 12 and the encapsulation 13, and a conductive layer 102 opposite to the conductive layer 101. A recess 104 can be formed during the rear half-etch operation. In some embodiments, the recess 104 is designed to avoid the location under the protrusions of the semiconductor devices 11, 12. After the unification operation of the semiconductor device package 1, as Figure 5H As shown, the recess 104 may be located adjacent to the rear periphery of a unibody semiconductor device package. In some embodiments, it may be... Figure 5G A protective layer is formed on the upper surface of the antenna 14 and the upper surface of the shielding layer 15 during, before or after the semi-etching operation.

[0071] In some embodiments, after a semi-etching operation, a surface finishing material (e.g., Sn or NiPdAg) may be deposited on the back surface of the carrier 10 to protect the bottom side of the carrier 10. In other embodiments, the surface finishing material may be formed by inkjet printing solder resist above the back surface of the carrier 10. In some embodiments, the surface finishing material may have a low absorption rate for electromagnetic waves.

[0072] refer to Figure 5HA unitization operation is performed to form a semiconductor device package 1. During the unitization operation, a suitable number of compartments can be separated or sawn by a laser operation. When the laser sawing operation is performed, the laser can be focused on the shielding layer 15, and after the operation, the shielding layer 25 in the individually separated package can be laterally exposed from the package body 13. In some other embodiments, roller blades can be implemented to perform the aforementioned separation or sawing operation individually or in combination with laser blades.

[0073] Figures 6A to 6H Some embodiments of a method for manufacturing a semiconductor device package 2 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly. The operation of the method for manufacturing the semiconductor device package 2 can be similarly applied to... Figure 2A , 3 And 4 semiconductor device packaging.

[0074] refer to Figure 6A The method of manufacturing semiconductor device package 2 includes providing a carrier 10'. The carrier 10' may be a pre-formed lead frame, such as a quad flat no-lead (QFN) structure. The carrier 10' comprises a Cu alloy.

[0075] refer to Figure 6B A semi-etching operation is performed on the carrier 10' to form a suitable number of recesses for accommodating semiconductor devices, such as semiconductor devices 11 and 12. Semiconductor devices 11 and 12 can be disposed on the upper surface 10"t of the etched carrier 10" using adhesives 111 and 121, respectively. Through the semi-etching operation, the etched carrier 10" may include a patterned surface at the upper surface 10"t, a patterned surface, or hereinafter referred to as a patterned layer or a patterned conductive layer.

[0076] refer to Figure 6C Semiconductor devices 11 and 12 are bonded to the etched carrier 10” via conductive lines 112 and 122, respectively. Encapsulation 13 may be disposed on the upper surface 10”t of the etched carrier 10”. Encapsulation 13 encapsulates semiconductor devices 11 and 12. In some other embodiments, semiconductor devices 11 and 12 may be bonded to the carrier 10” in a flip-chip manner.

[0077] refer to Figure 6D Grooves 13a and 13b are formed in the capsule 13 by laser removal operations (e.g., laser ablation) or any other suitable operation. Figure 6DFor example, several trenches 13b may be formed between a compartment housing semiconductor device 11 and a compartment housing semiconductor device 12. The widths of trenches 13a and 13b can be controlled by a laser removal operation. As illustrated, the depth of trench 13b may differ from the depth of trench 13a. The width of trench 13b may also differ from the width of trench 13a. In some embodiments, when trench 13a is positioned close to the upper surface 13t of the encapsulation, the depth of trench 13b allows the upper surface 10”t of the etch carrier 10” to be exposed from the encapsulation 13. In some embodiments, the depth of trench 13b is greater than the depth of trench 13a. In some embodiments, trench 13b may subsequently be formed with a shielding layer and trench 13a may subsequently be formed with an antenna structure.

[0078] Trench 13a and 13b are formed on the upper surface of the encapsulation 13. Trench 13a may protrude above semiconductor devices 11 and 12. Trench 13b may be positioned between semiconductor devices 11 and 12.

[0079] refer to Figure 6E A seed layer 51 can be formed on the encapsulation 13 following the contours of trenches 13a and 13b. The seed layer 51 can be formed on a portion of the encapsulation 13 exposed by an etch carrier 10". The seed layer 51 can be formed in trenches 13a and 13b of the encapsulation 13. The seed layer 51 can be formed by a sputtering operation. The seed layer 51 can contain Ti, TiCu, or other suitable materials. The seed layer 51 can contain magnetic materials, such as Ni, Fe, or stainless steel. The seed layer 51 can contain materials with high magnetic permeability. A conductive layer 52 is then formed on the seed layer 51 by a plating operation or other suitable operation. The conductive layer can be formed in trenches 13a and 13b. 52. Simultaneously, a conductive layer 52 may be formed on the back side of the etched carrier 10” to form a carrier 10”', such that the etched carrier 10” together with the newly deposited conductive layer 52 forms a composite carrier 10”'. The original carrier 10’ may contain a conductive material such as copper; therefore, for plating operations, forming the conductive layer 52 on the original carrier 10’ of this disclosure is more advantageous than forming it on an organic carrier counterpart. For example, the conductive layer 52 formed on the etched carrier 10” may have better thickness uniformity than the conductive layer formed on an organic carrier counterpart. Furthermore, the yield of forming the conductive layer 52 on the etched carrier 10” may be greater than the yield on the organic carrier counterpart.

[0080] The boundary between the etched carrier 10” and the conductive layer 52 can be observed. The conductive layer 52 comprises Cu or other suitable materials. In some embodiments, a seed layer 51 can be formed by a sputtering operation, selectively forming a sputtered seed layer on the front side of the etched carrier 10” and the encapsulation 13. Figure 6EFor example, carrier 10”' can have a double-layer structure.

[0081] In some other embodiments, the seed layer 51 can be formed by electroplating, electroless plating, or other suitable operations. In such cases, the seed layer 51 will be formed on both the front side (e.g., the side having semiconductor devices 11, 12, and encapsulation 13) and the rear side of the etched carrier 10”. Therefore, after forming the seed layer and the conductive layer 52, the carrier 10”’ can have a three-layer structure ( Figure 5E (Not shown in the text), such as Figure 4 Examples are provided below.

[0082] refer to Figure 6F A portion of the seed layer 51 and conductive layer 52 are removed through a grinding operation to form the antenna 14 and shielding layer 25. The antenna 14 comprises a seed layer 141 and a conductive layer 142. The shielding layer 25 comprises a seed layer 251 and a conductive layer 252. After the grinding operation, the antenna 14, shielding layer 25, and upper surface of the encapsulation body 13 are substantially coplanar, as shown below. Figure 6F Examples are provided below.

[0083] In some embodiments, the upper surfaces of the antenna 14 and shielding layer 25 may be recessed from the upper surface of the envelope 13 after polishing due to a flash etching operation following the polishing operation. The recesses in the antenna 14 and shielding layer 15 may appear as recessed structures due to the flash etching operation. In this case, the upper surface of the etched antenna or the etched shielding layer will be lower than the upper surface of the envelope 13. This configuration of the antenna and shielding layer can help avoid scratches during subsequent manufacturing or processing.

[0084] In some embodiments, a protective layer of conductive or insulating material can be formed on the upper surface of the antenna 14 and the upper surface of the shielding layer 25 by electroplating, spraying, or other suitable operations. Figure 6F (Not shown in the image). The protective layer may contain Ni, Au, Pd, their alloys, or other suitable materials. The protective layer, having a dielectric or insulating material, can be formed on the antenna 14 and shielding layer 15 by a spraying operation. The protective layer may contain a solder resist or other suitable materials.

[0085] refer to Figure 6GA half-etch operation is performed on the carrier 10”', for example, on the rear side of the carrier 10”', to pattern the rear side of the carrier 10”'. After the rear half-etch operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. The rear half-etch operation of the carrier 10”' can be performed after the formation of the antenna 14 and the shielding layer 15. The back surface morphology or pattern of the carrier 10 can be controlled during the rear half-etch operation. The carrier 10 includes a conductive layer 101 adjacent to the semiconductor devices 11, 12 and the encapsulation 13, and a conductive layer 102 opposite to the conductive layer 101. A recess 104 can be formed during the rear half-etch operation. In some embodiments, the recess 104 can be designed to avoid the location under the protrusions of the semiconductor devices 11, 12. After the unification operation of the semiconductor device package 1, as Figure 5H As shown, the recess 104 may be located adjacent to the rear periphery of a unibody semiconductor device package. In some embodiments, it may be... Figure 6G A protective layer is formed on the upper surface of the antenna 14 and the upper surface of the shielding layer 15 during, before or after the semi-etching operation.

[0086] refer to Figure 6H A unitization operation is performed to form a semiconductor device package 2. During the unitization operation, a suitable number of compartments can be separated or sawn by laser operation. When the laser sawing operation is performed, the laser can be focused on the encapsulation 13 between adjacent shielding layers 25, and after the operation, the shielding layers 25 in the individually separated packages can be laterally encapsulated by the encapsulation 13. In some other embodiments, roller blades can be implemented to perform the aforementioned separation or sawing operation individually or in combination with laser blades.

[0087] Figure 7 This is a cross-sectional view of a semiconductor device package 7 according to some embodiments of the present disclosure. The semiconductor device package 7 includes a carrier 10, semiconductor devices 11, 12 and 76, an encapsulation 13, a patterned conductive layer 74, interconnect elements 75 and electronic components 77.

[0088] The configuration and materials of carrier 10, semiconductor devices 11 and 12, and encapsulation 13 are similar. Figure 1A The configuration and materials of the encapsulation 13. The encapsulation 13 has a plurality of trenches to accommodate the patterned conductive layer 74 and interconnect elements 75. The trenches accommodating the patterned conductive layer 74 may be shallower than the trenches accommodating the interconnect elements 75.

[0089] The patterned conductive layer 74 includes a conductive layer 741, a conductive layer 742, and a seed layer 743. Conductive layers 741 and 742 may be traces. In some embodiments, conductive layer 741 may be a conductive pad. Conductive layer 743 may contain Ti, TiCu, or other suitable materials. Seed layers 741 and 742 may contain Cu or other suitable materials. Conductive layer 741 is separated from encapsulation 13 by seed layer 743. Conductive layer 742 is separated from encapsulation 13 by seed layer 743. Conductive layers 741 and 742 are surrounded by seed layer 743.

[0090] A patterned conductive layer 74 is embedded in a trench of the encapsulation 13. The thickness of the patterned conductive layer 74 can be adjusted. In some embodiments, the upper surface of the patterned conductive layer 74 may be coplanar with the upper surface of the encapsulation 13. The upper surface of the patterned conductive layer 74 may be higher or lower than the upper surface of the encapsulation 13. In some comparative embodiments where only the bottom side of the patterned conductive layer contacts the encapsulation 13 (i.e., the patterned conductive layer is patterned on the upper surface of the encapsulation), the embedded patterned conductive layer 74 of the present invention has better adhesion to the encapsulation 13 by forming contacts at the bottom side and sides. Furthermore, the spacing of the patterned conductive layers 74 (e.g., the distance between the center of one conductive layer 741 and the center of an adjacent conductive layer 741) can be easily controlled to match the spacing of the conductive bumps of the semiconductor device 76.

[0091] Interconnect element 75 includes a seed layer 751 and a conductive via 752. The seed layer 751 may contain Ti, TiCu, or other suitable materials. The conductive via 752 may contain Cu or other suitable materials. Interconnect element 75 electrically connects to carrier 101 via patterned conductive layer 74. Interconnect element 75 is in contact with patterned conductive layer 74 and carrier 101.

[0092] Semiconductor device 76 is disposed on the upper surface 13t of encapsulation 13. Semiconductor device 76 includes conductive bumps 761. Semiconductor device 76 is electrically connected to patterned conductive layer 74 via conductive bumps 761. Conductive bumps 761 contact conductive layer 741. Semiconductor device 76 can be flip-chip bonded to carrier 10. In some embodiments, semiconductor device 76 can be wire-bonded to carrier 10. Semiconductor device 76 may contain a chip. Semiconductor device 76 may contain a wafer-level chip-scale package. Semiconductor device 76 is different from semiconductor device 11 or 12. In some embodiments, semiconductor device 76 does not have any molded encapsulation on it.

[0093] Electronic component 77 may be disposed on the upper surface 13t of the encapsulation 13. Electronic component 77 is electrically connected to the patterned conductive layer 74. Electronic component 77 is in contact with conductive layer 742. Electronic component 77 may be in contact with conductive layers 741 and 742. In some embodiments, electronic component 77 may be a passive component (including, for example, a capacitor, resistor, or inductor). Electronic component 77 may be electrically connected to carrier 10. Electronic component 77 may be electrically connected to semiconductor device 76. In some embodiments, semiconductor device 76 may receive signals through electronic component 77 such that the signals are stable.

[0094] Figure 8 This is a cross-sectional view of a semiconductor device package 8 according to some embodiments of the present disclosure. The semiconductor device package 8 is similar to... Figure 7 The semiconductor device package 7 differs in that the semiconductor device 16 is mounted on a capsule 13 and molded by a capsule 73. The semiconductor device 16 and the electronic component 77 are protected by the capsule 73.

[0095] Semiconductor device 16 includes a conductive pad 163. Semiconductor device 16 has an active surface facing encapsulation 13. Semiconductor device 16 is electrically connected to a patterned conductive layer 74. The conductive pad 163 contacts the conductive layer 741. In some embodiments, semiconductor device 16 is electrically connected to an electronic component 77. Semiconductor device 16 is electrically connected to a carrier 10. Semiconductor device 16 is electrically connected to semiconductor device 11 or 12.

[0096] In some embodiments, semiconductor device 16 may be wire-contacted to carrier 10. Semiconductor device 16 may be substantially the same as or different from semiconductor device 11 or 12. Semiconductor device package 8 may serve as a multi-chip module.

[0097] Figure 9A This is a cross-sectional view of a semiconductor device package 9 according to some embodiments of the present disclosure. The semiconductor device package 9 is similar to... Figure 8 The semiconductor device package 8 differs in that the semiconductor device 16' is wire-bonded to the carrier 10 and the antenna 94, and the shielding layer 95 is disposed in the trench of the encapsulation 73.

[0098] Encapsulation 73 has an upper surface 73t opposite to the upper surface 13t of encapsulation 13. Encapsulation 73 has grooves to accommodate antenna 94. Encapsulation 73 further has additional grooves to accommodate shielding layer 95.

[0099] The configuration and function of antenna 94 are similar to Figure 1AThe configuration and function of antenna 14. Antenna 94 is disposed on the upper surface 73t of encapsulation body 73. Antenna 94 is embedded in encapsulation body 73. Antenna 94 is encapsulated by encapsulation body 73 at least laterally. Antenna 94 includes a seed layer 941 and a conductive layer 942. Seed layer 941 may contain Ti, TiCu or other suitable materials. Seed layer 941 may contain magnetic materials, such as Ni, Fe or stainless steel. Seed layer 941 may contain materials with high magnetic permeability. Conductive layer 942 may contain Cu or other suitable materials. Conductive layer 942 may be separated or spaced from encapsulation body 73 by seed layer 941. Conductive layer 942 is surrounded by seed layer 941 from the sidewalls and bottom.

[0100] The configuration and function of shielding layer 95 are similar to Figure 1A Configuration and function of shielding layer 15. Shielding layer 95 may be disposed on patterned conductive layer 74. Shielding layer 95 may be disposed in additional trenches of encapsulation 73. Shielding layer 95 is encapsulated by encapsulation 73. Shielding layer 95 may surround antenna 94 and semiconductor device 16'. Shielding layer 95 is separated from or spaced from antenna 94 by encapsulation 73.

[0101] The shielding layer 95 comprises a seed layer 951 and a conductive layer 952. The seed layer 951 may contain Ti, TiCu, or other suitable materials. The seed layer 951 may contain a magnetic material, such as Ni, Fe, or stainless steel. The seed layer 951 may contain a material with high magnetic permeability. The conductive layer 952 may contain Cu or other suitable materials. The conductive layer 952 is separated from or spaced apart from the encapsulation body 73 by the seed layer 951.

[0102] Semiconductor device package 9 may also include Figure 1A , 2A Semiconductor device packages 1, 2, 3, and 4 offer similar advantages.

[0103] Figure 9B This is a cross-sectional view of a semiconductor device package 9' according to some embodiments of the present disclosure. The semiconductor device package 9' is similar to... Figure 9A The semiconductor device package 9 differs in that a portion of the patterned conductive layer 74 (e.g., the portion surrounded by dashed lines) can act as an antenna, and the active surface of the semiconductor device 16 in the encapsulation 73 facing or in contact with the patterned conductive layer 74, as well as the shielding layer 95', can pass through the encapsulation 73 and the encapsulation 13.

[0104] The antenna, which may be a portion of the patterned conductive layer 74, may be configured substantially the same as antennas 14 or 94 as previously described. The antenna is disposed on the envelope 13 and configured to interact with either of the semiconductor devices 11 and 12. In some embodiments, the antenna may be disposed between conductive layers 741 and 742 of the patterned conductive layer 74. In some embodiments, the antenna may be adjacent to conductive layer 742. The antenna may be adjacent to conductive layer 741.

[0105] The shielding layer 95' comprises a seed layer 951' and a conductive layer 952'. The shielding layer 95' extends from the upper surface 10t of the carrier 10 to the upper surface 73t of the encapsulation 73. In some embodiments, the shielding layer 95, together with the interconnect element 75, serves as a shielding layer. The shielding layer 95' may be disposed on the periphery of the carrier 10. The shielding layer 95' may be disposed at the center of the carrier 10. The shielding layer 95' may be disposed to surround any one of the semiconductor devices 11, 12, and 16.

[0106] Figures 10A to 10H Some embodiments of a method for manufacturing a semiconductor device package 7 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly. The operation of manufacturing the semiconductor device package 7 can be similar to... Figures 5A to 5H The operation of manufacturing semiconductor device package 1.

[0107] refer to Figure 10A The method of manufacturing semiconductor device package 7 includes providing a carrier 10'. The carrier 10' may be a pre-formed lead frame, such as a quad flat no-lead (QFN) structure. The carrier 10' comprises a Cu alloy.

[0108] refer to Figure 10B A semi-etching operation is performed on the carrier 10' to form a suitable number of recesses for accommodating semiconductor devices, such as semiconductor devices 11 and 12. By means of the semi-etching operation, the etched carrier 10' may include a patterned surface at the upper surface 10't, the patterned surface or hereinafter referred to as a patterned layer or a patterned conductive layer.

[0109] refer to Figure 10C Semiconductor devices 11 and 12 are mounted on the upper surface 10”t of the etched carrier 10” using adhesives 111 and 121, respectively. Semiconductor devices 11 and 12 are bonded to the etched carrier 10” using conductive lines 112 and 122, respectively. An encapsulator 13 is mounted on the upper surface 10”t of the etched carrier 10”. The encapsulator 13 encapsulates semiconductor devices 11 and 12.

[0110] refer to Figure 10D Grooves 13a and 13b are formed in the capsule 13 by laser removal operations (e.g., laser ablation) or any other suitable operation. Figure 10DFor example, trench 13b is formed between a compartment housing semiconductor device 11 and a compartment housing semiconductor device 12. The widths of trenches 13a and 13b can be controlled by a laser removal operation. As illustrated, the depth of trench 13b may differ from the depth of trench 13a. The width of trench 13b may also differ from the width of trench 13a. In some embodiments, when trench 13a is positioned close to the upper surface 13t of the encapsulation, the depth of trench 13b allows the upper surface 10”t of the etched carrier 10” to be exposed from the encapsulation 13. In some embodiments, the depth of trench 13b is greater than the depth of trench 13a. In some embodiments, trench 13b may subsequently be formed with a shielding layer and trench 13a may subsequently be formed with an antenna structure.

[0111] Trench 13a and 13b are formed on the upper surface of the encapsulation 13. Trench 13a may protrude above semiconductor devices 11 and 12. Trench 13b may be positioned between semiconductor devices 11 and 12.

[0112] refer to Figure 10E A seed layer 51 can be formed on the outer surface of the encapsulation 13. The seed layer 51 can be formed on a portion of the encapsulation 13 exposed by the etch carrier 10". The seed layer 51 can be formed in the trenches 13a and 13b of the encapsulation 13. The seed layer 51 can be formed by a sputtering operation. The seed layer 51 can contain Ti, TiCu or other suitable materials. The seed layer 51 can contain magnetic materials, such as Ni, Fe or stainless steel. The seed layer 51 can contain materials with high magnetic permeability. A conductive layer 52 is then formed on the seed layer 51 by a plating operation or other suitable operation. The conductive layer can be formed in the trenches 13a and 13b. 52. Simultaneously, a conductive layer 52 may be formed on the back side of the etched carrier 10” to form a carrier 10”', such that the etched carrier 10” together with the newly deposited conductive layer 52 forms a composite carrier 10”'. The original carrier 10’ may contain a conductive material such as copper; therefore, for plating operations, forming the conductive layer 52 on the original carrier 10’ of this disclosure is more advantageous than forming it on an organic carrier counterpart. For example, the conductive layer 52 formed on the etched carrier 10” may have better thickness uniformity than the conductive layer formed on an organic carrier counterpart. Furthermore, the yield of forming the conductive layer 52 on the etched carrier 10” may be greater than the yield on the organic carrier counterpart.

[0113] The boundary between the etched carrier 10” and the conductive layer 52 can be observed. The conductive layer 52 comprises Cu or other suitable material. In some embodiments, a seed layer 51 can be formed by a sputtering operation. A sputtered seed layer can be selectively formed on the front side of the etched carrier 10” and the encapsulation 13. Figure 10EFor example, carrier 10”' can have a double-layer structure.

[0114] In some other embodiments, the seed layer 51 can be formed by electroplating, electroless plating, or other suitable operations. In such cases, the seed layer 51 will be formed on both the front side (e.g., the side having semiconductor devices 11, 12, and encapsulation 13) and the rear side of the etched carrier 10”. Therefore, after forming the seed layer and the conductive layer 52, the carrier 10”’ can have a three-layer structure ( Figure 10E (Not shown in the text), such as Figure 4 Examples are provided below.

[0115] refer to Figure 10F A portion of the seed layer 51 and conductive layer 52 is removed by a grinding operation to form a patterned conductive layer 74. The patterned conductive layer 74 includes conductive layers 741 and 742 and a seed layer 743. Conductive layer 741 may be a conductive pad. Conductive layer 742 may be a conductive trace. After the grinding operation, the upper surface of the patterned conductive layer 74 may be substantially coplanar with the upper surface of the encapsulation 13.

[0116] Interconnect element 75 includes a seed layer 751 and a conductive via 752. The seed layer 751 may contain Ti, TiCu, or other suitable materials. The conductive via 752 may contain Cu or other suitable materials. A patterned conductive layer 74 is electrically connected to the etched carrier 10” via the interconnect element 75. The interconnect element 75 and the patterned conductive layer 74 are formed simultaneously. The interconnect element 75 and the patterned conductive layer 74 are formed monolithically.

[0117] In some embodiments, due to a flash etching operation following the polishing operation, the upper surface of the patterned conductive layer 74 may be recessed from the upper surface of the encapsulation 13 after polishing. The grooves in the patterned conductive layer 74 may appear as recessed structures due to the flash etching operation. In this case, the upper surface of the patterned conductive layer 74 may be lower than the upper surface of the encapsulation 13.

[0118] In some embodiments, a protective layer having a conductive or insulating material can be formed on the upper surface of the patterned conductive layer 74 by electroplating, spraying, or other suitable operations. Figure 10F (Not shown in the image). The protective layer may contain Ni, Au, Pd, their alloys, or other suitable materials.

[0119] refer to Figure 10GA half-etch operation is performed on the carrier 10”', for example, on the rear side of the carrier 10”', to pattern the rear side of the carrier 10”'. After the rear half-etch operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. The rear half-etch operation on the carrier 10”' can be performed after the formation of the patterned conductive layer 74. The back surface morphology or pattern of the carrier 10 can be controlled during the rear half-etch operation. The carrier 10 includes a conductive layer 101 adjacent to the semiconductor devices 11, 12 and the encapsulation 13, and a conductive layer 102 opposite to the conductive layer 101. A recess 104 can be formed during the rear half-etch operation to expose the encapsulation 13 from the carrier 10”'. In some embodiments, the recess 104 may be designed to avoid the location under the protrusions of the semiconductor devices 11, 12. After the unification operation of the semiconductor device package 7, such as Figure 10G As shown, the recess 104 may be located adjacent to the rear periphery of a single-component semiconductor device package.

[0120] refer to Figure 10H A semiconductor device 76 is disposed on the upper surface 13t of the encapsulation 13. The semiconductor device 76 is electrically connected to a patterned conductive layer 74 via a conductive pad 761. The conductive pad 761 may contact conductive layers 741 and / or 742. An electronic component 77 is disposed on the upper surface of the encapsulation 13. The electronic component 77 is electrically connected to the patterned conductive layer 74. The electronic component 77 may contact conductive layers 741 or 742. The electronic component 77 may contact both conductive layers 741 and 742. In some embodiments, the semiconductor device 76 may comprise a chip. The semiconductor device 76 may comprise a wafer-level chip-scale package. The electronic component 77 may be a passive component (including, for example, a capacitor, resistor, or inductor). A unitization operation is performed to form the semiconductor device package 7.

[0121] Figures 11A to 11I Some embodiments of a method for manufacturing a semiconductor device package 8 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly.

[0122] Figures 11A to 11F The manufacturing process of semiconductor device packaging 8 can be similar to Figures 10A to 10F The manufacturing operation of semiconductor device packaging 7.

[0123] refer to Figure 11G , Figure 11G The attachment operation of the semiconductor device 16 and electrical component 77 is similar to Figure 10H Semiconductor equipment and electrical components, the difference being that semiconductor equipment 16 is different from semiconductor equipment 76.

[0124] refer to Figure 11HEncapsulation body 73 is disposed on the upper surface of encapsulation body 13. Encapsulation body 73 encapsulates semiconductor device 16 and electrical component 77.

[0125] refer to Figure 11I , Figure 11I The etching operation is similar to Figure 10G The etching operation. For example, a half-etch operation is performed on the back side of the carrier 10”' to pattern the back side of the carrier 10”'. After the back half-etch operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. A unification operation is performed to form a semiconductor device package 8.

[0126] Figures 12A to 12J Some embodiments of a method for manufacturing a semiconductor device package 9 according to some embodiments of the present disclosure are described below. The figures have been simplified to present aspects of the present disclosure more clearly.

[0127] Figures 12A to 12F The manufacturing process of semiconductor device packaging 9 can be similar to Figures 10A to 10F The manufacturing operation of semiconductor device packaging 7.

[0128] refer to Figure 12G The attachment operation of semiconductor device 16' is similar to that of semiconductor devices 11 or 12, except that semiconductor device 16' is disposed on encapsulation 13. Semiconductor device 16' is wire-bonded to patterned conductive layer 74 via conductive line 162. Conductive line 162 can be electrically connected to conductive layer 741 or conductive layer 742. Adhesive 161 is disposed between encapsulation 13 and semiconductor device 16'.

[0129] refer to Figure 12H A capsule 73 is disposed on the upper surface of the capsule 13. The capsule 73 encapsulates the semiconductor device 16'.

[0130] refer to Figure 12I The array configuration of antenna 94 and shielding layer 95 is similar to Figures 5D to 5F The array configuration of antenna 14 and shielding layer 15. The configuration, function, and materials of antenna 94 are similar to those of other antennas. Figure 1A The configuration, function, and materials of antenna 14 are described. Antenna 94 includes a seed layer 941 and a conductive layer 942. The configuration, function, and materials of shielding layer 95 are similar to those described above. Figure 1A The configuration, function, and materials of the shielding layer 15. The shielding layer 95 includes a seed layer 951 and a conductive layer 952.

[0131] refer to Figure 12J , Figure 12J The etching operation is similar to Figure 10GThe etching operation. For example, a half-etch operation is performed on the rear side of the carrier 10”' to pattern the rear side of the carrier 10”'. After the rear half-etch operation, the carrier 10 associated with the two conductive layers 101 and 102 is obtained. A unification operation is performed to form the semiconductor device package 9. In some embodiments, this is performed after the formation of the antenna 94 and the shielding layer 95. Figure 12J The semi-etching operation described herein is performed before the formation of antenna 94 and shielding layer 95. Figure 12J In some comparative embodiments of the semi-etching operation described herein, conductive material may be further deposited on the exposed encapsulation 73 at the rear side of the carrier 10”' during antenna and shielding layer formation, causing undesirable short circuits in the semiconductor package structure.

[0132] As used herein, spatial descriptions are given relative to a component or group of components, or a plane of a component or group of components, and for the orientation of a component as shown in the associated diagrams. Examples include “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” “above,” etc. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not affected by such arrangements.

[0133] As used herein and unless otherwise defined, the terms “substantially,” “essentially,” “approximately,” and “about” are used to describe and account for minor variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation has clearly occurred and situations that are very close to occurring. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may mean that two surfaces are coplanar within a few micrometers, for example, within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm.

[0134] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include multiple indicators. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the preceding component is directly on the following component (e.g., in physical contact with the following component), and the case where one or more intermediate components are located between the preceding and following components.

[0135] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not be drawn to scale. Differences may exist between the technical representations in this disclosure and actual apparatus due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically described. This specification and the drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limiting unless specifically indicated herein.

Claims

1. A semiconductor device package comprising: A carrier having a first surface and a second surface opposite to the first surface, the carrier comprising a first layer adjacent to the first surface and a second layer adjacent to the second surface, the second layer comprising a double layer; and A capsule encapsulating body, which is disposed on the first surface of the carrier. An antenna, which is mounted on the encapsulation body, comprises a seed layer and a conductive layer. The material of one of the seed layer and the conductive layer of the antenna is the same as the material of one of the two layers of the second layer.

2. The semiconductor device package according to claim 1, wherein the conductive material in the second layer is present in greater quantity than the conductive material in the first layer.

3. The semiconductor device package of claim 1, wherein the antenna is disposed in a groove on the surface of the package.

4. The semiconductor device package of claim 3, wherein one of the two layers comprises a material substantially the same as the seed layer.

5. The semiconductor device package of claim 1, further comprising a shielding layer disposed on the first surface of the carrier.

6. The semiconductor device package of claim 5, wherein the shielding layer comprises a seed layer and a conductive layer.

7. The semiconductor device package of claim 5, wherein the shielding layer surrounds the antenna.

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