Vertical transmon qubit device

Abstract

A chip surface substrate device structure (300) includes a first superconducting material (112) physically coupled to a crystalline substrate (206A, 206B), where the crystalline substrate is physically coupled to a second superconducting material (304B), and where the second superconducting material is physically coupled to a second crystalline substrate (102). In one implementation, the chip surface substrate device structure further includes a vertical Josephson junction in a via of the crystalline substrate, the vertical Josephson junction including the first superconducting material, a tunnel barrier, and the second superconducting material. In one implementation, the chip surface substrate device structure further includes a transmon qubit, the transmon qubit including the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to superconducting devices and, more particularly, to fabricating a vertical transmon qubit device having vertical Josephson junctions.

[0002] Quantum computing generally uses quantum mechanical phenomena for the purpose of performing computational and information processing functions. Quantum computing can be considered as opposed to classical computing, which typically operates on binary values using transistors. That is, a classical computer is capable of working with bit values of 0 or 1, while a quantum computer is capable of working with qubits that include superpositions of 0 and 1, capable of entangling multiple qubits, and using interference.

[0003] Quantum computing hardware can be different from classical computing hardware. Specifically, superconducting quantum circuits generally rely on Josephson junctions that can be fabricated in semiconductor devices. A Josephson junction generally exhibits the Josephson effect of a supercurrent, where current can flow indefinitely through a Josephson junction without an applied voltage. A Josephson junction can be created by weakly coupling two superconductors (a material that conducts electricity without resistance), for example, by a tunnel barrier.

[0004] One way a Josephson junction can be used in quantum computing is by embedding the Josephson junction in a superconducting circuit to form a qubit (quantum bit). A Josephson junction can be used to form a qubit by arranging the Josephson junction in parallel with a shunt capacitor. In the case where the shunt capacitor has a large capacitance such that the typical ratio of the Josephson energy to the charging energy in the qubit is greater than 10, this arrangement of the Josephson junction in parallel with the shunt capacitor is sometimes referred to as a transmon (which is an abbreviation of the phrase transmission line shunted plasma oscillation qubit). Although in some scenarios where the ratio of the Josephson energy to the charging energy in the qubit has a smaller ratio may not be referred to as a transmon, herein, a transmon can designate any arrangement of a Josephson junction in parallel with a shunt capacitor. There are other superconducting qubits that are not transmon qubits.

[0005] Compared to some other types of qubits, transmons generally have reduced charge noise sensitivity. The mechanism by which a transmon can reduce sensitivity to charge noise is by increasing the ratio of the Josephson energy to the charging energy.

[0006] Some problems with existing transmon qubits are that they occupy a relatively large amount of space. Specifically, the planar capacitors used in some transmon qubits take up a large area. The compactness of such transmon qubits is limited by surface and dielectric losses.

[0007] Then, there are also problems with certain types of existing Josephson junctions, and there are also problems in fabricating transmons from these Josephson junctions. One type of Josephson junction with both low losses and a low critical current can be made of shadow-evaporated aluminum, aluminum oxide, and aluminum (Al-A10x-Al). However, one problem with such a Josephson junction is that once the Josephson junction is formed, the resulting device is subject to cryogenic and process constraints. Summary of the Invention

[0008] An overview is given below to provide a basic understanding of one or more embodiments of the present invention. This overview is not intended to identify key or important elements, or to delineate any scope of a particular embodiment or any scope of any claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, devices, systems, chip surface substrate device structures, computer-implemented methods, apparatuses, and / or computer program products that facilitate vertical transmon qubit devices are described.

[0009] According to an embodiment, a chip surface substrate device structure is provided. In one example, the chip surface substrate device structure includes a first superconducting material physically coupled to a crystalline substrate, where the crystalline substrate is physically coupled to a second superconducting material, and where the second superconducting material is physically coupled to a second crystalline substrate. In one or more implementations, the chip surface substrate device structure may further include a vertical Josephson junction located in a via of the crystalline substrate, the vertical Josephson junction including the first superconducting material, a tunnel barrier, and the second superconducting material. In one or more implementations, the chip surface substrate device structure may also include a transmon qubit, the transmon qubit including the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

[0010] In some examples, the chip surface substrate device structure further includes an information transfer circuit communicatively coupled to the transmon qubit in the second superconducting material. An advantage of such a chip surface substrate device structure is that the transmon qubit and the information transfer circuit can be isolated from each other (except for intentional coupling for computational purposes), such that quantum information does not inadvertently leak from the transmon qubit.

[0011] In another embodiment, a method is provided. In one example, the method includes physically coupling a first superconducting material to a crystalline substrate. The method may further include physically coupling the crystalline substrate to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystalline substrate. The method may further include forming a vertical Josephson junction in a via of the crystalline substrate, the vertical Josephson junction including the first superconducting material, a tunnel barrier, and the second superconducting material. The method may further include forming a transmon qubit, the transmon qubit including the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material. An advantage of such a method may be that it can be used to fabricate transmon qubits that have improved scaling due to reduced shunt capacitor footprint compared to other types of capacitors.

[0012] In some examples, the method may further include removing a portion of the crystalline substrate such that an edge of the crystalline substrate is within an edge of the second superconducting material. An advantage of such a method is that such a narrowed superconducting material reduces coupling to an external circuit.

[0013] In another embodiment, a chip surface substrate device structure is provided. In one example, the chip surface substrate device constructs a vertical Josephson junction formed in a via of a crystalline substrate, the vertical Josephson junction including a first superconducting material physically coupled to a tunnel barrier, the tunnel barrier physically coupled to a second superconducting material. In one or more implementations, the chip surface substrate device structure may further include a transmon qubit, the transmon qubit including the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material. An advantage of such a chip surface substrate device structure may be that it provides scaling due to reduced capacitor footprint compared to other types of capacitors.

[0014] In some examples, the chip surface substrate device structure further includes a second transmon qubit formed of the first superconducting material and a crystalline substrate isolated from crosstalk with the transmon qubit. An advantage of such a chip surface substrate device structure is that the transmon qubit and the second transmon qubit are well controlled and no unwanted quantum information transfer occurs between the two qubits. An advantage of such a chip surface substrate device structure is that the transmon qubit and other superconducting qubits are well controlled and no unwanted quantum information transfer occurs between the two qubits (i.e., the other superconducting qubits are isolated from crosstalk with the transmon qubit).

[0015] In another embodiment, a method is provided. In one example, the method includes forming a vertical Josephson junction in a via of a crystalline substrate, the vertical Josephson junction including a first superconducting material physically coupled to a tunnel barrier, the tunnel barrier physically coupled to a second superconducting material. The method may further include forming a transmon qubit that includes the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material. An advantage of such a method can be that it can be used to fabricate transmon qubits that have improved scaling due to a reduced capacitor footprint compared to other types of capacitors.

[0016] In some examples, the method may further include covering a portion of the second superconducting material that is external to the vertical Josephson junction with the crystalline substrate. An advantage of covering this portion of the second superconducting material with the substrate can be that this portion of the second superconducting material is protected from oxidation.

[0017] In another embodiment, a chip surface substrate device structure is provided. In one example, the chip surface substrate device structure includes a vertical Josephson junction formed in a via of a silicon-on-metal (SOM) substrate, where the SOM is a superconductor. In one or more implementations, the chip surface substrate device structure may further include a transmon qubit that includes the vertical Josephson junction and a capacitor formed between a portion of the superconductor of the SOM and a second superconducting material. An advantage of such a chip surface substrate device structure can be that it provides scaling due to a reduced capacitor footprint compared to other types of capacitors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 An exemplary non-limiting chip surface substrate device structure including a vertical Josephson junction is shown in accordance with one or more embodiments described herein.

[0019] Figure 2 An exemplary non-limiting chip surface substrate device structure is shown after removing some materials in accordance with one or more embodiments described herein Figure 1 thereof.

[0020] Figure 3 An exemplary non-limiting chip surface substrate device structure is shown after removing some materials to form a vertical transmon qubit in accordance with one or more embodiments described herein Figure 2 thereof.

[0021] Figure 4Shows an exemplary non - restrictive chip - surface substrate device structure after removing some materials to form another vertical transmon qubit according to one or more embodiments described herein. Figure 2

[0022] Figure 5 Shows an exemplary non - restrictive chip - surface substrate device structure after removing some materials to form another vertical transmon qubit according to one or more embodiments described herein. Figure 3

[0023] Figure 6 Shows an exemplary non - restrictive top - view of a chip - surface substrate device structure according to one or more embodiments described herein. Figure 4

[0024] Figure 7 Shows an exemplary non - restrictive another top - view of a chip - surface substrate device structure according to one or more embodiments described herein. Figure 4

[0025] Figure 8 Shows an exemplary non - restrictive chip - surface substrate device structure after removing some materials to form another vertical transmon qubit according to one or more embodiments described herein. Figure 1

[0026] Figure 9 Shows an exemplary non - restrictive top - view of a chip - surface substrate device structure according to one or more embodiments described herein. Figure 8

[0027] Figure 10 Shows an exemplary non - restrictive top - view of a chip - surface substrate device structure according to one or more embodiments described herein. Figure 8

[0028] Figure 11 Shows an exemplary non - restrictive chip - surface substrate device structure after adding and removing some materials to form another vertical transmon qubit according to one or more embodiments described herein. Figure 1

[0029] Figure 12 Shows an exemplary non - restrictive chip - surface substrate device structure after initially removing some materials during the process of forming Figure 11 a vertical transmon qubit Figure 1

[0030] Figure 13Illustrates an exemplary non - restrictive chip surface substrate device structure after removing some materials according to one or more embodiments described herein. Figure 12

[0031] Figure 14 Shows an exemplary non - restrictive chip surface substrate device structure after adding some materials according to one or more embodiments described herein. Figure 13

[0032] Figure 15 Shows an exemplary non - restrictive chip surface substrate device structure after removing some materials according to one or more embodiments described herein. Figure 14

[0033] Figure 16 Shows an exemplary non - restrictive chip surface substrate device structure after adding some materials according to one or more embodiments described herein. Figure 15

[0034] Figure 17 Shows a top view of an exemplary non - restrictive chip surface substrate device structure according to one or more embodiments described herein. Figure 11

[0035] Figure 18 Shows another top view of an exemplary non - restrictive chip surface substrate device structure according to one or more embodiments described herein. Figure 11

[0036] Figure 19 Shows a flowchart of an exemplary non - restrictive computer - implemented method for facilitating the implementation of a vertical transmon qubit device according to one or more embodiments described herein.

[0037] Figure 20 Shows another flowchart of an exemplary non - restrictive computer - implemented method for facilitating the implementation of a vertical Josephson junction superconducting device according to one or more embodiments described herein.

[0038] Figure 21 Shows a block diagram of an exemplary non - restrictive operating environment in which one or more embodiments described herein can be facilitated. DETAILED DESCRIPTION

[0039] The following detailed description is merely illustrative and is not intended to limit the embodiments and / or the application or uses of the embodiments. Further, there is no intention to be bound by any of the information presented either explicitly or implicitly in the foregoing background or summary sections or in the detailed description section.

[0040] One or more embodiments will now be described with reference to the accompanying drawings, in which like reference numerals are used throughout to refer to like elements. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details in various instances.

[0041] In view of the above problems of existing transmon qubits, the present disclosure may be implemented to produce solutions to at least some of these problems in the form of a transmon qubit that includes a vertical Josephson junction. As used herein, some embodiments describing a transmon qubit (or Josephson junction) may refer to a vertical transmon qubit (or vertical Josephson junction). Such a vertical transmon qubit may have the advantage of being directly integrated into a circuit. Compared to some other vertical transmon qubits, such a vertical transmon qubit may also have reduced transmon decoherence, thus improving qubit characteristics. Such a vertical transmon qubit may have the advantage of being embedded in a very low-loss environment. Due to the smaller capacitor footprint, such a vertical transmon qubit may have the advantage of enabling scaling. The capacitor associated with the transmon may also be referred to as a shunt capacitor because it is in parallel with (i.e., shunts) the Josephson junction. Such a vertical transmon qubit may have the advantage of improved frequency variability compared to vertical transmon qubits produced using a shadow evaporation process.

[0042] Such a vertical transmon qubit may have the advantage of having an associated fabrication (or process) flow that is compatible with chip fabrication methods, thus enabling scaling of qubit junction fabrication. Such a vertical transmon qubit may have the advantage of confining the electric field distribution within the vertical transmon qubit, thus occupying a small volume while maintaining a uniform electric field distribution across the associated shunt capacitor (i.e., no local field concentration). Such a vertical transmon qubit may have the advantage of providing multiple ways to capacitively couple the vertical transmon qubit to a resonator.

[0043] Figure 1Shows an exemplary, non - limiting chip - surface substrate device structure including a vertical Josephson junction according to one or more embodiments described herein. The chip - surface substrate device structure 100 includes a substrate 102, a superconductor 104, substrates 106A, 106B, a superconductor 108, a tunnel barrier 110, a superconductor 112, and a superconductor 114. Exemplary materials and details of exemplary manufacturing techniques are described below and are also described in related U.S. Patent Application 15 / 934,400, filed on March 23, 2018.

[0044] In some examples, substrates 102 and 106 may have an initial thickness of approximately 500 micrometers (μm) to 800 μm. Then, in some examples, the various materials used may be used at temperatures up to about 500 degrees Celsius (C). In some examples, materials with a lower melting point, such as aluminum (Al), may be used, and these materials may start to deform at about 300C.

[0045] It can be recognized that some similar components of the chip - surface substrate device structure 100 are in contact with each other. For example, superconductor 104 and superconductor 108 are in contact, and superconductor 112 and superconductor 114 are in contact. It can be understood that this is a logical description. In some embodiments, these contacting superconductors may be of the same material and may be deposited in one step. In other embodiments, these contacting superconductors may be of different (or still the same) materials, which are deposited in separate steps.

[0046] The vertical Josephson junction of the chip - surface substrate device structure 100 includes a tunnel barrier 110, where superconductor 108 (and optionally in combination with superconductor 104) serves as the first capacitor plate of the vertical Josephson junction, and superconductor 112 (and optionally in combination with superconductor 114) serves as the second capacitor plate of the vertical Josephson junction. In some examples, the thickness of the superconductor of the first capacitor plate and the thickness of the superconductor of the second capacitor plate are approximately the same. This thickness may be greater than 100 nm.

[0047] In examples where the same superconducting material is used for both the first and second capacitor plates, the superconducting gaps on each side of the tunnel barrier may be equal, which can be used to determine the critical current of the vertical Josephson junction. The value of the critical current in the vertical Josephson junction may be based on the materials used, the thickness of the tunnel barrier 110, and the surface area of those materials in the junction. Multiple vertical Josephson junctions can be created based on the type of materials used, the thickness of those materials, and the size of the opening of the vertical Josephson junction, where the critical currents associated between these vertical Josephson junctions are more reproducible.

[0048] Another metric associated with the vertical Josephson junction can be the thickness of a material in the vertical Josephson junction where the magnetic field does not penetrate. When Al is used as the material in the layer, this thickness of the material can be 100 - 200 nm. Tungsten (W) can be another material used and has different properties when applied to the penetration of the magnetic field.

[0049] The vertical Josephson junction can be formed in a via of a substrate layer that includes substrate 106A and substrate 106B and can initially include the substrate where the superconductor 108, the tunnel barrier 110, and the superconductor 112 are located. The via generally can include an opening through the layers on the surface of the chip substrate, and a conductive connection can be formed between two other layers through the opening. This via can be created by etching into the substrate. In some examples, etching lithography can be implemented to etch the via, and the depth of the via is 100 - 200 nm. In some examples, a 1:1 aspect ratio between the height and the width of the via can be achieved.

[0050] It can be appreciated that according to the techniques of the present disclosure, the chip surface substrate device structure 100 presents one of several embodiments of a vertical Josephson junction that can be used in a vertical transmon qubit. For example, there can be an embodiment of a vertical Josephson junction that omits the superconductor 108 such that the tunnel barrier 110 is in contact with the superconductor 104. For example, there can also be an embodiment of a vertical Josephson junction that omits the superconductor 112 (and the superconductor 108 is correspondingly thicker), where the tunnel barrier is at a "top" of the via - a position at an end of the via opposite to the superconductor 104.

[0051] In some examples, the tunnel barrier 110 can be deposited on the chip surface substrate device structure 100 using a sputtering method, an evaporation method, an atomic layer deposition (ALD) method, or a chemical modification (e.g., oxidation) of the superconductor 104 or the superconductor 108. In some examples, the tunnel barrier 110 can be alumina (Al2O3), a non - superconducting metal (sometimes referred to as a "normal" metal), an oxide, or a nitride. In some examples, the tunnel barrier 110 can be formed by oxidation (after etching) of the exposed surface of the superconductor 104 or the superconductor 108. Generally, the tunnel barrier layer can be a thin layer of a non - conductive material.

[0052] In the chip surface substrate device structure 100, the superconductor 104 and the superconductor 108 (as well as the superconductor 112 and the superconductor 114) are in contact with or close to each other. Generally, two superconductors placed adjacent to each other in this arrangement or a similar arrangement behave as a single superconductor and will exhibit a single superconducting phase even if the two superconductors are made of different materials from each other.

[0053] The chip surface substrate device structure 100 can be considered a buried metal stream. In some examples, a portion of superconductor 104 is deposited onto substrate 102 and a portion of superconductor 104 is deposited onto substrate 106. Then, these two portions of superconductor 104 can be joined together to connect substrate 102 to superconductor 104 and substrate 106. In other words, after depositing the respective portions of superconductor 104 onto substrate 102 and substrate 106, the exposed surface of the first portion of superconductor 104 can be bonded to the exposed surface of the second portion of superconductor 104. In some examples, the bonding can be achieved with low temperature annealing or another adhesion method. There are other terms that can refer to the arrangement of the chip surface substrate device structure, such as silicon-on-metal (SOM).

[0054] Then, before or after substrate 106, superconductor 104, and substrate 102 are joined together, the top substrate layer (including substrate 106A and substrate 106B) can be polished to a thickness of approximately 100 - 200 nm. This thickness of 100 - 200 nm can be obtained by obtaining a crystalline silicon wafer having that thickness (such as those grown by a manufacturer), or by obtaining a crystalline silicon wafer having a thickness greater than 100 - 200 nm and then removing some of the crystalline silicon after coupling the substrate, superconductor, and second substrate such that its thickness is then 100 - 200 nm.

[0055] In some embodiments, superconductor 104 and other superconductors described herein can be titanium (Ti), tantalum (Ta), titanium nitride (TiN). In other examples, superconductor 108 and some superconductors described herein can be niobium (Nb) or aluminum (Al). Considerations regarding the properties of certain materials and their placement in the chip surface substrate device structure (such as the amount of heat treatment involved at the layers of the chip surface substrate device structure) can affect the material selection.

[0056] A cross-sectional side view of the chip surface substrate device structure 100 shows substrate 106A and substrate 106B as being separated. However, it can be understood that holes have been formed in this substrate layer, as shown in this cross-sectional side view, and substrate 106A and substrate 106B are still connected (e.g., from above, the substrate can appear as if holes have been formed in the middle of it). Other materials in the cross-sectional side view can be similarly attached, even though they appear separated in the cross-sectional side view.

[0057] In some examples, one or more of substrate 102, substrate 106A, and substrate 106B, as well as other substrates described herein, may be crystalline silicon (Si). The use of crystalline Si can improve the coherence time of qubits associated with vertical Josephson junctions as described herein. Additionally, in some examples, high-resistivity crystalline Si can be utilized, which can further improve the coherence time. In some examples, such crystalline Si can be grown.

[0058] In some examples, these various superconductors (i.e., superconductor 104, superconductor 108, superconductor 112, and superconductor 114) can include different types of materials from each other. In other examples, two or more of these different superconductors can be of the same type of material. In one embodiment, superconductor 104 can be Ti, superconductor 108 can be Ta, superconductor 112 can be Ta (the same as superconductor 108), and superconductor 114 can be TiN. In some examples, superconductor 112 is deposited to have a greater thickness than superconductor 104 and / or superconductor 108, and this increased thickness can help better control the removal of part or all of the superconductor 108 layer at a later time.

[0059] Figure 2 An example non-limiting chip surface substrate device structure is shown after removing some materials according to one or more embodiments described herein. Removing some materials in this way can be carried out in the Figure 1 process of creating a vertical transmon qubit from a vertical Josephson junction. Figure 1

[0060] In Figure 2 , some of substrate 106A have been removed to produce substrate 206A. In chip surface substrate device structure 200, some of substrate 106B have been removed to produce substrate 206B. Some of superconductor 114 have been removed to produce superconductor 214, and superconductor 214 can also be referred to as a top plate. To achieve the removal of materials, as Figure 2 shown elsewhere, etching (such as etch lithography) can be used. In some examples, a chip surface substrate device structure 200 is generated from chip surface substrate device structure 100 using a mask and reactive ion etching (RIE) method.

[0061] Figure 3 An example is shown according to one or more embodiments described herein after removing some materials to form a vertical transmon qubit 350 Figure 2Exemplary non - restrictive chip - surface - substrate device structures. In the chip - surface - substrate device structure 300, some of the superconductor 104 have been removed to create superconductor 304A, superconductor 304B, and superconductor 304C. Thus, the chip - surface - substrate device structure 300 includes a vertical transmon qubit having a superconductor 304B (also referred to as the bottom plate), a substrate 206A, a substrate 206B, a superconductor 108, a tunnel barrier 110, a superconductor 112, and a superconductor 214. In some examples, the chip - surface - substrate device structure 300 is generated from the chip - surface - substrate device structure 200 using a mask and RIE method.

[0062] In one example, the superconductor 214 may have a width of approximately 7.5 micrometers (μm); the superconductor 112, the tunnel barrier 110, and the superconductor 108 may have a width of approximately 100 nanometers (nm); the substrates 206A and 206B may have a height of approximately 100 nm; and the spacing between the superconductor 304A and the superconductor 304B and between the superconductor 304B and the superconductor 304C may be a distance of approximately 10 μm. Using these example dimensions, the transmon of the chip - surface - substrate device structure 300 will have the following metrics: a capacitance C of approximately 60 femtofarads (fF); a vertical Josephson junction height and width of approximately 100 nm each; a dielectric constant of Si(εSi) of approximately 11.7; and a lateral dimension of the transmon of approximately 7.5 μm.

[0063] Additionally, the substrates 206A and 206B may have a thickness of 50 - 300 nm or 20 - 500 nm, with a corresponding vertical Josephson junction width. The capacitance here can be determined as capacitance=(dielectric constant * area / plate separation)* permittivity of free space. Then, the permittivity of free space is 8.85 * 10 -12 F / m. Then, for a given capacitance, the corresponding plate separation or plate area can be determined. This estimate relies on the assumption that the capacitance of the transmon is dominated by the shunt capacitor plates rather than by the parasitic capacitance to ground or the intrinsic capacitance of the vertical Josephson junction.

[0064] These dimensions and metrics present the advantages of a relatively typical transmon because the transmon here is smaller. In contrast to this smaller transmon, a typical transmon may have a lateral dimension of 700 μm, which is almost two orders of magnitude larger than the lateral dimension of the transmon here.

[0065] Figure 4 Shown is, after removing some materials to form another vertical transmon qubit 450, according to one or more embodiments described herein Figure 2Exemplary non - restrictive chip - surface - substrate device structures. The difference between chip - surface - substrate device structure 300 and chip - surface - substrate device structure 400 is that, in chip - surface - substrate device structure 400, some materials of the top superconductor layer (superconductor 414, also known as the top plate) and the top substrate layers (substrate 406A and substrate 406B) have been removed relative to superconductor 304B, such that the edges of superconductor 304B extend beyond the corresponding edges of substrate 406A, substrate 406B, and superconductor 414.

[0066] In some examples, superconductor 304B can have single - side coupling, and in some examples, superconductor 304B can have multi - side coupling. As depicted, the vertical Josephson junction of chip - surface - substrate device structure 400 can have a height of approximately 100 - 200 nm, and then the associated bottom plate (superconductor 304B) to the resonator space can be in the range of a few micrometers. The top plate (superconductor 414) of the vertical Josephson junction can be narrowed relative to the corresponding top plate in chip - surface - substrate device structure 300 in order to reduce its coupling to the external circuit.

[0067] Figure 5 An exemplary non - restrictive chip - surface - substrate device structure after removing some materials to form another vertical transmon qubit 550 according to one or more embodiments described herein is shown. Figure 3 Exemplary non - restrictive chip - surface - substrate device structures. The difference between chip - surface - substrate device structure 300 and chip - surface - substrate device structure 500 is that, in chip - surface - substrate device structure 500, some materials of the top superconductor layer (superconductor 514, also known as the top plate) have been removed relative to superconductor 304B, substrate 206A, and substrate 206B, such that the edges of superconductor 304B, substrate 206A, and substrate 206B extend beyond the corresponding edges of superconductor 514.

[0068] Figure 6 An exemplary non - restrictive top - view of a chip - surface - substrate device structure according to one or more embodiments described herein is shown. Figure 4 The dashed line 616 indicates where the cross - sectional side - view of chip - surface - substrate device structure 400 occurs relative to chip - surface - substrate device structure 600. Chip - surface - substrate device structure 400 shows a side - view of the chip - surface - substrate device structure, while chip - surface - substrate device structure 600 shows the corresponding top - view of the chip - surface - substrate device structure. Through chip - surface - substrate device structure 600, the vertical transmon qubit is formed in a circular shape (as opposed to the rectangular shape of the vertical transmon qubit of chip - surface - substrate device structure 700).

[0069] The chip surface substrate device structure 600 is characterized by a circular capacitor pad shape. In one embodiment, the superconductor 604B includes the superconductor 304B, where the superconductor 304B is formed in a circular shape. In one embodiment, the superconductor 614 includes the superconductor 414, where the superconductor 414 is configured to be circular. Similarly, in an embodiment where the substrate 102 is exposed in this top view of the chip surface substrate device structure 600 having a substantially circular shape, the substrate 602 includes the substrate 102 (although there are portions of the substrate 602 that are not exposed in this view, and the substrate 602 may extend through the chip surface substrate device structure 600).

[0070] In the chip surface substrate device structure 600, the superconductors 304A and 304C can be used as couplers for external circuits. Additionally, multiple qubits can be connected through the same circuit.

[0071] Although a circular shape and a rectangular (or square) shape are described herein, it is understood that suitable shapes can be substantially circular, substantially elliptical, substantially rectangular, or substantially square, and there can be other embodiments that utilize other shapes.

[0072] The superconductors 604D and 604E include some superconductors that are not visible when considering Figure 4 the cross-sectional view.

[0073] In Figure 6 (and in similar figures depicting a top view), the superconductors 304A and 304C are used as microwave interconnections or resonators (sometimes also referred to as microwave resonators or resonator buses). That is, since the superconductors 304A, 304B, and 304C can be considered a bottom superconductor layer of the chip surface substrate device structure, this bottom superconductor layer can be used to communicatively access vertical transmon qubits. In different examples, a vertical transmon qubit includes a vertical Josephson junction and two capacitor pads (sometimes referred to as a top capacitor pad and a bottom capacitor pad respectively), and either of these two capacitor pads can also be used for a communication coupling.

[0074] The coupling between the resonator and the qubit is affected by placing a capacitor between the resonator and the qubit. The resonator can be used to measure the transmon, control the transmon, couple to the transmon, and / or couple the transmon to other transmons.

[0075] Figure 7 Illustrated is according to one or more embodiments described herein Figure 4Another top view of an exemplary non - restrictive chip - surface - substrate device structure. Chip - surface - substrate device structure 400 shows a side view of the chip - surface - substrate device structure, while chip - surface - substrate device structure 700 shows a corresponding top view of the chip - surface - substrate device structure. For chip - surface - substrate device structure 700, the vertical transmon qubit is formed in a rectangular shape (as opposed to the circular shape of the vertical transmon qubit of chip - surface - substrate device structure 700).

[0076] Chip - surface - substrate device structure 700 is characterized by a rectangular capacitor pad shape. In one embodiment, superconductor 704B includes superconductor 304B, where superconductor 304B is formed as a rectangle (or square). In one embodiment, superconductor 714 includes superconductor 414, where superconductor 414 is configured as a rectangle. Similarly, in an embodiment where substrate 102 is exposed in this top view of chip - surface - substrate device structure 700 having a substantially rectangular shape, substrate 702 includes substrate 102 (although there are portions of substrate 702 that are not exposed in this view and substrate 702 can extend through chip - surface - substrate device structure 700).

[0077] Given this configuration, chip - surface - substrate device structure 700 can be considered to have an etched - island layout. There are other terms that can refer to the arrangement of the chip - surface - substrate device structure.

[0078] Figure 8 An exemplary non - restrictive chip - surface - substrate device structure after removing some materials to form another vertical transmon qubit according to one or more embodiments described herein is shown. Figure 1 An exemplary non - restrictive chip - surface - substrate device structure. Chip - surface - substrate device structure 800 is similar to chip - surface - substrate device structure 300, although there are substrates 806C and 806D in chip - surface - substrate device structure 800 (since they are not etched away). By having substrates 806C and 806D, superconductors 304A and 304B are covered and not exposed to air, and thus have enhanced anti - oxidation protection relative to chip - surface - substrate device structure 300. For example, compared to the configuration in chip - surface - substrate device structure 500, this configuration in chip - surface - substrate device structure 800 can modify the metal - air contribution to the resonator.

[0079] Figure 9 An exemplary non - restrictive chip - surface - substrate device structure according to one or more embodiments described herein is shown. Figure 8Top view of an exemplary non - restrictive chip - surface - substrate device structure. Dashed line 916 indicates where the cross - sectional side view of chip - surface - substrate device structure 800 occurs relative to chip - surface - substrate device structure 900. Chip - surface - substrate device structure 800 shows a side view of the chip - surface - substrate device structure, while chip - surface - substrate device structure 900 shows the corresponding top view of this chip - surface - substrate device structure. For chip - surface - substrate device structure 900, the vertical transmon qubit is formed in a circular shape (opposite to the rectangular shape of the vertical transmon qubit of chip - surface - substrate device structure 1000).

[0080] Chip - surface - substrate device structure 900 is characterized by a circular capacitor pad shape. In an embodiment where substrate 906A is formed in a circular shape, substrate 906A includes both substrate 106A and substrate 106B. Viewed from the side, substrate 106A and substrate 106B appear to be separated by a vertical Josephson junction. However, viewed from the top, they can be seen to be connected, as represented by substrate 906A. In one embodiment, superconductor 914 includes superconductor 414, where superconductor 414 is configured to be circular. Similarly, in one embodiment, substrate 902 includes substrate 102, where substrate 102 is configured to be substantially circular in shape.

[0081] Substrates 906D and 906E have substrates that are not visible when considering Figure 8 the cross - sectional view. In chip - surface - substrate device structure 900, multiple qubits can be connected through the same circuit.

[0082] Figure 10 Shows a top view of an exemplary non - restrictive chip - surface - substrate device structure according to one or more embodiments described herein Figure 10 Dashed line 1016 indicates where the cross - sectional side view of chip - surface - substrate device structure 800 occurs relative to chip - surface - substrate device structure 1000. Chip - surface - substrate device structure 800 shows a side view of the chip - surface - substrate device structure, while chip - surface - substrate device structure 1000 shows the corresponding top view of this chip - surface - substrate device structure. For chip - surface - substrate device structure 1000, the vertical transmon qubit is formed in a rectangular shape (opposite to the circular shape of the vertical transmon qubit of chip - surface - substrate device structure 900).

[0083] The chip surface substrate device structure 1000 is characterized by a rectangular capacitor pad shape. In one embodiment, the substrate 1006A includes both the substrate 106A and the substrate 106B, which are formed in a rectangular (or square) shape. Looking at it from a side view, the substrate 106A and the substrate 106B appear to be separated by a vertical Josephson junction. However, looking at it from a top view, it can be seen that they are connected, as represented by the substrate 1006A. In one embodiment, the superconductor 1014 includes the superconductor 414, where the superconductor 414 is configured in a rectangular (or square) shape. Similarly, in one embodiment, the substrate 1002 includes the substrate 102, where the substrate 102 is configured in a substantially rectangular (or square) shape.

[0084] Given this configuration, the chip surface substrate device structure 1000 can be considered to have an etched island layout.

[0085] Figure 11 Shown is an exemplary non - restrictive chip surface substrate device structure after adding and removing some materials to form another vertical transmon qubit 1120 according to one or more embodiments described herein. Figure 1 One difference between the chip surface substrate device structure 1100 and the chip surface substrate device structure 300 is that the superconductor 1114 in the chip surface substrate device structure 1100 extends wider than the superconductor 214 of the chip surface substrate device structure 300. That is, the superconductor 1114 (also referred to as the top plate) extends wider than the superconductor 304B. In some examples, the superconductor 1114 can extend such that it extends across the space between the superconductor 304A and the superconductor 304B and the space between the superconductor 304B and the superconductor 304C. In some examples, the superconductor 1114 extends over at least a portion of one or both of the superconductor 304A and the superconductor 304B.

[0086] By elongating the superconductor 1114 relative to the other top plates, this elongation of the top plate can provide a connection away from the associated vertical Josephson junction 1116 (which is formed in a via 1118 of the superconductor 206A and the superconductor 206B). In other embodiments, although the top plate is elongated, it does not overlap with the superconductors (i.e., the superconductor 304A and the superconductor 304C) below it, which can include external circuit islands.

[0087] In some examples, the superconductor 304A (or 304C) can be part of a signal transfer circuit communicatively coupled to the transmon qubit 1120 (or 350, or 450, or 550). In different examples, the signal transfer circuit can include input, output, or readout circuitry, or one or more resonator buses.

[0088] In some examples, at least a portion of the second superconducting material 304A (or 304C) can be located outside of the transmon qubit and serve as the resonator bus 304A (or 304C). In some examples, at least a portion of the second superconducting material located outside of the transmon qubit can be covered by a crystalline substrate (e.g., similar to Figure 8 how the crystalline substrate 806C in

[0089] covers some of the superconductor 304A). Figure 8 In some examples, the resonator bus 304C can electrically couple the transmon qubit to a second transmon qubit, input, output, or readout circuitry, or a second resonator bus 304A, and the resonator bus 304C is formed on a second superconducting material (e.g., superconductor 304B). In some examples, the resonator bus 304A (or 304B) can be covered by a crystalline substrate (e.g., similar to

[0090] how the crystalline substrate 806C in Figure 8 covers some of the superconductor 304A).

[0091] Figure 12 illustrates after initial removal of some material during the formation of Figure 11 the vertical transmon qubit 1120 according to one or more embodiments described herein Figure 1Exemplary non - restrictive chip - surface substrate device structures. It can be appreciated that chip - surface substrate device structure 1200 is similar to chip - surface substrate device structure 200, but without superconductor 214. It can be further appreciated that there can be multiple embodiments where chip - surface substrate device structure 1200 is generated by starting from a chip - surface substrate device structure different from chip - surface substrate device structure 100 (such as a chip - surface substrate device structure with superconductor 114 omitted). In some examples, chip - surface substrate device structure 1200 is generated from chip - surface substrate device structure 100 using a mask and RIE method.

[0092] Figure 13 Illustrates, after removing some materials, according to one or more embodiments described herein Figure 12 Exemplary non - restrictive chip - surface substrate device structures. It can be appreciated that chip - surface substrate device structure 1300 is similar to chip - surface substrate device structure 300, but without superconductor 214. Chip - surface substrate device structure 1300 differs from chip - surface substrate device structure 1200 in that in chip - surface substrate device structure 1300 and relative to chip - surface substrate device structure 1200, a portion of superconductor 104 has been removed to produce superconductor 304A, superconductor 304B, and superconductor 304C. Additionally, the space between superconductor 304A and superconductor 304B and the space between superconductor 304B and superconductor 304C can be larger in chip - surface substrate device structure 1300 than in chip - surface substrate device structure 300. In some examples, chip - surface substrate device structure 1300 is generated from chip - surface substrate device structure 1200 using a mask and RIE method.

[0093] Figure 14 Shows, after adding some materials, according to one or more embodiments described herein Figure 13 Exemplary non - restrictive chip - surface substrate device structures. The material added in chip - surface substrate device structure 1400 relative to chip - surface substrate device structure 1300 is sacrificial material 1416. Sacrificial material 1416 is added to provide a platform on which superconductor 1114 is ultimately added and then the sacrificial material 1416 is ultimately removed.

[0094] In some examples, sacrificial material 1416 can comprise an oxide. In other examples, instead of or in addition to the sacrificial material, epitaxial silicon can be used rather than a sacrificial material that will be completely removed later, where at least some of the epitaxial silicon will remain in the resulting chip - surface substrate device structure including vertical transmon qubits.

[0095] Figure 15illustrates, after removing some materials, according to one or more embodiments described herein Figure 14 an exemplary non - restrictive chip - surface substrate device structure. In chip - surface substrate device structure 1500 and relative to chip - surface substrate device structure 1400, a portion of the sacrificial material 1416 has been removed to create sacrificial material 1516A and sacrificial material 1516B. In other words, the sacrificial material has been removed downward to the topmost layer of substrate 206A, substrate 206B, and superconductor 112. In an example where sacrificial material 1516A comprises silicon, CMP can be used to remove the material. In an example where sacrificial material 1516A includes an oxide, RIE can be used to remove the material.

[0096] Figure 16 illustrates, after adding some materials, according to one or more embodiments described herein Figure 15 an exemplary non - restrictive chip - surface substrate device structure. In chip - surface substrate device structure 1600 and relative to chip - surface substrate device structure 1500, superconductor 1114 has been added. Sacrificial material 1516A and sacrificial material 1516B provide support on which superconductor 1114 can rest when superconductor 1114 is added to chip - surface substrate device structure 1600.

[0097] Then, sacrificial material 1516A and sacrificial material 1516B can be removed to create Figure 11 chip - surface substrate device structure 1100. In some examples, sacrificial material 1516A and sacrificial material 1516B can be removed using vapor etching (e.g., using hydrogen fluoride (HF)).

[0098] Figure 17 illustrates, according to one or more embodiments described herein Figure 11 a top - view of an exemplary non - restrictive chip - surface substrate device structure. While chip - surface substrate device structure 1100 shows a cross - sectional side - view of the chip - surface substrate device structure, chip - surface substrate device structure 1700 shows a corresponding top - view of this chip - surface substrate device structure. Figure 11 The arrangement of the cross - sectional side - view relative to Figure 17 the top - view is shown by line 1716. For chip - surface substrate device structure 1700, the vertical transmon qubit is formed in a circular shape (as opposed to the rectangular shape of the vertical transmon qubit of chip - surface substrate device structure 1800). In one embodiment, superconductor 1714 includes superconductor 1114, where superconductor 1114 is formed in a circular shape.

[0099] The chip surface substrate device structure 1700 is characterized by a circular capacitor pad shape. In the chip surface substrate device structure 1700, multiple qubits can be connected through the same circuit.

[0100] Figure 18 The present invention shows one or more embodiments described herein. Figure 11 1700 . FIG. 18 is another top view of an exemplary non-limiting chip surface substrate device structure of FIG. 1800 . While chip surface substrate device structure 1100 illustrates a side view of a chip surface substrate device structure, chip surface substrate device structure 1800 illustrates a corresponding top view of such a chip surface substrate device structure. For chip surface substrate device structure 1800 , the vertical transmon qubit is formed into a rectangular shape (as opposed to the circular shape of the vertical transmon qubit of chip surface substrate device structure 1700 ). In one embodiment, superconductor 1814 includes superconductor 1114 , wherein superconductor 1114 is formed into a circular shape.

[0101] The chip surface substrate device structure 1800 is characterized by a rectangular capacitor pad shape. Given this configuration, the chip surface substrate device structure 1800 can be considered to have an etched island layout.

[0102] Figure 19 A flowchart is shown of an example non-limiting computer-implemented method for facilitating implementation of a vertical transmon qubit device in accordance with one or more embodiments described herein. In some examples, flowchart 1900 can be implemented by computer 2112. It is understood that the operations of flowchart 1900 can be implemented in an order different from that depicted. It is also understood that the operations of flowchart 1900 can be implemented in an order different from that depicted.

[0103] In a non-limiting example embodiment, a computing device (or system) (e.g., computer 2112) is provided that includes one or more processors and one or more memories storing executable instructions that, when executed by the one or more processors, can facilitate operations as described herein (including Figure 19 As a non-limiting example, one or more processors may facilitate execution of the method by directing or controlling one or more devices operable to perform semiconductor manufacturing.

[0104] like Figure 19 An advantage of the approach shown may be that it may be used to fabricate vertical transmon qubit devices, which allows for scaling due to the reduced capacitor footprint compared to other types of capacitors.

[0105] Operation 1902 depicts physically coupling (e.g., via computer 2112) a first superconducting material to a crystalline substrate. As used herein, physically coupling two materials can refer to mechanically or chemically coupling the materials, and can be distinguished from electrical coupling, which can involve configuring two things to transfer an electrical signal between them. In some examples, such a physical coupling arrangement can be referred to as different materials stacked on top of each other and can include a SOM substrate. Operation 1904 depicts physically coupling (e.g., via computer 2112) the crystalline substrate to a second superconducting material, where the second superconducting material is physically coupled to a second crystalline substrate.

[0106] In some examples, the operation includes removing a portion of the substrate such that an edge of the substrate is within an edge of the second superconducting material. For example, in chip surface substrate device structure 400, the substrate can be substrate 406A and substrate 406B, and the second superconducting material can be superconductor 304B. In this example, it can be seen that superconductor 304B extends further from the transmon level than substrate 406A or substrate 406B. Thus, the edges of substrate 406A and substrate 406B that extend away from the transmon are within the edges of superconductor 304B that extend away from the transmon.

[0107] In some examples, the operation includes removing a portion of the superconducting material such that an edge of the superconducting material is flush with an edge of the substrate. For example, in chip surface substrate device structure 400, the substrate can be substrate 406A and substrate 406B, and the superconducting material can be superconductor 414. In this example, it can be seen that superconductor 414 extends from the transmon level the same amount as both substrate 406A or substrate 406B. Thus, the edges of superconductor 414 that extend away from the transmon are flush with the edges of substrate 406A and substrate 406B that extend away from the transmon.

[0108] In some examples, the operation includes removing a portion of the superconducting material such that an edge of the superconducting material is within an edge of the substrate. For example, in chip surface substrate device structure 500, the substrate can be substrate 206A and substrate 206B, and the superconducting material can be superconductor 514. In this example, it can be seen that substrate 206A and substrate 206B extend further from the transmon level than superconductor 514. Thus, the edges of superconductor 514 that extend away from the transmon are within the edges of substrate 206A and substrate 206B that extend away from the transmon.

[0109] Operation 1906 depicts forming, e.g., via computer 2112, a vertical Josephson junction in a via of the crystal substrate, the vertical Josephson junction including the first superconducting material, a tunnel barrier, and the second superconducting material.

[0110] For example, in chip surface substrate device structure 100, the vertical Josephson junction can include superconductor 108, tunnel barrier 110 (used as a tunnel barrier herein), and superconductor 112. This vertical Josephson junction is formed in a via of substrate 106A and substrate 106B (the via can be a continuous part of the substrate before the via is formed, leaving substrate 106A and substrate 106B).

[0111] Operation 1908 depicts forming, e.g., via computer 2112, a transmon qubit that includes the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

[0112] In some examples, forming a vertical transmon qubit that includes the vertical Josephson junction and the capacitor includes forming a second vertical transmon qubit from the superconducting material and the substrate, the substrate being crosstalk isolated from the vertical transmon qubit by a space in one of the second superconducting materials. That is, a chip surface substrate device structure such as chip surface substrate device structure 100 can include multiple vertical transmon qubits, and these multiple vertical transmon qubits can be isolated from crosstalking with each other. In some examples where the chip surface substrate device structure includes multiple vertical transmon qubits or there are multiple vertical transmon qubits, a resonator bus can couple the vertical transmon qubit and the second vertical transmon qubit.

[0113] In some examples, the resonator bus is coupled to the second superconducting material. For example, such a second superconducting material can include superconductor 304A or superconductor 304C of chip surface substrate device structure 300, and the resonator bus can be part of or coupled to superconductor 304A or superconductor 304C.

[0114] In some examples, the first superconducting material includes the resonator bus. For example, in chip surface substrate device structure 100, when the vertical Josephson junction is isolated, some superconductors 114 away from the vertical Josephson junction can be retained, and this part of superconductor 114 can be used as the resonator bus.

[0115] Similarly, in some examples, the resonant bus is coupled to the superconducting material, and using the chip surface substrate device structure 100 as an example, when the vertical Josephson junction is isolated, some superconductors 114 away from the vertical Josephson junction can be retained, and this part of the superconductor 114 can be used as the resonant bus.

[0116] In some examples, the resonant bus is coupled to the vertical transmon qubit, and the second resonant bus is coupled to the vertical transmon qubit. For example, in Figure 6 superconductors 304A and 304C can both be used as the resonant bus. Thus, superconductor 304A can be the resonant bus coupled to the vertical transmon qubit, and superconductor 304C can be the second resonant bus coupled to the vertical transmon qubit. In some examples, more than two resonant buses can be coupled to the vertical transmon qubit.

[0117] In some examples, the readout resonator is coupled to and addresses the vertical transmon qubit, and not to the second vertical transmon qubit of the chip surface substrate device structure. A chip surface substrate device structure can include multiple vertical transmon qubits. In the case where a chip surface substrate device structure can include multiple vertical transmon qubits, a particular readout resonator can be coupled to only one of these vertical transmon qubits. For example, in the chip surface substrate device structure 600, superconductor 304A can be used as the readout resonator, and it can be coupled to one vertical transmon qubit.

[0118] In some examples, the vertical transmon qubit includes one vertical transmon qubit. The vertical transmon qubit generally can be a vertical transmon qubit including a vertical Josephson junction. The vertical Josephson junction exists in, for example, the chip surface substrate device structure 100, where the vertical Josephson junction includes superconductor 108, tunnel barrier 110, and superconductor 112.

[0119] In some examples, such an operation can include coupling a resonator to the first side of the superconducting material such that the superconducting material includes a single-sided coupling. Single-sided coupling generally includes a resonator coupled to the vertical transmon qubit. In the chip surface substrate device structure 600, where superconductor 304A is used as the resonator and superconductor 304C is omitted, superconductor 304A can be used as a single-sided coupler to form a single-sided coupling.

[0120] In some examples, such an operation includes connecting a first resonator to a first side of the superconducting material and connecting a second resonator to a second side of the superconducting material, such that the superconducting material includes multi-sided coupling (i.e., multiple resonators are electrically connected to multiple sides of the first superconducting material). Multi-sided coupling generally includes multiple resonators coupled to a vertical transmon qubit. In the chip surface substrate device structure 600, where the superconductors 304A and 304C each serve as a resonator, the chip surface substrate device structure 600 can have multi-sided coupling.

[0121] In some examples, a portion of the second superconducting material that is located outside the vertical Josephson junction is exposed to air. For example, in the chip surface substrate device structure 300, the portions of the superconducting material that are located outside the vertical Josephson junction can be the superconductors 304A and 304C. The superconductors 304A and 304C can be considered to be exposed to air because they are not covered by another material, such as a substrate. This arrangement can be seen to be opposite to the chip surface substrate device structure 800, where the superconductors 304A and 304C can be said to not be exposed to air because they are covered by the substrate 806C and the substrate 806D, respectively.

[0122] In some examples, this operation includes covering a portion of the second superconducting material that is located outside the vertical Josephson junction with the substrate, such that the portion of the second superconducting material that is located outside the vertical Josephson junction is covered by the substrate. For example, in the chip surface substrate device structure 800, the portions of the second superconducting material can be the superconductors 304A and 304C. As can be seen in the chip surface substrate device structure, the superconductors 304A and 304C are covered by the substrate 806C and the substrate 806D, respectively. By covering the superconductors 304A and 304C with the substrate 806C and the substrate 806D, respectively, the top interfaces of the superconductors 304A and 304C are changed, and the superconductors 304A and 304C can be protected from oxidation due to exposure to air.

[0123] Figure 20 A flowchart illustrating an example non-limiting computer-implemented method for facilitating the implementation of a vertical transmon qubit device in accordance with one or more embodiments described herein is shown. In some examples, the flowchart 2000 can be implemented by a computer 2112. It can be understood that the operations of the flowchart 2000 can be implemented in an order different from the depicted order. It can also be understood that the operations of the flowchart 1900 can be implemented in an order different from the depicted order.

[0124] In a non-limiting example embodiment, a computing device (or system) (e.g., computer 2112) is provided that includes one or more processors and one or more memories storing executable instructions that, when executed by the one or more processors, can facilitate the performance of operations as described herein (including non-limiting methods such as those shown in the Figure 20 flowchart). As a non-limiting example, the one or more processors can facilitate the performance of the method by directing or controlling one or more devices operable to perform semiconductor manufacturing.

[0125] Such as Figure 20 The advantages of the method shown can be that it can be used to fabricate a vertical transmon qubit device that allows for scaling due to a reduced capacitor footprint compared to other types of capacitors.

[0126] Operation 2002 depicts forming (e.g., by computer 2112) a vertical Josephson junction in a via of a crystal substrate, the vertical Josephson junction including a first superconducting material physically coupled to a tunnel barrier that is physically coupled to a second superconducting material. As used herein, physically coupling two materials can refer to mechanically or chemically coupling the materials and can be distinguished from electrical coupling, which can involve configuring two things to transfer an electrical signal between them. In some examples, this physical coupling arrangement can be referred to as different materials stacked on top of each other and can include a SOM substrate.

[0127] For example, in the chip surface substrate device structure 100, the vertical Josephson junction can include superconductor 108, tunnel barrier 110 (used herein as the tunnel barrier), and superconductor 112. This vertical Josephson junction is formed in a via of substrate 106A and substrate 106B (the via can be a continuous portion of the substrate before the via is formed, leaving substrate 106A and substrate 106B).

[0128] In some examples, the operation includes removing a portion of the substrate such that the edge of the substrate is within the edge of the second superconducting material. For example, in the chip surface substrate device structure 400, the substrate can be substrate 406A and substrate 406B, and the second superconducting material can be superconductor 304B. In this example, it can be seen that superconductor 304B extends further away from the transmon than substrate 406A or substrate 406B. Thus, the edges of substrate 406A and substrate 406B that extend away from the transmon are within the edges of superconductor 304B that extend away from the transmon.

[0129] In some examples, the operation includes removing a portion of the superconducting material such that the edge of the superconducting material is flush with the edge of the substrate. For example, in the chip surface substrate device structure 400, the substrate can be substrate 406A and substrate 406B, and the superconducting material can be superconductor 414. In this example, it can be seen that the superconductor 414 extends from the transmon level the same amount as both substrate 406A or substrate 406B. Thus, the edge of the superconductor 414 extending away from the transmon is flush with the edge of substrate 406A and substrate 406B extending away from the transmon.

[0130] In some examples, the operation includes removing a portion of the superconducting material such that the edge of the superconducting material is within the edge of the substrate. For example, in the chip surface substrate device structure 500, the substrate can be substrate 206A and substrate 206B, and the superconducting material can be superconductor 514. In this example, it can be seen that substrate 206A and substrate 206B extend further away from the transmon level than the superconductor 514. Thus, the edge of the superconductor 514 extending away from the transmon is within the edge of substrate 206A and substrate 206B extending away from the transmon.

[0131] Operation 2004 depicts forming (e.g., by computer 2112) a transmon qubit that includes the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material.

[0132] In some examples, forming a vertical transmon qubit that includes the vertical Josephson junction and the capacitor includes forming a second vertical transmon qubit from the superconducting material and the substrate, the second vertical transmon qubit being isolated from crosstalk with the vertical transmon qubit by a space in one of the second superconducting materials. That is, a chip surface substrate device structure such as chip surface substrate device structure 100 can include multiple vertical transmon qubits, and these multiple vertical transmon qubits can be isolated from crosstalk with each other. In some examples where the chip surface substrate device structure includes multiple vertical transmon qubits or there are multiple vertical transmon qubits, a resonant bus can couple the vertical transmon qubit and the second vertical transmon qubit.

[0133] In some examples, the resonant bus is connected to the second superconducting material. For example, such a second superconducting material can include superconductor 304A or superconductor 304C of chip surface substrate device structure 300, and the resonant bus can be coupled to superconductor 304A or superconductor 304C.

[0134] In some examples, the first superconducting material includes a resonant bus. For example, in the chip surface substrate device structure 100, when the vertical Josephson junction is isolated, some superconductors 114 away from the vertical Josephson junction can be retained, and this portion of the superconductor 114 can be used as a resonant bus.

[0135] Similarly, in some examples, the resonant bus is coupled to the superconducting material, and using the chip surface substrate device structure 100 as an example, when the vertical Josephson junction is isolated, some superconductors 114 away from the vertical Josephson junction can be retained, and this portion of the superconductor 114 can be used as a resonant bus.

[0136] In some examples, the resonant bus is coupled to the vertical transmon qubit, and a second resonant bus is coupled to the vertical transmon qubit. For example, in Figure 6 both the superconductor 304A and the superconductor 304C can be used as resonant buses. Thus, the superconductor 304A can be a resonant bus coupled to the vertical transmon qubit, and the superconductor 304C can be a second resonant bus coupled to the vertical transmon qubit. In some examples, more than two resonant buses can be coupled to the vertical transmon qubit.

[0137] In some examples, the readout resonator is coupled to and addresses the vertical transmon qubit, and not to the second vertical transmon qubit of the chip surface substrate device structure. A chip surface base device structure can include multiple vertical transmon qubits. In the case where a chip surface substrate device structure can include multiple vertical transmon qubits, a particular readout resonator can be coupled to only one of these vertical transmon qubits. For example, in the chip surface substrate device structure 600, the superconductor 304A can be used as a readout resonator, and it can be coupled to a vertical transmon qubit.

[0138] In some examples, the vertical transmon qubit includes a vertical transmon qubit. The vertical transmon qubit generally can be a vertical transmon qubit including a vertical Josephson junction. The vertical Josephson junction exists, for example, in the chip surface substrate device structure 100, where the vertical Josephson junction includes a superconductor 108, a tunnel barrier 110, and a superconductor 112.

[0139] In some examples, such an operation can include coupling a resonator to the first side of the superconducting material such that the superconducting material includes a single-sided coupling. Single-sided coupling generally includes coupling a resonator to a vertical transmon qubit. In the chip surface substrate device structure 600, where the superconductor 304A is used as the resonator and the superconductor 304C is omitted, the superconductor 304A can be used as a single-sided coupler to form a single-sided coupling.

[0140] In some examples, such an operation includes coupling a first resonator to the first side of the superconducting material and coupling a second resonator to the second side of the superconducting material such that the superconducting material includes a multi-sided coupling. Multi-sided coupling generally includes coupling multiple resonators to a single vertical transmon qubit. In the chip surface substrate device structure 600, where the superconductor 304A and the superconductor 304C each serve as a resonator, the chip surface substrate device structure 600 can have a multi-sided coupling.

[0141] In some examples, a portion of the second superconducting material that is located outside the vertical Josephson junction is exposed to air. For example, in the chip surface substrate device structure 300, the portions of the superconducting material that are located outside the vertical Josephson junction can be the superconductor 304A and the superconductor 304C. The superconductor 304A and the superconductor 304C can be considered to be exposed to air because they are not covered by another material, such as a substrate. This arrangement can be seen to be opposite to the chip surface substrate device structure 800, where the superconductor 304A and the superconductor 304C can be said to not be exposed to air because they are covered by the substrate 806C and the substrate 806D, respectively.

[0142] In some examples, this operation includes covering a portion of the second superconducting material that is located outside the vertical Josephson junction with the substrate such that the portion of the second superconducting material that is located outside the vertical Josephson junction is covered by the substrate. For example, in the chip surface substrate device structure 800, the portions of the second superconducting material can be the superconductor 304A and the superconductor 304C. As can be seen in the chip surface substrate device structure, the superconductor 304A and the superconductor 304C are covered by the substrate 806C and the substrate 806D, respectively. By covering the superconductor 304A and the superconductor 304C with the substrate 806C and the substrate 806D, respectively, the top interfaces of the superconductor 304A and the superconductor 304C are changed, and the superconductor 304A and the superconductor 304C can be protected from oxidation due to exposure to air.

[0143] To provide context for different aspects of the disclosed subject matter, Figure 21The following discussion is intended to provide a general description of a suitable environment in which aspects of the disclosed subject matter may be implemented. For example, the operating environment 2100 may be used to implement various aspects of the example, non-limiting computer-implemented methods that assist in implementing Figure 12 and 13 the vertical Josephson junction superconducting device of

[0144] Figure 21 A block diagram of an example non-limiting operating environment in which one or more embodiments described herein may be facilitated is shown. For the sake of brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. Referring to Figure 21 , a suitable operating environment 2100 for implementing various aspects of the present disclosure may also include a computer 2112. The computer 2112 may also include a processing unit 2114, a system memory 2116, and a system bus 2118. The system bus 2118 couples system components, including but not limited to the system memory 2116, to the processing unit 2114. The processing unit 2114 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit 2114. The system bus 2118 may be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE1394), and Small Computer System Interface (SCSI).

[0145] The system memory 2116 may also include volatile memory 2120 and non-volatile memory 2122. The basic input / output system (BIOS) is stored in the non-volatile memory 2122, which contains basic routines such as those for transferring information between elements within the computer 2112 during startup. By way of illustration and not limitation, the non-volatile memory 2122 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). The volatile memory 2120 may also include random access memory (RAM) that acts as an external cache. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

[0146] The computer 2112 may also include removable / non-removable, volatile / non-volatile computer storage media. Figure 21 For example, a magnetic disk storage device 2124 is shown. The magnetic disk storage device 2124 may also include, but is not limited to, devices such as disk drives, floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash cards, or memory sticks. The disk storage 2124 may also include storage media, separately or in combination with other storage media, including but not limited to optical disk drives such as compact disk ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital versatile disk ROM drives (DVD-ROM). To facilitate connecting the disk storage 2124 to the system bus 2118, a removable or non-removable interface, such as interface 2126, is typically used. Figure 21 Software that acts as an intermediary between a user and the basic computer resources described in a suitable operating environment 2100 is also depicted. Such software may also include, for example, an operating system 2128. The operating system 2128, which may be stored on the magnetic disk memory 2124, is used to control and allocate the resources of the computer 2112.

[0147] System application 2130 utilizes operating system 2128 to manage resources through program modules 2132 and program data 2134 stored, for example, in system memory 2116 or disk storage 2124. It should be understood that the present disclosure can be implemented with different operating systems or combinations of operating systems. A user inputs commands or information into computer 2112 through input device 2136. Input device 2136 includes, but is not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, dish satellite antenna, scanner, TV tuner card, digital camera, digital video camera, web camera, etc. These and other input devices are connected to processing unit 2114 via interface port 2138 through system bus 2118. Interface port 2138 includes, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output device 2140 uses some of the same type of ports as input device 2136. Thus, for example, a USB port can be used to provide input to computer 2112 and output information from computer 2112 to output device 2140. Output adapter 2142 is provided to account for output devices 2140 that require special adapters, such as monitors, speakers, and printers, as well as other output devices 2140. By way of illustration and not limitation, output adapter 2142 includes video and sound cards that provide connection means between output device 2140 and system bus 2118. It should be noted that other devices and / or device systems provide both input and output capabilities, such as remote computer 2144.

[0148] Computer 2112 can operate in a networked environment using a logical connection to one or more remote computers, such as remote computer 2144. The (one or more) remote computers 2144 can be computers, servers, routers, network PCs, workstations, microprocessor-based appliances, peer devices, or other common network nodes, etc., and generally can also include many or all of the elements described relative to computer 2112. For the sake of brevity, only the memory storage device 2146 of the remote computer 2144 is shown. The remote computer 2144 is logically connected to the computer 2112 through a network interface 2148 and then physically connected via a communication connection 2150. The network interface 2148 includes wired and / or wireless communication networks such as local area networks (LANs), wide area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN)) and its variants, packet-switched networks, and Digital Subscriber Line (DSL). The communication connection 2150 refers to the hardware / software used to connect the network interface 2148 to the system bus 2118. Although the communication connection 2150 is shown inside the computer 2112 for clarity of illustration, it can also be outside the computer 2112. The hardware / software for connecting to the network interface 2148 can also include (for illustrative purposes only) internal and external technologies, such as modems including conventional telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0149] The present invention can be a system, method, apparatus, and / or computer program product at any possible level of integrated technical detail. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to execute aspects of the present invention. The computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium can be, by way of example and not limitation, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer-readable storage medium can further include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium should not be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0150] The computer-readable program instructions described herein can be downloaded to a corresponding computing / processing device from a computer-readable storage medium or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device. The computer-readable program instructions for carrying out operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages (such as Smalltalk, C++, etc.) and procedural programming languages (such as the "C" programming language or similar programming languages). These computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, an electronic circuit (including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA)) can execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit for performing aspects of the present invention.

[0151] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium having instructions stored therein comprises an article of manufacture including instructions for implementing aspects of the functions / acts specified in one or more blocks of the flowchart and / or block diagram. The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0152] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to different embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a segment, or a portion of an instruction, which comprises one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a system based on dedicated hardware that performs the specified functions or acts or a combination of dedicated hardware and computer instructions.

[0153] Although the subject matter has been described above in the general context of computer-executable instructions of a computer program product running on one or more computers, those skilled in the art will recognize that the present disclosure may also or may be implemented in conjunction with other program modules. In general, program modules include routines, programs, components, data structures, etc., which perform specific tasks and / or implement specific abstract data types. Additionally, those skilled in the art will recognize that the computer-implemented methods of the present invention may be practiced with other computer system configurations, including single-processor or multi-processor computer systems, minicomputers, mainframe computers, and computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronic products, etc. However, some aspects of the present disclosure, if not all, may be practiced on a stand-alone computer. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0154] As used in this application, the terms "component", "system", "platform", "interface", etc. may refer to and / or may include computer-related entities or entities related to an operating machine with one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an executing thread, a program, and / or a computer. By way of illustration, both an application running on a server and the server may be components. One or more components may reside within a process and / or an executing thread, and a component may be located on one computer and / or distributed between two or more computers. In another example, corresponding components may execute from different computer-readable media having different data structures stored thereon. Components may communicate via local and / or remote procedure calls, such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with a local system, another component in a distributed system, and / or interacting with other systems across a network, such as the Internet). As another example, a component may be a device having a specific function provided by a mechanical component operated by an electrical or electronic circuit, which is operated by a software or firmware application executed by a processor. In such a case, the processor may be inside or outside the device and may execute at least a portion of the software or firmware application. As yet another example, a component may be a device that provides a specific function through an electronic component without mechanical components, where the electronic component may include a processor or other means for executing software or firmware, which at least partially imparts the function of the electronic component. In one aspect, a component may be emulated via a virtual machine within, for example, a cloud computing system.

[0155] In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any natural inclusive arrangement. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing instances. Further, the articles "a" and "an" as used in this specification and the drawings are generally to be construed to mean "one or more" unless otherwise specified or clear from the context as being directed to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. To avoid doubt, the subject matter disclosed herein is not limited by such examples. Further, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it intended to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0156] As used in this specification, the term "processor" can refer to substantially any computing processing unit or device, including but not limited to a single-core processor; a single processor with software multithreaded execution capabilities; a multi-core processor; a multi-core processor with software multithreaded execution capabilities; a multi-core processor with hardware multithreaded technology; a parallel platform; and a parallel platform with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a processor can utilize nanoscale architectures such as, but not limited to, molecule- and quantum-dot-based transistors, switches, and gates in order to optimize space usage or enhance the performance of a user device. A processor can also be implemented as a combination of computing processing units. In this disclosure, terms such as "storage", "storage device", "data storage", "data storage device", "database", and substantially any other information storage component related to the operation and functionality of a component are used to refer to "memory components", entities embodied in "memory", or components that include memory. It should be understood that the memory and / or memory components described herein can be volatile memory or non-volatile memory, or can include both volatile memory and non-volatile memory. By way of illustration and not limitation, non-volatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can, for example, act as an external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the memory components of the systems or computer-implemented methods disclosed herein are intended to include, but not be limited to, including these and any other suitable types of memory.

[0157] The foregoing content only includes examples of systems and computer-implemented methods. Of course, for the purpose of describing the present disclosure, it is impossible to describe every conceivable combination of components or computer-implemented methods, but those of ordinary skill in the art will recognize that many further combinations and permutations of the present disclosure are possible. In addition, insofar as the terms "including", "having", "owning", etc. are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term "comprising", as "comprising" is construed when used as a transitional word in a claim.

[0158] The description of the different embodiments has been presented for purposes of illustration, but the description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be obvious to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or technical improvements found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A chip surface substrate device structure, comprising: A first superconducting material physically coupled to a crystal substrate, wherein the crystal substrate is physically coupled to a second superconducting material, and wherein the second superconducting material is physically coupled to a second crystal substrate; A vertical Josephson junction located in a through-hole of the crystal substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material; and A transmon qubit, comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material, the capacitor having a top capacitor pad and a bottom capacitor pad; Wherein the top capacitor pad is the first superconducting material disposed above the crystal substrate, and the bottom capacitor pad is the second superconducting material disposed below the crystal substrate.

2. The chip surface substrate device structure of claim 1, wherein at least a portion of the second superconducting material is located outside the transmon qubit and serves as an information transfer circuit.

3. The chip surface substrate device structure of claim 2, wherein at least a portion of the second superconducting material located outside the transmon qubit is covered by the crystal substrate.

4. The chip surface substrate device structure of claim 1, further comprising: An information transfer circuit in the second superconducting material, the information transfer circuit being communicatively coupled to the transmon qubit.

5. The chip surface substrate device structure of claim 1, further comprising: An information transfer circuit that electrically couples the transmon qubit to one or more other qubits and / or input / output circuits; and Wherein the information transfer circuit is formed on the second superconducting material.

6. The chip surface substrate device structure of claim 2, wherein, The information transfer circuit includes a resonant bus; and further includes using a second capacitor to communicatively couple the transmon qubit to the resonant bus.

7. The chip surface substrate device structure of claim 6, wherein the resonant bus is covered by the crystal substrate.

8. A method of manufacturing a chip surface substrate device structure, comprising: Physically coupling a first superconducting material to a crystal substrate; Physically coupling the crystal substrate to a second superconducting material, wherein the second superconducting material is physically coupled to a second crystal substrate; Forming a vertical Josephson junction in a through-hole of the crystal substrate, the vertical Josephson junction comprising the first superconducting material, a tunnel barrier, and the second superconducting material; and Forming a transmon qubit, the transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material, the capacitor having a top capacitor pad and a bottom capacitor pad; Wherein the top capacitor pad is the first superconducting material disposed above the crystal substrate, and the bottom capacitor pad is the second superconducting material disposed below the crystal substrate.

9. The method of claim 8, further comprising: Removing a portion of the crystal substrate such that an edge of the crystal substrate is within an edge of the second superconducting material.

10. The method of claim 8, further comprising: Remove a portion of the first superconducting material such that an edge of the first superconducting material is flush with an edge of the crystal substrate.

11. The method of claim 8, further comprising: Remove a portion of the first superconducting material such that an edge of the first superconducting material is within an edge of the crystal substrate.

12. The method of claim 8, further comprising: Remove a portion of the first superconducting material such that an edge of the first superconducting material extends beyond an edge of the second superconducting material.

13. The method of claim 8, further comprising: Electrically couple a resonator to a first side of the first superconducting material or the second superconducting material.

14. The method of claim 8, further comprising: Electrically couple a plurality of resonators to a plurality of sides in a group consisting of the first superconducting material and the second superconducting material.

15. The method of claim 8, wherein a portion of the second superconducting material that is external to the vertical Josephson junction is exposed to air.

16. A chip surface substrate device structure, comprising: A vertical Josephson junction formed in a through hole of a crystal substrate, the vertical Josephson junction comprising a first superconducting material physically coupled to a tunnel barrier, the tunnel barrier physically coupled to a second superconducting material; and A transmon qubit, comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material, the capacitor having a top capacitor pad and a bottom capacitor pad; Wherein, the top capacitor pad is the first superconducting material disposed above the crystal substrate, and the bottom capacitor is the second superconducting material disposed below the crystal substrate.

17. The chip surface substrate device structure of claim 16, further comprising: A readout resonator, which is electrically coupled to and addresses the transmon qubit of the chip surface substrate device structure.

18. The chip surface substrate device structure of claim 16, further comprising: Another superconducting qubit; And A resonant bus that electrically couples the transmon qubit and the another superconducting qubit.

19. The chip surface substrate device structure of claim 16, further comprising: A second transmon qubit formed by the first superconducting material and the crystal substrate, the second transmon qubit being isolated from crosstalk with the transmon qubit.

20. The chip surface substrate device structure of claim 19, further comprising: A resonant bus that electrically couples the transmon qubit and the second transmon qubit.

21. A method of manufacturing a chip surface substrate device structure, comprising: Form a vertical Josephson junction in a through hole of a crystal substrate, the vertical Josephson junction comprising a first superconducting material physically coupled to a tunnel barrier, the tunnel barrier physically coupled to a second superconducting material; and Form a transmon qubit, the transmon qubit comprising the vertical Josephson junction and a capacitor formed between the first superconducting material and the second superconducting material, the capacitor having a top capacitor pad and a bottom capacitor pad; Wherein, the top capacitor pad is a first superconducting material disposed above the crystal substrate, and the bottom capacitor pad is a second superconducting material disposed below the crystal substrate.

22. The method of claim 21, further comprising: Covering a portion of the second superconducting material that is outside the vertical Josephson junction with the crystal substrate.

23. The method of claim 21, further comprising: Forming the first superconducting material such that an edge of the first superconducting material extends beyond an edge of the crystal substrate.

24. The method of claim 21, further comprising: A plurality of other superconducting qubits and a plurality of resonator buses, wherein each resonator bus electrically couples the transmon qubit to one or more of the plurality of other superconducting qubits.

25. A chip surface substrate device structure, comprising: A vertical Josephson junction formed in a via hole of a silicon-on-metal (SOM) substrate, wherein the SOM includes a superconductor; and A transmon qubit, including the vertical Josephson junction and a capacitor formed between a portion of the superconductor of the SOM and a second superconducting material, the capacitor having a top capacitor pad and a bottom capacitor pad; Wherein, the top capacitor pad is a superconductor of the SOM disposed on one side of the vertical Josephson junction, the second superconducting material is located on the other side of the vertical Josephson junction, and the bottom capacitor pad is the second superconducting material.

Images