Vertical transmon qubit device with microstrip waveguide

Abstract

A chip surface substrate device structure (200) comprising a superconducting material (214A) on a first side of a substrate (106A, 106B), and a second superconducting material (104) on a second side of the substrate and stacked on a second substrate (102), wherein the first side of the substrate and the second side of the substrate are opposite sides. In one embodiment, the substrate or the second substrate, or the substrate and the second substrate is crystalline silicon. In one embodiment, the chip surface substrate device structure further comprises a transmon qubit comprising a capacitor and a Josephson junction, the Josephson junction formed in a via of the substrate and comprising a tunnel barrier. In one embodiment, the chip surface substrate device structure further comprises a microstrip line electrically coupled to the transmon qubit.

Description

BACKGROUND

[0001] The present invention relates generally to superconducting devices, and more specifically to fabricating vertical transmon qubit devices with microstrip waveguides using silicon-on-metal (SOM) substrates.

[0002] Quantum computing generally uses quantum mechanical phenomena for the purpose of performing computational and information processing functions. Quantum computing can be viewed as being opposite to classical computing, which generally operates on binary values using transistors. That is, a classical computer can operate on bit values of 0 or 1, while a quantum computer operates on quantum bits that include a superposition of 0 and 1, can entangle multiple quantum bits, and uses interference.

[0003] Quantum computing hardware can differ from classical computing hardware. In particular, superconducting quantum circuits generally rely on Josephson junctions, which can be fabricated in semiconductor devices. A Josephson junction generally demonstrates the Josephson effect of supercurrent, in which current can flow through a Josephson junction without an applied voltage. A Josephson junction can be created by weakly coupling two superconductors (sometimes referred to as superconducting materials; materials that conduct electricity without resistance) such as by a tunnel barrier as described below.

[0004] One way that a Josephson junction can be used for quantum computing is by using the Josephson junction to form a qubit. A Josephson junction can be used to form a qubit by arranging the Josephson junction in parallel with a shunt capacitor. In the special case where the shunt capacitor has a large capacitance such that the typical ratio of Josephson energy to charging energy in the qubit is greater than 10, this arrangement of a Josephson junction in parallel with a shunt capacitor is sometimes referred to as a transmon (which is a shortened version of the phrase transmission line shunted plasma oscillation qubit). Those skilled in the art generally understand that a smaller ratio of Josephson and charging energy can not be referred to as a transmon, but for the purposes of the present invention, a transmon can refer to any arrangement of a Josephson junction in parallel with a shunt capacitor.

[0005] Transmons generally have reduced sensitivity to charge noise compared to some other types of qubits. One mechanism by which a transmon reduces sensitivity to charging noise is by increasing the ratio of Josephson energy to charging energy.

[0006] A problem with some prior art transmon qubits is that they occupy a relatively large amount of space. In particular, planar capacitors used in some transmon qubits occupy a large area. Compactness of such transmon qubits is limited by surface and dielectric losses.

[0007] Then, some types of prior art Josephson junctions also present problems when applied to transmons generated from these Josephson junctions. One type of Josephson junction with low loss and low critical current can be made from shadow-evaporated aluminum, aluminum oxide, and aluminum (Al-AlOx-Al). However, this Josephson junction has the problem that once the Josephson junction is formed, the resulting device is constrained by low temperature and process.

[0008] Additionally, transmon qubits utilizing vertical Josephson junctions often must be designed differently in order to be coupled to other microwave resonators and / or circuits. Encapsulated superconducting qubit elements in the prior art are often avoided due to losses associated with deposited dielectrics.

[0009] For vertical transmon qubits on a SOM, while coplanar waveguides can work for circuits on the bottom superconductor layer, this approach can not work for the top superconductor layer because the bottom metal layer is too close to this top layer in the SOM substrate. Thus, in other transmon qubits, only one metal level is used to define a resonator thereon, and specifically, the bottom metal layer is used to define a coupling circuit.

[0010] Additionally, in other approaches for transmon qubits, to form circuits or create resonators, it is necessary to access the buried metal by etching down to the buried metal of the SOM. SUMMARY

[0011] The following presents a summary to provide a basic understanding of one or more embodiments of the application. This summary is not intended to identify key or critical elements, or delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, devices, systems, chip surface substrate device structures, computer- implemented methods, apparatuses, and / or computer program products that facilitate vertical transmon qubit devices are described.

[0012] According to one embodiment, a chip surface substrate device structure is provided. In one example, the chip surface substrate device structure includes a superconducting material on a first side of a substrate; and a second superconducting material on a second side of the substrate and stacked on a second substrate, where the first side of the substrate and the second side of the substrate are opposite sides. In one or more implementations, the chip surface substrate device structure can further include a transmon qubit including: a capacitor; and a Josephson junction formed in a via of the substrate and including a tunnel barrier. In one or more implementations, the chip surface substrate device structure can further include a microstrip line formed from a portion of the superconducting material and electrically coupled to the transmon qubit.

[0013] Such a transmon qubit can have the advantage of providing easier and more options for electrical coupling. In particular, this advantage can be manifested in the ability to couple such a vertical transmon capacitively to a top layer microstrip line.

[0014] In some examples, the microstrip line includes a communication line that communicatively couples the transmon qubit with another device. Such a transmon qubit can have the advantage of providing easier and more options for electrical coupling. For example, this advantage can be manifested in the ability to couple such a vertical transmon capacitively to a top layer microstrip line.

[0015] In another embodiment, a method is provided. In one example, the method includes attaching a superconducting material to a first side of a substrate including crystalline silicon. The method can further include attaching a second superconducting material to a second side of the substrate, the first side and the second side being opposite sides, where the second superconducting material is attached to a second substrate including crystalline silicon. The method can further include forming a Josephson junction having at least one superconducting contact on the first side of the substrate; forming a transmon qubit from the Josephson junction and a capacitor; and electrically coupling a microstrip line to the transmon qubit. Such a transmon qubit can have the advantage of providing easier and more options for electrical coupling. In particular, this advantage can be manifested in the ability to couple such a vertical transmon capacitively to a top layer microstrip line.

[0016] In some examples of the method, the microstrip line is electrically coupled to one or more transmon qubits, and the microstrip line includes a portion of the superconducting material. Such a transmon qubit can have the advantage of providing easier and more options for electrical coupling. For example, this advantage can be manifested in the ability to couple such a vertical transmon capacitively to a top layer microstrip line.

[0017] In another embodiment, a chip surface substrate device structure is provided. In one example, the chip surface substrate device structure includes a crystalline silicon substrate attached to a superconducting material and a second superconducting material, the superconducting material and the second superconducting material attached to opposite sides of the crystalline silicon substrate, and a second crystalline substrate attached to the second superconducting material. In one or more implementations, the chip surface substrate device structure can further include a transmon qubit including a Josephson junction having a tunnel barrier, where the Josephson junction is located in a via of the crystalline silicon substrate. In one or more implementations, the chip surface substrate device structure can further include a microstrip line electrically coupled to the transmon qubit. Such a transmon qubit can have the advantage of providing easier choices for electrical coupling and more choices for electrical coupling. In particular, this advantage can be manifested in the ability to capacitively couple such a vertical transmon to a top layer microstrip line.

[0018] In some examples, a microstrip line is electrically coupled to one or more transmon qubits, and the microstrip line includes a portion of the superconducting material. Such a transmon qubit can have the advantage of providing easier choices for electrical coupling and more choices for electrical coupling. For example, this advantage can be manifested in the ability to capacitively couple such a vertical transmon to a top layer microstrip line.

[0019] In another embodiment, a method is provided. In one example, the method includes attaching a substrate including crystalline silicon to a superconducting material and a second superconducting material, the superconducting material and the second superconducting material attached to opposite sides of the substrate, and a second substrate including crystalline silicon attached to the second superconducting material. The method can further include forming a transmon qubit including a Josephson junction having at least one superconducting contact on a first side of the substrate. The method can further include electrically coupling a microstrip line to the transmon qubit. Such a transmon qubit can have the advantage of providing easier choices for electrical coupling and more choices for electrical coupling. In particular, this advantage can be manifested in the ability to capacitively couple such a vertical transmon to a top layer microstrip line.

[0020] In another embodiment, a chip surface substrate device structure is provided. In one example, the chip surface substrate device structure includes a silicon-on-metal (SOM) substrate. In one or more implementations, the chip surface substrate device structure can also include a transmon qubit including a Josephson junction formed in a via of the SOM substrate. In one or more implementations, the chip surface substrate device structure can also include a superconducting material coupled to the SOM substrate. In one or more implementations, the chip surface substrate device structure can also include a microstrip line electrically coupled to the transmon qubit. Such a transmon qubit can have the advantage of providing easier options for electrical coupling and more options for electrical coupling. In particular, this advantage can be manifested in the ability to couple such a vertical transmon capacitively to a top layer microstrip line. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 An example non-limiting chip surface substrate device structure including a vertical Josephson junction is shown in accordance with one or more embodiments described herein.

[0022] Figure 2 A cross-sectional view of a portion of the example non-limiting chip surface substrate device structure of Figure 1 after removal of some material to form a transmon qubit with a top surface microstrip waveguide in accordance with one or more embodiments described herein.

[0023] Figure 3 A top view of the example non-limiting chip surface substrate device structure of Figure 2 in accordance with one or more embodiments described herein.

[0024] Figure 4 A cross-sectional view of a portion of the example non-limiting chip surface substrate device structure of Figure 3 in accordance with one or more embodiments described herein.

[0025] Figure 5 Another cross-sectional view of a portion of the example non-limiting chip surface substrate device structure of Figure 3 in accordance with one or more embodiments described herein.

[0026] Figure 6 Another cross-sectional view of a portion of the example non-limiting chip surface substrate device structure of Figure 3 in accordance with one or more embodiments described herein.

[0027] Figure 7A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein. Figure 1 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein.

[0028] Figure 8 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein. Figure 7 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein.

[0029] Figure 9 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein. Figure 8 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein.

[0030] Figure 10 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein. Figure 8 A cross-sectional view showing a portion of an exemplary non-limiting chip surface base device structure of a transmon qubit with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein.

[0031] Figure 11 A flow diagram of an exemplary non-limiting computer-implemented method that facilitates implementing a vertical transmon qubit device with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein.

[0032] Figure 12 A flow diagram of an exemplary non-limiting computer-implemented method that facilitates implementing a vertical transmon qubit device with a microstrip waveguide on a SOM substrate is shown in accordance with one or more embodiments described herein.

[0033] Figure 13 A block diagram of an exemplary non-limiting operating environment in which one or more embodiments described herein can be facilitated is shown. DETAILED DESCRIPTION

[0034] The following detailed description is merely illustrative and is not intended to limit embodiments and / or the application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections or in the Detailed Description section.

[0035] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which like references symbols will be used to indicate like parts and in which: In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It can be evident, however, that embodiments of the present application can be practiced without some or all of these specific details. In other instances, processes, structures, materials, and combinations, that would be known by one of ordinary skill in the art have not been described in detail in order to avoid unnecessarily obscuring the intended

[0036] In view of the above-defined problems with electrical coupling circuits for prior art transmon qubits, the present disclosure can be implemented to produce a solution to one or more of these problems in the form of a vertical transmon qubit device with microstrip waveguides on a SOM substrate. As used herein, some embodiments describing a transmon qubit device (or Josephson junction) can refer to a vertical transmon qubit device (or vertical Josephson junction). Such a transmon qubit can have the advantage of providing easier options for electrical coupling and more options for electrical coupling. In particular, this advantage can be manifested in the ability to capacitively couple such a vertical transmon to a top layer microstrip line. Similar approaches (and advantages) can be found with respect to planar transmons.

[0037] An advantage of such a transmon qubit is that it allows for the bottom ground plane to be set to a reference for the transmon qubit and the microstrip line. This advantage extends to the ability to set the bottom ground plane to zero potential (i.e., ground potential) through a moat connection. Additionally, an advantage of such a transmon qubit is the ability to isolate circuitry on the chip edge with a moat to improve signal integrity.

[0038] Figure 1 An exemplary non-limiting chip surface base device structure including a vertical Josephson junction is shown in accordance with one or more embodiments described herein. The chip surface base device structure 100 includes a substrate 102, a superconductor 104, a substrate 106A, a substrate 106B, a superconductor 108, a tunnel barrier 110, a superconductor 112, and a superconductor 114. Exemplary materials and details of exemplary fabrication techniques are described below and in U.S. Patent Application 15 / 934,400, filed March 23, 2018.

[0039] In this arrangement of the chip surface base device structure 100, the superconductor 114 can be considered to be on a first side of the substrate 106A and the substrate 106B. The superconductor 104 can then be considered to be on a second side of the substrate 106A and the substrate 106B. The first side of the substrate 106A and 106B and the second side of the substrate 106A and 106B can be considered to be opposite sides of the substrate 106A and 106B.

[0040] In some examples, the substrate 102 can have an initial thickness of approximately 500 micrometers (pm) to 800 pm. Then, in some examples, the various materials used can be used at temperatures up to approximately 500 degrees Celsius (°C). In some examples, materials with lower melting points, such as aluminum (Al), can be used, and these materials can start to deform at approximately 300 °C.

[0041] It can be appreciated that some similar components of the chip surface base device structure 100 are in contact with each other, such as the superconductor 104 and the superconductor 108, the superconductor 112 and the superconductor 114. It can be appreciated that this is a logical description. In some embodiments, these contacting superconductors can be the same material and can be deposited in one step. In other embodiments, these contacting superconductors can be different (or still the same) materials deposited in separate steps.

[0042] The vertical Josephson junction of the chip surface base device structure 100 includes the tunnel barrier 110, the superconductor 108 (and optionally in combination with the superconductor 104) as a first electrode of the vertical Josephson junction, and the superconductor 112 (and optionally in combination with the superconductor 114) as a second electrode of the vertical Josephson junction. In some examples, the thickness of the superconductor of the first electrode and the thickness of the superconductor of the second electrode are approximately the same. This thickness can be greater than 100 nm.

[0043] In examples where the same superconducting material is used for both the first electrode and the second electrode, the superconducting gap on each side of the tunnel barrier can be equal, which can be used to determine a critical current (the critical current generally identifies the maximum supercurrent that can flow through a Josephson junction). The value of the critical current in a vertical Josephson junction can be based on the materials used and the surface area of those materials in the junction. Multiple vertical Josephson junctions can be created based on the type of materials used, the thickness of those materials, and the size of the opening of the vertical Josephson junction, where the critical current associated between these vertical Josephson junctions is more reproducible.

[0044] Another metric associated with a vertical Josephson junction can be the thickness of the material in the vertical Josephson junction that is not penetrated by a magnetic field. When aluminum (Al) is used as the material in the layer, the thickness of this material can be 100-200 nm. Tungsten (W) can be another material used, and has different properties than Al when applied to the penetration of a magnetic field.

[0045] The vertical Josephson junction can be formed in a via of a substrate layer, which includes the substrate 106A and the substrate 106B, and can initially contain the substrate in which the superconductor 108, the tunnel barrier 110, and the superconductor 112 reside. This via can be produced by etching into the substrate. In some examples, an etch lithography can be implemented to etch the via, where the depth of the via is 100-200 nm. In some examples, a 1 : 1 aspect ratio between the height and width of the via can be achieved. In some examples, the superconductor 108 can be omitted, such that the tunnel barrier 110 is in direct contact with the superconductor 104.

[0046] It can be appreciated that the chip-surface substrate device structure 100 presents one of several embodiments of a vertical Josephson junction that can be utilized in a vertical transmon qubit, in accordance with the technology of the present disclosure. For example, there can be an embodiment of a vertical Josephson junction that omits the superconductor 108, such that the tunnel barrier 110 is in contact with the superconductor 104. For example, there can also be an embodiment of a vertical Josephson junction that omits the superconductor 112 (the superconductor 108 is correspondingly thicker), with the tunnel barrier being placed at the "top" of the via - at the end of the via that is opposite the superconductor 104.

[0047] In some examples, the tunnel barrier 110 can be deposited on the chip-surface substrate device structure 100 using a sputtering method, an evaporation method, an atomic layer deposition (ALD) method, or growth or chemical modification (e.g., oxidation) of the superconductor 104 or 108. In some examples, the tunnel barrier 110 can be aluminum oxide (AI2O3), a non-superconducting metal (sometimes referred to as a "normal" metal), an oxide, or a nitride. In some examples, the tunnel barrier 110 can be formed by oxidation of the exposed surface (after etching) of the superconductor 104 or the superconductor 108. In general, the tunnel barrier layer can be a thin layer of a non-conducting material.

[0048] The chip-surface substrate device structure 100 can be considered to be the result of a buried metal flow. Then, before or after attaching the substrate 106, the superconductor 104, and the substrate 102 together, a top substrate layer including the substrate 106A and the substrate 106B can be ground to a thickness of about 100-200 nm. In some examples, the superconductor 104, as well as other superconductors described herein, can be titanium (Ti), tantalum (Ta), or titanium nitride (TiN).

[0049] In some examples, one or more of the superconductors described herein can be niobium (Nb) or aluminum (Al). Considerations regarding the properties of certain materials and their placement in the chip-surface substrate device structure, such as the amount of heat treatment involved at the layers of the chip-surface substrate device structure, can influence the selection of materials.

[0050] The cross-sectional side view of the chip-surface substrate device structure 100 shows that the substrate 106A and the substrate 106B are separate. However, it can be appreciated that a hole has been formed in this substrate layer, which is shown in this cross-sectional side view, and that the substrate 106A and the substrate 106B are still connected (e.g., from above, the substrate can appear as if a hole has been formed in the middle of it). Other materials in the cross-sectional side view can be similarly attached, although they appear to be separate in the cross-sectional side view.

[0051] In some examples, one or both of the substrates 102 and 106 can be crystalline silicon (Si). As described herein, using crystalline Si can improve the coherence time of a qubit associated with one of the vertical Josephson junctions. Additionally, in some examples, high resistivity crystalline Si can be used, which can further improve the coherence time of the qubit. In some instances, such crystalline Si can be grown.

[0052] In some examples, a portion of the superconductor 104 is deposited on the substrate 102 and a portion of the superconductor 104 is deposited on the substrate 106. These two portions of the superconductor 104 can then be bonded together to connect the substrate 102, the superconductor 104, and the substrate 106. In other words, after depositing respective portions of the superconductor 104 on the substrate 102 and the substrate 106, respectively, an exposed surface of the first portion of the superconductor 104 can then be bonded to an exposed surface of the second portion of the superconductor 104. In some examples, bonding can be achieved with low temperature annealing or another adhesion method.

[0053] In some examples, these various superconductors - i.e., the superconductor 104, the superconductor 108, the superconductor 112, and the superconductor 114 - can include different types of materials from one another. In other examples, two or more of these various superconductors can be the same type of material. In one embodiment, the superconductor 104 can be Ti, the superconductor 108 can be Ta, the superconductor 112 can be Ta (the same as the superconductor 108), and the superconductor 114 can be TiN. In some examples, the superconductor 112 is deposited to have a greater thickness than the superconductor 104 and / or the superconductor 108, and this increased thickness can facilitate better control of removing some or all of the superconductor 108 layer at a later time.

[0054] Figure 2 FIG. 2 shows a chip-on-substrate device structure after removing some material to form a transmon qubit with a top surface microstrip waveguide, in accordance with one or more embodiments described herein. Figure 1 An example non-limiting chip-on-substrate device structure.

[0055] In Figure 2 , some of the superconductor 114 has been removed to produce the superconductor 214A, the superconductor 214B, and the superconductor 214C. To achieve the removal of material, as Figure 2 indicated, and elsewhere, etching (e.g., etch lithography) can be used. In some examples, the chip-on-substrate device structure 200 is produced from the chip-on-substrate device structure 100 using a mask and a reactive ion etching (RIE) method. In some examples, the superconductor 214A can be used as a superconducting contact on one side of a Josephson junction.

[0056] In one example, the superconductor 214A can have a width of approximately 7.5 micrometers (pm); the superconductor 112, the tunnel barrier 110, and the superconductor 108 can have a width of approximately 100 nanometers (nm); the spacing between the superconductor 214A and the superconductor 214B and between the superconductor 214B and the superconductor 214C can be a distance of approximately 10 pm. The height of the Josephson junction comprising the superconductor 108, the tunnel barrier 110, and the superconductor 112 can be 100-200 nm. Additionally, the substrate 106A and the substrate 106B can have a thickness of 50-300 nm or 20-500 nm, with a corresponding Josephson junction width.

[0057] In this example, the chip surface base device structure 200 contains a grounded qubit (i.e., connected to a ground potential) - as the superconductor 104 is connected to the transmon - and the rest of the chip surface base device structure. That is, the superconductor 104 serves as a ground plane. Utilizing a bottom ground plane in this way can have the advantage of obtaining electrical isolation from crosstalk. The superconductor 214B and the superconductor 214C then serve as top circuit waveguides or microstrip lines.

[0058] These dimensions and metrics have advantages over typical transmons, as the transmons here are smaller. In contrast to such smaller transmons, a typical transmon can have a lateral dimension of 700 pm, which is nearly two orders of magnitude larger than the lateral dimension of the transmons here.

[0059] An advantage of having two layers of superconducting material (as opposed to embodiments having one layer of superconducting material) is that this second layer of superconducting material can become an option for communication with an associated qubit.

[0060] Figure 3 FIG. 1 shows a top view of an exemplary non-limiting chip surface base device structure according to one or more embodiments described herein. Figure 2 FIG. 3 shows a top view of an exemplary non-limiting chip surface base device structure according to one or more embodiments described herein. The substrate 306 comprises the substrate 106A and the substrate 106B. While the chip surface base device structure 200 shows a side view of the chip surface base device structure, the chip surface base device structure 300 shows a corresponding top view of the chip surface base device structure. The chip surface base device structure 300 features a circular capacitor pad shape. With the chip surface base device structure 300, a vertical transmon qubit is formed in a circular shape, and it can be appreciated that the vertical transmon qubit can be formed in other shapes, such as a square shape, a rectangular shape, or an elliptical (oval) shape. In the chip surface base device structure 300, multiple qubits can be connected through the same circuitry.

[0061] Substrate 306 includes a combination of substrate 106A and substrate 106B. While looking at a cross-sectional side view (indicated by dashed line 320), substrate 106A and substrate 106B appear to be separate because they are separated by the transmon qubit in this particular cross-section. Elsewhere, substrate 106A and substrate 106B are connected, and this connection is reflected in substrate 306 in chip-on-substrate device structure 300. Superconductor 214B and superconductor 214C comprise a microstrip waveguide for chip-on-substrate device structure 300.

[0062] Superconductor 314D and superconductor 314E serve as an electrical ground for chip-on-substrate device structure 300 and have a ground electrical potential.

[0063] Chip-on-substrate device structure 300 is marked with three dashed lines, which indicate other cross-sectional views of chip-on-substrate device structure 300. In addition to dashed line 320, two of these dashed lines - dashed line 316 and dashed line 318 - correspond to the cross-sectional regions shown in Figure 4 and 5 respectively.

[0064] Figure 4 A cross-sectional view of a portion of an exemplary, non-limiting chip-on-substrate device structure in accordance with one or more embodiments described herein is shown. Figure 3 Chip-on-substrate device structure 400 represents a cross-sectional view of chip-on-substrate device structure 300 at dashed line 316. In chip-on-substrate device structure 400, superconductor 104 has a ground electrical potential. The distance between superconductor 104 and superconductor 214B can be approximately 100 nm (i.e., the height of substrate 306 can be approximately 100 nm).

[0065] Figure 5 Another cross-sectional view of a portion of an exemplary, non-limiting chip-on-substrate device structure in accordance with one or more embodiments described herein is shown. Figure 3 Chip-on-substrate device structure 500 represents a cross-sectional view of chip-on-substrate device structure 300 at dashed line 318. The height of substrate 306 can be approximately 100 nm, and the height of superconductor 314D is higher than the height of substrate 306, and thus is higher than 100 nm here.

[0066] As can be seen in chip-on-substrate device structure 500, superconductor 104 (sometimes referred to as a buried ground) and superconductor 314D are electrically connected and thus at the same electrical potential, while superconductor 314D is accessible from the "top" of chip-on-substrate device structure 500. Connecting to a buried ground from the top of a chip in this way can have the advantage of avoiding an additional fabrication step to obtain an electrical connection to the buried ground from the top of the chip.

[0067] Figure 6 shows a portion of an exemplary non-limiting chip-surface substrate device structure according to one or more embodiments described herein. Figure 3 shows another cross-sectional view of a portion of an exemplary non-limiting chip-surface substrate device structure. Chip-surface substrate device structure 600 represents a cross-sectional view of chip-surface substrate device structure 300 at dashed line 316, which is further extended in both directions such that dashed line 316 covers the entire length of chip-surface substrate device structure 300.

[0068] In the chip-surface substrate device structure, the height of substrate 306 is about 100 nm. Then, the distance between superconductor 214B and superconductor 314D, and the distance between superconductor 214B and superconductor 314E is much larger than the height of substrate 306, e.g., 10-100 microns.

[0069] This approach can have the advantage of providing different ways to fabricate circuits, as the transmon qubits can be accessed in different ways. For example, in different embodiments, instead of accessing the transmon qubits of chip-surface substrate device structure 600 from superconductor 104 (which can be referred to as a bottom layer), the transmon qubits can also be accessed from superconductor 214A (which can be referred to as a top layer) via, e.g., top layer microstrips formed by superconductor 214B or superconductor 214C.

[0070] Figure 7 shows a portion of an exemplary non-limiting chip-surface substrate device structure according to one or more embodiments described herein. Figure 1 shows an exemplary non-limiting chip-surface substrate device structure. In contrast to chip-surface substrate device structure 200, where an etch is performed to remove portions of the top superconductor layer, here, a similar etch is performed, but the etch is deeper, and portions of the top substrate layer and the superconductor layer underneath it are also removed.

[0071] With respect to chip-surface substrate device structure 100, portions of substrate 106A and substrate 106B are removed, resulting in substrate 706A and substrate 706C, and substrate 706B and substrate 706D, respectively. In addition, portions of superconductor 104 are removed, resulting in superconductor 704A, superconductor 704B, and superconductor 704C.

[0072] The portions of superconductor 104 that have been removed can be referred to as defined gaps between superconductor 704A, superconductor 704B, and superconductor 704C. As shown, defined gap 716A is the defined gap between superconductor 704A and superconductor 704B, and defined gap 716B is the defined gap between superconductor 704B and superconductor 704C.

[0073] Due to its electrical isolation, this arrangement in the chip-surface substrate device structure 700 can be said to result in a floating qubit. Then, in some embodiments, the top surface (comprising the superconductor 214A, the superconductor 214B, and the superconductor 214C) can be patterned differently from the bottom surface (comprising the superconductor 704A, the superconductor 704B, and the superconductor 704C) by etching. This different patterning can be possible because the etching into the bottom plane defines the bottom capacitor of the transmon qubit, and thus a different patterning can be applied to cause this bottom capacitor to have different characteristics.

[0074] Figure 8 A top view of an exemplary non-limiting chip-surface substrate device structure is shown in accordance with one or more embodiments described herein. Figure 7 The chip-surface substrate device structure 800 and the chip-surface substrate device structure 200 differ in that in the chip-surface substrate device structure 800 some of the bottom substrate layers - substrates 102 - are visible, and this corresponds to the material that was removed to produce the chip-surface substrate device structure 700.

[0075] With the chip-surface substrate device structure 800, the vertical transmon qubit is formed in a circular shape, and it can be appreciated that the vertical transmon qubit can be formed in other shapes, such as a square shape, a rectangular shape, or an elliptical (oval) shape. In the chip-surface substrate device structure 800, multiple qubits can be connected through the same circuitry.

[0076] The chip-surface substrate device structure 800 is marked with a dashed line, which represents another cross-sectional view of the chip-surface substrate device structure 800. This dashed line - dashed line 816 - corresponds to the cross-sectional area shown in Figure 9

[0077] Figure 9 A cross-sectional view of a portion of an exemplary non-limiting chip-surface substrate device structure is shown in accordance with one or more embodiments described herein. Figure 8 The chip-surface substrate device structure 900 represents a cross-sectional view of the chip-surface substrate device structure 800 at the point of the dashed line 816. The distance between the superconductor 104 and the superconductor 214B can be approximately 100 nm (i.e., the height of the substrate 806 can be approximately 100 nm).

[0078] Figure 10 A cross-sectional view of a portion of an exemplary non-limiting chip-surface substrate device structure is shown in accordance with one or more embodiments described herein. Figure 8 ​FIG. 10B shows another cross-sectional view of a portion of an exemplary, non-limiting chip-on-substrate device structure. The chip-on-substrate device structure 1000 features a planar Josephson junction, including superconductor 1014B, superconductor 1014C, and tunnel barrier 1016. In the process of forming this planar Josephson junction, superconductor 1014A and superconductor 1014D have been deposited, and superconductor 1014A and superconductor 1014D can be used to electrically couple to microstrip waveguides. A shunt capacitor (not shown to scale) for a transmon qubit can be implemented in superconductor 1014B and superconductor 1014C. In some examples, superconductor 1014B and superconductor 1014C can each function as a superconducting contact on one side of a Josephson junction.

[0079] Additionally, in the chip-on-substrate device structure 1000, some of the top layer of the substrate has been removed, as shown by substrate 1006. It can be noted that while some of the substrate 1006 has been removed, it has not been removed down to the level of the superconductor 104 at any location, so the superconductor 104 is still completely covered by the substrate 1006.

[0080] In the chip-on-substrate device structure 1000, a qubit is implemented by a planar Josephson junction on top of the SOM. External circuitry can then make use of microstrip lines, such as those electrically coupled to superconductor 1014B and / or superconductor 1014C. For example, for a top silicon thickness (tSi) ~ 200 nm, the width (wpmstrip) of a 50-ohm microstrip line is ~ 100 nm.

[0081] Figure 11 A flowchart illustrating an exemplary, non-limiting computer-implemented method of facilitating implementation of a vertical transmon qubit device, in accordance with one or more embodiments described herein, is shown. In some examples, the flowchart 1100 can be implemented by the computer 1312. It can be appreciated that the operations of the flowchart 1100 can be implemented in an order different than that depicted. It can also be appreciated that the operations of the flowchart 1100 can be implemented in an order different than that depicted.

[0082] In non-limiting example embodiments, a computing device (or system) (e.g., the computer 1312) is provided that includes one or more processors and one or more memories storing executable instructions that, when executed by the one or more processors, can facilitate performance of operations as described herein, including as Figure 11 the non-limiting method shown in the flowchart. As a non-limiting example, the one or more processors can facilitate performance of the method by directing or controlling one or more devices operable to perform semiconductor manufacturing.

[0083] As shown byFigure 11 Such transmon qubits produced by the methods depicted can have the advantage of providing easier choices for electrical coupling and more choices for electrical coupling. In particular, this advantage can be manifested in the ability to couple such vertical transmons to top layer microstrip lines.

[0084] Operation 1102 depicts attaching (e.g., by computer 1312) a superconducting material to a first side of a substrate comprising crystalline silicon. Operation 1104 depicts attaching (e.g., by computer 1312) a second superconducting material to a second side of the substrate, the first side and the second side being opposite sides, wherein the second superconducting material is attached to a second substrate comprising crystalline silicon.

[0085] In some examples, attaching the two materials can include physically coupling the two materials to each other, including mechanically or chemically coupling the two materials. In some examples, this physical coupling arrangement can be referred to as the various materials being stacked on top of each other, and can include a SOM base. In some examples, the first substrate comprises crystalline silicon. In some examples, the second substrate comprises crystalline silicon. The crystalline silicon can be used in the process of manufacturing the SOM substrate.

[0086] Operation 1106 depicts forming (e.g., by computer 1312) a Josephson junction comprising a tunnel barrier in a via of the substrate. Operation 1107 depicts forming (e.g., by computer 1312) a capacitor shunting the Josephson junction. Operation 1108 depicts forming (e.g., by computer 1312) a transmon qubit from the Josephson junction and the shunt capacitor.

[0087] In some examples, the transmon qubit is grounded (i.e., connected to a ground potential) through the second superconducting material. For example, in the chip surface base device structure 200, the superconductor 104 can have a ground potential, thereby grounding the transmon qubit formed in part by the superconductor 108, the tunnel barrier 110, and the superconductor 112.

[0088] In some examples, the transmon qubit is electrically isolated (i.e., not physically connected) from a portion of the second superconducting material through a defined gap or interruption in the second superconducting material. For example, in the chip surface base device structure 700, when the transmon qubit is attached to the superconductor 704B, it is electrically isolated from the superconductor 704A and the superconductor 704C, as shown by the defined gap 716A (between the superconductor 704A and the superconductor 704B) and the defined gap 716B (between the superconductor 704B and the superconductor 704C).

[0089] In some examples, the second superconducting material includes a communication line that communicatively (or electrically) couples the transmon qubit with another device. For example, in the chip surface base device structure 200, the superconductor 104 can be used as a communication coupling between a transmon qubit of the chip surface base device structure 200 and another transmon qubit.

[0090] In some examples, the transmon qubit includes a vertical transmon qubit. One example of such a vertical transmon qubit can be found in the chip surface base device structure 200.

[0091] In some examples, the transmon qubit includes a planar transmon qubit that includes a planar overlap Josephson junction and a capacitor. One example of such a planar transmon qubit can be found in the chip surface base device structure 1000, where the planar overlap Josephson junction is formed by the superconductor 1014B, the tunnel barrier 1016, and the superconductor 1014C.

[0092] Operation 1110 illustrates electrically coupling (e.g., by the computer 1312) the microstrip line to the transmon qubit.

[0093] In some examples, the microstrip line is electrically coupled to one or more transmon qubits, and the microstrip line includes a portion of the superconducting material. That is, a portion of the superconducting material can be used as the microstrip line itself.

[0094] In some examples, the isolation trench electrically isolates the microstrip line from a second microstrip line or a second transmon qubit. For example, in the chip surface base device structure 300, the superconductor 104 can have a ground potential. Since the superconductor 314D and the superconductor 314E (possibly in combination with other features) are attached to the superconductor 104, they can have the same ground potential as the superconductor 104. In this arrangement, the superconductor 314D and the superconductor 314E can electrically isolate each of the superconductor 214B and the superconductor 214C, which can each be used as a microstrip line.

[0095] A general method of grounding a ground plane is to expose the buried metal somewhere on the chip surface base device structure to physically connect with external control circuitry. Thus, using an isolation trench can have the advantage of providing a direct connection to this underlying, buried metal. Additionally, providing a trench around the chip edge can have the advantage of improving signal integrity, since there is more electrical isolation from crosstalk.

[0096] A coplanar waveguide can generally include a signal line and a ground potential surrounding it. A microstrip can then generally include a signal line on top of a chip surface base device structure with a ground potential around it that is distanced from (or coupled with) features of the chip surface base device structure. This creates a different impedance, or different microwave mode for the microstrip relative to the coplanar waveguide, and these different characteristics can provide advantages for methods that utilize the microstrip.

[0097] In some examples, a ground potential source is electrically coupled to the isolation trench, where the ground potential source causes the superconducting material to have the ground potential. For example, in the case where the isolation trench (e.g., superconductor 314D and superconductor 314E in chip surface base device structure 600) is attached to the superconducting material (e.g., superconductor 104), then by electrically coupling the ground potential source to the isolation trench, both the isolation trench and the superconducting material can have the ground potential.

[0098] Figure 12 A flowchart illustrating an example, non-limiting, computer-implemented method that facilitates implementing a vertical transmon qubit device in accordance with one or more embodiments described herein is shown. In some examples, flowchart 1200 can be implemented by computer 1312. It can be appreciated that the operations of flowchart 1200 can be implemented in an order different than as depicted. It can also be appreciated that the operations of flowchart 1200 can be implemented in different order than as depicted.

[0099] In a non-limiting example embodiment, a computing device (or system) (e.g., computer 1312) is provided that includes one or more processors and one or more memories storing executable instructions that, when executed by the one or more processors, can facilitate performance of operations as described herein, including non-limiting methods as shown in the flowcharts. Figure 12 As a non-limiting example, the one or more processors can facilitate performance of the methods by directing or controlling one or more devices operable to perform semiconductor manufacturing.

[0100] Such transmon qubits as produced by the methods depicted in Figure 12 This transmon qubit can have advantages that provide for easier selection of electrical couplings and more selection of electrical couplings. In particular, this advantage can be manifested in the ability to couple such vertical transmon capacitors to top layer microstrip lines.

[0101] Operation 1202 describes attaching (e.g., by computer 1312) a substrate including crystalline silicon to a superconducting material and a second superconducting material, the first superconducting material and the second superconducting material attached to opposite sides of the substrate, and the second substrate including crystalline silicon attached to the second superconducting material.

[0102] In some examples, the physical coupling arrangement can be referred to as various materials being stacked on top of one another, and can include a SOM substrate. In some examples, the first substrate includes crystalline silicon.

[0103] Operation 1204 illustrates forming (e.g., by the computer 1312) a transmon qubit including a capacitor of a Josephson junction and a shunt Josephson junction, the Josephson junction having at least one superconducting contact on a first side of a substrate. The superconducting contact can include a physical contact between the Josephson junction and a superconducting material located on the first side of the substrate.

[0104] In some examples, the transmon qubit is grounded through the second superconducting material. For example, in the chip surface substrate device structure 200, the superconductor 104 can have a ground potential, thereby grounding the transmon qubit formed in part by the superconductor 108, the tunnel barrier 110, and the superconductor 112.

[0105] In some examples, the transmon qubit is electrically isolated from a portion of the second superconducting material through a defined gap or interruption in the second superconducting material. For example, in the chip surface substrate device structure 700, when the transmon qubit is attached to the superconductor 704B, it is electrically isolated from the superconductor 704A and the superconductor 704C, as shown by the defined gap 716A (between the superconductor 704A and the superconductor 704B) and the defined gap 716B (between the superconductor 704B and the superconductor 704C).

[0106] In some examples, the microstrip line includes a communication line that communicatively couples the transmon qubit with another device. For example, in the chip surface substrate device structure 200, the superconductor 104 can be used as a communication coupling between the transmon qubit of the chip surface substrate device structure 200 and another transmon qubit.

[0107] In some examples, the transmon qubit includes a vertical transmon qubit. One example of such a vertical transmon qubit can be found in the chip surface substrate device structure 200.

[0108] In some examples, the transmon qubit includes a planar transmon qubit. One example of such a planar transmon qubit can be found in the chip surface substrate device structure 1000.

[0109] Operation 1206 illustrates electrically coupling (e.g., by the computer 1312) a microstrip line to the transmon qubit.

[0110] In some examples, the microstrip line is electrically coupled to the transmon qubit, and the microstrip line includes a portion of the superconducting material. That is, a portion of the superconducting material can be used as the microstrip line itself.

[0111] In some examples, the isolation trench electrically isolates the microstrip line from a second microstrip line or a second transmon qubit. For example, in the chip surface base device structure 300, the superconductor 104 can have a ground potential. Since the superconductor 314D and the superconductor 314E (possibly in combination with other features) are attached to the superconductor 104, they can have the same ground potential as the superconductor 104. In this arrangement, the superconductor 314D and the superconductor 314E can electrically isolate each of the superconductor 214B and the superconductor 214C, which can each be used as a microstrip line.

[0112] In some examples, a ground potential source is electrically coupled to the isolation trench, where the ground potential source causes the superconducting material to have a ground potential. For example, where the isolation trench (e.g., the superconductor 314D and the superconductor 314E in the chip surface base device structure 600) is attached to the superconducting material (e.g., the superconductor 104), then by electrically coupling the ground potential source to the isolation trench, both the isolation trench and the superconducting material can have a ground potential.

[0113] To provide a context for various aspects of the disclosed subject matter, Figure 13 and the following discussion is intended to provide a general description of a suitable environment in which various aspects of the disclosed subject matter can be implemented. For example, the operating environment 1300 can be used to implement aspects of the example, non-limiting computer-implemented method that facilitates implementing Figure 12 and 13 vertical Josephson junction superconducting devices.

[0114] Figure 13 A block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated is shown. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. Reference is made to Figure 13The suitable operating environment 1300 for implementing various aspects of this disclosure may further include a computer 1312. The computer 1312 may further include a processing unit 1314, system memory 1316, and a system bus 1318. The system bus 1318 couples system components, including but not limited to system memory 1316, to the processing unit 1314. The processing unit 1314 may be any of a variety of available processors. Dual microprocessor and other multiprocessor architectures may also be used as the processing unit 1314. The system bus 1318 may be any of several bus architectures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronic Devices (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0115] System memory 1316 may also include volatile memory 1320 and non-volatile memory 1322. The Basic Input / Output System (BIOS), containing basic routines such as transferring information between components within computer 1312 during startup, is stored in non-volatile memory 1322. By way of illustration and not limitation, non-volatile memory 1322 may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory 1320 may also include random access memory (RAM) used as an external cache. By way of illustration and not limitation, RAM can be obtained in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct memory bus RAM (DRRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0116] Computer 1312 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 13A disk storage device 1324 is also shown. A disk storage device 1324 also can include, but is not limited to, devices such as a magnetic disk drive, a soft disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage device 1324 also can include a storage medium, separately or in combination with other storage devices, including, but not limited to, magnetic, magneto-optical drives and / or optical drives such as Compact Disk ROM (CD-ROM), CD recordable (CD-R), CD Rewriteable (CD-RW), or Digital Versatile Disk ROM (DVD-ROM). To facilitate connection of the disk storage device 1324 to the system bus 1318, a removable or non-removable interface is typically used, such as interface 1326. Figure 13 Software is also described that acts as an intermediary between users and the basic computer resources described in the suitable operating environment 1300. Such software can also include, for example, an operating system 1328. The operating system 1328, which can be stored on disk storage 1324, acts to control and allocate resources of the computer 1312.

[0117] System applications 1330 take advantage of the management of the resources by the operating system 1328 through program modules 1332 and program data 1334, such as stored in system memory 1316 or on disk storage 1324. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer 1312 through input device(s) 1336. Input devices 1336 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit 1314 through the system bus 1318 via interface port(s) 1338. Interface port(s) 1338 include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) 1340 use some of the same type of ports as input device(s) 1336. Thus, for example, a USB port can be used to provide input to and output from computer 1312. Output adapter 1342 is provided to illustrate that there are some output devices 1340 like monitors, speakers, and printers, among other output devices 1340, that require special adapters. The output adapters 1342 include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device 1340 and the system bus 1318. It should be noted that other devices and / or systems of devices provide both input and output capabilities such as remote computer(s) 1344.

[0118] The computer 1312 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1344. The remote computer 1344 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based appliance, a peer device or other common network node, and typically includes many or all of the elements described relative to the computer 1312, above. For purposes of brevity, only a memory storage device 1346 is illustrated with the remote computer 1344. The remote computer 1344 is logically connected to the computer 1312 through a network interface 1348 and then physically connected via a communication connection 1350. The network interface 1348 encompasses wire and / or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and others. WAN technologies include, but are not limited to, point-to-point links, circuit-switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet-switching networks, and Digital Subscriber Line (DSL). The communication connection 1350 refers to the hardware / software employed to connect the network interface 1348 to the system bus 1318. While the communication connection 1350 is shown for illustrative clarity inside the computer 1312, it can also be external to the computer 1312. The hardware / software for connecting the network interface 1348 to the system bus 1318 can also include internal and external technologies for wired and / or wireless communication, such as modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

[0119] The present application can be a system, a method, an apparatus, and / or a computer program product at any possible technical detail of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0120] The computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to storage media within the respective computing / processing device for execution by a processor. Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and a procedural programming language such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0121] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0122] The flow diagrams and block diagrams in the drawings are illustrative of possible architectures, functions, and operations for systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flow diagrams and block diagrams can represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0123] While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on one and / or more computers, those skilled in the art will recognize that the disclosure also can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in local and remote memory storage devices.

[0124] As used in this application, the terms “component,” “system,” “platform,” “interface,” and the like can refer to and / or can include a computer-related entity or an entity that is related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one computer and / or across multiple computers. In another example, a component can be a virtual machine executing in a cloud computing system.

[0125] Also, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in the subject specification and annexed drawings should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. As used herein, the term “example” and / or “exemplary” are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “example” and / or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to exclude equivalents of an example structure and / or technology known to those of ordinary skill in the art.

[0126] As employed in this specification, the term "processor" can refer to substantially any computing processing unit or device comprising single-core processors; single-processors with software multithread execution capability; multi- core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can employ nano- scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. Processors can also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components," entities embodied in a memory, or components including memory. It is appreciated that memory and / or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which can be utilized as external cache memory, for example, as an illustration and not a limitation. RAM can be available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0127] The foregoing description includes only examples of the system and computer-implemented method. Of course, not every combination of components or computer-implemented method can be described in order to describe the present disclosure. It will be apparent, however, to those having ordinary skill in the art that many further combinations and permutations of the disclosure are possible. Moreover, as used in the detailed description, claims, appendices and drawings, the terms "include," "have," "possess," and the like are intended to be inclusive in a manner similar to the term "comprise," "comprises," "comprising" and "includes" when utilized in the claims.

[0128] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A chip surface base device structure using a silicon on metal (SOM) substrate, comprising: a superconducting material on a first side of the substrate; a second superconducting material on a second side of the substrate and stacked on a second substrate, wherein the first side of the substrate and the second side of the substrate are opposite sides; a transmon qubit, comprising: a capacitor; and a Josephson junction in parallel with the capacitor, wherein the Josephson junction is formed in a via of the substrate and includes a tunnel barrier; and a microstrip line formed from a portion of the superconducting material and electrically coupled to the transmon qubit, wherein the substrate and the second substrate comprise crystalline silicon; wherein the substrate and the second substrate are not in contact with each other.

2. The chip surface base device structure of claim 1, further comprising: a second device; and an isolation trench electrically isolating the microstrip line from the second device, wherein the second device comprises a second microstrip line or a second transmon qubit.

3. The chip surface base device structure of claim 2, further comprising: a ground potential source electrically coupled to the isolation trench, wherein the ground potential source causes the second superconducting material to have a ground potential.

4. The chip surface base device structure of claim 1, wherein the second superconducting material grounds the transmon qubit.

5. The chip surface base device structure of claim 1, wherein the transmon qubit is electrically isolated from a portion of the second superconducting material by a defined gap in the second superconducting material.

6. The chip surface base device structure of claim 1, wherein the microstrip line comprises a communication line communicatively coupling the transmon qubit with another device.

7. A method of fabricating a chip surface base device structure, comprising: attaching a superconducting material to a first side of a substrate comprising crystalline silicon; attaching a second superconducting material to a second side of the substrate, the first side and the second side being opposite sides, wherein the second superconducting material is attached to a second substrate comprising crystalline silicon; forming a Josephson junction having at least one superconducting contact on the first side of the substrate in a via of the substrate; forming a transmon qubit from a Josephson junction and a capacitor, the Josephson junction being in parallel with the capacitor and including a tunnel barrier; and electrically coupling a microstrip line to the transmon qubit, the microstrip line being formed from a portion of the superconducting material; wherein the substrate and the second substrate are not in contact with each other.

8. The method of claim 7, wherein the microstrip line is electrically coupled to one or more transmon qubits.

9. The method of claim 7, further comprising: forming an isolation trench electrically isolating the microstrip line from a second microstrip line or a second transmon qubit.

10. The method of claim 9, further comprising: ​ a ground potential source is electrically coupled to the isolation trench and causes the second superconducting material to have a ground potential.

11. The method of claim 7, wherein the forming the transmon qubit comprises forming a vertical transmon qubit.

12. The method of claim 7, wherein the forming the transmon qubit comprises forming a planar transmon qubit.

13. A chip-on-surface substrate device structure, comprising: a crystalline silicon substrate attached to a superconducting material and a second superconducting material, the superconducting material and the second superconducting material attached to opposite sides of the crystalline silicon substrate, and a second crystalline silicon substrate attached to the second superconducting material; a transmon qubit comprising a Josephson junction having a tunnel barrier and a shunt capacitor in parallel with the Josephson junction, wherein the Josephson junction is located in a via of the crystalline silicon substrate; and a microstrip line electrically coupled to the transmon qubit, the microstrip line comprising a portion of the superconducting material; wherein the crystalline silicon substrate is not in contact with the second crystalline silicon substrate.

14. The chip-on-surface substrate device structure of claim 13, wherein the microstrip line is electrically coupled to one or more transmon qubits.

15. The chip-on-surface substrate device structure of claim 13, further comprising: an isolation trench electrically isolating the microstrip line from a second microstrip line or a second transmon qubit.

16. The chip-on-surface substrate device structure of claim 15, further comprising: a ground potential source electrically coupled to the isolation trench and causing the second superconducting material to have a ground potential.

17. The chip-on-surface substrate device structure of claim 13, wherein the second superconducting material is a ground potential for the transmon qubit.

18. A method of fabricating a chip-on-surface substrate device structure, comprising: attaching a substrate comprising crystalline silicon to a superconducting material and a second superconducting material, the superconducting material and the second superconducting material attached to opposite sides of the substrate, and a second substrate comprising crystalline silicon attached to the second superconducting material; forming a transmon qubit comprising a capacitor and a Josephson junction in parallel with the capacitor, the Josephson junction formed in a via of the substrate and comprising a tunnel barrier; and electrically coupling a microstrip line to the transmon qubit, the microstrip line comprising a portion of the superconducting material; wherein the substrate is not in contact with the second substrate.

19. The method of claim 18, wherein the microstrip line is electrically coupled to one or more transmon qubits.

20. The method of claim 18, wherein the forming the transmon qubit comprises forming a vertical transmon qubit having the Josephson junction in a via of the substrate.

21. The method of claim 18, wherein forming the transmon qubit comprises forming a planar transmon qubit comprising a planar overlapping Josephson junction and a capacitor.

22. A chip surface substrate device structure, comprising: a silicon-on-metal (SOM) substrate, wherein the metal of the silicon-on-metal substrate is a superconducting metal; a transmon qubit comprising a Josephson junction formed in a via of the silicon-on-metal substrate and a shunt capacitor in parallel with the Josephson junction, wherein the Josephson junction comprises a tunnel barrier; a superconducting material physically attached to the silicon-on-metal substrate; and a microstrip line electrically coupled to the transmon qubit, wherein the microstrip line is formed from a portion of the superconducting material; the silicon-on-metal substrate comprises crystalline silicon.

23. The chip surface substrate device structure of claim 22, wherein the superconducting material is formed on a surface of the silicon-on-metal substrate.

24. The chip surface substrate device structure of claim 22, wherein the superconducting material is formed on a sidewall of the via of the silicon-on-metal substrate.

25. The chip surface substrate device structure of claim 22, wherein the superconducting material is formed on a sidewall of the Josephson junction of the transmon qubit.

26. The chip surface substrate device structure of claim 22, wherein the superconducting material is formed on a sidewall of the shunt capacitor of the transmon qubit.

27. The chip surface substrate device structure of claim 22, wherein the superconducting material is formed on a sidewall of the microstrip line of the transmon qubit.

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