A semiconductor package structure and a manufacturing method thereof

Abstract

The present invention provides a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes: a chip to be encapsulated, which includes a substrate and a metallization layer located on the substrate. Among them, the upper surface of the chip to be encapsulated has alignment marks; a molding layer formed on the upper surface of the chip to be encapsulated. The molding layer includes metal pillars located on the upper surface of the chip to be encapsulated and electrically connected to the metallization layer, a semi-sealed cavity located around the alignment marks, and a molding compound layer covering the metal pillars and the semi-sealed cavity; a redistribution layer located on the upper surface of the molding layer. The redistribution layer includes a dielectric layer and a metal wire layer located on the dielectric layer. By introducing a semi-sealed cavity that can protect the alignment marks from being contaminated, the alignment marks can be directly exposed after molding without other additional processes, providing precise positioning for subsequent processes.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology packaging, and particularly to a semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the trend of multi-functionalization and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to cooperate with the development of the new generation of electronic products, especially the development of products such as smart phones, tablet computers, and ultrabooks, the size of chips is developing in the directions of higher density, faster speed, smaller size, and lower cost. The emergence of fan-out wafer-level packaging technology provides a broader development prospect for the improvement of technology.

[0003] In a fan-out multi-layer packaging structure, the encapsulant used during encapsulation is a light-shielding material. After the encapsulation process is completed, the alignment marks on the previous layer will be blocked, resulting in the inability to find suitable alignment marks that meet the high-precision requirements in subsequent processes such as exposure and etching.

[0004] Therefore, in semiconductor chip packaging, how to accurately align after the encapsulation process is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor packaging structure and a preparation method thereof. By adding a semi-sealed structure, it can block the alignment marks before the encapsulation process, so that after the grinding process, the alignment points can be directly exposed without other additional process steps.

[0006] To achieve the above purpose and other related purposes, the present invention provides a preparation method for a semiconductor packaging structure, and the method at least includes the following steps:

[0007] 1) Provide a chip to be encapsulated with alignment marks. The chip to be encapsulated includes a substrate and a metallization layer located on the substrate. Among them, the alignment marks are located on the upper surface of the metallization layer;

[0008] 2) Deposit metal pillars, which are formed on the upper surface of the chip to be encapsulated and are electrically connected to the metallization layer;

[0009] 3) Fix a semi-sealed cavity; the semi-sealed cavity is a cavity with one open side and other sides closed, and the open side of the semi-sealed cavity is buckled on the alignment marks;

[0010] 4) Encapsulate, and use an encapsulant to completely cover the metal pillars and the semi-sealed cavity to form an encapsulation layer on the metallization layer;

[0011] 5) Grind the encapsulation layer until the upper surface of the metal pillars and the alignment marks are exposed;

[0012] 6) Form a rewiring layer, which includes a dielectric layer and a metal wire layer located above the dielectric layer. Wherein, the upper surface of the metal column is exposed in the dielectric layer, and the metal wire layer is electrically connected to the metal column.

[0013] Optionally, in step 3), the method of fixing the semi-sealed cavity includes mounting.

[0014] Optionally, the mounting step at least includes:

[0015] 3-1) Coat an adhesive on the opening surface of the semi-sealed cavity;

[0016] 3-2) Place the side coated with the adhesive on the alignment mark and bond and fix it to the metallization layer.

[0017] Optionally, the metallization layer includes a dielectric layer and a metal interconnect structure formed in the dielectric layer, and the material of the metal interconnect structure includes any one of copper, aluminum, and titanium.

[0018] Optionally, the upper surface of the metal interconnect structure is flush with or higher than the upper surface of the dielectric layer.

[0019] Optionally, the method for preparing the metal column includes a wire bonding process and an electroplating process.

[0020] Optionally, the material of the metal column includes any one of copper, aluminum, and titanium.

[0021] Optionally, the material of the semi-sealed cavity includes glass, plastic, ceramic, and metal.

[0022] Optionally, the material of the encapsulant includes one of epoxy-based resin, liquid thermosetting epoxy resin, and plastic compound.

[0023] Optionally, the encapsulation includes a compression molding process, a transfer molding process, a liquid encapsulation molding process, a vacuum lamination process, or a spin coating process.

[0024] Optionally, the grinding includes chemical mechanical polishing.

[0025] Optionally, step 6) at least includes the following steps:

[0026] 6-1) Form a dielectric layer on the upper surface of the encapsulation layer, and the dielectric layer fills the semi-sealed cavity and covers the encapsulation layer;

[0027] 6-2) Expose the upper surface of the metal column through a photolithography and etching process;

[0028] (6-3) A metal wire layer is formed on the upper surface of the dielectric layer, and the metal wire layer is electrically connected to the metal posts.

[0029] The present invention also provides a semiconductor package structure, which includes:

[0030] A chip to be packaged, which includes a substrate and a metallization layer located on the substrate. Among them, the upper surface of the metallization layer has alignment marks;

[0031] A plastic encapsulation layer is formed on the upper surface of the chip to be packaged. The plastic encapsulation layer includes metal posts located on the upper surface of the chip to be packaged and electrically connected to the metallization layer, a semi-sealed cavity located around the alignment marks, and a plastic encapsulant layer covering the metal posts and the semi-sealed cavity;

[0032] A redistribution layer is located on the upper surface of the plastic encapsulation layer. The redistribution layer includes a dielectric layer and a metal wire layer located on the dielectric layer. Among them, the dielectric layer exposes the upper surface of the metal posts, and the metal wire layer is electrically connected to the metal posts.

[0033] Optionally, there is also an adhesive layer between the semi-sealed cavity and the metallization layer.

[0034] Optionally, the cross-sectional shape of the semi-sealed cavity includes a circle, a triangle, a square or a hexagon.

[0035] The present invention also provides a method for manufacturing a semiconductor multi-chip package structure. After manufacturing a semiconductor package structure by using the method described in any one of the above, taking the alignment marks on the metallization layer as a reference, bonding at least one second metallization layer to the redistribution layer to form an electrical connection, where the upper surface of the second metallization layer has second alignment marks; continue to repeat steps 2)-6) in the above steps to form a semiconductor multi-chip package structure.

[0036] The present invention also provides a semiconductor multi-chip package structure, which is characterized in that the structure includes at least one second metallization layer bonded on the semiconductor chip package structure described in any one of the above, and the upper surface of the second metallization layer has alignment marks; at least one second plastic encapsulation layer is formed on the upper surface of the second metallization layer. The second plastic encapsulation layer includes second metal posts located on the upper surface of the second metallization layer and electrically connected to the second metallization layer, a second semi-sealed cavity located around the second alignment marks, and a second plastic encapsulant layer covering the second metal posts and the second semi-sealed cavity; at least one second redistribution layer is formed on the upper surface of the second plastic encapsulation layer.

[0037] As described above, in the semiconductor chip package, by introducing a semi-sealed cavity above the alignment mark, the present invention can protect the alignment mark from being blocked by the encapsulant. In subsequent processes, the alignment mark is not exposed by other process means, providing a clearly visible alignment mark for subsequent exposure and lithography processes, and eliminating the problem of alignment failure. Description of the Drawings

[0038] Figure 1 Shown is a flowchart of the preparation of a semiconductor package structure.

[0039] Figure 2 Shown is a schematic diagram of a chip to be encapsulated with alignment marks.

[0040] Figure 3 Shown is a schematic diagram of depositing metal pillars in Embodiment 1.

[0041] Figure 4 Shown is a schematic diagram of mounting a semi-sealed cavity in Embodiment 1.

[0042] Figure 5 Shown is a schematic diagram after encapsulation in Embodiment 1.

[0043] Figure 6 Shown is a schematic diagram after grinding in Embodiment 1.

[0044] Figure 7 Shown is a schematic diagram of forming a redistribution layer in Embodiment 1.

[0045] Figure 8 Shown is a schematic diagram of a semiconductor multi-chip package in Embodiment 2.

[0046] Element Label Description

[0047] 10 Chip to be encapsulated

[0048] 11 Metallization layer

[0049] 12 Encapsulation layer

[0050] 13 Redistribution layer

[0051] 101 Substrate

[0052] 102 Alignment mark

[0053] 111 Dielectric layer

[0054] 112 Metal interconnect structure

[0055] 121 Encapsulant layer

[0056] 122 Semi-sealed cavity

[0057] 123 Metal pillar

[0058] 131 Dielectric layer

[0059] 132 Metal wire layer

[0060] 21 Second metallization layer

[0061] 22 Second encapsulation layer

[0062] 23 Second redistribution layer

[0063] 211 Second dielectric layer

[0064] 212 Second metal interconnect structure

[0065] 221 Second encapsulant layer

[0066] 222 Second semi-sealed cavity

[0067] 223 Second metal post

[0068] 231 Second dielectric layer

[0069] 232 Second metal wire layer

[0070] 202 Second alignment mark Detailed implementation manners

[0071] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] Please refer to Figures 1 to 8 Note that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, number, and ratio of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0073] Embodiment 1

[0074] As Figures 1 to 7 shown, this embodiment provides a semiconductor package structure and a manufacturing method thereof.

[0075] As Figure 7As shown in the figure, the semiconductor packaging structure provided in this embodiment includes: a substrate 101, a metallization layer 11 located on the substrate, an alignment mark 102 marked on the metallization layer, and a molding compound layer 12 located on the upper surface of the metallization layer. The molding compound layer 12 includes metal posts 123 located above the metallization layer and electrically connected to the metallization layer, a semi-sealed cavity 122 located outside the alignment mark 102, and a molding compound layer 121 located above the metallization layer and covering the metal posts and the semi-sealed cavity. A redistribution layer 13 is located above the molding compound layer 12. The redistribution layer 13 includes a dielectric 131 and a metal wire layer 132. The redistribution layer 13 is electrically connected to the metallization layer 11 through the metal posts 123.

[0076] This embodiment also provides a method for manufacturing the semiconductor packaging structure. Please refer to Figure 1 , and the method for manufacturing the semiconductor packaging structure includes the following steps:

[0077] 1) Provide a chip to be packaged with alignment marks. The chip to be packaged includes a substrate and a metallization layer located on the substrate. The alignment marks are located on the upper surface of the chip to be packaged.

[0078] 2) Deposit metal posts, which are formed on the upper surface of the chip to be packaged and are electrically connected to the metallization layer.

[0079] 3) Mount a semi-sealed cavity. The semi-sealed cavity is a cavity with one open side and other sides closed. The open side of the semi-sealed cavity is buckled on the alignment marks.

[0080] 4) Molding: Use a molding compound to completely cover the metal posts and the semi-sealed cavity, and form a molding compound layer on the metallization layer.

[0081] 5) Grinding: Grind the molding compound layer until the upper surface of the metal posts and the alignment marks are exposed.

[0082] 6) Form a redistribution layer. The redistribution layer includes a dielectric layer and a metal wire layer located above the dielectric layer. The dielectric layer exposes the upper surface of the metal posts, and the metal wire layer is electrically connected to the metal posts.

[0083] The technical solution of this embodiment will be further described in detail below with reference to the accompanying drawings.

[0084] As Figure 2 shown, perform step 1). Provide a chip 10 to be packaged with alignment marks. The chip 10 to be packaged includes: a substrate 101, a metallization layer 11 located on the substrate. The metallization layer 11 includes a dielectric layer 111 and metal interconnect structures 112 located in the dielectric layer. The alignment marks 102 are located on the chip to be tested.

[0085] Optionally, the material of the metal interconnect structure includes any one of copper, aluminum, and titanium. The upper surface of the metal interconnect structure is flush with or higher than the upper surface of the dielectric layer.

[0086] Specifically, in this embodiment, copper is used as the material for the metal interconnect structure, and the upper surface of the metal interconnect structure is higher than the upper surface of the dielectric layer.

[0087] As Figure 3 shown, step 2) is performed to deposit the metal pillar 123 to form an electrical connection with the metallization layer 11.

[0088] Optionally, the preparation method of the metal pillar includes an electroplating process and a wire bonding process.

[0089] Optionally, the material of the metal pillar includes any one of copper, aluminum, and titanium.

[0090] As Figure 4 shown, step 3) is performed to mount the semi-sealed cavity 122 so that the semi-sealed cavity is buckled on the alignment mark 102. The semi-sealed cavity can ensure that in the subsequent encapsulation process, the encapsulant will not be poured onto the alignment mark, thereby providing a clear alignment point for the subsequent manufacturing process.

[0091] The semi-sealed cavity is a cavity with one open side and the other sides closed. The semi-sealed cavity can be a three-dimensional structure such as a hemispherical shape or a cylindrical shape. The cross-section of the cavity can be a quadrilateral, a hexagon, a circle, a triangle, or any other shape. The cross-sectional area of the semi-sealed cavity is larger than the surface area of the alignment mark so that the semi-sealed cavity can completely cover the alignment mark and prevent the alignment mark from being contaminated by the encapsulant.

[0092] Optionally, the material of the semi-sealed cavity includes glass, plastic, ceramic, and metal.

[0093] In step 3), the semi-sealed cavity is fixed above the alignment mark by a mounting method. In this embodiment, the mounting method of the semi-sealed cavity includes the following steps:

[0094] 3-1) Coat an adhesive on the open surface of the semi-sealed cavity;

[0095] 3-2) Buckle the surface coated with the adhesive onto the alignment mark and bond and fix it to the metallization layer.

[0096] Therefore, there is still an adhesive layer (not shown) between the fixed semi-sealed cavity and the metallization layer.

[0097] As Figure 5As shown, step 4) is carried out, i.e., encapsulation, to form an encapsulation layer 12 on the surface of the metallization layer. The above structure is encapsulated with an encapsulation material to completely wrap the metal posts 123 and the semi-sealed cavity 122. The upper surface of the formed encapsulation layer 12 after encapsulation is higher than the upper surfaces of the semi-sealed cavity 122 and the metal posts 123. The encapsulation layer 12 includes metal posts 123 located above the metallization layer and electrically connected to the metallization layer, a semi-sealed cavity 122 located outside the alignment mark 102, and an encapsulation material layer 121 located above the metallization layer and covering the metal posts and the cavity walls.

[0098] Optionally, the material used for the encapsulation includes one of epoxy resin, liquid thermosetting epoxy resin, and plastic compound.

[0099] Optionally, the process used for the encapsulation includes compression molding process, liquid sealing molding process, spin coating process, and transfer molding process.

[0100] As Figure 6 shown, step 5) is carried out, i.e., grinding the encapsulation layer 12 until the alignment mark 102 and the metal posts 123 are exposed.

[0101] Optionally, the grinding method includes chemical mechanical polishing.

[0102] As Figure 7 shown, step 6) is carried out, i.e., forming a redistribution layer 13 on the upper surface of the encapsulation layer 12. The redistribution layer 13 includes a dielectric layer 131 and a patterned metal line layer 132 located in the dielectric layer 131. Specifically, the preparation method of the redistribution layer at least includes the following steps:

[0103] 6-1) Depositing a dielectric layer, the dielectric layer filling the holes surrounded by the cavity walls of the semi-sealed cavity and covering the upper surfaces of the encapsulation layer and the metal posts.

[0104] 6-2) Through photolithography and etching, exposing the upper surface of the metal posts,

[0105] 6-3) Forming a metal line layer, through photolithography and etching, forming a patterned metal line layer.

[0106] Optionally, the material of the metal line layer includes any one of copper, aluminum, gold, nickel, and titanium. The metal line layer can be formed by physical vapor deposition, chemical vapor deposition, magnetron sputtering, electroplating, electroless plating, or other processes.

[0107] As described above, the semiconductor package structure and its preparation method provided in this embodiment can protect the alignment mark from being blocked by the encapsulation glue by introducing a semi-sealed cavity above the alignment mark. In subsequent processes that require alignment, the alignment mark can be directly exposed without other additional means.

[0108] Embodiment 2

[0109] This embodiment provides a semiconductor multi-layer chip packaging structure and a manufacturing method. Based on the semiconductor chip packaging structure provided in Embodiment 1, at least one chip is bonded to the redistribution layer in Embodiment 1 to form a semiconductor multi-layer chip packaging structure with multiple chips.

[0110] As an example, as Figure 8 shown, the semiconductor two-layer chip packaging structure provided in this embodiment includes: a second metallization layer 21 located above the structure provided in Embodiment 1. The second metallization layer 21 is electrically connected to the redistribution layer 13 in Embodiment 1. The upper surface of the second metallization layer 21 has a second alignment mark 202; a second plastic encapsulation layer 22 located on the upper surface of the second metallization layer 22. The second plastic encapsulation layer 22 includes a second metal post 223 located above the second metallization layer and electrically connected to the second metallization layer, a second semi-sealed cavity 222 located outside the second alignment mark 202, and a second plastic encapsulation material layer 221 located above the second metallization layer and covering the second metal post and the second semi-sealed cavity. A second redistribution layer 23 is located above the second plastic encapsulation layer 22. Among them, the second redistribution layer 23 includes a second dielectric layer 231 and a second metal wire layer 232. The second redistribution layer 23 is electrically connected to the second metallization layer 21 through the metal post 223. In this embodiment, the same parts as those in the first embodiment are numbered the same and will not be described in detail here.

[0111] The manufacturing method of the semiconductor two-layer chip packaging structure provided in this embodiment includes: by repeating steps 2) to 6) in Embodiment 1 on the basis of the semiconductor chip packaging method provided in Embodiment 1, the semiconductor two-layer chip packaging structure provided in this embodiment can be formed.

[0112] In another example, the manufacturing method of the semiconductor multi-layer chip packaging structure further includes repeatedly performing steps 2) to 6) in Embodiment 1 multiple times to obtain a semiconductor multi-layer chip packaging structure.

[0113] As described above, during the manufacturing process of the semiconductor multi-layer chip packaging structure, by introducing semi-sealed cavities that can protect the alignment marks from being contaminated by the plastic encapsulation material multiple times, the alignment marks can be directly exposed without other additional processes after encapsulation, providing clean and visible alignment marks for subsequent processes such as exposure and lithography, and eliminating the problem of alignment failure.

[0114] In summary, the semiconductor chip packaging structure and its manufacturing method of the present invention, the method comprising: 1) providing a chip to be encapsulated with alignment marks, the chip to be encapsulated including a substrate and a metallization layer located on the substrate, wherein the alignment marks are located on the upper surface of the metallization layer; 2) depositing metal pillars, formed on the upper surface of the chip to be encapsulated and electrically connected to the metallization layer; 3) fixing a semi-sealed cavity, the semi-sealed cavity being a cavity with one open face and the other faces closed, the open face of the semi-sealed cavity being buckled above the alignment marks; 4) encapsulating with plastic, completely covering the metal pillars and the semi-sealed cavity with a plastic encapsulant to form a plastic encapsulation layer on the metallization layer; 5) grinding, grinding the plastic encapsulation layer until the upper surfaces of the metal pillars and the alignment marks are exposed; 6) forming a redistribution layer, the redistribution layer including a dielectric layer and a metal wire layer located on the dielectric layer, wherein the dielectric layer exposes the upper surfaces of the metal pillars, and the metal wire layer is electrically connected to the metal pillars. By introducing the semi-sealed cavity that can protect the alignment marks from being contaminated by the plastic encapsulant once or multiple times, the alignment marks can be directly exposed after plastic encapsulation without any other additional processes, providing precise positioning for subsequent processes.

[0115] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor package structure, characterized in that, the method comprises the following steps: 1) Provide a chip to be encapsulated with alignment marks. The chip to be encapsulated includes a substrate and a metallization layer located on the substrate. Among them, the alignment marks are located on the upper surface of the metallization layer; 2) Deposit metal pillars, formed on the upper surface of the chip to be encapsulated, and electrically connected to the metallization layer; 3) Fix a semi-sealed cavity. The semi-sealed cavity is a cavity with one open face and the other faces closed. The open face of the semi-sealed cavity is buckled on the alignment marks. The fixing method of the semi-sealed cavity includes mounting; 4) Encapsulate with plastic, completely covering the metal pillars and the semi-sealed cavity with plastic encapsulant, and form a plastic encapsulation layer on the metallization layer; 5) Grind the plastic encapsulation layer until the upper surface of the metal pillars and the alignment marks are exposed; 6) Form a redistribution layer. The redistribution layer includes a dielectric layer and a metal wire layer located on the dielectric layer. Among them, the dielectric layer exposes the upper surface of the metal pillars, and the metal wire layer is electrically connected to the metal pillars.

2. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the step of mounting at least includes: 3-1) Coat an adhesive on the open face of the semi-sealed cavity; 3-2) Buckle the face coated with the adhesive on the alignment marks and bond and fix it to the metallization layer.

3. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the metallization layer includes a dielectric layer and a metal interconnect structure formed in the dielectric layer. The material of the metal interconnect structure includes any one of copper, aluminum, and titanium.

4. The method for preparing a semiconductor package structure according to claim 3, characterized in that, the upper surface of the metal interconnect structure is flush with the upper surface of the dielectric layer or higher than the upper surface of the dielectric layer.

5. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the method for preparing the metal pillars includes a wire bonding process and an electroplating process.

6. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the material of the metal pillars includes any one of copper, aluminum, and titanium.

7. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the material of the semi-sealed cavity includes glass, plastic, ceramic, metal.

8. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the material of the plastic encapsulant includes one of epoxy resin, liquid thermosetting epoxy resin, and plastic compound.

9. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the encapsulation with plastic includes a compression molding process, a transfer molding process, a liquid encapsulation molding process, a vacuum lamination process, or a spin coating process.

10. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the grinding includes chemical mechanical polishing.

11. The method for preparing a semiconductor package structure according to claim 1, characterized in that, the step 6) at least includes the following steps: 6-1) Form a dielectric layer on the upper surface of the plastic encapsulation layer, and the dielectric layer fills the semi-sealed cavity and covers the plastic encapsulation layer; 6-2) Expose the upper surface of the metal pillar through a photolithography and etching process; 6-3) Form a metal wire layer on the upper surface of the dielectric layer, and the metal wire layer is electrically connected to the metal pillar.

12. A semiconductor packaging structure, characterized in that the semiconductor packaging structure is a structure fabricated according to the manufacturing method described in any one of claims 1 to 11, and the semiconductor packaging structure includes: a chip to be encapsulated, the chip to be encapsulated includes a substrate and a metallization layer located on the substrate, wherein, a registration mark is provided on the upper surface of the metallization layer; a plastic encapsulation layer, formed on the upper surface of the chip to be encapsulated, the plastic encapsulation layer includes metal pillars located on the upper surface of the chip to be encapsulated and electrically connected to the metallization layer, a semi-sealed cavity located outside the registration mark, and a plastic encapsulation material layer covering the metal pillars and the semi-sealed cavity; a redistribution layer, located on the upper surface of the plastic encapsulation layer, the redistribution layer includes a dielectric layer and a metal wire layer located on the dielectric layer, wherein, the dielectric layer exposes the upper surface of the metal pillar, and the metal wire layer is electrically connected to the metal pillar.

13. The semiconductor packaging structure according to claim 12, characterized in that there is also an adhesive layer between the semi-sealed cavity and the metallization layer.

14. The semiconductor packaging structure according to claim 12, characterized in that the cross-sectional shape of the semi-sealed cavity includes a circle, a triangle, a square or a hexagon.

15. A method for manufacturing a semiconductor multi-chip packaging structure, characterized in that the method includes fabricating a semiconductor packaging structure by using the method described in claim 1, and then, taking the registration mark on the metallization layer as a reference, bonding at least one second metallization layer to the redistribution layer to form an electrical connection, wherein a second registration mark is provided on the upper surface of the second metallization layer; continuing to repeat steps 2) to 6) in claim 1 to form a semiconductor multi-chip packaging structure.

16. A semiconductor multi-chip packaging structure, characterized in that the structure includes at least one second metallization layer bonded on the semiconductor packaging structure described in claim 12, and a second registration mark is provided on the upper surface of the second metallization layer; at least one second plastic encapsulation layer, formed on the upper surface of the second metallization layer, the second plastic encapsulation layer includes second metal pillars located on the upper surface of the second metallization layer and electrically connected to the second metallization layer, a second semi-sealed cavity located outside the second registration mark, and a second plastic encapsulation material layer covering the second metal pillars and the second semi-sealed cavity; at least one second redistribution layer, formed on the upper surface of the second plastic encapsulation layer.

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