Display panel and display device comprising the same

Abstract

A display panel and a display device including the same are provided. The display panel includes a substrate including a first area, a second area, and a third area between the first area and the second area; a first structure in the second area and including a pixel electrode, a counter electrode, at least one organic material layer, and an intermediate layer between the pixel electrode and the counter electrode; and a plurality of recesses in the third area and separating the at least one organic material layer and the counter electrode, wherein a first recess of the plurality of recesses is disposed in a multi-layer film including a lower layer and an upper layer, wherein the upper layer includes an inorganic material layer and a first step adjacent to the first recess, the first step having a height higher than an upper surface of the lower layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0055836, filed on May 13, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Exemplary embodiments of the inventive concept relate to a display panel, and more specifically, to a display panel having a first region within a display area and a display device including the display panel. Background Technology

[0003] Display devices are devices used to present information in a visual form. Various types of display devices with characteristics such as thinness, light weight, and low power consumption have been cited. Therefore, the use of display devices is becoming increasingly widespread.

[0004] The various functions available for connecting to or integrating with display devices have increased, and the size of the display area of ​​these devices has also increased. In order to add various functions while expanding the area occupied by the display area, technologies for arranging components within the display area are being researched. Summary of the Invention

[0005] According to an exemplary embodiment of the inventive concept, a display panel is provided, the display panel comprising: a substrate including a first region, a second region, and a third region located between the first region and the second region; a first structure located in the second region and including a pixel electrode, a counter electrode, at least one organic material layer, and an intermediate layer located between the pixel electrode and the counter electrode; and a plurality of grooves located in the third region, separating the at least one organic material layer and separating the counter electrode, wherein a first groove of the plurality of grooves is disposed in a multilayer film including a lower layer and an upper layer, wherein the upper layer includes an inorganic material layer and a first step adjacent to the first groove, the first step having a height higher than the upper surface of the lower layer.

[0006] The upper layer may include a conductive oxide layer, a metal layer, or an inorganic insulating layer.

[0007] The lower layer may include an inorganic insulating film.

[0008] The upper layer may include a pair of tips protruding toward the center of the first groove.

[0009] A portion of the bottom surface of the upper layer can be separated from the upper surface of the lower layer at each point in the tip.

[0010] The undercut structure can be located between each of the tips and the underlying layer, and the width of the undercut structure can be larger than the width of the hole or recess in the underlying layer.

[0011] The display panel may also include a residual layer located in the undercut structure.

[0012] The residual layer may include organic materials.

[0013] The upper layer may include: a first sub-upper layer located above the lower layer; and a second sub-upper layer located above the first sub-upper layer, and includes an organic insulating material.

[0014] The first sub-layer may include inorganic insulating materials.

[0015] The display panel may further include: a thin-film transistor located between the substrate and the first structure; a first organic insulating layer and a second organic insulating layer located between the thin-film transistor and the pixel electrode; and a pixel defining film stacked with the pixel electrode.

[0016] The second sub-upper layer may include the same material as the first organic insulating layer, the second organic insulating layer, or the pixel defining film.

[0017] A thin-film transistor may include: a semiconductor layer; a gate electrode at least partially stacked with the semiconductor layer; and a first electrode electrically connected to the semiconductor layer. The display panel may also include a connection electrode connecting the first electrode to a pixel electrode.

[0018] The first sub-layer may include the same material as the first electrode.

[0019] The first sub-layer may include the same material as the connecting electrodes.

[0020] The display panel may also include a third sub-upper layer located between the second sub-upper layer and the first sub-upper layer.

[0021] A thin-film transistor may include: a semiconductor layer; a gate electrode at least partially stacked with the semiconductor layer; and a first electrode electrically connected to the semiconductor layer. The display panel may also include a connection electrode connecting the first electrode to a pixel electrode, and a third sub-upper layer comprising the same material as the connection electrode.

[0022] The third sub-upper layer may include a multi-layer structure, wherein the end of the third sub-upper layer facing the center of the first groove is covered by a second organic insulating layer.

[0023] The display panel may also include a storage capacitor, which includes: a lower electrode made of the same material as the gate electrode; and an upper electrode partially stacked with the lower electrode. The first structure further includes: a gate insulating layer located between the semiconductor layer and the gate electrode; a first interlayer insulating layer located between the lower electrode and the upper electrode; and a second interlayer insulating layer located between the upper electrode and the first electrode.

[0024] The lower layer may include the same material as the gate insulating layer, the first interlayer insulating layer, or the second interlayer insulating layer.

[0025] The lower layer may include: a first sub-lower layer comprising an inorganic insulating material; and a second sub-lower layer located above the first sub-lower layer comprising an organic insulating material.

[0026] The first step of the upper layer can be separated from the upper surface of the second sub-layer by the encapsulation layer in the first groove.

[0027] The display panel may further include: a thin-film transistor located between a substrate and a first structure; a first organic insulating layer and a second organic insulating layer located between the thin-film transistor and a pixel electrode; and a pixel defining film stacked with the pixel electrode, wherein the second sub-underlying layer comprises the same material as the first organic insulating layer or the second organic insulating layer.

[0028] The display panel may also include a first opening located in the first region and penetrating the display panel.

[0029] The display panel may also include a thin-film encapsulation layer, which is located above the first structure and includes an inorganic encapsulation layer and an organic encapsulation layer, wherein the inorganic encapsulation layer is continuously arranged along the inner surface of each of the plurality of grooves.

[0030] According to an exemplary embodiment of the inventive concept, a display device is provided, the display device comprising: a display panel including a substrate, the substrate including a first region, a second region and a third region located between the first region and the second region; and electronic components corresponding to the first region, wherein the display panel further comprises: a laminated structure located in the second region and including a pixel electrode, a counter electrode, at least one organic material layer and an intermediate layer located between the pixel electrode and the counter electrode; and a plurality of grooves located in the third region and cutting the at least one organic material layer and the counter electrode, wherein at least one of the plurality of grooves is disposed in a multilayer film including a lower layer and an upper layer, and the upper layer includes an inorganic material layer and at least one step.

[0031] According to an exemplary embodiment of the inventive concept, a display device is provided, the display device comprising: a substrate including a second region, a first region for accommodating components and a third region located between the first region and the second region; electrodes and an organic material layer located in the second region; and a groove located in the third region, separating the organic material layer and separating the electrodes, wherein the groove includes a lower layer and an upper layer, wherein the upper layer includes an inorganic material layer and a step, the step being raised above the upper surface of the lower layer. Attached Figure Description

[0032] The above and other features of the inventive concept will become more apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0033] Figure 1This is a schematic perspective view of a display device according to an exemplary embodiment of the inventive concept;

[0034] Figure 2 and Figure 3 This is a schematic cross-sectional view of a display device according to an exemplary embodiment of the inventive concept;

[0035] Figure 4A , Figure 4B , Figure 4C and Figure 4D This is a schematic cross-sectional view of a display panel according to an exemplary embodiment of the inventive concept;

[0036] Figure 5 This is a schematic plan view of a display panel according to an exemplary embodiment of the inventive concept;

[0037] Figure 6 This is an equivalent circuit diagram of the pixels of a display panel according to an exemplary embodiment of the inventive concept;

[0038] Figure 7 This is a plan view of a portion of a display panel according to an exemplary embodiment of the inventive concept;

[0039] Figure 8 This is a cross-sectional view of a display panel according to an exemplary embodiment of the inventive concept;

[0040] Figure 9 This is an exemplary embodiment based on the inventive concept. Figure 8 A schematic cross-sectional view of an enlarged portion of the display panel;

[0041] Figure 10A , Figure 10B , Figure 10C and Figure 10D This is a cross-sectional view illustrating the process of forming a groove according to an exemplary embodiment of the inventive concept;

[0042] Figure 11 , Figure 12 and Figure 13 This is a cross-sectional view of a portion of a display panel according to an exemplary embodiment of the inventive concept;

[0043] Figure 14 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the inventive concept;

[0044] Figure 15 yes Figure 14 An enlarged view of a portion of the display panel;

[0045] Figure 16 , Figure 17 and Figure 18A schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the inventive concept; and

[0046] Figure 19 , Figure 20 and Figure 21 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0047] Exemplary embodiments of the inventive concept will now be described with reference to the accompanying drawings. However, the inventive concept can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0048] The same reference numerals in the accompanying drawings can denote the same elements, therefore, their descriptions can be omitted.

[0049] A statement used in the singular form may contain a statement in the plural form, unless it has a distinctly different meaning in the context.

[0050] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, that layer, region, or component may be formed directly on the other layer, region, or component, or there may be intermediate layers, intermediate regions, or intermediate components.

[0051] For ease of explanation, the dimensions of the components in the attached diagram may be exaggerated.

[0052] When specific embodiments can be implemented differently, the specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described sequence.

[0053] It will be understood that when a layer, region, or component is referred to as being "connected to" another layer, region, or component, that layer, region, or component may be directly connected to said other layer, region, or component, or there may be intermediate layers, intermediate regions, or intermediate components. It will also be understood that when a layer, region, or component is referred to as being "electrically connected to" another layer, region, or component, that layer, region, or component may be directly electrically connected to said other layer, region, or component, or there may be intermediate layers, intermediate regions, or intermediate components.

[0054] In the examples below, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0055] Figure 1 This is a schematic perspective view of a display device 1 according to an exemplary embodiment of the inventive concept.

[0056] Reference Figure 1 The display device 1 includes a first region OA and a display region DA that at least partially surrounds the first region OA. The display region DA may be referred to as a second region. The display device 1 can display an image by using light emitted from a plurality of pixels located in the display region DA. The first region OA may be completely surrounded by the display region DA. The first region OA may be as described below. Figure 2 The region where the described component is located.

[0057] The intermediate region MA can be located between the first region OA and the display region DA, and the display region DA can be surrounded by the outer region PA. The intermediate region MA can be called the third region, and the outer region PA can be called the fourth region. The intermediate region MA and the outer region PA can be non-display regions where no pixels are located. The intermediate region MA can be completely surrounded by the display region DA, and the display region DA can be completely surrounded by the outer region PA.

[0058] In the following description, by way of example, display device 1 is described as an organic light-emitting display device, but display device 1 is not limited thereto. In another embodiment, display device 1 may be a display device such as a quantum dot light-emitting display device.

[0059] Although Figure 1 The illustration shows a first region OA that is substantially circular, but the inventive concept is not limited thereto. There can be two or more first regions OA, and the shape of each first region OA can be varied, such as circular, elliptical, polygonal, star-shaped, rhomboid, etc.

[0060] Figure 2 and Figure 3 It is along Figure 1 The schematic cross-sectional view of the display device 1 according to an exemplary embodiment of the inventive concept is taken by line II-II'.

[0061] Reference Figure 2 The display device 1 may include a display panel 10 and an input sensing layer 40 and an optical functional layer 50 located on the display panel 10. The display panel 10, the input sensing layer 40, and the optical functional layer 50 may be covered by a window 60. The display device 1 may be various types of electronic devices such as mobile phones, laptops, or smartwatches.

[0062] Display panel 10 can display images. Display panel 10 includes pixels located in display area DA. Pixels may include display elements and pixel circuitry connected to the display elements. Display elements may include organic light-emitting diodes, quantum dot organic light-emitting diodes, etc.

[0063] The input sensing layer 40 can acquire coordinate information based on external input (e.g., a touch event). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces connected to the sensing electrodes. The input sensing layer 40 may be located on the display panel 10. The input sensing layer 40 can sense external input using mutual capacitance and / or self-capacitance methods.

[0064] The input sensing layer 40 can be formed directly on the display panel 10, or it can be formed separately and then bonded to the display panel 10 by an adhesive layer such as an optically transparent adhesive. For example, the input sensing layer 40 can be formed sequentially after the process of forming the display panel 10. In this case, the input sensing layer 40 can be part of the display panel 10, and the adhesive layer may not be located between the input sensing layer 40 and the display panel 10. Figure 2 The input sensing layer 40 is shown to be located between the display panel 10 and the optical functional layer 50; however, the input sensing layer 40 may be located above the optical functional layer 50.

[0065] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (e.g., external light) incident from the outside through window 60 toward the display panel 10. The anti-reflective layer may include a retarder and a polarizer. The retarder may be film-type or liquid crystal coated type, and may include a λ / 2 retarder and / or a λ / 4 retarder. The polarizer may also be film-type or liquid crystal coated type. Film-type retarders / polarizers may include stretched synthetic resin films, and liquid crystal coated retarders / polarizers may include liquid crystals arranged in a specific manner. The retarder and polarizer may also include a protective film. The retarder and polarizer or protective film may be the substrate layer of the anti-reflective layer.

[0066] In another exemplary embodiment of the inventive concept, the antireflective layer may include a black matrix and color filters. The color filters can be arranged according to the color of light emitted from each pixel of the display panel 10. In another exemplary embodiment of the inventive concept, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer located on different layers. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can interfere destructively, thereby reducing the reflectivity of external light.

[0067] The optical functional layer 50 may include a lens layer. The lens layer can improve the light output efficiency of light emitted from the display panel 10 or reduce color deviation. The lens layer may include a layer having a concave or convex lens shape and / or may include multiple layers with different refractive indices. The optical functional layer 50 may include both an anti-reflective layer and a lens layer, or may include one of an anti-reflective layer and a lens layer.

[0068] In an exemplary embodiment of the inventive concept, the optical functional layer 50 can be formed sequentially after the processes for forming the display panel 10 and / or the input sensing layer 40. In this case, the adhesive layer may not be located between the optical functional layer 50, the display panel 10, and / or the input sensing layer 40.

[0069] The display panel 10, the input sensing layer 40, and / or the optical functional layer 50 may include openings. In this respect, Figure 2 The diagram illustrates a display panel 10, an input sensing layer 40, and an optical functional layer 50, each including a first opening 10H, a second opening 40H, and a third opening 50H. The first opening 10H, second opening 40H, and third opening 50H are stacked on top of each other to form continuous openings in the display panel 10, the input sensing layer 40, and the optical functional layer 50. The first opening 10H, second opening 40H, and third opening 50H correspond to a first region OA. In other words, the first opening 10H, second opening 40H, and third opening 50H are located in the first region OA. In another exemplary embodiment of the inventive concept, one or more of the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include openings. For example, one or two components selected from the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include openings. Optionally, the display panel 10, the input sensing layer 40, and the optical functional layer 50 may not include openings, such as... Figure 3 As shown in the image.

[0070] As described above, the first region OA can be a component region (e.g., a sensor region, camera region, speaker region, etc.) where components 20 configured to add various functions to the display device 1 are located. Components 20 can be located in the first opening 10H, the second opening 40H, and the third opening 50H, such as... Figure 2 As shown in the diagram. Optionally, component 20 may be located below display panel 10, as shown in the diagram. Figure 3 As shown in the image.

[0071] Component 20 may include electronic components. For example, component 20 may be an electronic component that uses light or sound. For example, the electronic component may include a sensor (such as an infrared sensor) for outputting and / or receiving light, a camera for capturing images by receiving light, a sensor for outputting and sensing light or sound to measure distance or identify fingerprints, a small lamp for outputting light, a speaker for outputting sound, etc. The electronic component using light may use light of various wavelengths, such as visible light, infrared light, ultraviolet light, etc. In an exemplary embodiment of the inventive concept, the first region OA may be a transmissive region, wherein light and / or sound output from component 20 to the outside or input from the outside toward component 20 can pass through the transmissive region.

[0072] In another exemplary embodiment of the inventive concept, when the display device 1 is used as a smartwatch or an instrument panel for a vehicle, component 20 may be a component such as a clock hand or a needle indicating specific information (e.g., the speed of the vehicle). When the display device 1 includes a clock hand or an instrument panel for a vehicle, component 20 may be exposed to the outside through window 60, which may include an opening corresponding to the first region OA.

[0073] Component 20 may include components associated with the function of the display panel 10 as described above, or may include accessories such as those that enhance the aesthetics of the display panel 10. A layer including an optically clear adhesive may be located between the window 60 and the optical functional layer 50.

[0074] Figures 4A to 4D This is a schematic cross-sectional view of a display panel 10 according to an exemplary embodiment of the inventive concept.

[0075] Reference Figure 4A The display panel 10 may include a display layer 200 located on a substrate 100. The substrate 100 may include a glass material or a polymer resin. The substrate 100 may be formed as a multilayer structure. For example, such as Figure 4A As shown in the enlarged view, the substrate 100 may include a first substrate layer 101, a first barrier layer 102, a second substrate layer 103, and a second barrier layer 104. The first substrate layer 101, the first barrier layer 102, the second substrate layer 103, and the second barrier layer 104 may be stacked sequentially.

[0076] Each of the first matrix layer 101 and the second matrix layer 103 may include a polymer resin. For example, the first matrix layer 101 and the second matrix layer 103 may include polymer resins such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc. The aforementioned polymer resins may be transparent.

[0077] The first barrier layer 102 and the second barrier layer 104 are barrier layers used to prevent the penetration of external foreign matter. The first barrier layer 102 and the second barrier layer 104 may include materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y ( ) material, single layer or multiple layers.

[0078] Display layer 200 has multiple pixels. Display layer 200 may include: display element layer 200A, including display elements located in each pixel; and pixel circuit layer 200B, including pixel circuitry and an insulating layer located in each pixel. Display element layer 200A may have pixel electrodes, counter electrodes, and a stacked structure between pixel electrodes and counter electrodes, and each display element may be an organic light-emitting diode (OLED). Each pixel circuit may include a thin-film transistor and a storage capacitor.

[0079] The display elements of the display layer 200 may be covered by an encapsulation component such as a thin-film encapsulation layer 300, which may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. When the display panel 10 includes a substrate 100 comprising a polymer resin and a thin-film encapsulation layer 300 comprising an inorganic encapsulation layer and an organic encapsulation layer, the flexibility of the display panel 10 may be increased.

[0080] The display panel 10 may include a penetrating portion (i.e., a first opening) 10H that penetrates the display panel 10. The penetrating portion 10H may be located in a first region OA, in which case the first region OA may be a region with an opening. Figure 4A Each of the substrate 100 and the thin-film encapsulation layer 300 may include a through-hole 100H and a through-hole 300H, both corresponding to the through-port 10H of the display panel 10. The display layer 200 may also include a through-hole 200H corresponding to the first region 0A.

[0081] In another exemplary embodiment of the inventive concept, such as Figure 4B As shown, the substrate 100 may not include the via corresponding to the first region OA. The display layer 200 may include the via 200H corresponding to the first region OA. The thin-film encapsulation layer 300 may not include the via corresponding to the first region OA. In another exemplary embodiment of the inventive concept, as... Figure 4C As shown, the display layer 200 may not include the via corresponding to the first region OA.

[0082] Figures 4A to 4C The illustration shows that the display element layer 200A is not located in the first region OA, but the inventive concept is not limited thereto. In another exemplary embodiment of the inventive concept, such as Figure 4D As shown, the auxiliary display element layer 200C may be located in the first region OA. The auxiliary display element layer 200C may include display elements that operate with a different structure and / or method than the display elements of the display element layer 200A.

[0083] In an exemplary embodiment of the inventive concept, each pixel in display element layer 200A may include an active OLED, and auxiliary display element layer 200C may include pixels comprising passive OLEDs. When auxiliary display element layer 200C includes a display element comprising a passive OLED, the components including pixel circuitry may not be present beneath the passive OLED. For example, the portion of pixel circuitry layer 200B located beneath auxiliary display element layer 200C may not include transistors and storage capacitors.

[0084] In another exemplary embodiment of the inventive concept, the auxiliary display element layer 200C may include a display element of the same type as the display element of the display element layer 200A (e.g., an active OLED), but the structure of the pixel circuitry corresponding to the auxiliary display element layer 200C may differ from the structure of the pixel circuitry corresponding to the display element layer 200A. For example, the pixel circuitry below the auxiliary display element layer 200C (e.g., a pixel circuitry with a light-shielding film between the substrate and the transistor) may include a different structure than the pixel circuitry below the display element layer 200A. Optionally, the display element of the auxiliary display element layer 200C may be operated according to a different control signal than that of the display element of the display element layer 200A. Components that do not require relatively high transmittance (e.g., infrared sensors, etc.) may be located in a first region OA of the auxiliary display element layer 200C. In this case, the first region OA may be both a component region and an auxiliary display region.

[0085] Figure 5 This is a schematic plan view of the display panel 10 according to an exemplary embodiment of the inventive concept. Figure 6 This is an equivalent circuit diagram of a pixel P of a display panel 10 according to an exemplary embodiment of the inventive concept.

[0086] Reference Figure 5 The display panel 10 may include a first area OA, a display area DA as a second area, a middle area MA as a third area, and a peripheral area PA as a fourth area. Figure 5 This can be a view of the base 100 of the display panel 10. For example, the base 100 may have a first region OA, a display region DA, a middle region MA, and a peripheral region PA.

[0087] Display panel 10 includes a plurality of pixels P located in display area DA. For example... Figure 6 As shown, each pixel P may include a pixel circuit PC and an organic light-emitting diode (OLED) connected to the pixel circuit PC as a display element. The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. Each pixel P may emit, for example, red, green, blue, or white light through the OLED.

[0088] The second thin-film transistor T2 is a switching thin-film transistor that can be connected to the scan line SL and the data line DL, and can transfer the data voltage input from the data line DL to the first thin-film transistor T1 based on the switching voltage input from the scan line SL. A storage capacitor Cst can be connected to the second thin-film transistor T2 and the drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the second thin-film transistor T2 and the first power supply voltage ELVDD supplied to the drive voltage line PL.

[0089] The first thin-film transistor T1 is a driving thin-film transistor that can be connected to the driving voltage line PL and the storage capacitor Cst. It can control the driving current flowing from the driving voltage line PL through the organic light-emitting diode (OLED) based on the voltage stored in the storage capacitor Cst. The OLED can emit light with a specific brightness according to the driving current. The counter electrode (e.g., cathode) of the OLED can receive a second power supply voltage ELVSS.

[0090] Figure 6 The illustration shows a pixel circuit PC comprising two thin-film transistors and one storage capacitor, but the inventive concept is not limited thereto. The number of thin-film transistors and the number of storage capacitors can be varied depending on the design of the pixel circuit PC. For example, in addition to the two thin-film transistors mentioned above, the pixel circuit PC may include four or more thin-film transistors.

[0091] Refer again Figure 5 The intermediate region MA can surround the first region OA in the plan view. The intermediate region MA is the area where display elements such as OLEDs are not located, and signal lines used to provide signals to pixels P located around the first region OA can pass through the intermediate region MA. The scan driver 1100 that provides scan signals to each pixel P, the data driver 1200 that provides data signals to each pixel P, the main power supply wiring that provides the first power supply voltage and the second power supply voltage, etc., can be located in the peripheral region PA. Figure 5 The data driver 1200 is shown positioned adjacent to one side of the substrate 100, but according to another exemplary embodiment of the inventive concept, the data driver 1200 may be located on a flexible printed circuit board (FPCB) electrically connected to a pad (or “soldering pad”) located on one side of the display panel 10.

[0092] Figure 7 This is a plan view of a portion of a display panel 10 according to an exemplary embodiment of the inventive concept.

[0093] Reference Figure 7Pixel P is located in the display area DA surrounding the first area OA. Some pixels P can be separated from each other around the first area OA, and the first area OA can be located between pixels P. For example, in a plan view, pixels P can be located above and below the first area OA, and pixels P can be located to the left and right of the first area OA.

[0094] Among the signal lines supplying signals to pixel P, the signal line adjacent to the first region OA can bypass the first region OA. In other words, the signal line can travel around the first region OA. Figure 7 In the plan view, at least one data line DL passing through the display area DA can extend in the y-direction to provide data signals to pixels P located above and below the first area OA, respectively, and can bypass the edge of the first area OA in the intermediate area MA. In the plan view, at least one scan line SL passing through the display area DA can extend in the x-direction to provide scan signals to pixels P located to the left and right of the first area OA, respectively, and can bypass the edge of the first area OA in the intermediate area MA.

[0095] The bypass portion SL-D of scan line SL can be located on the same layer as the extension portion SL-L of scan line SL passing through display area DA, and can be integrally formed with the extension portion SL-L. The bypass portion DL-D1 of the first data line DL1 in data lines DL can be formed on a different layer than the extension portion DL-L1 of the first data line DL1 passing through display area DA. The bypass portion DL-D1 and the extension portion DL-L1 of the first data line DL1 can be connected via a contact hole CNT. The bypass portion DL-D2 of the second data line DL2 in data lines DL can be located on the same layer as the extension portion DL-L2 of the second data line DL2, and can be integrally formed with the extension portion DL-L2.

[0096] One or more grooves G may be located between the first region OA and the area where the scan line SL and data line DL in the intermediate region MA bypass the first region OA. In a plan view, each of the grooves G may have an annular shape around the first region OA, and the grooves G may be separated from each other.

[0097] Figure 8 This is a cross-sectional view of the display panel 10-1 according to an exemplary embodiment of the inventive concept. Figure 9 yes Figure 8 An enlarged view of a portion of the display panel 10-1. Figure 8 Can be along Figure 7 The cross section cut by line VIII-VIII' corresponds to the line in the middle.

[0098] Reference Figure 8The display area DA of the display panel 10-1 in the invention, the substrate 100 may include a glass material or a polymer resin. In an exemplary embodiment of the inventive concept, the substrate 100 may include, for example, Figure 4A The enlarged image shows multiple layers.

[0099] A buffer layer 201 may be formed on the substrate 100 to prevent impurities from penetrating into the semiconductor layer Act of the thin-film transistor (TFT). The buffer layer 201 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multiple layers including the inorganic insulating materials described above.

[0100] The pixel circuit PC may be located on the buffer layer 201. The pixel circuit PC may include a thin-film transistor (TFT) and a storage capacitor Cst. The thin-film transistor (TFT) may include a semiconductor layer Act, a gate electrode GE, and a source electrode SE and a drain electrode DE as first electrodes. Figure 8 The thin-film transistor TFT shown can be compared with a reference. Figure 6 The described driving thin-film transistor T1 corresponds to this. The data line DL of the pixel circuit PC is electrically connected to the switching thin-film transistor T2 included in the pixel circuit PC. In this embodiment, a top-gate type is shown where the gate electrode GE is located above the semiconductor layer Act and the gate insulating layer 203 is located between the gate electrode GE and the semiconductor layer Act; however, according to another exemplary embodiment of the inventive concept, the thin-film transistor TFT can be a bottom-gate type.

[0101] The semiconductor layer Act may include polycrystalline silicon. Optionally, the semiconductor layer Act may include amorphous silicon, oxide semiconductor, organic semiconductor, etc. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include conductive materials including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be a multilayer or a single layer including the aforementioned materials.

[0102] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The gate insulating layer 203 may be a single layer or multiple layers including the materials mentioned above.

[0103] The source electrode SE and drain electrode DE, which are the first electrodes electrically connected to the semiconductor layer Act, can be located on the same layer as the data line DL, and can include the same material as the data line DL. The source electrode SE, drain electrode DE, and data line DL can include materials with good conductivity. The source electrode SE and drain electrode DE can include conductive materials comprising Mo, Al, Cu, Ti, etc., and can be a multilayer or a single layer including the aforementioned materials. In an exemplary embodiment of the inventive concept, the source electrode SE, drain electrode DE, and data line DL can be formed as a Ti / Al / Ti multilayer.

[0104] The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2 stacked on top of each other, and a first interlayer insulating layer 205 may be located between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may be stacked with a thin-film transistor (TFT). Figure 8 The diagram illustrates the gate electrode GE of a thin-film transistor (TFT) serving as the lower electrode CE1 of a storage capacitor Cst. In another exemplary embodiment of the inventive concept, the storage capacitor Cst may not be stacked with the TFT. The storage capacitor Cst may be covered by a second interlayer insulating layer 207. The upper electrode CE2 of the storage capacitor Cst may comprise a conductive material including Mo, Al, Cu, Ti, etc., and may be a multilayer or a single layer comprising the aforementioned materials.

[0105] The first interlayer insulation layer 205 and the second interlayer insulation layer 207 may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first interlayer insulation layer 205 and the second interlayer insulation layer 207 may be a single layer or multiple layers comprising the aforementioned materials.

[0106] The pixel circuit PC, including the thin-film transistor (TFT) and the storage capacitor (Cst), can be covered by an inorganic insulating layer 208. The inorganic insulating layer 208 prevents wiring, including metals such as aluminum that might be damaged by etchants, from being exposed to the etching environment during the manufacturing process of the display device 1. The inorganic insulating layer 208 can extend to the intermediate region MA.

[0107] The inorganic insulating layer 208 may comprise inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may be formed as a single layer or multiple layers. In an exemplary embodiment of the inventive concept, the inorganic insulating layer 208 may comprise SiN x The inorganic insulating layer 208 can have approximately Or a greater thickness. In another exemplary embodiment of the inventive concept, the thickness of the inorganic insulating layer 208 can be... or larger or larger or larger or larger or larger or larger or larger or larger or larger or larger or larger or Or larger. Furthermore, the inorganic insulating layer 208 can have... to The thickness.

[0108] The first organic insulating layer 209 may be located on the inorganic insulating layer 208. The upper surface of the first organic insulating layer 209 may be substantially flat.

[0109] The pixel circuit PC can be electrically connected to the pixel electrode 221. For example, as... Figure 8 As shown, the contact metal layer CM (e.g., a connection electrode) can be located between the thin-film transistor TFT and the pixel electrode 221. The contact metal layer CM can contact the thin-film transistor TFT through contact holes formed in the first organic insulating layer 209, and the pixel electrode 221 can contact the contact metal layer CM through contact holes formed in the second organic insulating layer 211 above the contact metal layer CM. The contact metal layer CM can include a conductive material comprising Mo, Al, Cu, Ti, etc., and can be a multilayer or a single layer comprising the aforementioned materials. In an exemplary embodiment of the inventive concept, the contact metal layer CM can be formed as a Ti / Al / Ti multilayer.

[0110] The first organic insulating layer 209 and the second organic insulating layer 211 may comprise polymers such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, and organic insulating materials such as acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. In an exemplary embodiment of the inventive concept, the first organic insulating layer 209 and the second organic insulating layer 211 may comprise polyimide.

[0111] Pixel electrode 221 may be formed above the second organic insulating layer 211. Pixel electrode 221 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). In another exemplary embodiment of the inventive concept, pixel electrode 221 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof. In another exemplary embodiment of the inventive concept, pixel electrode 221 may also include a film comprising ITO, IZO, ZnO, or In2O3 above / below the aforementioned reflective film.

[0112] A pixel defining film 215 may be formed on the pixel electrode 221. The pixel defining film 215 may include an opening exposing the upper surface of the pixel electrode 221 and may cover the edge of the pixel electrode 221. The pixel defining film 215 may include an organic insulating material. Furthermore, the pixel defining film 215 may include materials such as SiN. x SiON or SiO x Inorganic materials. Furthermore, the pixel-defining film 215 may include organic insulating materials and inorganic insulating materials.

[0113] The intermediate layer 222 may include a light-emitting layer 222b. The intermediate layer 222 may include a first functional layer 222a located below the light-emitting layer 222b and / or a second functional layer 222c located on the light-emitting layer 222b. The light-emitting layer 222b may include a high molecular weight organic material or a low molecular weight organic material that emits light of a specific color.

[0114] The first functional layer 222a can be a single layer or multiple layers. For example, when the first functional layer 222a comprises a high molecular weight material, the first functional layer 222a can be a hole transport layer (HTL) with a single-layer structure, and can include poly(3,4)-ethylenedihydroxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a comprises a low molecular weight material, the first functional layer 222a can include a hole injection layer (HIL) and an HTL.

[0115] The second functional layer 222c is not always provided. For example, the second functional layer 222c is formed when the first functional layer 222a and the light-emitting layer 222b comprise high molecular weight materials. The second functional layer 222c can be a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0116] The light-emitting layer 222b of the intermediate layer 222 can be configured for each pixel in the display area DA. The light-emitting layer 222b can be patterned to correspond to the pixel electrode 221. Unlike the light-emitting layer 222b, the first functional layer 222a and / or the second functional layer 222c can exist not only in the display area DA but also in the intermediate area MA.

[0117] The counter electrode 223 may include a conductive material with low work function. For example, the counter electrode 223 may include a (semi-)transparent layer, which may include Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), alloys thereof, etc. The counter electrode 223 may also include a layer such as ITO, IZO, ZnO, or In2O3 above the (semi-)transparent layer including the aforementioned materials. The counter electrode 223 may be formed not only above the display region DA, but also above the intermediate region MA. The first functional layer 222a, the second functional layer 222c, and the counter electrode 223 may be formed by thermal deposition.

[0118] The capping layer 230 may be located on the counter electrode 223. For example, the capping layer 230 may include lithium fluoride (LiF) and may be formed by thermal deposition. In exemplary embodiments of the inventive concept, the capping layer 230 may be omitted.

[0119] Spacer 217 may be formed on pixel defining film 215. For example, spacer 217 may be formed on the side of pixel defining film 215 that is stacked with contact metal layer CM. Spacer 217 may include an organic insulating material such as polyimide. Alternatively, spacer 217 may include an inorganic insulating material or include both organic and inorganic insulating materials.

[0120] The spacer 217 may comprise a material different from or the same as the pixel defining film 215. For example, the pixel defining film 215 and the spacer 217 may be formed together in a masking process using a halftone mask. In an exemplary embodiment of the inventive concept, the pixel defining film 215 and the spacer 217 may comprise polyimide.

[0121] Organic light-emitting diodes (OLEDs) can be covered by a thin-film encapsulation layer 300. The thin-film encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. For example, Figure 8The thin-film encapsulation layer 300 is shown to include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 located between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. In another exemplary embodiment of the inventive concept, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order can be varied. For example, the organic encapsulation layer 320 can be disposed below the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

[0122] Both the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers including the aforementioned materials.

[0123] The organic encapsulation layer 320 may include polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, polyimides, and polyethylene. In an exemplary embodiment of the inventive concept, the organic encapsulation layer 320 may include acrylates.

[0124] The thickness of the first inorganic encapsulation layer 310 and the thickness of the second inorganic encapsulation layer 330 can be different from each other. The thickness of the first inorganic encapsulation layer 310 can be greater than the thickness of the second inorganic encapsulation layer 330. Optionally, the thickness of the second inorganic encapsulation layer 330 can be greater than the thickness of the first inorganic encapsulation layer 310, or the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can have the same thickness.

[0125] Reference Figure 8 The intermediate region MA may include a first sub-intermediate region SMA1, which is relatively far from the first region OA, and a second sub-intermediate region SMA2, which is relatively close to the first region OA. The second sub-intermediate region SMA2 is located between the first region OA and the first sub-intermediate region SMA1. A line and a groove G that bypass the first region OA may be located in the intermediate region MA.

[0126] Line (e.g., such as) Figure 8 The data line DL shown in the display area DA can also be located as follows: Figure 8 The first sub-intermediate region SMA1 is shown in the diagram. The data line DL located in the first sub-intermediate region SMA1 can be referenced. Figure 7 The described data line DL bypass portions (e.g., DL-D1 and DL-D2) correspond to this. The first sub-intermediate region SMA1 can be a line region or bypass region in which a data line such as the aforementioned data line DL bypasses.

[0127] In another exemplary embodiment of the inventive concept, data lines DL can be arranged alternately, and an insulating layer is located between the data lines DL. For example, adjacent data lines DL can be arranged alternately such that one of the adjacent data lines DL is below the insulating layer (e.g., the first organic insulating layer 209), and the other of the adjacent data lines DL is above the insulating layer (e.g., the first organic insulating layer 209). When the data lines DL are arranged alternately and the insulating layer is located between the data lines DL, the distance (e.g., Δd, pitch) between the data lines DL can be reduced. Although Figure 8 The data line DL located in the display area DA is shown, but reference... Figure 7 The described scan line SL (e.g., the bypass portion SL-D of the scan line SL) may be located in the first sub-intermediate region SMA1.

[0128] The separator PW and the groove G can be located in the second sub-intermediate region SMA2 of the intermediate region MA.

[0129] The spacer PW can be located between adjacent recesses G. The spacer PW can be formed by sequentially stacking a portion 209P of the layer forming the first organic insulating layer 209, a portion 215P of the layer forming the pixel defining film 215, and a portion 217P of the layer forming the spacer 217. The height from the upper surface of the substrate 100 to the upper surface of the spacer PW can be lower than the height from the upper surface of the substrate 100 to the upper surface of the spacer 217. In other words, the top of the spacer PW can be set lower than the top of the spacer 217.

[0130] The intermediate region MA may include inorganic contact regions ICR. Inorganic contact regions ICR may be located between adjacent grooves G. Inorganic contact regions ICR are the direct contact areas of layers comprising inorganic material. For example, Figure 8 The inorganic layer (in other words, the upper UL) is shown to be in direct contact with the buffer layer 201 in the inorganic contact region ICR. The upper UL can contact the buffer layer 201 through openings formed in each of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207.

[0131] One or more grooves G may be located in the second sub-intermediate region SMA2. Organic material layers included in the intermediate layer 222 (e.g., the first functional layer 222a and / or the second functional layer 222c) may be cut (e.g., separated) by the grooves G. The second sub-intermediate region SMA2 may be a grooved region or a cut-off region (or a separated region) of the organic material layer.

[0132] The groove G can be formed prior to the process of forming the intermediate layer 222; therefore, the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 can be cut off or separated by the groove G, such as Figure 8 and Figure 9 As shown in the figure. In addition, the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can be arranged continuously along the inner surface of each of the plurality of grooves G.

[0133] The groove G can be formed in the multilayer film ML between the substrate 100 and the pixel electrode 221. For example... Figure 8 As shown, with respect to the separator PW, the groove G may include at least one or more grooves located between the separator PW and the display area DA and between the separator PW and the first area OA.

[0134] The multilayer film ML may include a stacked structure of a lower layer LL and an upper layer UL. Therefore, both the lower layer LL and the upper layer UL may consist of a single layer or multiple layers. The lower layer LL may include at least one inorganic insulating film, and the upper layer UL may include at least one of a conductive oxide layer, a metal layer, and an inorganic insulating layer.

[0135] The lower LL layer may include at least one inorganic insulating film, and may include, for example: Figure 8 The plurality of inorganic insulating films 203, 205 and 207 shown herein. The plurality of inorganic insulating films 203, 205 and 207 may each comprise the same material as the gate insulating layer 203, the first interlayer insulating layer 205 and the second interlayer insulating layer 207 in the display area DA.

[0136] The upper UL layer can be located above the lower LL layer. The upper UL layer may include inorganic materials. For example, the inorganic materials of the upper UL layer may include conductive oxides such as IZO, ITO, ZnO, In2O3, IGO, and / or AZO. Furthermore, the inorganic materials may include metals such as Mo, Al, Cu, and / or Ti. Additionally, the inorganic materials may include insulating materials such as silicon nitride, silicon oxide, and / or silicon oxynitride.

[0137] Although Figure 8 The upper UL is shown to comprise the same material as the inorganic insulating layer 208 in the display area DA, but the inventive concept is not limited thereto. In another exemplary embodiment of the inventive concept, the upper UL (e.g., a first sub-upper UL1) may be located between the first organic insulating layer 209 and the contact metal layer CM, such as... Figure 17 As shown in the figure, and can be located between the second organic insulating layer 211 and the pixel electrode 221, such as Figure 18 As shown in the image.

[0138] The following will refer to Figure 9 Describe groove G in detail.

[0139] The groove G can be formed in the depth direction (-z direction) of the multilayer film ML. The groove G can be located above the substrate 100 and the buffer layer 201. In other words, the upper surface of the buffer layer 201 can be exposed through the groove G. The exposure of the upper surface of the buffer layer 201 through the groove G can mean that the bottom surface of the groove G and the upper surface of the buffer layer 201 can be located on the same plane.

[0140] In another exemplary embodiment of the inventive concept, such as Figure 13 As shown, the groove G can be formed to expose the upper surface of the substrate 100. In this case, the bottom surface of the groove G and the upper surface of the substrate 100 can be located on the same plane. In another exemplary embodiment of the inventive concept, the bottom surface of the groove G can be located on the same plane as a dummy surface between the upper surface of the substrate 100 and the upper surface of the lower layer LL. In this case, the recess forming the groove G can be included in the lower layer LL.

[0141] The groove G may include an upper hole UL-h penetrating the upper layer UL and a lower hole LL-h or a recess formed in the lower layer LL. In exemplary embodiments of the inventive concept, such as... Figure 9 As shown, the groove G may include an upper hole UL-h of the upper UL layer and a lower hole LL-h of the lower LL layer. The lower LL layer may include a recess that does not completely penetrate the lower LL layer. When the recess is included, the bottom surface of the groove G may be on the same plane as the dummy surface between the upper surface of the substrate 100 and the upper surface of the lower LL layer.

[0142] The groove G can have an undercut UC structure. Figure 9 In this embodiment, the first width W1 of the upper UL can be smaller than the second width W2 of the lower LL. Furthermore, in an exemplary embodiment of the inventive concept, the upper UL may include at least one or more steps. Due to the steps of the upper UL, the undercut UC structure of the groove G can be formed to have a third width W3 larger than the second width W2 of the lower LL. The steps of the upper UL may refer to the portion of the upper UL separated from the lower LL by a gap.

[0143] The end of the upper UL protruding toward the groove G (e.g., toward the center of the groove G) can form a pair of tips PT. In this embodiment, each of the tips PT can be a portion of the bottom surface of the upper UL separated from the upper surface of the lower LL by a step of the upper UL. Therefore, as Figure 9 As shown, each of the tips PT can be separated from the upper surface of the lower layer LL by a first height h. The first height h can be the same as the height of the step of the upper layer UL.

[0144] The protruding length d1 of each of the tips PT can be smaller than the depth d of the groove G. The protruding length d1 of the tip PT can be less than about 2 μm. For example, the protruding length d1 of the tip PT can be from 1 μm to 1.5 μm. The depth d of the groove G can be about 2 μm or more, 2.5 μm or more, 3 μm or more, or 3.5 μm or more. As mentioned above, the depth d of the groove G can be formed to be as much as the step of the upper UL as the thickness t of the lower layer LL.

[0145] As mentioned above, including organic light-emitting diodes (OLEDs) Figure 8 In the stacked structure of an OLED, the organic material layers can be cut or separated by the recess G. For example, the first functional layer 222a and the second functional layer 222c can be cut or separated (centered on the recess G) around the recess G, as shown below. Figure 9 As shown in the diagram. Similarly, the counter electrode 223 and the capping layer 230 can be cut off or separated (centered on the groove G) around the groove G. Although Figure 9 and will be described below Figures 11 to 21 The diagram shows that the first functional layer 222a, the second functional layer 222c, the counter electrode 223, and the capping layer 230 (centered on the groove G) are cut off or separated around the groove G, but the inventive concept is not limited thereto. As described above, the second functional layer 222c and / or the capping layer 230 can be omitted, in which case the omitted second functional layer 222c and / or the capping layer 230 may not exist around the groove G.

[0146] Figures 10A to 10D This is a cross-sectional view illustrating the manufacturing process of the groove G according to an exemplary embodiment of the inventive concept.

[0147] Reference Figure 10A First, a lower hole LL-h is formed in the lower layer LL. As described above, the lower layer LL can be located on the buffer layer 201 located on the substrate 100, but in some cases, the lower layer LL may include the buffer layer 201.

[0148] Then, an organic layer OL can be formed above the lower hole LL-h. The organic layer OL can be formed to be embedded in the lower hole LL-h. The organic layer OL can be formed at a first depth d0, which can be greater than the thickness t of the lower layer LL. The upper surface of the organic layer OL can be formed to be higher than the upper surface of the lower layer LL by a first height h'. The first height h' can be... Figure 9 The first height h of the steps of the upper UL shown is the same.

[0149] The width W3' of the organic layer OL located above the lower layer LL can be formed to be larger than the second width W2 of the lower hole LL-h. However, the inventive concept is not limited thereto. For example, the width W3' of the organic layer OL can be the same as the second width W2 of the lower hole LL-h. Next, an upper layer UL can be formed to cover the organic layer OL.

[0150] Reference Figure 10B An upper aperture UL-h can be formed in the upper UL layer to correspond to the lower aperture LL-h. As described above, the first width W1 of the upper aperture UL-h can be formed to be smaller than the second width W2 of the lower aperture LL-h to accommodate the undercut UC structure. At least a portion of the upper surface of the organic layer OL can be exposed through the upper aperture UL-h.

[0151] The ends of the organic layer OL and the upper hole UL-h can be formed to have a specific length d1', and the length d1' can be related to the above. Figure 9 The protruding length d1 of the tip PT described in the text is the same.

[0152] Then, the organic layer OL can be removed through the top hole UL-h. The organic layer OL can be removed by wet etching or dry etching. After removing the organic layer OL, the desired result is as follows: Figure 10C The shape shown is illustrated. By removing the organic layer OL, a groove G comprising a lower hole LL-h and an upper hole UL-h can be formed.

[0153] like Figure 10D As shown, the residual layer OLr can be included in the groove G. The residual layer OLr can be an organic layer OL in... Figure 10B The portion of the organic layer OL that was not removed during the process of removing the organic layer OL. The residual layer OLr can be retained in the undercut UC structure of the groove G.

[0154] like Figure 10C and Figure 10D As shown, after removing the organic layer OL, one or more organic material layers located on the upper layer UL, which are part of the laminated structure, can be cut or separated by the groove G.

[0155] Figures 11 to 13 This is a cross-sectional view of a portion of the display panel 10-2 according to an exemplary embodiment of the inventive concept. Figure 12 yes Figure 11 A magnified image of a portion. Figure 13 yes Figure 11 A modified embodiment.

[0156] Reference Figure 11 The structure of the display area DA of the display panel 10-2 in this embodiment can be the same as... Figure 8The structure of the display area DA is the same, but the structure of the middle area MA (in other words, the structure of the groove G) differs from the previously mentioned embodiment. The differences in the structure of the groove G will be described primarily below.

[0157] The groove G is defined within a multilayer film ML, which includes an upper layer UL and a lower layer LL. The lower layer LL may include at least one inorganic insulating film and may include multiple inorganic insulating films 203, 205, and 207, such as... Figure 11 As shown in the figure. The plurality of inorganic insulating films 203, 205 and 207 may each comprise the same material as the gate insulating layer 203, the first interlayer insulating layer 205 and the second interlayer insulating layer 207 in the display area DA.

[0158] The upper UL layer can be located above the lower LL layer. Figure 11 (or Figure 12 The structure of the upper UL in ) and Figure 8 (or Figure 9 The structure of the upper UL in the above embodiment is different. In this embodiment, the upper UL may include a first sub-upper UL1 and a second sub-upper UL2 located above the first sub-upper UL1.

[0159] The first sub-upper layer UL1 may include inorganic materials. The first sub-upper layer UL1 may include conductive oxides such as IZO, ITO, ZnO, In2O3, IGO, and / or AZO. Furthermore, the inorganic materials may include metals such as Mo, Al, Cu, and / or Ti. Additionally, the inorganic materials may include insulating materials such as silicon nitride, silicon oxide, and / or silicon oxynitride.

[0160] The second sub-upper layer UL2 may include organic insulating materials. The second sub-upper layer UL2 may include polymers such as PMMA or PS, polymer derivatives having phenol groups, and organic insulating materials such as acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, and mixtures thereof.

[0161] Figure 11 The illustration shows that the first sub-upper layer UL1 comprises the same material as the inorganic insulating layer 208 in the display area DA, and the second sub-upper layer UL2 comprises the same material as the first organic insulating layer 209 in the display area DA; however, the inventive concept is not limited thereto. In another exemplary embodiment of the inventive concept, the first sub-upper layer UL1 may comprise the same material as the data line DL or the contact metal layer CM in the display area DA, and the second sub-upper layer UL2 may comprise the same material as the first organic insulating layer 209 or the second organic insulating layer 211 located above the data line DL or the contact metal layer CM in the display area DA.

[0162] The second sub-upper layer UL2 can be omitted. However, as described above, since a portion of the first sub-upper layer UL1 is formed to be separated from the upper surface of the lower layer LL by a step, the second sub-upper layer UL2 can be located on the first sub-upper layer UL1 to support the first sub-upper layer UL1 from above, thereby increasing the structural reliability of the display panel 10-2.

[0163] The following will refer to Figure 12 Describe groove G in detail.

[0164] The groove G can be formed along the depth direction of the multilayer film ML. The groove G can be located above the substrate 100 and the buffer layer 201. In other words, the upper surface of the buffer layer 201 can be exposed through the groove G. The exposure of the upper surface of the buffer layer 201 through the groove G can mean that the bottom surface of the groove G and the upper surface of the buffer layer 201 can be located on the same plane.

[0165] The groove G may include an upper hole penetrating the upper layer UL and a lower hole LL-h or a recess formed in the lower layer LL. In exemplary embodiments of the inventive concept, such as... Figure 12 As shown, the groove G may include the first upper hole UL1-h of the first sub-upper layer UL1, the second upper hole UL2-h of the second sub-upper layer UL2, and the lower hole LL-h of the lower layer LL.

[0166] The groove G can have an undercut UC structure. Figure 12 In this embodiment, the width of the upper UL (e.g., the first width W1 of the first upper hole UL1-h) can be smaller than the second width W2 of the lower LL. Furthermore, in this embodiment, the upper UL may include at least one step. For example, the upper UL may include a step located on the opposite side of the groove G. Due to the step of the upper UL, the undercut UC structure of the groove G can be formed to have a third width W3 that is larger than the second width W2 of the lower LL.

[0167] The protruding ends of the upper UL towards the groove G (e.g., towards the center of the groove G) (e.g., the end of the first sub-upper UL1) may form a pair of tips PT. The protruding length d1 of each tip PT may be smaller than the depth d of the groove G. The protruding length d1 of the tip PT may be less than about 2 μm. For example, the protruding length d1 of the tip PT may be from 1 μm to 1.5 μm. The depth d of the groove G may be about 2 μm or more, 2.5 μm or more, 3 μm or more, or 3.5 μm or more.

[0168] Figure 13 The structure of the groove G in the middle and Figure 12 The structure of the groove G in the middle is different.

[0169] The groove G can be formed to expose the upper surface of the substrate 100. In this case, the bottom surface of the groove G and the upper surface of the substrate 100 can be located on the same plane. In another exemplary embodiment of the inventive concept, the bottom surface of the groove G can be located on the same plane as a dummy surface between the upper surface of the substrate 100 and the upper surface of the lower layer LL. In this case, the recess forming the groove G can be included in the lower layer LL.

[0170] The groove G is disposed in the multilayer film ML, which includes an upper layer UL and a lower layer LL. Figure 13 In the middle, the lower layer LL may include a first sub-lower layer LL1 and a second sub-lower layer LL2 comprising at least one inorganic insulating film. The first sub-lower layer LL1 may include the same material as the buffer layer 201 in the display area DA, and the second sub-lower layer LL2 may include the same material as the gate insulating layer 203, the first interlayer insulating layer 205 and the second interlayer insulating layer 207 in the display area DA.

[0171] The groove G can be formed to expose the upper surface of the substrate 100. The groove G may include a first upper hole UL1-h and a second upper hole UL2-h penetrating the upper layer UL, and a first lower hole LL1-h and a second lower hole LL2-h formed in the lower layer LL. The groove G may include a first upper hole UL1-h of a first sub-upper layer UL1, a second upper hole UL2-h of a second sub-upper layer UL2, a first lower hole LL1-h of a first sub-lower layer LL1, and a second lower hole LL2-h of a second sub-lower layer LL2.

[0172] Figure 14 This is a schematic cross-sectional view of a portion of the display panel 10-3 according to an exemplary embodiment of the inventive concept. Figure 15 yes Figure 14 A magnified view of part A.

[0173] Reference Figure 14 , Figure 14 The display area DA and Figure 8 The display areas DA are the same, but the structure of the middle area MA is different.

[0174] A groove G is disposed in a multilayer film ML, which includes an upper layer UL and a lower layer LL. The lower layer LL may include at least one inorganic insulating film. The lower layer LL may include the same material as the gate insulating layer 203, the first interlayer insulating layer 205 and the second interlayer insulating layer 207 in the display area DA.

[0175] The upper UL layer may include a first sub-upper UL layer 1, a second sub-upper UL layer 2 located above the first sub-upper UL layer 1, and a third sub-upper UL layer 3 between the first sub-upper UL layer 1 and the second sub-upper UL layer 2. The third sub-upper UL layer 3 may be directly located on the first sub-upper UL layer 1 and may support the first sub-upper UL layer 1. In an exemplary embodiment of the inventive concept, the first sub-upper UL layer 1 may include the same material as the inorganic insulating layer 208 in the display area DA, the third sub-upper UL layer 3 may include the same material as the contact metal layer CM in the display area DA, and the second sub-upper UL layer 2 may include the same material as the second organic insulating layer 211 in the display area DA.

[0176] In this configuration, the first organic insulating layer 209 between the inorganic insulating layer 208 and the contact metal layer CM in the display area DA can be removed from the intermediate area MA. Therefore, the spacer PW located in the intermediate area MA can be formed by stacking a portion 211P of the layer forming the second organic insulating layer 211, a portion 215P of the layer forming the pixel defining film 215, and a portion 217P of the layer forming the spacer 217. The height from the upper surface of the substrate 100 to the upper surface of the spacer PW can be lower than the height from the upper surface of the substrate 100 to the upper surface of the spacer 217.

[0177] In this embodiment, the second sub-upper layer UL2 can be configured to cover the third sub-upper layer UL3. (Refer to...) Figure 15 The third sub-upper layer UL3 can be located above the first sub-upper layer UL1, and the second sub-upper layer UL2 can cover the third sub-upper layer UL3. The end UL1-e of the first sub-upper layer UL1 can protrude much more toward the center of the groove G than the end UL3-e of the third sub-upper layer UL3. In other words, the end UL3-e of the third sub-upper layer UL3 can be positioned closer to the separator PW than the end UL1-e of the first sub-upper layer UL1.

[0178] The second sub-upper layer UL2 can be positioned to cover the end UL3-e of the third sub-upper layer UL3. For example... Figure 15As shown, the third sub-upper layer UL3 can have a structure in which multiple layers UL31, UL32, and UL33 are stacked. The multiple layers UL31, UL32, and UL33 can form, for example, a structure in which Ti / Al / Ti is stacked sequentially. The third sub-upper layer UL3, as a three-layer Ti / Al / Ti, can be formed in the same mask process as the contact metal layer CM. As mentioned above, when the third sub-upper layer UL3 is a multilayer including aluminum such as Ti / Al / Ti, the third sub-upper layer UL3 may be easily damaged during the process. Therefore, relatively robust titanium can be formed to form a second sub-upper layer UL2 covering the end UL3-e of the third sub-upper layer UL3 to prevent any aluminum damage to the side surface of the third sub-upper layer UL3 (in other words, the end UL3-e) by forming uneven shapes or undercuts.

[0179] Figures 16 to 18 These are schematic cross-sectional views of a portion of display panels 10-4, 10-5, and 10-6 according to exemplary embodiments of the inventive concept. Figures 16 to 18 Display panels 10-4, 10-5, and 10-6 are Figure 8 Examples of modifications. In the following text, repeated content will be omitted, and the differences will be described primarily.

[0180] Reference Figure 16 The structure of groove G and Figure 11 The structure of the groove G is similar, but the structure of the upper UL is different. Figure 11 The upper UL structure may include a first sub-upper UL1 and a second sub-upper UL2 located above the first sub-upper UL1. The first sub-upper UL1 may include a metal layer, and the second sub-upper UL2 may include an organic insulating material. In this embodiment, the first sub-upper UL1 may include the same material as the contact metal layer CM in the display area DA, and the second sub-upper UL2 may include the same material as the second organic insulating layer 211 in the display area DA.

[0181] The inorganic contact region ICR is located in the intermediate region MA (in other words, the second sub-intermediate region SMA2) and is the direct contact region of the layer including the inorganic material. The inorganic contact region ICR having metal-inorganic material contact can be formed by allowing the first sub-upper layer UL1, which is a metal layer, to directly contact the buffer layer 201.

[0182] Figure 17 and Figure 18 The depths d' and d" of the groove G in this embodiment are different from the depths of the groove G in the previously mentioned embodiment. Figure 17 and Figure 18As shown, the groove G includes a lower layer LL and an upper layer UL. The lower layer LL includes multiple inorganic insulating layers, and the upper layer UL includes a first sub-upper layer UL1 containing inorganic materials and a second sub-upper layer UL2 containing organic insulating materials.

[0183] Reference Figure 17 The inorganic insulating layer 208 in the display area DA may be located between the first organic insulating layer 209 and the contact metal layer CM. The inorganic insulating layer 208 may include the same material as the upper UL layer (e.g., the first sub-upper UL layer 1) of the groove G in the intermediate area MA. The second sub-upper UL layer 2 may include the same material as the second organic insulating layer 211 in the display area DA. Figure 14 A similar third sub-upper layer may be located between the first sub-upper layer UL1 and the second sub-upper layer UL2. The third sub-upper layer may include the same material as the contact metal layer CM in the display area DA. (See reference...) Figure 18 The first sub-upper layer UL1 may include the same material as the inorganic insulating layer 208 in the display area DA, and the second sub-upper layer UL2 may include the same material as the pixel defining film 215 in the display area DA.

[0184] Figure 17 The depth d' of the groove G in the groove can be formed to be deeper than in the previously described embodiment. Figures 10A to 10C Similarly, the groove G can be formed by forming an organic layer and then removing the organic layer. The depth d' of the groove G can be controlled by using an organic layer stacked prior to forming the first sub-upper layer UL1 in which the tip PT is formed. Compared to the previously described embodiment, a portion of the first organic insulating layer 209 located below the inorganic insulating layer 208 in the display area DA can fill the groove G, and the first organic insulating layer 209 can be removed to increase the thickness of the first organic insulating layer 209 by increasing the depth d' of the groove G.

[0185] Similarly, Figure 18 The depth d" of the groove G in the middle can be formed as a ratio Figure 17 The depth d' of the groove G is large. The depth d" of the groove G can be controlled by using organic layers (such as the first organic insulating layer 209 and the second organic insulating layer 211) stacked before forming the first sub-upper layer UL1 in which the tip PT is formed. For example, compared to the previously described embodiment, a portion of the first organic insulating layer 209 and the second organic insulating layer 211 located below the inorganic insulating layer 208 in the display area DA can fill the groove G, and the first organic insulating layer 209 and the second organic insulating layer 211 can be removed to increase the depth d" of the groove G by increasing the thickness of the first organic insulating layer 209 and the second organic insulating layer 211.

[0186] Figures 19 to 21These are schematic cross-sectional views of a portion of display panels 10-7, 10-8, and 10-9 according to exemplary embodiments of the inventive concept. Figures 19 to 21 Display panels 10-7, 10-8, and 10-9 are Figure 8 Examples of modifications. In the following text, repeated content will be omitted, and the differences will be described primarily.

[0187] Reference Figure 19 The structure of groove G and Figure 8 The structure of the groove G is similar, but the structure of the lower LL is different. Figure 8 The structure of the lower LL layer. A groove G is disposed in the multilayer film ML, which includes a lower LL layer and an upper UL layer. In this embodiment, the lower LL layer may include a first sub-lower LL layer 1 and a second sub-lower LL layer 2 located above the first sub-lower LL layer 1.

[0188] The first sub-lower layer LL1 may include an inorganic insulating material, and the second sub-lower layer LL2 may include an organic insulating material. The first sub-lower layer LL1 may include at least one inorganic insulating layer. Figure 19 The inorganic insulating layer may include a portion of the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207. The second sub-lower layer LL2 may include a portion of the first organic insulating layer 209. The upper layer UL, including the inorganic layer, may be located above the second sub-lower layer LL2, and the upper layer UL may have a step having a height higher than the upper surface of the lower layer LL (e.g., the second sub-lower layer LL2), as in the previously described embodiments. (Refer to...) Figure 21 In an exemplary embodiment, the second sub-lower layer LL2 may cover the side of the first sub-lower layer LL1 located in the groove G.

[0189] Figure 19 The structure of the separator PW in the middle Figure 8 The structure of the separator PW is the same, so repeated descriptions are omitted.

[0190] Reference Figure 20 The groove G is disposed in the multilayer film ML, which includes a lower layer LL and an upper layer UL. In this embodiment, the lower layer LL may include a first sub-lower layer LL1, a second sub-lower layer LL2 located above the first sub-lower layer LL1, and a third sub-lower layer LL3 located above the second sub-lower layer LL2.

[0191] The first child lower layer LL1 and the second child lower layer LL2 and Figure 19 The first sub-layer LL1 and the second sub-layer LL2 are the same. Figure 20 and Figure 19The difference lies in the inclusion of a third sub-lower layer LL3. The third sub-lower layer LL3 may include a portion of the second organic insulating layer 211. The upper layer UL may include an inorganic layer and may be located directly on the second organic insulating layer 211. Similar to the previously described embodiments, the upper layer UL may have a step that is higher than the upper surface of the lower layer LL (e.g., the third sub-lower layer LL3).

[0192] Figure 20 The structure of the separator PW in the middle Figure 8 The structure of the separator PW is the same, so repeated descriptions are omitted.

[0193] The display panel according to an exemplary embodiment of the present invention can prevent external impurities such as moisture around the first region from damaging the display element. However, it should be understood that other effects and features of the inventive concept have been shown, and other effects and features of the inventive concept can be learned from the above description.

[0194] Although the inventive concept has been described with reference to one or more exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to the inventive concept without departing from the spirit and scope of the inventive concept set forth in the claims.

Claims

1. A display panel comprising: a substrate including a first region, a second region, and a third region between the first region and the second region; a first structure in the second region and including a pixel electrode, a counter electrode, at least one organic material layer, and an intermediate layer between the pixel electrode and the counter electrode; and a plurality of recesses in the third region and separating the at least one organic material layer and separating the counter electrode, wherein a first recess of the plurality of recesses is provided in a multi-layer film including an underlayer and an upper layer, wherein the upper layer includes an inorganic material layer and a first step adjacent to the first recess, the first step having a height higher than an upper surface of the underlayer, wherein the underlayer has a hole or a recess defining the first recess, and wherein the first recess has an undercut structure and the inorganic material layer defines an upper surface and a side surface of the undercut structure.

2. The display panel according to claim 1, wherein the upper layer includes a conductive oxide layer, a metal layer, or an inorganic insulating layer.

3. The display panel according to claim 1, wherein the underlayer includes an inorganic insulating film.

4. The display panel according to claim 1, wherein the upper layer includes a pair of tips protruding toward a center of the first recess.

5. The display panel according to claim 4, wherein a portion of a bottom surface of the upper layer is separated from the upper surface of the underlayer at each of the tips.

6. The display panel according to claim 4, wherein the undercut structure is between each of the tips and the underlayer, and a width of the undercut structure is larger than a width of the hole or the recess in the underlayer.

7. The display panel according to claim 6, further comprising: a residual layer in the undercut structure.

8. The display panel according to claim 7, wherein the residual layer includes an organic material.

9. The display panel according to claim 1, wherein the upper layer includes: a first sub-upper layer above the underlayer; and a second sub-upper layer above the first sub-upper layer and including an organic insulating material.

10. The display panel according to claim 9, wherein the first sub-upper layer includes an inorganic insulating material.

11. The display panel according to claim 9, further comprising: a thin film transistor between the substrate and the first structure; a first organic insulating layer and a second organic insulating layer between the thin film transistor and the pixel electrode; and a pixel defining film superposed with the pixel electrode.

12. The display panel according to claim 11, wherein the second sub-upper layer includes a same material as the first organic insulating layer, the second organic insulating layer, or the pixel defining film.

13. The display panel according to claim 11, wherein the thin film transistor includes a semiconductor layer, a gate electrode superposed at least partially with the semiconductor layer, and a first electrode electrically connected to the semiconductor layer, and ​ ​ The display panel further includes a connection electrode connecting the first electrode to the pixel electrode.

14. The display panel of claim 13, wherein, The first sub-overlayer includes the same material as the first electrode.

15. The display panel of claim 13, wherein, The first sub-overlayer includes the same material as the connection electrode.

16. The display panel of claim 11, further comprising: a third sub-overlayer between the second sub-overlayer and the first sub-overlayer.

17. The display panel of claim 16, wherein, The thin film transistor includes a semiconductor layer, a gate electrode at least partially superposed with the semiconductor layer, and a first electrode electrically connected to the semiconductor layer, The display panel further includes a connection electrode connecting the first electrode to the pixel electrode, and The third sub-overlayer includes the same material as the connection electrode.

18. The display panel of claim 16, wherein, The third sub-overlayer includes a multi-layer structure, and an end of the third sub-overlayer facing a center of the first recess is covered by the second organic insulating layer.

19. The display panel of claim 13, further comprising a storage capacitor, the storage capacitor including: a lower electrode including the same material as the gate electrode; and an upper electrode at least partially superposed with the lower electrode, wherein the first structure further includes: a gate insulating layer between the semiconductor layer and the gate electrode; a first interlayer insulating layer between the lower electrode and the upper electrode; and a second interlayer insulating layer between the upper electrode and the first electrode.

20. The display panel of claim 19, wherein, The lower layer includes the same material as the gate insulating layer, the first interlayer insulating layer, or the second interlayer insulating layer.

21. The display panel of claim 1, wherein, The lower layer includes: a first sub-lower layer including an inorganic insulating material; and a second sub-lower layer above the first sub-lower layer including an organic insulating material.

22. The display panel of claim 21, wherein, The second sub-lower layer covers a side of the first sub-lower layer in the first recess.

23. The display panel of claim 21, further comprising: a thin film transistor between the base and the first structure; a first organic insulating layer and a second organic insulating layer between the thin film transistor and the pixel electrode; and a pixel defining film superposed with the pixel electrode, wherein the second sub-lower layer includes the same material as the first organic insulating layer or the second organic insulating layer.

24. The display panel of claim 1, further comprising: a first opening in the first region and penetrating the display panel.

25. The display panel of claim 1, further comprising: a thin film encapsulation layer above the first structure and including an inorganic encapsulation layer and an organic encapsulation layer, The inorganic encapsulation layer is continuously disposed along an inner surface of each of the plurality of grooves.

26. A display device, comprising: a display panel including a substrate including a first area, a second area, and a third area between the first area and the second area; and an electronic element corresponding to the first area, wherein the display panel further includes: a layered structure in the second area and including a pixel electrode, a counter electrode, at least one organic material layer, and an intermediate layer between the pixel electrode and the counter electrode; and a plurality of grooves in the third area and cutting the at least one organic material layer and the counter electrode, wherein at least one of the plurality of grooves is provided in a multi-layer film including a lower layer and an upper layer, and the upper layer includes an inorganic material layer and at least one step, wherein the lower layer has a hole or a recess defining the at least one groove, and wherein the at least one groove has an undercut structure, and the inorganic material layer defines an upper surface and a side surface of the undercut structure.

27. A display device, comprising: a substrate including a second area, a first area for accommodating components, and a third area between the first area and the second area; an electrode and an organic material layer in the second area; and a groove in the third area and separating the organic material layer and separating the electrode, wherein the groove includes a lower layer and an upper layer, wherein the upper layer includes an inorganic material layer and a step raised above an upper surface of the lower layer, wherein the lower layer has a hole or a recess defining the groove, and wherein the groove has an undercut structure, and the inorganic material layer defines an upper surface and a side surface of the undercut structure.

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