Light emitting diode and method of manufacturing the same

Abstract

A light emitting diode and a manufacturing method thereof are disclosed. The light emitting diode comprises a semiconductor stack, a transparent conductive layer, an insulating layer, a first electrode layer, and a second electrode layer. The semiconductor stack comprises a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in a first direction. The transparent conductive layer is formed on the semiconductor stack and electrically connected to the second semiconductor layer. The insulating layer is formed on the transparent conductive layer and comprises a first opening. The first electrode layer is formed on the insulating layer and comprises a first pad region and a first extension region. The first extension region extends from an edge of the first pad region in a second direction. The second electrode layer is formed on the insulating layer and electrically connected to the first semiconductor layer. The first extension region contacts the transparent conductive layer through the first opening, and the first extension region completely surrounds the first opening. The first extension region and the second electrode layer do not overlap in the first direction.

Description

Technical Field

[0001] This invention relates to light-emitting diodes, and more particularly to light-emitting diodes with improved brightness and / or enhanced current distribution, and related manufacturing methods. Background Technology

[0002] Light-emitting diodes (LEDs) have excellent characteristics such as low power consumption, low heat generation, long operating life, shock resistance, small size, and fast response speed, making them suitable for various lighting and display applications.

[0003] Traditional LEDs use compound semiconductor materials and generate light by the recombination of holes in the P-type semiconductor layer and electrons in the N-type semiconductor layer. One existing LED manufacturing process uses five photomasks to define the semiconductor stack's mesa, current blocking layer, transparent conductive layer, electrodes, and insulating protective layer. Using fewer photomasks reduces costs and improves yield. Summary of the Invention

[0004] This invention provides a light-emitting diode (LED) comprising a semiconductor stack, wherein a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially stacked; a transparent conductive layer is formed on the semiconductor stack and electrically connected to the second semiconductor layer; an insulating layer is formed on the transparent conductive layer and includes a first opening; and an electrode layer is formed on the insulating layer and includes a first pad region and a first extension region; wherein the first extension region contacts the transparent conductive layer through the first opening, and the first extension region completely surrounds the first opening.

[0005] This invention provides another light-emitting diode, comprising a semiconductor stack, wherein a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially stacked; a through-well located in the semiconductor stack, including a sidewall and a bottom, wherein the through-well exposes a portion of the second semiconductor layer, the light-emitting layer, and the first semiconductor layer; a transparent conductive layer formed on the semiconductor stack and electrically connected to the second semiconductor layer; an insulating layer formed on the transparent conductive layer, including a first opening; and an electrode layer formed on the insulating layer, including a first pad region and a first extension region; wherein the first extension region contacts the transparent conductive layer through the first opening, and the first extension region overlaps with the through-well, but the first extension region does not make electrical contact with the first semiconductor layer through the through-well.

[0006] This invention provides another light-emitting diode, comprising a semiconductor stack, wherein a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially stacked; a transparent conductive layer is formed on the semiconductor stack and electrically connected to the second semiconductor layer; an insulating layer is formed on the transparent conductive layer, comprising a first opening and a plurality of mutually separated blocking islands located in the first opening; and an electrode layer is formed on the insulating layer, comprising a first pad region and a first extension region; wherein the first extension region at least partially overlaps with the blocking islands, and the first extension region contacts the transparent conductive layer through the first opening. Attached Figure Description

[0007] Figures 1A to 1D A schematic diagram illustrating the photomask pattern for fabricating the light-emitting diode 100 according to the first embodiment of this application;

[0008] Figure 2 This is a top view of the light-emitting diode 100 according to the first embodiment of this application;

[0009] Figure 3 A cross-sectional view of a light-emitting diode 100;

[0010] Figures 4A to 4D A schematic diagram illustrating the photomask pattern for fabricating a light-emitting diode 200 according to a second embodiment of the present invention;

[0011] Figure 5 This is a top view of the light-emitting diode 200 according to the second embodiment of this application;

[0012] Figure 6 A cross-sectional view of a light-emitting diode 200;

[0013] Figure 7 This is a top view of the light-emitting diode 200a according to the third embodiment of this application;

[0014] Figure 8 A cross-sectional view of a light-emitting diode 200a;

[0015] Figures 9A to 9D A schematic diagram illustrating the photomask pattern for fabricating a light-emitting diode 300 according to the fourth embodiment of this application;

[0016] Figure 10 This is a top view of the light-emitting diode 300 according to the fourth embodiment of this application;

[0017] Figure 11 A cross-sectional view of a light-emitting diode 300;

[0018] Figures 12A to 12C A schematic diagram of the photomask pattern for fabricating a light-emitting diode 400 according to the fifth embodiment of this application;

[0019] Figure 13This is a top view of the light-emitting diode 400 according to the fifth embodiment of this application;

[0020] Figure 14A and Figure 14B This is a two-section view of a light-emitting diode 400;

[0021] Figures 15A to 15C A schematic diagram of the photomask pattern for the sixth embodiment of this application of the light-emitting diode 500;

[0022] Figure 16 This is a top view of the light-emitting diode 500 according to the sixth embodiment of this application;

[0023] Figure 17 This is a cross-sectional view of a light-emitting diode 500.

[0024] Symbol Explanation

[0025] 100, 200, 200A, 300, 400, 500 LEDs

[0026] Photomask patterns: 102, 104, 106, 108, 202, 204, 206, 208, 302, 304, 306, 308, 405, 406, 408, 505, 506, 508

[0027] 102b, 104b, 106b, 108b, 202b, 204b, 206b, 208b, 302b, 304b, 306b, 308b, 405b, 406b, 408b, 505b, 506b, 508b blank areas

[0028] 102e, 202e, 405e, 505e Edge of the high platform

[0029] 102p, 104p, 106p, 108p, 202p, 204p, 206p, 208p, 302p, 304p, 306p, 308p, 405p, 406p, 408p, 505p, 506p, 508p Reserved Area

[0030] 102h, 202h, 202k, 302h, 405h, 505h, 505k Trap Penetration

[0031] Edges of 104e and 204e transparent conductive layers

[0032] 106e, 206e, 306e, 406e insulation layer edges

[0033] 108e, 208e, 308e, 408e electrode layer edges

[0034] 110, 210, 310, 410, 510 semiconductor stacks

[0035] 112, 212, 312, 412, 512 First semiconductor layer

[0036] 114, 214, 314, 414, 514 light-emitting layers

[0037] 116, 216, 316, 416, 516 Second semiconductor layer

[0038] 118, 218, 318, 418, 518 transparent conductive layers

[0039] 120, 220, 320, 420, 520 insulation layers

[0040] 118a, 118b, 218a, 218b, 318a, 318b transparent conductive layer openings

[0041] 120h, 120g, 120j, 220g, 220j, 320h, 420g, 420h, 420j, 520h, 520j insulation layer opening

[0042] 120r, 220h, 320r, 420r, 520r insulation layer annular opening

[0043] 122, 222, 322, 422, 522 electrode layers

[0044] 124, 224, 324, 424, 524 Gaotai District

[0045] Exposure areas 125, 225, 325, 425, and 525

[0046] 220d, 320d blocking islands

[0047] 262, 462, 562 (bottom)

[0048] 264, 464, 564 sidewalls

[0049] EXTp and EXTn extension regions

[0050] PDp and PDn pad areas Detailed Implementation

[0051] In the following description, exemplary embodiments of the present invention will be illustrated in detail to enable those skilled in the art to fully understand the spirit of the invention. The present invention is not limited to the following embodiments, but may be implemented in other forms. In this specification, some identical symbols denote elements having the same or similar structure, function, or principle, and can be deduced by those skilled in the art from the teachings of this specification. For the sake of brevity, elements with the same symbols will not be repeated.

[0052] Example 1

[0053] Figures 1A to 1D The photomask patterns implemented for fabricating the light-emitting diode 100 according to the embodiments of this application are shown and are respectively labeled as photomask pattern 102, photomask pattern 104, photomask pattern 106, and photomask pattern 108. Figure 2 A top view of a light-emitting diode 100 fabricated according to the aforementioned photomask pattern is shown. Figure 3 LED 100 Figure 2 A cross-sectional view of line segment III-III.

[0054] as Figure 3 As shown, the light-emitting diode 100 includes a semiconductor stack 110 formed on a substrate (not shown), a transparent conductive layer 118, an insulating layer 120, and an electrode layer 122.

[0055] According to the manufacturing method of the light-emitting diode 100 in Embodiment 1 of this application, firstly, a semiconductor stack 110 is formed on a substrate. The substrate can be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate can be a patterned substrate, that is, the substrate has a patterned structure on its upper surface. Light emitted from the semiconductor stack 110 can be refracted by the patterned structure, thereby improving the brightness of the light-emitting diode. In addition, the patterned structure mitigates or suppresses misalignment between the substrate and the semiconductor stack 110 caused by lattice mismatch, thereby improving the epitaxial quality of the semiconductor stack 110.

[0056] In one embodiment of this application, a semiconductor stack 110 can be formed on a substrate by means of metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE) or ion plating, such as sputtering or evaporation.

[0057] The semiconductor stack 110 includes a buffer structure (not shown), a first semiconductor layer 112, a light-emitting layer 114, and a second semiconductor layer 116 sequentially formed on a substrate. The buffer structure can reduce the aforementioned lattice mismatch and suppress dislocations, thereby improving epitaxial quality. The material of the buffer layer includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes multiple sublayers (not shown). The sublayers may be made of the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the first sublayer is grown by sputtering and the second sublayer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second, and third sublayers include the same material, such as AlN. In one embodiment of this application, the first semiconductor layer 112 and the second semiconductor layer 116, such as cladding layers or confinement layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 112 is an n-type semiconductor, and the second semiconductor layer 116 is a p-type semiconductor. A light-emitting layer 114 is formed between the first semiconductor layer 112 and the second semiconductor layer 116. Electrons and holes combine in the light-emitting layer 114 under the drive of an electric current, converting electrical energy into light energy to emit light. The wavelength of the light emitted by the light-emitting diode 100 or the semiconductor stack 110 can be adjusted by changing the physical properties and chemical composition of one or more layers in the semiconductor stack 110.

[0058] The material of the semiconductor stack 110 includes Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)P is a group III-V semiconductor material, where 0≤x, y≤1; x+y≤1. Depending on the material of the light-emitting layer, when the semiconductor stack 110 is made of the AlInGaP series, it can emit red light with wavelengths between 610nm and 650nm or yellow light with wavelengths between 550nm and 570nm. When the semiconductor stack 110 is made of the InGaN series, it can emit blue or deep blue light with wavelengths between 400nm and 490nm or green light with wavelengths between 490nm and 550nm. When the semiconductor stack 110 is made of the AlGaN series, it can emit UV light with wavelengths between 400nm and 250nm. The light-emitting layer 114 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the light-emitting layer 114 can be an i-type, p-type, or n-type semiconductor.

[0059] Next, with Figure 1A The photomask pattern 102, and the patterned semiconductor stack 110. In Figure 1A In the diagram, blank area 102b corresponds to the etched area in the semiconductor stack 110 where the second semiconductor layer 116, the light-emitting layer 114, and a portion of the first semiconductor layer 112 are to be removed; retained area 102p corresponds to the retained area of ​​the semiconductor stack 110 that is not etched away. In the etched area, for example, dry etching is performed from the upper surface of the second semiconductor layer 116 downwards until an upper surface of the first semiconductor layer 112 is exposed. Therefore, according to... Figures 1A to 1D In the light-emitting diode 100 formed by the photomask pattern, such as Figure 3 As shown, the reserved area 102p of the photomask pattern 102 corresponds to the formation of the high plateau area 124, and the etched area in the semiconductor stack 110 corresponds to the formation of the exposed area 125. The exposed area 125 exposes part of the sidewall of the second semiconductor layer 116, part of the sidewall of the light-emitting layer 114, part of the sidewall of the first semiconductor layer 112, and part of the upper surface of the first semiconductor layer 112. Figure 2 The image also shows the raised platform edge 102e corresponding to the photomask pattern 102, wherein the area outside the raised platform edge 102e is the exposed area 125, and the exposed area 125 also includes the through-trap 102h.

[0060] Next, a transparent conductive layer 118 is formed on the semiconductor stack 110, as if... Figure 2 and Figure 3As shown. For example, a transparent conductive layer 118 can be deposited on the semiconductor stack 110, electrically contacting the second semiconductor layer 116 to laterally disperse the current. The transparent conductive layer 118 can be a metal or a transparent conductive material. The metal can be selected from a thin electrode layer with light transmittance, and the transparent conductive material is transparent to the light emitted by the light-emitting layer 114, including materials such as indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), or indium zinc oxide (IZO). Then, a photolithography process and an etching process are used... Figure 1B The photomask pattern 104 in the image contains a patterned transparent conductive layer 118. In the photomask pattern 104, the transparent conductive layer 118 corresponding to the reserved region 104p is retained, while the transparent conductive layer 118 corresponding to the blank region 104b is removed, resulting in the image shown below. Figure 2 as well as Figure 3 The results are shown. Figure 2 The remaining edge 104e of the transparent conductive layer is shown. The transparent conductive layer 118 is located on the raised area 124 and does not cover the exposed area 125. In one embodiment, the transparent conductive layer 118 has an opening that exposes the second semiconductor layer 116 beneath it. In one embodiment, as... Figure 1B and Figure 2 As shown, the transparent conductive layer 118 has an opening 118a. In one embodiment, as... Figure 1B and Figure 2 As shown, the transparent conductive layer 118 has an opening 118b that exposes the through-well 102h, the second semiconductor layer 116 around the through-well 102h and between two adjacent through-wells 102h, so that the second semiconductor layer 116 between adjacent through-wells 102h is not covered by the transparent semiconductor layer 118.

[0061] Next, an insulating layer 120 is formed on the transparent conductive layer 118, the insulating layer 120 having openings 120h, 120g, 120j, and 120r. For example, an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, aluminum oxide, or a combination or stack of the above materials, is first deposited on the transparent conductive layer 118. The insulating material can be a single layer or a stack of multiple layers. Then, a photolithography process and an etching process are used... Figure 1C The photomask pattern 106 in the middle is used to pattern insulating material to form an insulating layer 120. Figure 1C In the photomask pattern 106, the insulating material corresponding to the reserved area 106p is retained, while the insulating material corresponding to the blank area 106b is removed, resulting in the following: Figure 2 as well as Figure 3 The results are shown. Figure 2 For example, insulating layer 120 has openings 120h, 120g, 120j, 120r, and an insulating layer edge 106e. For example... Figure 2and Figure 3 As shown, opening 120g corresponds to the position of opening 118a in the transparent conductive layer 118, and the width of opening 120g is greater than the width of opening 118a in the transparent conductive layer, exposing the transparent conductive layer 118 and the second semiconductor layer 116. Opening 120h exposes the transparent conductive layer 118 below it. Opening 120j corresponds to the position of the through-well 102h and exposes the first semiconductor layer 112 within the through-well 102h. Opening 120r exposes the first semiconductor layer 112 within the exposure area 125.

[0062] Next, an electrode layer 122 is formed on the insulating layer 120, wherein the electrode layer 122 has pad regions PDn and PDp and extension regions EXTn and EXTp. For example, a conductive material is deposited on the insulating layer 120. Figure 1D The photomask pattern 108 in the image pattern patterns conductive material to form electrode layer 122. The conductive material includes metals such as chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), rhodium (Rh), or platinum (Pt), or alloys or stacks of these materials. In the photomask pattern 108, the conductive material corresponding to the reserved area 108p is retained, and the conductive material corresponding to the blank area 108b is removed, resulting in an electrode layer 122. Figure 2 as well as Figure 3 The results are shown. Figure 2 The electrode layer edge 108e is shown. (Similar to...) Figure 2 As shown, each pad region PDn and PDp can be used to support the bonding wire in subsequent manufacturing processes. Two extension regions EXTP extend from the pad region PDp. An extension region EXTn extends from the pad region PDn and is located between the two extension regions EXTP, extending towards the pad region PDp. The electrode layer configuration of the light-emitting diode in this application is not limited to this; for example, the number, position, and area of ​​the pad regions and extension regions can be adjusted according to the light-emitting area and operating current of the light-emitting diode.

[0063] In one embodiment, as Figure 2 As shown, the portion of the extension region EXTp corresponding to the opening 120h has a width wider than the opening 120h, so that the extension region EXTp completely covers the opening 120h. Figure 3 In the middle, the extended region EXTp contacts the transparent conductive layer 118 through the opening 120h and is electrically connected to it.

[0064] In this embodiment, the pad region PDp and the extended region EXTP serve as the anode of the light-emitting diode 100. As... Figure 2 and Figure 3As shown, the pad region PDp contacts and is electrically connected to the second semiconductor layer 116 through the insulating layer opening 120g and the transparent conductive layer opening 118a. The extension region EXTp contacts the transparent conductive layer 118 through the spaced openings 120h, which allows the current flowing through the second semiconductor layer 116 to be evenly distributed, thereby increasing the luminous efficiency of the light-emitting diode 100.

[0065] In addition, the pad area PDp directly contacts the second semiconductor layer 116 through the opening 120g of the insulating layer and the opening 118a of the transparent conductive layer, which can increase the adhesion between the electrode layer 122 and the second semiconductor layer 116 and prevent the electrode layer 122 of the pad area PDp from being peeled off by the stress of the welding line during the subsequent formation of the welding line.

[0066] The pad region PDn and the extension region EXTn serve as the cathodes of the light-emitting diode 100. They contact the first semiconductor layer 112 through the insulating layer openings 120j and 120r and the through-well 102h, thus forming an electrical connection with it. The extension region EXTn contacts the first semiconductor layer 112 at intervals through the spaced openings 120j and the through-well 102h, which allows the current flowing through the first semiconductor layer 112 to be evenly distributed, thereby increasing the luminous efficiency of the light-emitting diode 100.

[0067] In one embodiment, such as Figure 2 and Figure 3 As shown, the opening 120r is annular in top view, meaning that a portion of the insulating layer 120 is retained below the pad area PDn, forming a current blocking region. The pad area PDn only contacts the first semiconductor layer 112 through the annular opening 120r. In this way, current is forced to diffuse towards the extension region EXTn, preventing most of the current from flowing directly downwards from the pad area PDn into the semiconductor stack 110, thus avoiding current congestion.

[0068] In one embodiment, the extension region EXTp completely covers the opening 120h, which allows the extension region EXTp to contact the transparent conductive layer 118 even when the photomask pattern 108 and the photomask pattern 106 are offset during the manufacturing process.

[0069] In addition, such as Figure 3As shown, the sidewall of opening 120h is an inclined surface when viewed from the side. The angle between the bottom surface of insulating layer 120 and the inner sidewall of opening 120h is an acute angle, which can be between 20 and 70 degrees. In this way, when the extension area EXTp is disposed above opening 120h, it can conformally cover the insulating layer 120, avoiding the extension area EXTp from undulating due to the thickness of insulating layer 120, which could easily lead to problems such as peeling of insulating layer 120 from the underlying layer or poor adhesion. Similarly, the sidewalls of openings 120g, 120j, 120r, and the sidewalls of insulating layer openings in various embodiments of this application are inclined surfaces when viewed from the side.

[0070] Compared with the prior art, the manufacturing method of the light-emitting diode 100 according to Embodiment 1 of this application and the photomask pattern for making the light-emitting diode 100 can simplify the manufacturing process and save costs.

[0071] Example 2

[0072] Figures 4A to 4D This shows photomask patterns 202, 204, 206, and 208 implemented according to Embodiment 2 of this application for fabricating a light-emitting diode 200. As in Embodiment 1, photomask patterns 202, 204, 206, and 208 are used to define the high plateau region, the transparent conductive layer, the insulating layer, and the electrode layer, respectively. Figure 5 A top view of a light-emitting diode 200 fabricated based on the aforementioned photomask pattern is shown. Figure 6 LED 200 Figure 5 A sectional view of line segment VI-VI.

[0073] The similarities or similarities between Embodiment 2 and Embodiment 1 can be understood through the relevant teachings of Embodiment 1, and will not be repeated here.

[0074] Similar to Example 1, Figure 6 The light-emitting diode 200 includes a semiconductor stack 210, a transparent conductive layer 218, an insulating layer 220, and an electrode layer 222. The semiconductor stack 210 has a first semiconductor layer 212, a light-emitting layer 214, and a second semiconductor layer 216 stacked sequentially.

[0075] like Figures 4A to 4D , Figure 5 and Figure 6As shown, in photomask pattern 202, the blank area 202b corresponds to the etched area of ​​the second semiconductor layer 216, the light-emitting layer 214, and a portion of the first semiconductor layer 212 on the semiconductor stack 210 to be removed; the retained area 202p corresponds to the retained area that is not removed, to form the raised area 224 and the exposed area 225. In photomask pattern 204, the transparent conductive layer 218 corresponding to the retained area 204p is retained, while the transparent conductive layer 218 corresponding to the blank area 204b is removed. In photomask pattern 206, the insulating layer 220 corresponding to the retained area 206p is retained, while the insulating layer 220 corresponding to the blank area 206b is removed. In photomask pattern 208, the electrode layer 222 corresponding to the retained area 208p is retained, while the electrode layer 222 corresponding to the blank area 208b is removed.

[0076] Figure 5 The raised platform edge 202e, the transparent conductive layer edge 204e, the insulating layer edge 206e, and the electrode layer edge 208e are shown. Two extension regions EXTp are connected to both sides of the pad region PDp, and the extension region EXTn extends from the pad region PDn.

[0077] Figure 5 and Figure 6 The diagram shows a through-well 202h defined by photomask pattern 202. Unlike the first embodiment, the extension region EXTP also includes multiple through-wells 202k. Each through-well 202h and 202k has a sidewall 264 and a bottom 262. The sidewall 264 exposes the second semiconductor layer 216, the light-emitting layer 214, and a portion of the first semiconductor layer 212. The bottom 262 exposes the first semiconductor layer 212.

[0078] The transparent conductive layer 218 formed by the photomask pattern 204, such as Figure 5 as well as Figure 6 As shown. Figure 5 The remaining edge 204e of the transparent conductive layer is shown. The transparent conductive layer 218 is located on the raised area 224 and does not cover the exposed area 225. In one embodiment, the transparent conductive layer 218 has an opening. In one embodiment, as... Figure 4B and Figure 5 As shown, the transparent conductive layer 218 has an opening 218a, exposing the second semiconductor layer 216 beneath it. In one embodiment, as... Figure 4B and Figure 5 As shown, the transparent conductive layer 218 has an opening 218b that exposes the second semiconductor layer 216 around the through-well 202h and between two adjacent through-wells 202h, so that the second semiconductor layer 216 between adjacent through-wells 202h is not covered by the transparent semiconductor layer 218. The difference from Embodiment 1 is that the transparent conductive layer 218 further has an opening 218j that exposes the through-well 202k.

[0079] The insulating layer 220 formed by the photomask pattern 206, such as Figure 5 as well as Figure 6 As shown. The insulating layer 220 has openings 220h, 220g, 220j, 220r, and an insulating layer edge 206e. Similar to the light-emitting diode 100 of Embodiment 1, opening 220g is located at the position of opening 218a of the transparent conductive layer 218, and the width of opening 220g is greater than the width of opening 218a of the transparent conductive layer, exposing the transparent conductive layer 218 and the second semiconductor layer 216. Opening 220h is located at the position of the through-well 202k, exposing the transparent conductive layer 218 below it. Opening 220j is located at the through-well 202h, exposing the first semiconductor layer 212 within the through-well 202h. Opening 220r exposes the first semiconductor layer 212 within the exposure region 225.

[0080] from Figure 4C and Figure 5 As can be seen, compared to the light-emitting diode 100 in Embodiment 1 and the photomask pattern used to fabricate the light-emitting diode 100, the photomask pattern 206 can further pattern the insulating layer 220 to form a blocking island 220d. The blocking island 220d and the insulating layer 220 surrounding it form an annular opening 220h, adjacent to the edge of the through-well 202k. The blocking island 220d completely covers the through-well 202k. As... Figure 5 and Figure 6 As shown, the extension region EXTp at least partially overlaps with the through-well 202k. The electrode layer 222 of the extension region EXTp contacts the transparent conductive layer 218 through the annular opening 220h and is electrically in contact with the second semiconductor layer 216. Because there is no transparent conductive layer 218 in the through-well 202k and it is covered by the blocking island 220d, the extension region EXTp of the electrode layer 222 does not have electrical contact with the first semiconductor layer 212 through the through-well 202k.

[0081] When the electrode layer 222 is an opaque metallic material, light in the region below the extended region EXTP may be blocked by the extended region EXTP. Therefore, removing a portion of the second semiconductor layer 216 and the light-emitting layer 214 below the extended region EXTP to form a through-well 202k forces current to diffuse into the unblocked semiconductor stack 210. This reduces the proportion of light emitted after electron-hole recombination in the unblocked semiconductor stack 210 that is blocked by the extended region EXTP, thereby increasing the brightness of the light-emitting diode 200. On the other hand, by using the slope of the through-well 202k or in conjunction with the insulating layer 220 covering it, some of the light emitted by the light-emitting layer 214 can be reflected, changing the direction of the light and improving the light extraction efficiency of the light-emitting diode 200.

[0082] Example 3

[0083] Figure 7 A top view of a light-emitting diode 200a is shown. Figure 8 LED 200a Figure 7 A cross-sectional view of line segment VIII-VIII. The light-emitting diode 200a is fabricated using photomask patterns 202 and 208, just like the other diodes. However, the photomask pattern 204 used to define the transparent conductive layer 218 and the photomask pattern 206 used to define the insulating layer 220 are different from those used in the other diodes. Figure 4B and Figure 4C The results are slightly different.

[0084] The similarities or similarities between Embodiment 3 and Embodiment 2 can be understood through the relevant teachings of Embodiments 1 and 2, and will not be repeated here.

[0085] as Figure 7 As shown, the transparent conductive layer edge 204e defined by the photomask pattern 204 has an opening 218h, and the annular opening 220h of the insulating layer and the through-well 202k completely fall within the opening 218h. In contrast, Figure 5 The annular opening 220h does not fall into opening 218j, while the trap 202k falls completely into opening 218j. Therefore, ... Figure 7 Consistent, Figure 8 In the extended region EXTp, the electrode layer 222 does not contact the transparent conductive layer 218 through the annular opening 220h. The electrode layer 222 of the extended region EXTp directly contacts the second semiconductor layer 216 through the annular opening 220h.

[0086] Compared to Figure 5 , Figure 7 Several openings 220a are added to the edge 206e of the insulating layer defined by the photomask pattern 206. A transparent conductive layer 218 is exposed in each opening 220a. Therefore, Figure 8 In the extended region EXTp, the electrode layer 222 can contact the transparent conductive layer 218 through the opening 220a.

[0087] Example 4

[0088] Figures 9A to 9D Examples show photomask patterns 302, 304, 306, and 308 implemented according to Embodiment 4 of this application for fabricating a light-emitting diode 300, which are used to define a high plateau region, a transparent conductive layer, an insulating layer, and an electrode layer, respectively. Figure 10 A top view of a light-emitting diode 300 fabricated according to the aforementioned photomask pattern is shown. Figure 11 LED 300 Figure 10 A cross-sectional view of line segment XI-XI.

[0089] Similar to the aforementioned embodiments, Figure 10 The light-emitting diode 300 includes a semiconductor stack 310, a transparent conductive layer 318, an insulating layer 320, and an electrode layer 322. The semiconductor stack 310 has a first semiconductor layer 312, a light-emitting layer 314, and a second semiconductor layer 316 stacked sequentially.

[0090] like Figures 9A to 9D , Figure 10 and Figure 11 As shown, in photomask pattern 302, the blank area 302b corresponds to the etched area of ​​the second semiconductor layer 316, the light-emitting layer 314, and part of the first semiconductor layer 312 on the semiconductor stack 310 to be removed; the retained area 302p corresponds to the retained area of ​​the semiconductor stack 310 that is not removed, to form the raised area 324 and the exposed area 325. In photomask pattern 304, the transparent conductive layer 318 corresponding to the retained area 304p is retained, while the transparent conductive layer 318 corresponding to the blank area 304b is removed. In photomask pattern 306, the insulating layer 320 corresponding to the retained area 306p is retained, while the insulating layer 320 corresponding to the blank area 306b is removed. In photomask pattern 308, the electrode layer 322 corresponding to the retained area 308p is retained, while the electrode layer 322 corresponding to the blank area 308b is removed.

[0091] The similarities or similarities between Embodiment 4 and the previous embodiments can be understood through the prior related teachings and will not be repeated. For example, photomask patterns 302 and 304 are the same as photomask patterns 102 and 104 in Embodiment 1, respectively. Therefore, LED 300 and LED 100 also include through-well 302h and transparent conductive layer openings 318a and 318b; photomask pattern 308 is the same as photomask pattern 208 in Embodiment 2.

[0092] as Figure 10 As shown, the insulating layer edge 306e defined by the photomask pattern 306 constitutes the opening 320h and the opening 320r located below the pad area PDn. Unlike the previous embodiment, in this embodiment, the opening 320h is a single and continuous opening, and multiple blocking islands 320d are provided within the opening 320h. The blocking islands 320d are formed by patterning the insulating layer 320. The extension region EXTp at least partially overlaps with the blocking islands 320d. As... Figure 11 As shown, the electrode layer 322 of the extended region EXTp can contact the transparent conductive layer 318 through the opening 320h. The presence of the blocking island 320d allows for a more uniform distribution of current in the transparent conductive layer 318.

[0093] Example 5

[0094] In Examples 1 through 4, four photomasks were used to define the high-mount area, the transparent conductive layer, the insulating layer, and the electrode layer, respectively, to fabricate the light-emitting diode (LED). However, the present invention is not limited to this. In Example 5, the photomask patterns used to define the high-mount area and the transparent conductive layer are integrated into one. Therefore, Example 5 only requires three photomasks to fabricate the LED.

[0095] Figures 12A to 12C Examples show three photomask patterns implemented in the fabrication of the light-emitting diode 400 according to Embodiment 5 of this application, which are respectively labeled as photomask pattern 405, photomask pattern 406, and photomask pattern 408. Figure 13 A top view of a light-emitting diode 400 fabricated according to the aforementioned photomask pattern is shown. Figure 14A and Figure 14B LEDs 400 respectively Figure 13 Two sectional views of line segments XIVA-XIVA and XIVB-XIVB.

[0096] The similarities or similarities between Embodiment 5 and the previous embodiments can be understood through the previous related teachings and will not be repeated.

[0097] as Figure 14A and Figure 14B As shown, the light-emitting diode 400 includes a semiconductor stack 410, a transparent conductive layer 418, an insulating layer 420, and an electrode layer 422. The semiconductor stack 410 has a first semiconductor layer 412, a bulk light-emitting layer 414, and a second semiconductor layer 416 stacked sequentially thereon.

[0098] In terms of the manufacturing process, as in the aforementioned embodiments, a semiconductor stack 410 and a transparent conductive layer 418 can be sequentially formed on a substrate (not shown). Then, a photomask pattern 405 is used to simultaneously pattern the semiconductor stack 410 and the transparent conductive layer 418. Figure 12A and Figure 14A In the diagram, blank area 405b corresponds to the etched area where the transparent conductive layer 418, the second semiconductor layer 416, the light-emitting layer 414, and part of the first semiconductor layer 412 are to be removed; retained area 405p corresponds to the retained area where the layers are not removed. Therefore, in Figure 14A In the photomask pattern 405, the reserved area 405p corresponds to the formation of a raised platform area 424, and a transparent conductive layer 418 is formed on the raised platform area 424. The etched area 405b corresponds to the formation of an exposed area 425, wherein the exposed area 425 includes a through-well 405h. Figure 13The diagram also shows the raised platform corresponding to the photomask pattern 405 and the edge 405e of the transparent conductive layer. In one embodiment, due to different etching conditions in the manufacturing process, the transparent conductive layer 418 may be over-etched, causing its edge to shrink inward, that is, the edge of the transparent conductive layer 418 is surrounded by the raised platform edge 405e. In one embodiment, the distance between the raised platform edge 405e and the edge of the transparent conductive layer 418 is less than 3 μm. Figure 13 The through-well 405h also exposes the first semiconductor layer 412. As shown in Figure 14B, the through-well 405h has sidewalls 464 and a bottom 462. The sidewalls 464 are formed by the transparent conductive layer 418, the second semiconductor layer 416, the light-emitting layer 414, and a portion of the side surface of the first semiconductor layer 412 exposed by the through-well 405h. The bottom 462 is formed by the upper surface of the first semiconductor layer 412 exposed by the through-well 405h.

[0099] An insulating layer 420 is then formed on the transparent conductive layer 118 and patterned according to the photomask pattern 406 of Figure 12B to have openings 420h, 420j, 420g and annular opening 420r. In the photomask pattern 406, the insulating layer 420 corresponding to the reserved area 406p is retained, while the insulating layer 420 corresponding to the blank area 406b is removed. Figure 13 The remaining edge of the insulation layer 406e is shown. Figure 14A In this configuration, opening 420g is located below the pad area PDp, and opening 420h is located below the extension area EXTp. Both openings 420h and 420g expose the transparent conductive layer 418. As in Embodiment 1, the annular opening 420r exposes the first semiconductor layer 412, and opening 420j is located at the position of the through-well 405h, exposing the first semiconductor layer 412 within the through-well 405h.

[0100] Electrode layer 422 is then formed on insulating layer 420 and patterned according to photomask pattern 408 to have pad regions PDn and PDp and extension regions EXTp and EXTn. In photomask pattern 408, electrode layer 422 corresponding to reserved region 408p is retained, while electrode layer 422 corresponding to blank region 408b is removed. Figure 13 Metal edge 408e is shown. Two extension regions EXTp are connected to both sides of the pad region PDp, and extension region EXTn is connected to the top of the pad region PDn.

[0101] as Figure 13 As shown, the pad region PDp overlaps with the opening 420g, the extension region EXTp partially overlaps with the opening 420h, and the extension region EXTn partially overlaps with the opening 420j.

[0102] The electrode layer 422 in the pad region PDp and the extension region EXTp serves as the anode of the light-emitting diode 400, and contacts the transparent conductive layer 418 through openings 420g and 420h, respectively, which is electrically connected to the second semiconductor layer 116.

[0103] The electrode layer 422 in the pad region PDn and the extension region EXTn serves as the cathode of the light-emitting diode 400, and directly contacts the first semiconductor layer 412 through the opening 420j and the annular opening 420r in the through-well 405h.

[0104] Example 5 only requires three photomasks, namely photomask pattern 405, photomask pattern 406, and photomask pattern 408, to fabricate the light-emitting diode 400, which simplifies the manufacturing process and reduces the manufacturing cost.

[0105] In other embodiments, Figure 13 The extended region EXTp can completely surround the opening 420h, similar to Embodiment 1, allowing the extended region EXTp to make relatively certain contact with the transparent conductive layer 418 in the opening 420h. The photomask pattern 406 can also be varied to produce a barrier island 220d and annular opening 220h similar to those in Embodiment 2.

[0106] Example 6

[0107] Figures 15A to 15C For example, the three photomask patterns implemented in the fabrication of the light-emitting diode 500 according to Embodiment 6 of this application are labeled as photomask pattern 505, photomask pattern 506, and photomask pattern 508, respectively. They have blank areas 505b, 506b, and 508b, and reserved areas 505p, 506p, and 508p, respectively, to define the high plateau area and the transparent conductive layer, insulating layer, and electrode layer. Figure 16 A top view of a light-emitting diode 500 fabricated based on the aforementioned photomask pattern is shown. Figure 17 This shows a cross-sectional view of the light-emitting diode 500 along line segment XVII-XVII in section 16. As in Embodiment 5, only three photomasks are needed to fabricate the light-emitting diode 500.

[0108] The similarities or similarities between Embodiment Six and the previous Embodiment Five can be understood from the prior teachings and will not be repeated. Opening 520h is located below the extension region EXTp and exposes the transparent conductive layer 518. As in Embodiment One, the annular opening 520r exposes the first semiconductor layer 512, and 520j is located at the position of the through-well 505h, exposing the first semiconductor layer 512 within the through-well 505h.

[0109] Figure 15A and Figure 16As shown, the semiconductor stack 510 of the light-emitting diode 500 includes a raised area 524, an exposed area 525, a raised edge 505e, and a through-well 505h defined according to the photomask pattern 505. Furthermore, unlike Embodiment 5, the semiconductor stack 510 also includes a through-well 505k located below the pad area PDp. Each through-well 505k and 505h has a sidewall 564 and a bottom 562. The sidewall 564 is formed by the side surface of the transparent conductive layer 518, the second semiconductor layer 516, and the light-emitting layer 514 exposed by the through-well 505k or 505h. The bottom 562 is formed by the upper surface of the first semiconductor layer 512 exposed by the through-well 505k or 505h.

[0110] Among them, the 505k through-well at least partially overlaps with the PDp pad area. Figures 15A-15C and Figure 16 In this embodiment, the through-well 505k is located within the pad region PDp. Unlike embodiment five, the insulating layer 520 covers the bottom 562 and sidewall 564 of the through-well 505k, so that the electrode layer 522 of the pad region PDp does not contact the first semiconductor layer 512 within the bottom 562 of the through-well 505k.

[0111] The presence of through-wells 505k increases the contact area between the pad region PDp of the electrode layer 522 and the insulating layer 520, thereby increasing the adhesion of the electrode layer 522 and preventing the electrode layer 522 from being peeled off by the stress of the bonding wire during the subsequent bonding process. In another embodiment, several through-wells 505k can be provided in the semiconductor stack 510 under the pad region PDp to make the electrode layer 522 adhere more firmly to the insulating layer 520.

[0112] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A light-emitting diode, characterized in that, Include: A semiconductor stack, wherein a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially stacked in a first direction; A transparent conductive layer is formed on the semiconductor stack and is electrically connected to the second semiconductor layer; An insulating layer is formed on the transparent conductive layer, including a first opening; as well as A first electrode layer is formed on the insulating layer, including a first solder pad region and a first extension region, wherein the first extension region connects to the first solder pad region and includes a segment extending in a second direction. as well as The second electrode layer is formed on the insulating layer and is electrically connected to the first semiconductor layer; The first extended region contacts the transparent conductive layer through the first opening; and The first extension region does not overlap with the second electrode layer in the first direction: The section includes a first part located on the first opening and a second part connected to the first part; In a top view, in a direction perpendicular to the second direction, the first portion has a first width, the first opening has a second width, and the second portion has a third width; The first width is greater than the second width and the third width.

2. The light-emitting diode of claim 1 further comprises a plurality of through-wells located in the semiconductor stack, wherein each of the through-wells comprises a sidewall and a bottom, wherein the sidewall comprises a sidewall of the second semiconductor layer, a sidewall of the light-emitting layer and a portion of the sidewall of the first semiconductor layer, and the bottom comprises the upper surface of the first semiconductor layer; The transparent conductive layer includes an opening that exposes the perforated traps.

3. The light-emitting diode of claim 1 further comprises a plurality of through-wells located in the semiconductor stack and the transparent conductive layer, wherein each of the through-wells comprises a sidewall and a bottom, wherein the sidewall comprises the sidewall of the transparent conductive layer, the sidewall of the second semiconductor layer, the sidewall of the light-emitting layer and a portion of the sidewall of the first semiconductor layer, and the bottom comprises the upper surface of the first semiconductor layer; The first pad area is located on one of the through-wells, and the insulating layer covers one of the through-wells.

4. A light-emitting diode, characterized in that, Include: A semiconductor stack, comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially; A penetration well, located in the semiconductor stack, includes sidewalls and a bottom, wherein the penetration well exposes the second semiconductor layer, the light-emitting layer and a portion of the first semiconductor layer; A transparent conductive layer is formed on the semiconductor stack and electrically connected to the second semiconductor layer; An insulating layer is formed on the transparent conductive layer, including a first opening; as well as An electrode layer is formed on the insulating layer and includes a first pad region and a first extension region; The first extension region contacts the transparent conductive layer through the first opening, and the first extension region overlaps with the through-well, but the first extension region does not contact the first semiconductor layer through the through-well. The transparent conductive layer includes a second opening corresponding to the through-well below the first extension region; and In a top view, the first extension area has a width smaller than the width of the through-hole.

5. The light-emitting diode as described in claim 4, wherein, The insulation layer also includes a barrier island surrounded by the first opening.

6. The light-emitting diode as described in claim 5, wherein, The barrier island covers the tunnel and the first extension area extends onto the barrier island.

7. A light-emitting diode, characterized in that, Includes: A semiconductor stack, comprising a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially; A transparent conductive layer is formed on the semiconductor stack and is electrically connected to the second semiconductor layer; An insulating layer is formed on the transparent conductive layer, including a first opening and a plurality of mutually separated barrier islands located in the first opening; as well as An electrode layer is formed on the insulating layer and includes a first pad region and a first extension region; The first extension region has a portion that overlaps with the blocking islands, and the first extension region contacts the transparent conductive layer through the first opening.

8. The light-emitting diode as claimed in claim 7, wherein, The first opening includes a portion located below the first pad area.

9. The light-emitting diode as claimed in claim 7, wherein, The first extension area is set along the first opening.

10. The light-emitting diode of claim 1 or 7, wherein the transparent conductive layer includes a second opening located below the first pad region, exposing the second semiconductor layer.

11. The light-emitting diode of claim 7, further comprising: A penetration well is located in the semiconductor stack, exposing the second semiconductor layer, the light-emitting layer, and a portion of the first semiconductor layer; The insulation layer also includes a third opening exposing the bottom of the tunnel; and The electrode layer also includes a second pad area and a second extension area, the second extension area contacting the first semiconductor layer through the third opening.

12. The light-emitting diode as claimed in claim 1 or 7, further comprising: Multiple through-wells are located in the semiconductor stack, exposing the second semiconductor layer, the light-emitting layer, and a portion of the first semiconductor layer; The transparent conductive layer includes a fourth opening that exposes the perforated traps and the second semiconductor layer between adjacent perforated traps.

13. The light-emitting diode as claimed in claim 1, 4 or 7, wherein the insulating layer further includes a fifth opening, and the first pad region is electrically connected to the second semiconductor layer through the fifth opening.

Images