Scan Driver and Display Device Having the Same

Abstract

A scan driver and a display device having the scan driver are provided. The scan driver includes a plurality of stages. The n-th stage (n is a natural number) among the plurality of stages includes a first input circuit and a second input circuit that respectively control the voltage of a first node in response to carry signals of a previous stage and a next stage, a first output circuit that outputs an n-th carry signal corresponding to a carry clock signal in response to the voltage of the first node, a second output circuit that outputs an n-th scan signal and an n-th sense signal corresponding to a scan clock signal and a sense clock signal respectively in response to the voltage of the first node, and a sampling circuit that stores the carry signal of the previous stage in response to a first selection signal and supplies a control voltage to the first node in response to a second selection signal and the stored carry signal.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0060734, filed with the Korean Intellectual Property Office (KIPO) on May 23, 2019, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure generally relates to a scan driver and a display device having the scan driver. Background art

[0004] A display device includes a data driver, a scan driver, and pixels. The data driver generates data signals, and the scan driver generates scan signals. The scan driver sequentially supplies the scan signals to the pixels, and accordingly, the pixels are sequentially selected. The data signals are provided to the selected pixels, and the selected pixels emit light having a luminance corresponding to the data signals. Summary of the invention

[0005] Aspects of exemplary embodiments relate to a scan driver capable of selecting only specific pixels to measure mobility information and threshold voltage information of driving transistors in each pixel.

[0006] Aspects of exemplary embodiments also relate to a scan driver configured to selectively generate scan signals and a display device having the scan driver.

[0007] According to an embodiment of the present disclosure, a scan driver is provided, which includes a plurality of stages. Among them, the nth stage (n is a natural number) of the plurality of stages includes a first input circuit, a second input circuit, a first output circuit, a second output circuit, and a sampling circuit. The first input circuit is configured to control the voltage of a first node in response to a carry signal of the previous stage of the nth stage supplied to a first input terminal. The second input circuit is configured to control the voltage of the first node in response to a carry signal of the next stage of the nth stage supplied to a second input terminal. The first output circuit is configured to output an nth carry signal corresponding to a carry clock signal supplied to a first clock terminal to a first output terminal in response to the voltage of the first node. The second output circuit is configured to output an nth scan signal corresponding to a scan clock signal supplied to a second clock terminal to a second output terminal in response to the voltage of the first node and output an nth sense signal corresponding to a sense clock signal supplied to a third clock terminal to a third output terminal in response to the voltage of the first node. The sampling circuit is configured to store the carry signal of the previous stage in response to a first selection signal supplied to a first control terminal and supply a control voltage supplied through a reference power supply terminal to the first node in response to a second selection signal supplied to a second control terminal and the stored carry signal of the previous stage.

[0008] Each of the first input circuit, the second input circuit, the first output circuit, the second output circuit, and the sampling circuit may include an oxide semiconductor transistor.

[0009] The control voltage may be a gate turn-on voltage for turning on the oxide semiconductor transistor.

[0010] The sampling circuit may include a first transistor, a capacitor, a second transistor, and a third transistor. The first transistor is connected between a first input terminal and a first control node, and the first transistor includes a gate electrode connected to a first control terminal. The capacitor is connected between the first control node and a reference power supply terminal. The second transistor is connected between the reference power supply terminal and a second control node, and the second transistor includes a gate electrode connected to the first control node. The third transistor is connected between the second control node and the first node, and the third transistor includes a gate electrode connected to a second control terminal.

[0011] The first transistor may include a first sub-transistor and a second sub-transistor connected in series with each other. One electrode of the first sub-transistor and one electrode of the second sub-transistor may be connected to the second control node.

[0012] The sampling circuit may discharge the first node in response to a scan start signal supplied to a third control terminal.

[0013] The sampling circuit may further include a fourth transistor, wherein the fourth transistor is coupled between a first power supply terminal to which a first power supply is applied and a first node, and the fourth transistor includes a gate electrode coupled to a third control terminal. The first power supply may have a voltage level lower than the voltage level of the control voltage.

[0014] A stage that receives a carry signal of a previous stage having a pulse overlapping with a pulse of a first selection signal may be selected from among a plurality of stages. The selected stage may output a sense signal corresponding to a sense clock signal after a pulse of a second selection signal is applied.

[0015] A stage may be initialized in response to a scan start signal corresponding to a carry signal of a previous stage.

[0016] The scan driver may further include a feedback circuit, wherein the feedback circuit is configured to supply a control voltage to the first input circuit and the second input circuit in response to the voltage of the first node.

[0017] The first input circuit may include a fifth transistor and a sixth transistor, wherein the fifth transistor includes a first electrode coupled to a first input terminal, a second electrode coupled to a feedback node, and a gate electrode coupled to the first input terminal, and the sixth transistor includes a first electrode coupled to the feedback node, a second electrode coupled to the first node, and a gate electrode coupled to the first input terminal. The feedback circuit may include a seventh transistor, wherein the seventh transistor includes a first electrode coupled to a reference power supply terminal, a second electrode coupled to the feedback node, and a gate electrode coupled to the first node.

[0018] The second input circuit may control the voltage of the first node in response to the voltage of the second node. The second input circuit may include a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein the ninth transistor includes a first electrode coupled to the first node, a second electrode coupled to the feedback node, and a gate electrode coupled to a second input terminal, the tenth transistor includes a first electrode coupled to the feedback node, a second electrode coupled to a first power supply terminal to which a first power supply is applied, and a gate electrode coupled to the second input terminal, the eleventh transistor includes a first electrode coupled to the first node, a second electrode coupled to the feedback node, and a gate electrode coupled to the second node, and the twelfth transistor includes a first electrode coupled to the feedback node, a second electrode coupled to a first power supply terminal to which a first power supply is applied, and a gate electrode coupled to the second node.

[0019] The scan driver may further include a controller, wherein the controller is configured to supply a sense clock signal to the second node and is configured to discharge the second node in response to the voltage of the first node.

[0020] The first input circuit may include a fifth transistor and a sixth transistor. The fifth transistor includes a first electrode connected to a reference power supply terminal, a second electrode connected to a feedback node, and a gate electrode connected to a first input terminal. The sixth transistor includes a first electrode connected to the feedback node, a second electrode connected to a first node, and a gate electrode connected to the first input terminal. The feedback circuit may include a seventh transistor. The seventh transistor includes a first electrode connected to the reference power supply terminal, a second electrode connected to the feedback node, and a gate electrode connected to the first node.

[0021] The scan driver may further include a feedback circuit. The feedback circuit is configured to supply the nth scan signal or the nth sense signal to the first input circuit and the second input circuit.

[0022] According to an embodiment of the present disclosure, a display device is provided. The display device includes a plurality of pixels, a scan driver, a data driver, and a compensator. The plurality of pixels are respectively connected to scan lines, sense lines, readout lines, and data lines. The scan driver includes a plurality of stages configured to supply scan signals to the scan lines and supply sense signals to the sense lines. The data driver is configured to supply data signals to the data lines. The compensator is configured to generate a compensation value for compensating for the degradation of the pixels based on the sensed values provided from the readout lines. Among the plurality of stages, the nth stage (n is a natural number) includes a first input circuit, a second input circuit, a first output circuit, a second output circuit, and a sampling circuit. The first input circuit is configured to control the voltage of a first node in response to a carry signal of the previous stage of the nth stage supplied to a first input terminal. The second input circuit is configured to control the voltage of the first node in response to a carry signal of the next stage of the nth stage supplied to a second input terminal. The first output circuit is configured to output an nth carry signal corresponding to a carry clock signal supplied to a first clock terminal to a first output terminal in response to the voltage of the first node. The second output circuit is configured to output an nth scan signal corresponding to a scan clock signal supplied to a second clock terminal to a second output terminal in response to the voltage of the first node and output an nth sense signal corresponding to a sense clock signal supplied to a third clock terminal to a third output terminal in response to the voltage of the first node. The sampling circuit is configured to store the carry signal of the previous stage in response to a first selection signal supplied to a first control terminal and supply a control voltage supplied through a reference power supply terminal to the first node in response to a second selection signal supplied to a second control terminal and the stored carry signal of the previous stage.

[0023] The scan driver may further include a dummy stage. The dummy stage is configured to generate a reference carry signal corresponding to a scan start signal and provide the reference carry signal to the first stage among the plurality of stages as the carry signal of the previous stage. The dummy stage may be electrically separated from the scan lines and the sense lines.

[0024] In a first cycle, a data signal may be supplied to a data line, and a first select signal may be supplied to a stage. In a second cycle, the data signal may not be supplied to the data line, and a second select signal may be supplied to the stage.

[0025] A stage that receives a carry signal from a previous stage having a pulse overlapping with a pulse of the first select signal may be selected from among a plurality of stages. When a pulse of the second select signal is applied, the selected stage may output a sense signal corresponding to a sense clock signal.

[0026] A sampling circuit may discharge a first node in response to a scan start signal supplied to a third control terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which like reference numerals refer to like elements throughout. However, the present invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary for a complete understanding of the aspects and features of the present invention by those of ordinary skill in the art may not be described.

[0028] In the drawings, for clarity of illustration, dimensions may be exaggerated. It should be understood that when an element is referred to as being “between” two elements, the element may be the only element between the two elements, or there may also be one or more intervening elements. Throughout the specification, like reference numerals refer to like elements.

[0029] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is shown including Figure 1 an example of a pixel in the display device shown.

[0031] Figure 3 is shown including Figure 1 an example of a scan driver in the display device shown.

[0032] Figure 4 is shown including Figure 1 an example of a stage in the scan driver shown.

[0033] Figure 5 is shown in Figure 4 an example of a waveform of a signal measured in the stage shown.

[0034] Figure 6 is a waveform diagram showing an example of a signal measured in the stage shown in Figure 4 .

[0035] Figure 7 is a waveform diagram showing another example of a signal measured in the stage shown in Figure 4 .

[0036] Figure 8 is a graph showing the voltage-current characteristics of transistors included in the stage shown in Figure 4 .

[0037] Figure 9 is a circuit diagram showing an example of a stage included in the scan driver shown in Figure 1 .

[0038] Figure 10 is a circuit diagram showing an example of a stage included in the scan driver shown in Figure 1 . DETAILED DESCRIPTION

[0039] Example embodiments of the present disclosure may specifically illustrate different variations and shapes in specific instances. However, the examples are not limited to certain shapes and variations. For example, in some embodiments, equivalent materials may be used as substitutes.

[0040] Meanwhile, in the following embodiments and drawings, elements not directly related to the present disclosure may be omitted from the description, and the dimensional relationships between the respective elements in the drawings may be exaggerated for ease of understanding and may not be drawn to actual scale. It should be noted that when assigning reference numerals to the elements of each drawing, even if the same element is shown in different drawings, the same reference numeral indicates the same element.

[0041] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the spirit and scope of the inventive concept.

[0042] The terms used in this document are for the purpose of describing specific embodiments only and are not intended to limit the inventive concept. Unless clearly indicated otherwise in the context, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms. It should also be understood that when the terms "comprise" and / or "comprising" are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, when describing embodiments of the inventive concept, the use of "may" means "one or more embodiments of the inventive concept".

[0043] As used herein, the terms "substantially", "about", and similar terms are used as approximate terms rather than terms of degree and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0044] In addition, any numerical range recited herein is intended to include all sub-ranges of the same numerical precision that fall within the recited range. For example, the range "1.0 to 10.0" is intended to include all sub-ranges between the recited minimum value of 1.0 and the recited maximum value of 10.0 (and including the recited minimum value of 1.0 and the recited maximum value of 10.0), i.e., all sub-ranges having a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10.0, such as 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations that fall within it, and any minimum numerical limitation recited in this specification is intended to include all greater numerical limitations that fall within it. Accordingly, the applicant reserves the right to amend this specification (including the claims) to expressly recite any sub-ranges that fall within the ranges expressly recited herein.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the specification, and should not be interpreted in an idealized or overly formal sense.

[0046] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure.

[0047] Referring to Figure 1 , the display device 10 according to an embodiment of the present disclosure may include a timing controller 11, a data driver 12, a scan driver (or gate driver) 13, a sensor (or sensing driver) 14, and a pixel unit (or display panel) 15.

[0048] The timing controller 11 may provide a gray value (or gray level value), a control signal, etc. to the data driver 12. Additionally, the timing controller 11 may provide a clock signal, a control signal, etc. to the scan driver 13.

[0049] The data driver 12 may generate data signals to be provided to data lines D1 to Dq (q is a positive integer) by using the gray value, control signal, etc. received from the timing controller 11. For example, the data driver 12 may sample the gray value by using a clock signal and provide the data signals corresponding to the gray value to the data lines D1 to Dq in units of pixel rows.

[0050] The scan driver 13 may generate scan signals to be provided to scan lines SC1 to SCp (p is a positive integer) by receiving a clock signal, a control signal, etc. from the timing controller 11. For example, the scan driver 13 may sequentially provide scan signals of pulses having a gate-on voltage (e.g., pulses reaching the gate-on voltage level or on-voltage level) to the scan lines SC1 to SCp. For example, the scan driver 13 may generate scan signals by sequentially transmitting pulses of the gate-on voltage to the next stage according to a clock signal. For example, the scan driver 13 may be configured in the form of a shift register.

[0051] Additionally, the scan driver 13 may generate sensing signals to be provided to sensing lines SS1 to SSp. For example, the scan driver 13 may sequentially provide sensing signals of pulses having a gate-on voltage to the sensing lines SS1 to SSp. For example, the scan driver 13 may generate sensing signals by sequentially transmitting pulses of the gate-on voltage to the next stage according to a clock signal.

[0052] However, the above operations of the scan driver 13 are associated with operations in a display period (e.g., an active period or data recording period in which data signals are provided to data lines D1 to Dq), and operations in a sensing period (e.g., a blanking period, a vertical blanking period, or an edge period) will be described later with reference to Figure 6 which will be described later. The display period and the sensing period may be included in one frame period (or one frame).

[0053] The sensor 14 can measure the degradation information of the pixel based on the current or voltage received through the receiving lines R1 to Rq. For example, the degradation information of the pixel can be the mobility information of the driving transistor, the threshold voltage information of the driving transistor, the degradation information of the light-emitting element, etc. In addition, the sensor 14 can measure the characteristic information of the pixel corresponding to the environment based on the current or voltage received through the receiving lines R1 to Rq. For example, the sensor 14 can measure the characteristic information of the pixel that changes according to temperature or humidity.

[0054] The pixel unit 15 can include pixels PXij (or a plurality of pixels). The pixel PXij (i and j are positive integers) can be connected to a corresponding data line (e.g., Dj), a corresponding scan line (e.g., SCi), a corresponding sensing line (e.g., SSi), and a corresponding receiving line (e.g., Rj). In other words, the pixel PXij can be connected to the i-th scan line SCi and can be connected to the j-th data line Dj.

[0055] Figure 2 is a circuit diagram showing an example of a pixel included in Figure 1 the display device shown.

[0056] Referring to Figure 2 , the pixel PXij can include switching elements M1, M2, and M3, a storage capacitor Cst, and a light-emitting element LD. Each of the switching elements M1, M2, and M3 can be implemented with an n-type transistor.

[0057] The first switching element (or driving transistor) M1 can include a first electrode connected to the first power supply VDD (or the first power supply line to which the first power supply VDD is applied), a second electrode connected to the second node Nb, and a gate electrode connected to the first node Na.

[0058] The second switching element (or switching transistor) M2 can include a first electrode connected to the data line Dj, a second electrode connected to the first node Na, and a gate electrode connected to the scan line SCi.

[0059] The third switching element (or sensing transistor) M3 can include a first electrode connected to the receiving line Rj, a second electrode connected to the second node Nb, and a gate electrode connected to the sensing line SSi.

[0060] The storage capacitor Cst can be connected between the first node Na and the second node Nb.

[0061] The anode of the light-emitting element LD can be connected to the second node Nb, and the cathode of the light-emitting element LD can be connected to the second power supply VSS (or the second power supply line to which the second power supply VSS is applied). The light-emitting element LD can be configured with an organic light-emitting diode, an inorganic light-emitting diode, etc.

[0062] During the display period within one frame period, pulses of a gate-on voltage (e.g., gate-on voltage level or on-voltage level) may be applied to the scan line SCi and the sense line SSi. A corresponding data signal may be applied to the data line Dj, and a first reference voltage may be applied to the receive line Rj. The second switching element M2 and the third switching element M3 may be turned on, and the storage capacitor Cst may store a voltage corresponding to the difference between the data signal and the first reference voltage. Subsequently, when the second switching element M2 and the third switching element M3 are turned off, the drive current amount flowing through the first switching element M1 may be determined corresponding to the voltage stored in the storage capacitor Cst, and the light-emitting element LD may emit light corresponding to the drive current amount.

[0063] Figure 3 is a diagram showing an example of a scan driver included in Figure 1 the display device shown.

[0064] Referring to Figure 3 , the scan driver 13 may include a plurality of stages ST1, ST2, and ST3. Additionally, the scan driver 13 may further include a dummy stage ST0.

[0065] A clock signal CLKs, a first signal (or first selection signal) S1, a second signal (or second selection signal) S2, a control voltage Von (e.g., gate-on voltage Von or high voltage), a first power supply Vss1 (e.g., gate-off voltage or first low voltage), and a second power supply (or second low voltage) Vss2 may be applied to the dummy stage ST0 and the stages ST1, ST2, and ST3. The clock signal CLKs, the first signal S1, and the second signal S2 may be included in the control signal and may be provided from the timing controller 11. The control voltage Von, the first power supply Vss1, and the second power supply Vss2 may be provided from the timing controller 11, the data driver 12, or a separate power supply.

[0066] The clock signal CLKs may include a first clock signal (or carry clock signal) CR_CK, a second clock signal (or scan clock signal) SC_CK, and a third clock signal (or sense clock signal) SS_CK.

[0067] Each of the first clock signal CR_CK, the second clock signal SC_CK, and the third clock signal SS_CK may be set to a square wave signal that alternately repeats between a logic high level and a logic low level. The logic high level may correspond to the gate-on voltage, and the logic low level may correspond to the gate-off voltage. For example, the logic high level may be a voltage value of about 10V to about 30V, and the logic low level may be a voltage value of about -16V to about -3V.

[0068] In an embodiment, a clock signal CLKs may be provided to odd-numbered stages ST1 and ST3, and an inverted clock signal may be provided to even-numbered stages ST2 (and a dummy stage ST0). The period of the inverted clock signal may be equal to the period of the clock signal CLKs. The inverted clock signal may have a phase that is inverted with respect to the phase of the clock signal CLKs, or a phase that is delayed by half a period with respect to the phase of the clock signal CLKs. In an embodiment, the inverted clock signal may be provided to odd-numbered stages ST1 and ST3, and the clock signal CLKs may be provided to even-numbered stages ST2 (and a dummy stage ST0).

[0069] Each of a first signal S1 and a second signal S2 may include a pulse having a logic high level. The first signal S1 and the second signal S2 may be used to select one of the stages ST1, ST2, and ST3. A description will be made later with reference to Figure 6 a configuration for selecting one of the stages ST1, ST2, and ST3 by using the first signal S1 and the second signal S2.

[0070] A control voltage Von may correspond to a gate-on voltage, and each of a first power supply Vss1 and a second power supply Vss2 may correspond to a gate-off voltage. For example, the control voltage Von may have a voltage value of about 10V to about 30V. In an embodiment, the first power supply Vss1 and the second power supply Vss2 may be the same (e.g., the first power supply Vss1 and the second power supply Vss2 may have the same voltage level). In other embodiments, the second power supply Vss2 may have a voltage level lower (or smaller) than the voltage level of the first power supply Vss1. For example, the first power supply Vss1 may be set in a range of about -14V to about -1V, and the second power supply Vss2 may be set in a range of about -16V to about -3V.

[0071] The dummy stage ST0 may generate a reference carry signal CR[0] in response to a scan start signal (or start pulse) STVP, and provide the reference carry signal CR[0] to the first stage ST1. The scan start signal STVP may be included in a control signal and may be provided from a timing controller 11. The dummy stage ST0 is not connected to a scan line and a sense line, and may be electrically separated (e.g., electrically isolated) from the scan line and the sense line.

[0072] Levels ST1, ST2, and ST3 can output scan signals SC[1], SC[2], and SC[3] and carry signals CR[1], CR[2], and CR[3] respectively in response to carry signals provided from the previous level. For example, the first level ST1 can output the first scan signal SC[1] to the first scan line SC1 in response to the reference carry signal CR[0], and output the first carry signal CR[1] to the second level ST2. The first carry signal CR[1] can also be provided to the dummy level ST0. Similarly, the second level ST2 can output the second scan signal SC[2] to the second scan line SC2 in response to the first carry signal CR[1], and provide the second carry signal CR[2] to the third level ST3 and the first level ST1. That is, the nth (n is a positive integer) level can output the nth scan signal to the nth scan line in response to the (n - 1)th carry signal, and provide the nth carry signal to the (n + 1)th level and the (n - 1)th level.

[0073] Figure 4 is a circuit diagram showing an example of the levels included in Figure 1 the scan driver shown in. Figure 3 The first level ST1 to the third level ST3 (and the dummy level ST0) shown in are substantially similar to each other, and the level ST will be described as including the first level ST1 to the third level ST3.

[0074] Referring to Figure 4 , the level ST can include a first clock terminal IN_CK1, a second clock terminal IN_CK2, a third clock terminal IN_CK3, a first input terminal IN1, a second input terminal IN2, a first control terminal IN_S1, a second control terminal IN_S2, a third control terminal IN_S3, a reference power terminal IN_V0, a first power terminal IN_V1, a second power terminal IN_V2, a first output terminal OUT1, a second output terminal OUT2, and a third output terminal OUT3.

[0075] The first clock signal (or carry clock signal) CR_CK can be provided to the first clock terminal IN_CK1, the second clock signal (or scan clock signal) SC_CK can be provided to the second clock terminal IN_CK2, and the third clock signal (or sense clock signal) SS_CK can be provided to the third clock terminal IN_CK3.

[0076] The carry signal of the previous level (i.e., the previous level carry signal CR[N - 1]) can be provided to the first input terminal IN1, the carry signal of the next level (i.e., the carry signal of the next level CR[N]+1) can be provided to the second input terminal IN2, and the scan start signal (or start pulse) STVP can be provided to the third control terminal IN_S3.

[0077] The first signal (or first selection signal) S1 can be supplied to the first control terminal IN_S1, and the second signal (or second selection signal) S2 can be supplied to the second control terminal IN_S2.

[0078] The control voltage (or gate conduction voltage) Von can be supplied to the reference power supply terminal IN_V0, the first power supply Vss1 can be applied to the first power supply terminal IN_V1, and the second power supply Vss2 can be applied to the second power supply terminal IN_V2.

[0079] The carry signal CR[N] can be output through the first output terminal OUT1, the scan signal SC[N] can be output through the second output terminal OUT2, and the sense signal SS[N] can be output through the third output terminal OUT3.

[0080] The stage ST can include a first sub-stage SST1 to a fifth sub-stage SST5. The first sub-stage SST1 to the fifth sub-stage SST5 can include a first transistor T1, a second transistor T2, a third transistor T3, and fourth transistors T4-1 and T4-2, a first auxiliary transistor T1-1, a second auxiliary transistor T2-1, and a third auxiliary transistor T3-1, a seventh transistor T7, an eighth transistor T8, ninth transistors T9-1 and T9-2, tenth transistors T10-1 and T10-2, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor TT13, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, eighteenth transistors T18-1 and T18-2, nineteenth transistors T19-1 and T19-2, a twentieth transistor T20, and a twenty-first transistor T21, and first capacitors C1, C2, and C3. Each of the transistors can be an oxide semiconductor transistor or an n-type transistor.

[0081] The first sub-stage (or sampling unit, sampling circuit) SST1 can store the carry signal of the previous stage (i.e., the previous stage carry signal CR[N-1]) in response to the first signal (or first control signal) S1 supplied to the first control terminal IN_S1, and supply the control voltage Von supplied through the reference power supply terminal IN_V0 to the first node N_Q in response to the second signal (or second selection signal) S2 supplied to the second control terminal IN_S2 and the stored previous stage carry signal CR[N-1]. In addition, the first sub-stage SST1 can discharge the first node N_Q in response to the scan start signal STVP supplied to the third control terminal IN_S3.

[0082] The first sub - stage SST1 may include the eighteenth transistors T18 - 1 and T18 - 2, the nineteenth transistors T19 - 1 and T19 - 2, the twentieth transistor T20, the twenty - first transistor T21, and the third capacitor C3. The eighteenth transistors T18 - 1 and T18 - 2 may be implemented by a dual - gate transistor including the (18 - 1)th transistor T18 - 1 and the (18 - 2)th transistor T18 - 2, and the nineteenth transistors T19 - 1 and T19 - 2 may be implemented by a dual - gate transistor including the (19 - 1)th transistor T19 - 1 and the (19 - 2)th transistor T19 - 2.

[0083] The (18 - 1)th transistor T18 - 1 and the (18 - 2)th transistor T18 - 2 may be electrically connected between the first node N_Q and the second power - supply terminal IN_V2. The (18 - 1)th transistor T18 - 1 may include a first electrode connected to the first node N_Q, a second electrode connected to the third node (or feedback node) N_FB, and a gate electrode connected to the third control terminal IN_S3. The (18 - 2)th transistor T18 - 2 may include a first electrode connected to the third node N_FB, a second electrode connected to the second power - supply terminal IN_V2 to which the second power supply Vss2 is applied, and a gate electrode connected to the third control terminal IN_S3.

[0084] In response to the scan start signal STVP, the (18 - 1)th transistor T18 - 1 and the (18 - 2)th transistor T18 - 2 may discharge or pull down the first node N_Q by using the second power supply Vss2.

[0085] The (19 - 1)th transistor T19 - 1 and the (19 - 2)th transistor T19 - 2 may be connected between the first input terminal IN1 and the first control node N_S. The (19 - 1)th transistor T19 - 1 may include a first electrode connected to the first input terminal IN1, a second electrode connected to the second control node N_SF, and a gate electrode connected to the first control terminal IN_S1. The (19 - 2)th transistor T19 - 2 may include a first electrode connected to the second control node N_SF, a second electrode connected to the first control node N_S, and a gate electrode connected to the first control terminal IN_S1.

[0086] The (19 - 1)th transistor T19 - 1 and the (19 - 2)th transistor T19 - 2 may transmit the carry - in signal CR[N - 1] from the previous stage to the first control node N_S in response to the first signal S1.

[0087] The third capacitor C3 may be connected between the reference power supply terminal IN_V0 and the first control node N_S. The third capacitor C3 may be charged by the carry signal CR[N-1] of the previous stage transmitted through the (19-1)th transistor T19-1 and the (19-2)th transistor T19-2 or store the carry signal CR[N-1] of the previous stage.

[0088] The twentieth transistor T20 may include a first electrode connected to the reference power supply terminal IN_V0, a second electrode connected to the second control node N_SF, and a gate electrode connected to the first control node N_S. The twentieth transistor T20 may transmit the control voltage Von to the second control node N_SF in response to the voltage of the first control node N_S (e.g., the carry signal CR[N-1] of the previous stage).

[0089] The twenty-first transistor T21 may include a first electrode connected to the second control node N_SF, a second electrode connected to the first node N_Q, and a gate electrode connected to the second control terminal IN_S2. The twenty-first transistor T21 may transmit the voltage of the second control node N_SF (e.g., the control voltage Von) in response to the second signal S2.

[0090] In an embodiment, during a display period (or data writing period), in a period where the carry signal CR[N-1] of the previous stage of the gate conduction voltage and the first signal S1 of the gate conduction voltage overlap with each other, the first sub-stage SST1 may turn on the twentieth transistor T20 while charging the third capacitor C3 by using the carry signal CR[N-1] of the previous stage. In addition, when the second signal S2 of the gate conduction voltage is applied during a blanking period (or sensing period), the first sub-stage SST1 may transmit the control voltage Von to the first node N_Q through the twentieth transistor T20 and the twenty-first transistor T21. In other words, the first node N_Q may be charged.

[0091] The second sub-stage (or charger or first input unit or first input circuit) SST2 may control the voltage of the first node N_Q in response to the carry signal of the previous stage (i.e., the carry signal CR[N-1] supplied to the first input terminal IN1).

[0092] The second sub-stage SST2 may include fourth transistors T4-1 and T4-2. The fourth transistors T4-1 and T4-2 may be implemented by a dual-gate transistor including the (4-1)th transistor T4-1 and the (4-2)th transistor T4-2.

[0093] The (4-1) transistor T4-1 and the (4-2) transistor T4-2 can be coupled between the first input terminal IN1 and the first node N_Q. The (4-1) transistor T4-1 can include a first electrode coupled to the first input terminal IN1, a second electrode coupled to the third node N_FB, and a gate electrode coupled to the first input terminal IN1. The (4-2) transistor T4-2 can include a first electrode coupled to the third node N_FB, a second electrode coupled to the first node N_Q, and a gate electrode coupled to the first input terminal IN1.

[0094] The second sub-stage SST2 (or the fourth transistors T4-1 and T4-2) can charge the first node N_Q by receiving the carry signal CR[N-1] from the previous stage.

[0095] The third sub-stage SST3 (or the stabilizer or the second input unit or the second input circuit) can control the voltage of the first node N_Q in response to the carry signal of the next stage (i.e., the carry signal CR[N+1] supplied to the second input terminal IN2).

[0096] The third sub-stage SST3 can include the ninth transistors T9-1 and T9-2 and the tenth transistors T10-1 and T10-2. The ninth transistors T9-1 and T9-2 can be implemented by a dual-gate transistor including the (9-1) transistor T9-1 and the (9-2) transistor T9-2, and the tenth transistors T10-1 and T10-2 can be implemented by a dual-gate transistor including the (10-1) transistor T10-1 and the (10-2) transistor T10-2.

[0097] The ninth transistors T9-1 and T9-2 and the tenth transistors T10-1 and T10-2 can be coupled between the first node N_Q and the second power supply terminal IN_V2.

[0098] The (9-1) transistor T9-1 can include a first electrode coupled to the first node N_Q, a second electrode coupled to the third node N_FB, and a gate electrode coupled to the second input terminal IN2. The (9-2) transistor T9-2 can include a first electrode coupled to the third node N_FB, a second electrode coupled to the second power supply terminal IN_V2, and a gate electrode coupled to the second input terminal IN2.

[0099] Similarly, the (10-1) transistor T10-1 can include a first electrode coupled to the first node N_Q, a second electrode coupled to the third node N_FB, and a gate electrode coupled to the second node N_QB. The (10-2) transistor T10-2 can include a first electrode coupled to the third node N_FB, a second electrode coupled to the second power supply terminal IN_V2, and a gate electrode coupled to the second node N_QB.

[0100] In response to the next-stage carry signal CR[N+1], the (9-1)th transistor T9-1 and the (9-2)th transistor T9-2 can discharge or pull down the first node N_Q using the second power supply Vss2. Similarly, the (10-1)th transistor T10-1 and the (10-2)th transistor T10-2 can discharge the first node N_Q in response to the voltage of the second node N_QB.

[0101] That is, the third sub-stage SST3 can discharge the first node N_Q in response to the next-stage carry signal CR[N+1] and the voltage of the second node N_QB.

[0102] The fourth sub-stage (or feedback unit or feedback circuit) SST4 can supply the control voltage Von to the second sub-stage SST2 and the third sub-stage SST3 in response to the voltage of the first node N_Q.

[0103] The fourth sub-stage SST4 can include the sixteenth transistor T16.

[0104] The sixteenth transistor T16 can include a first electrode connected to the reference power supply terminal IN_V0, a second electrode connected to the third node N_FB, and a gate electrode connected to the first node N_Q.

[0105] When the first node N_Q is charged, the fourth sub-stage SST4 (or the sixteenth transistor T16) can charge the third node N_FB with the control voltage Von.

[0106] The fifth sub-stage (or inverter or controller) SST5 supplies the third clock signal (or sense clock signal) SS_CK to the second node N_QB, and can discharge the second node N_QB in response to the voltage of the first node N_Q.

[0107] The fifth sub-stage SST5 can include the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the thirteenth transistor T13.

[0108] The seventh transistor T7 can include a first electrode connected to the third clock terminal IN_CK3, a second electrode connected to the second node N_QB, and a gate electrode connected to the fourth node N_C.

[0109] The eighth transistor T8 can include a first electrode connected to the second node N_QB, a second electrode connected to the second power supply terminal IN_V2, and a gate electrode connected to the first node N_Q.

[0110] The twelfth transistor T12 can include a first electrode connected to the third clock terminal IN_CK3, a second electrode connected to the fourth node N_C, and a gate electrode connected to the third clock terminal IN_CK3.

[0111] The thirteenth transistor T13 may include a first electrode connected to the fourth node N_C, a second electrode connected to the first power supply terminal IN_V1, and a gate electrode connected to the first node N_Q.

[0112] The fifth sub-stage SST5 supplies a signal synchronized with the third clock signal SS_CK to the second node N_QB, and may discharge the second node N_QB when the voltage of the first node N_Q is sufficiently higher than the voltage level of the first power supply Vss1.

[0113] The sixth sub-stage (or the first output unit or the first output circuit) SST6 may output a carry signal CR[N] corresponding to the first clock signal (or carry clock signal) CR_CK supplied to the first clock terminal IN_CK1 to the first output terminal OUT1 in response to the voltage of the first node N_Q.

[0114] The sixth sub-stage SST6 may include a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1. In addition, the sixth sub-stage SST6 may further include a first auxiliary transistor T1-1, a second auxiliary transistor T2-1, a third auxiliary transistor T3-1, and a second capacitor C2.

[0115] The first transistor T1 may include a first electrode connected to the third clock terminal IN_CK3, a second electrode connected to the third output terminal OUT3, and a gate electrode connected to the first node N_Q.

[0116] The second transistor T2 may include a first electrode connected to the third output terminal OUT3, a second electrode connected to the first power supply terminal IN_V1, and a gate electrode connected to the second input terminal IN2.

[0117] The third transistor T3 may include a first electrode connected to the third output terminal OUT3, a second electrode connected to the first power supply terminal IN_V1, and a gate electrode connected to the second node N_QB.

[0118] The first capacitor C1 may be coupled between the first node N_Q and the third output terminal OUT3.

[0119] The first capacitor C1 may store the control voltage Von transmitted through the second sub-stage SST2 and the fourth sub-stage SST4. When the first node N_Q is charged, the first transistor T1 may transmit the third clock signal SS_CK to the third output terminal OUT3. The third clock signal SS_CK may be output as the sense signal SS[N].

[0120] The second transistor T2 can discharge or pull down the output of the third output terminal OUT3 in response to the next-stage carry signal CR[N+1], and the third transistor T3 can discharge or pull down the output of the third output terminal OUT3 in response to the voltage of the second node N_QB.

[0121] That is, the sixth sub-stage SST6 can output the third clock signal SS_CK as the sense signal SS[N] in response to the voltage of the first node N_Q, and can pull down the sense signal SS[N] in response to the next-stage carry signal CR[N+1] and the voltage of the second node N_QB.

[0122] The first auxiliary transistor T1-1 can include a first electrode connected to the second clock terminal IN_CK2, a second electrode connected to the second output terminal OUT2, and a gate electrode connected to the first node N_Q.

[0123] The second auxiliary transistor T2-1 can include a first electrode connected to the second output terminal OUT2, a second electrode connected to the first power supply terminal IN_V1, and a gate electrode connected to the second input terminal IN2.

[0124] The third auxiliary transistor T3-1 can include a first electrode connected to the second output terminal OUT2, a second electrode connected to the first power supply terminal IN_V1, and a gate electrode connected to the second node N_QB.

[0125] The second capacitor C2 can be connected between the first node N_Q and the second output terminal OUT2.

[0126] The second capacitor C2 can store the control voltage Von transmitted through the second sub-stage SST2 and the fourth sub-stage SST4. When the first node N_Q is charged, the first auxiliary transistor T1-1 can transmit the second clock signal SC_CK to the second output terminal OUT2. The second clock signal SC_CK can be output as the scan signal SC[N].

[0127] The second auxiliary transistor T2-1 can discharge or pull down the output of the second output terminal OUT2 in response to the next-stage carry signal CR[N+1], and the third auxiliary transistor T3-1 can discharge or pull down the output of the second output terminal OUT2 in response to the voltage of the second node N_QB.

[0128] That is, the sixth sub-stage SST6 can output the second clock signal SC_CK as the scan signal SC[N] in response to the voltage of the first node N_Q, and pull down the scan signal SC[N] in response to the next-stage carry signal CR[N+1] and the voltage of the second node N_QB.

[0129] The seventh sub-stage (or second output unit or second output circuit) SST7 can output a scan signal SC[N] corresponding to a second clock signal (or scan clock signal) SC_CK supplied to a second clock terminal IN_CK2 to a second output terminal OUT2 in response to a voltage of a first node N_Q, and output a sense signal SS[N] corresponding to a third clock signal SS_CK (or sense clock signal) supplied to a third clock terminal IN_CK3 to a third output terminal OUT3 in response to the voltage of the first node N_Q.

[0130] The seventh sub-stage SST7 can include an eleventh transistor T11, a fifteenth transistor T15, and a seventeenth transistor T17.

[0131] The eleventh transistor T11 can include a first electrode connected to a first output terminal OUT1, a second electrode connected to a second power supply terminal IN_V2, and a gate electrode connected to a second node N_QB.

[0132] The fifteenth transistor T15 can include a first electrode connected to a first clock terminal IN_CK1, a second electrode connected to the first output terminal OUT1, and a gate electrode connected to the first node N_Q.

[0133] The seventeenth transistor T17 can include a first electrode connected to the first output terminal OUT1, a second electrode connected to the second power supply terminal IN_V2, and a gate electrode connected to a second input terminal IN2.

[0134] When the first node N_Q is charged, the fifteenth transistor T15 can transmit a first clock signal CR_CK to the third output terminal OUT3 and output the first clock signal CR_CK as a carry signal CR[N].

[0135] The eleventh transistor T11 can discharge or pull down the output of the second output terminal OUT2 in response to a voltage of the second node N_QB, and the seventeenth transistor T17 can discharge or pull down the output of the second output terminal OUT2 in response to a carry signal CR[N+1] of the next stage.

[0136] That is, the seventh sub-stage SST7 can output the first clock signal CR_CK as a carry signal CR[N] in response to the voltage of the first node N_Q, and can pull down the carry signal CR[N] in response to the carry signal CR[N+1] of the next stage and the voltage of the second node N_QB.

[0137] Figure 5 It shows in Figure 4Waveform diagram of an example of a signal measured in the stage shown. One frame period may include a display period (or active period) in which a data signal is provided to a data line or an image is displayed, and a sensing period (e.g., a vertical blanking period or a period in which no valid data signal is provided to the data line) located between the display period and an adjacent display period. In Figure 5 the signals measured in the stage operated in the display period are shown.

[0138] Referring to Figures 4 to 5 , each of the first signal S1, the second signal S2, and the scan start signal STVP may have a gate-off voltage (or logic low level). For example, the gate-off voltage may be equal to the voltage level of the first power supply Vss1 or the voltage level of the second power supply Vss2 described with reference to Figure 4 .

[0139] The control voltage Von may be equal to the gate-on voltage Von.

[0140] Each of the first clock signal CR_CK, the second clock signal SC_CK, and the third clock signal SS_CK may repeatedly have a logic high level and a logic low level. In other words, the first clock signal CR_CK, the second clock signal SC_CK, and the third clock signal SS_CK may each alternate between the logic high level and the logic low level.

[0141] At a first time t1, the third clock signal SS_CK may change from the gate-off voltage to the gate-on voltage Von. In a first period P1 between the first time t1 and a second time t2, the third clock signal SS_CK may maintain the gate-on voltage Von.

[0142] The fifth sub-stage SST5 may transmit the third clock signal SS_CK of the gate-on voltage Von to the second node N_QB. When the twelfth transistor T12 is turned on, the voltage of the fourth node N_C may rise. The seventh transistor T7 may be turned on in response to the voltage of the fourth node N_C. The voltage of the second node N_QB (i.e., the second node voltage V_QB) may rise to the gate-on voltage Von.

[0143] At the second time t2, the third clock signal SS_CK may change to the gate-off voltage.

[0144] During a second period P2 between the second time t2 and a third time t3, the previous stage carry signal CR[N-1] may change from the gate-off voltage to the gate-on voltage Von and maintain the gate-on voltage Von.

[0145] The second sub-stage SST2 can charge the first node N_Q and the third node N_FB by receiving the carry signal CR[N-1] from the previous stage. The fourth transistors T4-1 and T4-2 can be turned on in response to the carry signal CR[N-1] of the gate conduction voltage Von, and the carry signal CR[N-1] of the gate conduction voltage Von can be transmitted to the first node N_Q and the third node N_FB. The voltage of the first node N_Q (i.e., the first node voltage V_Q) can rise, and the voltage of the third node N_FB (i.e., the third node voltage V_FB) can rise. Each of the first node voltage V_Q and the third node voltage V_FB can rise to the gate conduction voltage Von.

[0146] Meanwhile, the eighth transistor T8 of the fifth sub-stage SST5 can be turned on in response to the first node voltage V_Q. The second node N_QB can be discharged or pulled down to the second power supply Vss2. The second node voltage V_QB can be changed to the gate-off voltage.

[0147] In addition, each of the first transistor T1, the first auxiliary transistor T1-1, and the fifteenth transistor T15 of the sixth sub-stage SST6 can be turned on. However, during the second cycle P2, each of the third clock signal SS_CK, the second clock signal SC_CK, and the first clock signal CR_CK has the gate-off voltage. Therefore, each of the scan signal SC[N], the sense signal SS[N], and the carry signal CR[N] can have the gate-off voltage.

[0148] At the third time t3, each of the first clock signal CR_CK, the second clock signal SC_CK, and the third clock signal SS_CK can be changed to the gate conduction voltage Von. In addition, during the third cycle P3 between the third time t3 and the fourth time t4, each of the first clock signal CR_CK, the second clock signal SC_CK, and the third clock signal SS_CK can maintain the gate conduction voltage Von.

[0149] Each of the first transistor T1 and the first auxiliary transistor T1-1 of the sixth sub-stage SST6 and the fifteenth transistor T15 of the seventh sub-stage SST7 remains in the on state. Therefore, each of the scan signal SC[N], the sense signal SS[N], and the carry signal CR[N] can have the gate conduction voltage Von according to the third clock signal SS_CK, the second clock signal SC_CK, and the first clock signal CR_CK.

[0150] Meanwhile, due to the capacitive coupling (or capacitive boosting) of the first capacitor C1 and the second capacitor C2 of the sixth sub-stage SST6, the first node voltage V_Q can rise to a voltage level greater than the gate conduction voltage Von (e.g., Von + ΔV).

[0151] The gate-source voltage (e.g., Vgs) of each of the (4-2)th transistor T4-2, the (9-1)th transistor T9-1, the (10-1)th transistor T10-1, and the (18-1)th transistor T18-1 may be equal to the difference between the voltage level of the second power supply Vss2 and the gate-on voltage Von (i.e., Vss2 - Von). Therefore, the current leaking from the first node N_Q through the (4-2)th transistor T4-2, the (9-1)th transistor T9-1, the (10-1)th transistor T10-1, and the (18-1)th transistor T18-1 is very small, and correspondingly, the leakage current may not need to be considered.

[0152] At the fourth time t4, the next-stage carry signal CR[N + 1] may change from the gate-off voltage to the gate-on voltage Von. During the fourth period P4 between the fourth time t4 and the fifth time t5, the next-stage carry signal CR[N + 1] may maintain the gate-on voltage Von.

[0153] The sixth sub-stage SST6 and the seventh sub-stage SST7 may pull down each of the scan signal SC[N], the sense signal SS[N], and the carry signal CR[N] in response to the next-stage carry signal CR[N + 1] of the gate-on voltage Von. Each of the second transistor T2 and the second auxiliary transistor T2-1 of the sixth sub-stage SST6 and the seventeenth transistor T17 of the seventh sub-stage SST7 may be turned on in response to the next-stage carry signal CR[N + 1] of the gate-on voltage Von, and the scan signal SC[N], the sense signal SS[N], and the carry signal CR[N] may change to the first power supply Vss1 (i.e., the gate-off voltage).

[0154] In addition, the third sub-stage SST3 may discharge the first node N_Q in response to the next-stage carry signal CR[N + 1] of the gate-on voltage Von. The ninth transistors T9-1 and T9-2 of the third sub-stage SST3 may be turned on in response to the next-stage carry signal CR[N + 1] of the gate-on voltage Von, and the first node voltage V_Q may change to the second power supply Vss2 (i.e., the gate-off voltage).

[0155] At the fifth time t5, the third clock signal SS_CK may change from the gate-off voltage to the gate-on voltage Von.

[0156] The operation of the stage ST in the fifth period P5 between the fifth time t5 and the sixth time t6 may be substantially similar to the operation of the stage ST in the first period P1. Therefore, the redundant description will not be repeated.

[0157] Figure 6 is a waveform diagram showing an example of the signals measured in the Figure 4 shown stage.

[0158] Refer to Figures 4 to 6 , the operation of stage ST in display period P_SCAN is substantially similar to that of stage ST described in Refer to Figure 5 , and thus the redundant description will not be repeated.

[0159] As Figure 6 shown, during the first sub-period PS1 between the first time t1 and the second time t2, the first signal (or the first control signal) may have a gate-on voltage.

[0160] The stage that receives the carry signal CR[N - 1] (i.e., the carry signal of the previous stage) of the previous stage with a pulse overlapping the pulse of the first signal S1 (i.e., the pulse of the gate-on voltage) can be selected from among stages ST1, ST2, and ST3 (see Figure 3 ). That is, the stage that receives the carry signal CR[N - 1] of the previous stage overlapping the first signal S1 can be selected.

[0161] In the selected stage, the (19 - 1)th transistor T19 - 1 and the (19 - 2)th transistor T19 - 2 can be turned on in response to the first signal S1 with the gate-on voltage. The first control node N_S can be charged by the carry signal CR[N - 1] of the previous stage with the gate-on voltage. The voltage of the first control node N_S (i.e., the first control node voltage V_S) can rise to the gate-on voltage. The first control node voltage V_S can be maintained at the gate-on voltage through the third capacitor C3.

[0162] The blanking period (or sensing period) P_BLANK may include a second sub-period PS2, a third sub-period PS3, and a fourth sub-period PS4.

[0163] During the second sub-period PS2 between the third time t3 and the fourth time t4, the second signal (or the second control signal) S2 may have a gate-on voltage.

[0164] In the selected stage, the twenty-first transistor T21 can be turned on in response to the second signal S2 with the gate-on voltage. At the same time, the on-state of the twentieth transistor T20 can be maintained by the first control node voltage V_S. Therefore, the control voltage Von can be provided to the first node N_Q. The first node N_Q can be charged with the control voltage Von. The voltage of the first node N_Q (i.e., the first node voltage V_Q) can rise to the gate-on voltage.

[0165] In the selected stage, each of the first transistor T1, the first auxiliary transistor T1 - 1, and the fifteenth transistor T15 can be turned on in response to the first node voltage V_Q.

[0166] However, each of the first clock signal CR_CK, the second clock signal SC_CK, and the third clock signal SS_CK can hold a gate-off voltage, and correspondingly, a carry signal CR[N], a scan signal SC[N], and a sense signal SS[N] each having a gate-off voltage can be output.

[0167] Subsequently, during a third sub-period PS3 between a fifth time t5 and a sixth time t6, the second clock signal SC_CK can have a gate-on voltage. Since the first auxiliary transistor T1-1 remains in an on state, the scan signal SC[N] corresponding to the second clock signal SC_CK having a gate-on voltage can be output through the second output terminal OUT2.

[0168] Similarly, the third clock signal SS_CK can have a gate-on voltage. Since the first transistor T1 remains in an on state, the sense signal SS[N] corresponding to the third clock signal SS_CK having a gate-on voltage can be output through the third output terminal OUT3.

[0169] That is, after the second signal S2 (i.e., a pulse of a gate-on voltage) is applied, the selected stage can output the scan signal SC[N] corresponding to the second clock signal SC_CK and output the sense signal SS[N] corresponding to the third clock signal SS_CK.

[0170] Due to the capacitive coupling of the first capacitor C1 and the second capacitor C2, the first node voltage V_Q can rise to a voltage level greater than the gate-on voltage (e.g., Von + ΔV (see Figure 4 ).

[0171] The gate-source voltage (e.g., Vgs) of each of the (4-2) transistor T4-2, the (9-1) transistor T9-1, the (10-1) transistor T10-1, and the (18-1) transistor T18-1 can be equal to the difference between the voltage level of the second power supply Vss2 and the gate-on voltage Von (i.e., Vss2 - Von). Therefore, the current leaking from the first node N_Q through the (4-2) transistor T4-2, the (9-1) transistor T9-1, the (10-1) transistor T10-1, and the (18-1) transistor T18-1 is very small, and correspondingly, the leakage current can be ignored (or not considered).

[0172] Meanwhile, the first clock signal CR_CK holds a gate-off voltage. Correspondingly, a carry signal CR[N] having a gate-off voltage can be output, or no valid (or active) carry signal CR[N] can be output.

[0173] Subsequently, in the fourth sub-period PS4 between the seventh time t7 and the eighth time t8, the scan start signal STVP may have a gate-on voltage.

[0174] In the selected stage, the (18-1)th transistor T18-1 and the (18-2)th transistor T18-2 may be turned on in response to the scan start signal STVP having a gate-on voltage, and the first node N_Q may be discharged to the second power supply Vss2. Accordingly, the first node voltage V_Q may be pulled down or discharged to the gate-off voltage.

[0175] As described with reference to Figures 3 to 6 The scan driver 13 (and the display device 10) according to an embodiment of the present disclosure includes a plurality of stages ST1, ST2, and ST3 that respectively output a carry signal, a scan signal, and a sense signal, and each of the plurality of stages ST1, ST2, and ST3 may include a first sub-stage (or a sampling unit or a sampling circuit) SST1 that stores the previous-stage carry signal CR[N-1] in response to the first signal S1. Therefore, only the stage that receives the previous-stage carry signal CR[N-1] overlapping with the first signal S1 (e.g., the previous-stage carry signal CR[N-1] having a gate-on voltage) is selected, and in the blanking period P_BLANK, the scan signal SC[N] and the sense signal SS[N] are output through the selected stage.

[0176] Figure 7 is a waveform diagram showing an example of signals measured in the stage shown in Figure 4 In Figure 7 is shown Figure 4 the voltage of the first control node N_S (i.e., the first control node voltage V_S), the voltage of the second control node N_SF (i.e., the second control node voltage V_SF), the voltage of the first node N_Q (i.e., the first node voltage V_Q), and the voltage of the second node N_QB (the second node voltage V_QB) in the stage shown in

[0177] Referring to Figure 4 , Figure 6 and Figure 7 , the operation of the stage ST in the period between the first time t1 and the second time t2 may be substantially similar to the operation of the stage ST in the first sub-period PS1 described with reference to Figure 6 In addition, the operation of the stage ST in the period between the third time t3 and the fourth time t4 may be substantially the same as the operation of the stage ST in the second sub-period PS2 described with reference to Figure 6 Therefore, redundant descriptions will not be repeated.

[0178] During the period between the first time t1 and the second time t2, the first signal (or the first control signal) S1 may have a gate-on voltage.

[0179] Among a plurality of stages ST1, ST2, and ST3 (see Figure 3 ), a stage that can selectively receive a carry signal CR[N-1] of a previous stage overlapping with the first signal S1 is selected.

[0180] In the selected stage, the (19-1)th transistor T19-1 and the (19-2)th transistor T19-2 can be turned on in response to the first signal S1 of the gate conduction voltage. The first control node N_S can be charged by the carry signal CR[N-1] of the previous stage of the gate conduction voltage. The voltage of the first control node N_S (i.e., the first control node voltage V_S) can rise to the gate conduction voltage. The first control node voltage V_S can be maintained at the gate conduction voltage through the third capacitor C3.

[0181] At the same time, in order to enable the selected stage to operate normally in response to the second signal (or the second control signal) S2 of the gate conduction voltage during the blanking period P_BLANK (or the sensing period), during the holding period P_HOLD between the second time t2 and the third time t3, the first control node voltage V_S is maintained at the gate conduction voltage, and the leakage current should be prevented or reduced. For example, when the scan driver 13 (or the display device 10) is driven at 60 Hz (see Figure 1 ), the holding period P_HOLD can be about 16 ms.

[0182] As described with reference to Figure 4 , in the stage ST according to an embodiment of the present disclosure, the first electrode of the (19-2)th transistor T19-2 can be connected to the second control node N_SF, and the second electrode of the twentieth transistor T20 can be connected to the second control node N_SF.

[0183] During the holding period P_HOLD, the twentieth transistor T20 remains in the on state in response to the first control node voltage V_S of the gate conduction voltage, and thus the second control node voltage V_SF can be equal to the control voltage Von (or the gate conduction voltage). The gate-source voltage of the (19-2)th transistor T19-2 can be equal to the difference between the first signal S1 and the second control node voltage V_SF. For example, the first signal S1 of the gate-off voltage can be in the range of about -16V to about -3V. When the second control node voltage V_SF is in the range of about 10V to about 30V, the gate-source voltage of the (19-2)th transistor T19-2 can be about -30V or less (i.e., Vss2-Von).

[0184] Therefore, during the hold period P_HOLD, the current (or leakage current) flowing through the (19 - 2)th transistor T19 - 2 is further reduced, or the current leakage of the first control node N_S is prevented or reduced. Accordingly, the first control node voltage V_S can be stably held at the gate - on voltage.

[0185] Reference will be made to Figure 8 describe the leakage current of the (19 - 2)th transistor T19 - 2.

[0186] Figure 8 is a graph showing the voltage - current characteristics of the transistors included in the Figure 4 stage shown.

[0187] Referring to Figure 8 , the first curve CURVE1 represents the current Ids flowing through the transistor according to the gate - source voltage Vgs of the transistors included in the stage ST. The transistor can be an oxide semiconductor transistor.

[0188] When the gate - source voltage Vgs is 0V (i.e., the first point PT1), the current Ids is ideally 0, but in reality it can be about 1.E - 08A (i.e., 1nA to 10nA). That is, when the gate - source voltage Vgs is 0V, there may be a leakage current.

[0189] As the gate - source voltage Vgs increases in the negative direction, the current Ids can be further reduced.

[0190] When the gate - source voltage Vgs is about - 30V (i.e., at the second point PT2), the current Ids can be about 1.E - 14A (i.e., 10fA), and is about 1 / 100000 of that when the gate - source voltage Vgs is 0V.

[0191] Meanwhile, although the saturation of the current Ids when the current Ids is about 1.E - 14A (i.e., 10fA) is shown in Figure 8 , this is due to the performance limit of the measuring instrument. As the gate - source voltage Vgs increases in the negative direction, the current Ids (or leakage current) can be further reduced.

[0192] Returning to reference Figure 4 and Figure 7 , during the period between the third time t3 and the fourth time t4, the second node voltage V_QB can be held at the gate - off voltage.

[0193] As referred to Figure 4As described, the fifth sub-stage SST5 can operate synchronously with the third clock signal (or sense clock signal) SS_CK, and the second node N_QB is held at the gate-off voltage by the third clock signal SS_CK of the gate-off voltage. That is, the second node N_QB can be controlled using the third clock signal SS_CK. Therefore, a separate circuit configuration for controlling the second node voltage V_QB in the blanking period P_BLANK is not required, and the area of the first sub-stage SST1 (or sampling circuit) that allows the stage ST to operate in the blanking period P_BLANK can be relatively reduced.

[0194] As referred to Figures 7 to 8 As described, the stage ST (or the first sub-stage (or sampling circuit) SST1) stores the previous-stage carry signal CR[N-1] in the first control node N_S, and a gate-on voltage can be applied by connecting the second electrode of the transistor (e.g., the (19-2)th transistor T19-2) connected to the first control node N_S to the second control node N_SF. Therefore, during the hold period P_HOLD, the leakage current through the first control node N_S of the corresponding transistor is prevented or reduced, and the scan driver 13 and the display device 10 including the stage ST can perform the selective scan / sense operation more stably.

[0195] Figure 9 is a circuit diagram showing an example of the stage included in Figure 1 the scan driver shown. In Figure 9 is shown a stage ST-1 corresponding to the Figure 4 stage ST shown.

[0196] Referring to Figure 4 and Figure 9 except for the connection configuration of the (4-1)th transistor T4-1 of the second sub-stage SST2, Figure 9 the stage ST-1 shown in Figure 4 can be substantially similar to the

[0197] The (4-1)th transistor T4-1 may include a first electrode connected to the reference power supply terminal IN_V0, a second electrode connected to the third node N_FB, and a gate electrode connected to the first input terminal IN1.

[0198] Accordingly, the second sub-stage SST2 (or the fourth transistors T4-1 and T4-2) can charge the first node N_Q by receiving the control voltage Von in response to the previous-stage carry signal CR[N-1].

[0199] Figure 10 is a circuit diagram showing an example of the stage included in Figure 1Circuit diagram of an example of a stage in the scan driver shown. In Figure 10 is shown the stage ST-2 corresponding to the stage ST shown in Figure 4 .

[0200] Referring to Figure 4 and Figure 10 , except for the fourth sub-stage SST4, Figure 10 the stage ST-2 shown in Figure 4 may be substantially similar to the stage ST shown in

[0201] . Therefore, redundant descriptions will be omitted.

[0202] The fourth sub-stage (or feedback circuit) SST4 may receive the scan signal SC[N] or the sense signal SS[N], and supply the scan signal SC[N] or the sense signal SS[N] to the second sub-stage SST2 and the third sub-stage SST3.

[0203] The sixteenth transistor T16 may include a first electrode that receives the scan signal SC[N] or the sense signal SS[N] (or is connected to the second output terminal OUT2 or the third output terminal OUT3), a second electrode connected to the third node N_FB, and a gate electrode connected to the first node N_Q.

[0204] When the scan signal SC[N] or the sense signal SS[N] that outputs the gate-on voltage is applied, the fourth sub-stage SST4 (or the sixteenth transistor T16) may charge the third node N_FB with the control voltage Von.

[0205] According to the present disclosure, the scan driver and the display device include a plurality of stages that respectively output a carry signal, a scan signal, and a sense signal, and each of the plurality of stages may include a sampling circuit configured to store the carry signal of the previous stage in response to a first signal. Therefore, only the stage that receives the carry signal of the previous stage overlapping with the first signal (for example, the carry signal of the previous stage with the gate-on voltage) is selected, and the scan signal and the sense signal may be output through the selected stage.

[0206] In addition, the sampling circuit stores the carry signal of the previous stage at the first control node, and may apply the gate-on voltage by connecting one electrode of the transistor connected to the first control node to the second control node. Therefore, the leakage current through the first control node of the corresponding transistor is prevented or reduced, and the scan driver and the display device may perform the selective scan / sense operation more stably.

[0207] Although the present invention has been described in connection with its preferred embodiments, it will be understood by those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the invention as defined by the appended claims.

[0208] Accordingly, the scope of the present invention should not be limited by the specific embodiments described herein, but should be defined by the appended claims and their equivalents.

Claims

1. A scanning driver, comprising: Multiple stages, wherein the n-th stage among the multiple stages includes: A first input circuit configured to control the voltage of a first node in response to a carry signal of the previous stage of the n-th stage supplied to a first input terminal; A second input circuit configured to control the voltage of the first node in response to a carry signal of the next stage of the n-th stage supplied to a second input terminal; A first output circuit configured to output an n-th carry signal corresponding to a carry clock signal supplied to a first clock terminal to a first output terminal in response to the voltage of the first node; A second output circuit configured to output an n-th scan signal corresponding to a scan clock signal supplied to a second clock terminal to a second output terminal in response to the voltage of the first node, and output an n-th sense signal corresponding to a sense clock signal supplied to a third clock terminal to a third output terminal in response to the voltage of the first node; and A sampling circuit configured to store the carry signal of the previous stage in response to a first selection signal supplied to a first control terminal, and configured to supply a control voltage supplied through a reference power supply terminal to the first node in response to a second selection signal supplied to a second control terminal and the stored carry signal of the previous stage, wherein n is a natural number, wherein the sampling circuit includes: A first transistor connected between the first input terminal and a first control node, and the first transistor includes a gate electrode connected to the first control terminal; A capacitor connected between the first control node and the reference power supply terminal; A second transistor connected between the reference power supply terminal and a second control node, and the second transistor includes a gate electrode connected to the first control node; and A third transistor connected between the second control node and the first node, and the third transistor includes a gate electrode connected to the second control terminal.

2. The scanning driver according to claim 1, wherein, Each of the first input circuit, the second input circuit, the first output circuit, the second output circuit, and the sampling circuit includes an oxide semiconductor transistor.

3. The scanning driver according to claim 2, wherein, The control voltage is a gate turn-on voltage to turn on the oxide semiconductor transistor.

4. The scanning driver according to claim 1, wherein, The first transistor includes a first sub-transistor and a second sub-transistor connected in series with each other, and wherein one electrode of the first sub-transistor and one electrode of the second sub-transistor are connected to the second control node.

5. The scanning driver according to claim 1, wherein, The sampling circuit is configured to discharge the first node in response to a scan start signal supplied to a third control terminal.

6. The scanning driver according to claim 5, wherein, The sampling circuit further includes: A fourth transistor connected between a first power supply terminal to which a first power supply is applied and the first node, and the fourth transistor includes a gate electrode connected to the third control terminal; and wherein the first power supply has a voltage level lower than the voltage level of the control voltage.

7. The scanning driver according to claim 6, wherein, Select, from among the stages, the stage that receives the carry signal of the previous stage having a pulse overlapping with the pulse of the first selection signal. The selected stage is configured to output the sense signal corresponding to the sense clock signal after the pulse of the second selection signal is applied.

8. The scanning driver according to claim 6, wherein, The stage is initialized in response to a scan start signal corresponding to the carry signal of the previous stage.

9. A display device, comprising: A plurality of pixels, each of the plurality of pixels being connected to a scan line, a sense line, a readout line, and a data line; A scan driver including a plurality of stages configured to supply a scan signal to the scan line and a sense signal to the sense line; A data driver configured to supply a data signal to the data line; And A compensator configured to generate a compensation value for compensating for deterioration of the pixel based on a sensed value provided from the readout line, wherein the n-th stage among the plurality of stages includes: A first input circuit configured to control the voltage of a first node in response to the carry signal of the previous stage of the n-th stage supplied to a first input terminal; A second input circuit configured to control the voltage of the first node in response to the carry signal of the next stage of the n-th stage supplied to a second input terminal; A first output circuit configured to output an n-th carry signal corresponding to a carry clock signal supplied to a first clock terminal to a first output terminal in response to the voltage of the first node; A second output circuit configured to output an n-th scan signal corresponding to a scan clock signal supplied to a second clock terminal to a second output terminal in response to the voltage of the first node, and to output an n-th sense signal corresponding to a sense clock signal supplied to a third clock terminal to a third output terminal in response to the voltage of the first node; and A sampling circuit configured to store the carry signal of the previous stage in response to a first selection signal supplied to a first control terminal, and to supply a control voltage supplied through a reference power terminal to the first node in response to a second selection signal supplied to a second control terminal and the stored carry signal of the previous stage, where n is a natural number, wherein the sampling circuit includes: A first transistor connected between the first input terminal and a first control node, and the first transistor includes a gate electrode connected to the first control terminal; A capacitor connected between the first control node and the reference power terminal; A second transistor connected between the reference power terminal and a second control node, and the second transistor includes a gate electrode connected to the first control node; and A third transistor connected between the second control node and the first node, and the third transistor includes a gate electrode connected to the second control terminal.

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