Semiconductor device with spike field plate structure and current spreading region

Abstract

Semiconductor devices having a spur field plate structure and a current spreading region are provided. A semiconductor device includes a semiconductor substrate having a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; a plurality of rows of spur field plate structures formed in the semiconductor substrate, the spur field plate structures extending into the drift region through the source region and the body region; a strip gate structure formed in the semiconductor substrate and separating adjacent rows of the spur field plate structures; and a current spreading region of the first conductivity type formed below the body region in a semiconductor mesa between adjacent ones of the spur field plate structures and free of the strip gate structure. The current spreading region is configured to increase a channel current distribution in the semiconductor mesa.

Description

Background Art

[0001] Power MOSFETs (metal-oxide-semiconductor field-effect transistors) typically have field plates for charge compensation, providing significant improvements in area-specific on-resistance (RxA). Some power transistor cell designs use strip trenches for the field plates, with the gate electrode in the same strip trench as the field electrode. Other power transistor cell designs place the field plate in a deep, needle-shaped trench in the center of the cell and surround the needle trench with a separate trench containing the gate electrode. The increased semiconductor mesa area between the deep needle trench in the center of the cell and the surrounding gate trench is expected to provide even lower overall on-resistance.

[0002] Unlike the strip field plate design, the cell design with a needle-shaped field plate trench at the center of the cell does not integrate the gate electrode into the field plate trench. Instead, the gate electrode is moved to a separate trench that surrounds the needle-shaped field plate trench at the center of the cell. To reduce the area-specific on-resistance, the gate trench must now form a grid across the chip (die) to use the additional semiconductor mesa area for current conduction.

[0003] As such, a cell design with a needle-shaped field plate trench at the center of the cell provides lower area-specific on-resistance and also reduces the device's output charge, which contributes significantly to overall losses in target applications. However, conventional cell designs with needle-shaped field plate trenches do not allow for easy reduction of gate charge and gate-drain charge because the total gate area is significantly increased compared to a gate-stripe layout.

[0004] Therefore, a need exists for a cell design with pin-shaped field plate trenches and lower gate charge and gate-drain charge with reduced impact on area-specific on-resistance. Summary of the Invention

[0005] According to an embodiment of a semiconductor device, the semiconductor device includes: a semiconductor substrate including a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; a plurality of rows of thorn-shaped field plate structures formed in the semiconductor substrate, the thorn-shaped field plate structures extending into the drift region through the source region and the body region; a strip-shaped gate structure formed in the semiconductor substrate and separating adjacent rows of thorn-shaped field plate structures; and a current diffusion region of the first conductivity type formed below the body region in a semiconductor mesa, the semiconductor mesa being between adjacent thorn-shaped field plate structures in the thorn-shaped field plate structure and having no strip-shaped gate structure, the current diffusion region being configured to increase the channel current distribution in the semiconductor mesa.

[0006] The current spreading region may abut a sidewall of the spiked field plate structure.

[0007] Individually or in combination, the current diffusion region may be defined by adjacent ones of the strip-shaped gate structures.

[0008] Individually or in combination, the current spreading region may extend laterally from a sidewall of each thorn-shaped field plate structure to a sidewall of an adjacent strip-shaped gate structure.

[0009] Either alone or in combination, the current spreading region may include a stripe extending longitudinally between adjacent ones of the spiky field plate structures and intersecting an adjacent one of the stripe gate structures.

[0010] Either individually or in combination, the strip gate structure may have a lateral extension that partially extends between adjacent ones of the thorn field plate structures, such that a gap exists between each lateral extension and an adjacent strip gate structure, and a current diffusion region may be defined in the gap between the lateral extension of the strip gate structure and the adjacent strip gate structure.

[0011] Either alone or in combination, the current spreading region may include a stripe that extends longitudinally between adjacent ones of the stab field plate structures and terminates before reaching an adjacent one of the stripe gate structures.

[0012] Either alone or in combination, the current spreading region may be defined by contact grooves that extend parallel to the stripe-shaped gate structure and are aligned with the multiple rows of spike-shaped field plate structures.

[0013] Alone or in combination, the thorn-shaped field plate structures may each include a field electrode disposed in the trench and a field dielectric insulating the field electrode from the semiconductor substrate.

[0014] Individually or in combination, the spiky field plate structures may each include a connection region connected to and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and the current spreading region may be formed adjacent to the connection region of the spiky field plate structures.

[0015] Either alone or in combination, the current diffusion region may have a peak doping concentration at a depth in the semiconductor substrate that is shallower than the bottom of the stripe-shaped gate structure.

[0016] According to an embodiment of a method for producing a semiconductor device, the method includes: forming a drift region of a first conductivity type in a semiconductor substrate, forming a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming multiple rows of thorn-shaped field plate structures in the semiconductor substrate, the thorn-shaped field plate structures extending into the drift region through the source region and the body region; forming a strip-shaped gate structure in the semiconductor substrate and separating adjacent rows of thorn-shaped field plate structures; and forming a current diffusion region of the first conductivity type below the body region in a semiconductor mesa, the semiconductor mesa being between adjacent thorn-shaped field plate structures in the thorn-shaped field plate structure and having no strip-shaped gate structure, the current diffusion region being configured to increase the channel current distribution in the semiconductor mesa.

[0017] Forming the current spreading region may include implanting a dopant species of the first conductivity type through the body region using the same photolithography mask used to form the source region.

[0018] Either individually or in combination, forming the current diffusion region may include: after forming the source region, forming a photolithography mask on the semiconductor substrate, and the photolithography mask has a strip opening that extends longitudinally between adjacent thorn-shaped field plate structures in the thorn-shaped field plate structure and intersects with the adjacent strip-shaped gate structure in the strip-shaped gate structure; and using the photolithography mask having the strip opening to implant a first conductive type dopant material through the body region.

[0019] Either individually or in combination, the strip gate structure may have a lateral extension that partially extends between adjacent thorn field plate structures in the thorn field plate structure, so that a gap exists between each lateral extension and an adjacent strip gate structure, and forming a current diffusion region may include: after forming a source region, forming a photolithography mask on the semiconductor substrate, and the photolithography mask has an opening above the gap between the lateral extension of the strip gate structure and the adjacent strip gate structure; and using the photolithography mask having an opening above the gap to implant a dopant substance of the first conductivity type through the body region.

[0020] Either individually or in combination, forming the current diffusion region may include: forming a strip groove in the semiconductor substrate, wherein the strip groove extends longitudinally between adjacent thorn-shaped field plate structures in the thorn-shaped field plate structure and terminates before reaching an adjacent strip gate structure in the strip gate structure; and injecting a first conductive type dopant material into the strip groove.

[0021] Either individually or in combination, forming the current diffusion region may include: etching contact grooves into the semiconductor substrate, wherein the contact grooves extend parallel to the strip gate structure and are aligned with multiple rows of spiked field plate structures, each contact groove having unetched strip regions parallel to each other; and injecting a first conductive type dopant substance into the contact grooves.

[0022] Forming the multiple rows of spiked field plate structures may include, alone or in combination, etching multiple rows of trenches in the semiconductor substrate; and forming a field electrode and a field dielectric insulating the field electrode from the semiconductor substrate in each trench.

[0023] Either individually or in combination, the spiky field plate structures may each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and forming the current spreading region may include forming the current spreading region adjacent to the connection region of the spiky field plate structure.

[0024] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The elements of the drawings are not necessarily to scale with respect to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments may be combined unless they exclude each other. The embodiments are depicted in the drawings and are described in detail in the following description.

[0026] Figure 1A illustrates a partial cross-sectional view of a power transistor cell having a current spreading region, and Figure 1B Different partial cross-sectional views of the same power transistor cell are shown.

[0027] Figure 2A Shown for Figure 1A and 1B The voltage drop of the cell shown in , but without the current spreading region, and Figure 2B Shown for Figure 1A and 1B The voltage drop of the cell with current spreading region shown in .

[0028] Figure 3 A partial cross-sectional view of another power transistor cell having a current spreading region is illustrated.

[0029] Figure 4A Shown for Figure 3 The voltage drop of the cell shown in , but without the current spreading region, and Figure 4B Shown for Figure 3 The voltage drop of the cell with current spreading region shown in .

[0030] Figures 5 to 9 Corresponding plan views of additional embodiments of current spreading regions are illustrated. DETAILED DESCRIPTION

[0031] Embodiments described herein provide a power transistor cell design featuring needle-shaped field plate trenches and lower gate and gate-drain charges, with a reduced impact on area-specific on-resistance. The power transistor device has multiple rows of spike-shaped field plate structures formed in a semiconductor substrate, and strip-shaped gate structures separating adjacent rows of spike-shaped field plate structures. Current diffusion regions are formed in semiconductor mesas, which are located between adjacent spike-shaped field plate structures and are free of strip-shaped gate structures. The current diffusion regions are configured to increase channel current distribution in the semiconductor mesas, thereby reducing gate and gate-drain charges with little to no adverse impact on area-specific on-resistance. The terms "needle-shaped" and "spine-shaped" are used interchangeably herein to describe trench structures formed in a semiconductor substrate and having a small or narrow perimeter or width proportional to their height / depth in the substrate—in contrast to strip-shaped trench structures, which grow longer as they go deeper.

[0032] Figure 1A illustrates a partial cross-sectional view of a power transistor unit, and Figure 1B The diagrams depict different partial cross-sectional views of the same power transistor cell. A semiconductor device may include dozens, hundreds, thousands, or even more power transistor cells, integrated on the same die and electrically coupled in parallel to form a power transistor. The semiconductor device may be a power MOSFET, an IGBT (insulated gate bipolar transistor), a HEMT (high electron mobility transistor), or the like. In each case, the semiconductor device includes a semiconductor substrate 100 comprising a drift region 102 of a first conductivity type, a body region 104 of a second conductivity type formed above the drift region 102, and a source region 106 of the first conductivity type separated from the drift region 102 by the body region 104. A drain region 108 of the semiconductor device may be disposed on the opposite side of the semiconductor substrate 100 from the source region 106. As used herein, the term "source region" is intended to refer to the source region of a power MOSFET or HEMT, or the emitter region of an IGBT. Similarly, the term "drain region" as used herein is intended to mean the drain region of a power MOSFET or HEMT, or the collector region of an IGBT.

[0033] In the case of an n-channel device, the first conductivity type is n-type and the second conductivity type is p-type. Conversely, in the case of a p-channel device, the first conductivity type is p-type and the second conductivity type is n-type.

[0034] For n-channel or p-channel devices, the semiconductor device includes multiple rows of thorn-shaped field plate structures 110 formed in a semiconductor substrate 100. The semiconductor device also includes a strip-shaped gate structure 112 formed in the semiconductor substrate 100 and separating adjacent rows of thorn-shaped field plate structures 110. An interlayer dielectric 114 such as an oxide, nitride, etc. insulates the electrical connection to the strip-shaped gate structure 112 from the electrical connection to the thorn-shaped field plate structure 110 and can provide a highly doped contact region 115 for electrically contacting the body region 104. As mentioned above, in Figure 1A and 1B Only part of one transistor unit is shown. However, Figures 5 to 9 Various embodiments of semiconductor devices are shown, wherein stripe-shaped gate structures 112 separate adjacent stab-shaped field plate structures 110 .

[0035] The thorn-shaped field plate structure 110 extends into the drift region 102 through the source region 106 and the body region 104 . Figure 1A and 1B The main current flow path of the device shown in FIG is vertical, from the source region 106 to the drain region 108, and is controlled by the voltage applied to the gate electrode 116 of the stripe-shaped gate structure 112. When the device is in the blocking state, the field plate 118 of the thorn-shaped field plate structure 110 shapes the electric field established in the semiconductor substrate 100, thereby protecting the gate dielectric 120 and enhancing the breakdown characteristics of the device.

[0036] Each of the thorn-shaped field plate structures 110 includes a field electrode 118 disposed in a trench 122 and a field dielectric 124 insulating the field electrode 118 from the semiconductor substrate 100. Each of the strip-shaped gate structures 112 includes a gate electrode 116 disposed in a trench 126 separated from the field plate trench 122 and a gate dielectric 120 insulating the gate electrode 116 from the semiconductor substrate 100. The strip-shaped gate structures 112 extend along at least two sides (e.g., parallel but not orthogonal) of the needle-shaped field plate structures 110, or may even extend along all four sides of the needle-shaped field plate structures 110, but not in a continuous grid. That is, even if the strip-shaped gate structures 112 extend along all four sides of the needle-shaped field plate structures 110, some of the strip-shaped gate structures 112 may have interruptions or gaps, resulting in semiconductor mesas 128 located between adjacent ones of the thorn-shaped field plate structures 110 and devoid of strip-shaped gate structures 112.

[0037] The power transistor cell design has a lower overall on-resistance due to the use of the thorn field plate structures 110 and the stripe gate structures 112. However, not all of the semiconductor material between adjacent thorn field plate structures 110 is affected by the gate voltage because the gate trenches 126 are formed as strips and therefore do not completely surround individual ones of the thorn field plate structures 110, as explained above.

[0038] In order to reduce the area-specific on-resistance of the semiconductor device while also reducing gate charge and gate-drain charge, the device further includes a current diffusion region 130 of the first conductivity type, which is formed below the body region 104 in the semiconductor mesas 128. The semiconductor mesas 128 are positioned between adjacent ones of the thorn-shaped field plate structures 110 and are free of the strip-shaped gate structure 112. The current diffusion region 130 has a higher average doping concentration than the drift region 102, and thus increases the channel current distribution in the semiconductor mesas 128 without the strip-shaped gate structure 112.

[0039] The current diffusion region 130 distributes the channel current in the semiconductor mesas 128 into which the gate trench 126 does not extend. By including the current diffusion region in at least the semiconductor mesas 128 positioned between adjacent ones of the spike-shaped field plate structures 110 and without the strip-shaped gate structure 112, a region of lower resistance of the first conductivity type is provided directly below the body region 104 in these mesa regions 128, thereby allowing the channel current to spread laterally in a more distributed manner as it flows into the upper portion of the drift region 102 and vertically toward the drain region 108.

[0040] Figure 2A Shown for Figure 1A and 1B The voltage drop in the electron quasi-Fermi potential of the cell shown in FIG but without the current spreading region 130, and Figure 2B Shown for Figure 1A and 1B The voltage drop of the cell with the current spreading region 130 is shown in FIG. Figure 2B It is shown that the semiconductor device having the current spreading region 130 has better channel current spreading, which results in a lower voltage drop for the device. For example, in some cases, the current spreading region 130 can improve the area-specific on-resistance (RxA) from 30 milliohms mm 2 Down to 27.3 milliohms mm 2 The amount of on-resistance improvement is based on the increase in doping of the current spreading region 130. In one embodiment, the current spreading region 130 has a graded doping profile that increases toward the body region 104 for reducing on-resistance.

[0041] However, a practical limit on the doping concentration of the current spreading region 130 is set by a corresponding reduction in VFPmax. This requires careful optimization due to the altered field distribution compared to devices with a continuous grid surrounding the field plate structure, resulting in a higher breakdown voltage (BVDSS) and VFPmax for the same epitaxial layer stack.

[0042] VFPmax is not directly measurable at the device, but can be determined on a test structure in which the field electrode 118 is separated from the source. Using such a test structure, the potential of the field electrode 118 can be changed. By varying the potential of the field electrode 118, the blocking capability of the device changes. Therefore, the breakdown voltage may first rise with an increase in the field electrode potential, reaching a maximum value defined as VFPmax. A further increase in the potential at the field electrode 118 leads to a rapid drop in the breakdown voltage, which means that the characteristic breakdown voltage above VFP is typically asymmetric. In order to provide a stable device behavior that is robust to process tolerances, the device can be designed in such a way that VFPmax is always positive.

[0043] If the field electrode potential is kept constant (e.g., typically at zero volts when the field electrode 118 is connected to the source potential), an increase in doping produces the same behavior - first a rising breakdown voltage, and later a falling breakdown voltage. VFPmax is therefore a measure of how far the device is from the theoretical maximum doping. VFPmax is also an indicator of how much charge may be generated at the field-oxide interface in an avalanche event. In such an operating mode, some hot carrier injection occurs at this interface, and the charge generated plays a similar role as increasing the field electrode potential, having the same effect. In order to compare the performance, including on-resistance, of structures designed in different ways, not only the breakdown voltage but also the VFPmax should be comparable.

[0044] Table 1 below shows the results for different unit designs (including Figure 1A and 1B The following items for the cell design shown in the figure are expressed in milliohms per mm 2 Measured area-specific on-resistance (Ron XA); VFPmax measured in volts; breakdown voltage measured in volts (BVDSS); FOM (Figure of Merit) for gate charge (FOMg), which is the product of on-resistance and gate charge and is measured in milliohm-nC; and FOM for gate-drain charge (FOMgd), which is the product of on-resistance and gate-drain charge and is also measured in milliohm-nC.

[0045]

[0046] The cell designs each have a spike-shaped field plate structure at the center of the cell and the same epitaxial layer stack. However, "Cell Design 1" has gate trenches surrounding the spike-shaped field trenches in a closed (continuous) lattice-like manner. "Cell Design 2" is Figure 1A and 1B The cell shown in , but without the current spreading region 130. "Cell Design 3" is Figure 1A and 1B The unit shown in FIG has a -2 The current diffusion region 130 is formed by the implantation dose of Figure 1A and 1B The unit shown in FIG has a -2 The current diffusion region 130 is formed by the implantation dose of Figure 1A and 1B The unit shown in FIG has a 1.5e12 cm -2 The current diffusion region 130 is formed by the implantation dose of Figure 1A and 1B The unit shown in FIG has a -2 The current diffusion region 130 is formed by an implantation dose of .

[0047] Setting the implant dose for the current diffusion region 130 too high results in a negative VFPmax and reduces BVDSS, where the higher implant dose translates into increased doping. The doping concentration of the current diffusion region 130 depends on the device configuration and the target voltage level. Therefore, the current diffusion region 130 can have different base doping levels for different cell configurations and voltage levels.

[0048] The doping level of the current spreading region 130 affects the on-resistance (Ron) of the device. The on-resistance Ron corresponds to a defined amount of dopant per area and extends to a certain depth, so even if both regions 102 and 130 have the same conductivity type, a doping change in the current spreading region 130 compared to the base doping of the drift region 102 can be identified.

[0049] The current diffusion region 130 is formed below the body region 104 of the device, but preferably not too far below the gate trench 126. If the current diffusion region 130 extends too far below the gate trench 126, the electric field will increase at the bottom of the gate trench 126, which may cause the gate dielectric to degrade and eventually break down. The gate dielectric 120 can be thicker at the bottom of the gate trench 126 to mitigate this risk. Ideally, the current diffusion region 130 does not extend below the gate trench 130 at all. However, this may not be practical. Therefore, the current diffusion region 130 may have some lateral extension below the gate trench 126, which may be difficult to avoid. In the case of a thick bottom oxide, a deeper gate trench 126 can be used so that the gate electrode 116 is long enough to fully open the device channel.

[0050] As explained above, the current diffusion region 130 has a higher average doping concentration than the drift region 102. The current diffusion region 130 therefore has a lower resistance than the drift region 102, allowing the channel current to spread (distribute) faster in multiple dimensions. The maximum doping concentration of the current diffusion region 130 is ideally at the junction with the body region 104, but this may not be practical. In one embodiment, the peak doping concentration of the current diffusion region 130 is at a depth in the semiconductor substrate 100 that is shallower than the bottom of the strip-shaped gate structure 112. The peak doping concentration of the current diffusion region 130 can be 1.5 to 5 times the average doping concentration, for example, 2 to 4 times.

[0051] By providing current spreading regions 130 below body regions 104 in semiconductor mesas 128 located between adjacent ones of the spike field plate structures 110 and without strip gate structures 112, the spike field plate structures 110 can be arranged in a lattice, while gate structures 112 can be formed as strips extending along two sides (e.g., parallel but not orthogonal) of each spike field plate 110, or even along all four sides without forming a closed (continuous) lattice. Current spreading regions 130 increase channel current distribution in semiconductor mesas 128 located between adjacent ones of the spike field plate structures 110 and without strip gate structures 112, thereby reducing gate charge and gate-drain charge with little to no adverse effect on area-specific on-resistance.

[0052] Next described are various embodiments for the location, shape, and formation of the current diffusion region 130 within each cell of the power semiconductor device. The current diffusion region 130 may abut the sidewalls 132 of the spike field plate structure 110, for example, as in Figure 1A and 1B The current diffusion region 130 may extend laterally from the sidewall 132 of each thorn-shaped field plate structure 110 to the sidewall 134 of the adjacent strip-shaped gate structure 112, as shown in FIG. Figure 1A and 1B As shown in .

[0053] Figure 3 A partial cross-sectional view of a power transistor cell according to another embodiment is illustrated. Figure 3 The power transistor cell embodiment shown in FIG is similar to Figure 1A and 1B . However, the difference is that each of the thorn-shaped field plate structures 110 has a connection region 300 that is connected to the field electrode 118 and is narrower than the field electrode 118. The connection region 300 is provided in the upper portion of the field plate trench 122 and provides an electrical connection point to the field electrode 118, which is positioned lower in the field plate trench 122 than the connection region 300. According to this embodiment, the current diffusion region 130 is formed adjacent to the connection region 300 of the thorn-shaped field plate structure 100. In addition, by using the connection region 300 to contact the wider buried field plate 118, a smaller semiconductor mesa width (W) is achieved. m ). Therefore, the mesa doping can be higher while at the same time the width into which the channel current diffuses is smaller.

[0054] Table 2 below shows the results for different unit designs (including Figure 3 The area-specific on-resistance (Ron XA), VFPmax, breakdown voltage (BVDSS), FOM (Figure of Merit) for gate charge (FOMg), and FOM for gate-drain charge (FOMgd) of the cell design shown in FIG.

[0055]

[0056] Except for "Unit Design 3" to "Unit Design 6" corresponding to Figure 3 The unit embodiment shown in the Figure 1A and 1B Except for the cell embodiment of FIG. 1 , the cell design simulation parameters summarized in Table 2 are the same as those summarized in Table 1. Comparison of the simulation results for “Cell Design 3” to “Cell Design 6” in Table 1 and Table 2 shows that, compared with Figure 1A and 1B Compared to the unit embodiment shown in FIG, Figure 3 The cell embodiment illustrated in allows for more efficient lateral spreading of the channel current, which results in less negative impact on the on-resistance.

[0057] Figure 4A Shown for Figure 3 The voltage drop in the electron quasi-Fermi potential of the cell shown in FIG but without the current spreading region 130, and Figure 4B Shown for Figure 3 The voltage drop of the cell with current spreading region 130 is shown in FIG. Figure 2B , Figure 4B It is shown that the semiconductor device having the current spreading region 130 has better channel current spreading, which results in a lower voltage drop for the device. As previously explained herein, the amount of on-resistance improvement corresponds to the doping level of the current spreading region 130 .

[0058] Figures 5 to 9 1 and 2 illustrate corresponding plan views of additional embodiments of current spreading regions 130. Figures 5 to 9 In FIG. 1 , the body region 104 and the source region 106 are obscured / out of view to provide an unobstructed view of the current spreading region 130 in each case. Figures 5 to 9 The semiconductor device shown in FIG may have Figures 1A-1B and Figure 3 The same or similar epitaxial layer stack structure as shown in .

[0059] exist Figure 5 In the embodiment, the current diffusion region 130 is adjacent to the sidewall 132 of each thorn-shaped field plate structure 110 and is defined by the adjacent strip-shaped gate structures 112 in the strip-shaped gate structures 112. The current diffusion region 130 can be formed by implanting a first conductive type dopant material through the body region 104 using the same photolithography mask used to form the source region 106. Therefore, no additional photolithography process is required, and no degradation of the edge termination blocking capability of the device occurs. That is, the existing source lithography is used, and only an additional implantation step is required over the entire area to form the current diffusion region 130. However, relatively high energy implantation is required to form the current diffusion region 130 below the body region 104, which may result in large variations in the depth of the implanted ions. For example, the implanted dopant material is activated by annealing to form the current diffusion region 130.

[0060] exist Figure 6 In the embodiment, the current diffusion region 130 is formed as a strip 600, and the strip 600 is longitudinally ( Figure 6 In one embodiment, the strip gate structure 112 is perpendicular to the longitudinal extension direction of the strip 600 of the current diffusion region 130 ( Figure 6 direction "x" in the image.

[0061] The current diffusion region 130 may be formed by forming an additional photolithography mask on the semiconductor substrate 100 after forming the source region 106, wherein the additional photolithography mask has a longitudinal direction ( Figure 6The embodiment further includes forming a stripe-shaped opening extending in the direction "y" in the direction of the stripe gate structure 112 and intersecting a neighboring stripe gate structure 112; and implanting a dopant substance of the first conductivity type through the body region 104 using an additional photolithography mask having the stripe-shaped opening. Although an additional photolithography step is required according to this embodiment, the current diffusion region 200 / 600 is formed only in the target region, thereby minimizing the impact on the breakdown voltage, DIBL (drain induced barrier lowering), and avalanche.

[0062] exist Figure 7 In the embodiment, the strip gate structure 112 has a lateral extension 700, which partially extends between adjacent ones of the thorn-shaped field plate structures 110, so that a gap 702 exists between each lateral extension 700 and an adjacent strip gate structure 110. For example, the strip gate structure 112 can be formed along an orthogonal direction ( Figure 7 direction "y"), but does not extend from one stripe-shaped gate trench structure 112 to the Figure 7 The adjacent (proximate) stripe-shaped gate trench structures 112 extend longitudinally in the direction “x” in FIG. The current spreading region 130 is defined by a gap 702 in the lateral extension 700 of the stripe-shaped gate structure 112 .

[0063] The current diffusion region 130 may be formed by forming an additional photolithography mask on the semiconductor substrate 100 after forming the source region 106, wherein the additional photolithography mask has an opening above the gap 702 between the lateral extensions 700 of the strip-shaped gate structure 112. Then, a dopant substance of the first conductivity type is implanted through the body region 104 using the additional photolithography mask having an opening above the gap 702. Figure 6 In the embodiment shown in FIG. Figure 7 The embodiment illustrated in FIG. 1 requires an additional photolithography step and forms the current spreading region 130 only in a target area to minimize the impact on breakdown voltage, DIBL, and avalanche. Figure 7 The embodiment illustrated in provides additional flexibility to the FOMg / FOMgd / Ron tradeoffs described previously herein in conjunction with Tables 1 and 2.

[0064] exist Figure 8 In the embodiment, the current diffusion region 130 is formed as a strip 800, and the strip 800 is longitudinally ( Figure 8 In one embodiment, the strip gate structure 112 is perpendicular to the longitudinal extension direction of the strip 800 of the current diffusion region 130 ( Figure 8 direction "x" in the image.

[0065] The current diffusion region 130 may be formed by forming a stripe-shaped groove in the semiconductor substrate 100, the stripe-shaped groove being longitudinally ( Figure 8 The stripe-shaped grooves are extended in the direction "y" in the stripe-shaped gate structures 112 and terminate before reaching the adjacent stripe-shaped gate structures 112; and a dopant material of the first conductivity type is implanted into the stripe-shaped grooves. Figure 6 and 7 In the embodiment shown in FIG. Figure 8 The embodiment illustrated in FIG. 1 also forms the current diffusion region 130 in the target region to minimize the impact on breakdown voltage, DIBL, and avalanche. However, by forming a stripe-shaped groove in the semiconductor substrate 100 that extends transversely to the stripe-shaped gate structure 112, a lower ion implantation energy can be used to form the stripe 800 of the current diffusion region 130 because the implantation is not performed through the body region 104 or only through a partial thickness of the body region 104, thereby narrowing the distribution of the implanted ion depth.

[0066] The current diffusion ion implantation is not performed on the strip gate structure 112. Instead, the open contact groove is used for tilted implantation from the sidewall 132 of the thorn field plate trench 110 without the need for additional photolithography steps. The contact groove can be open over the entire length of the field plate trench 122. Figure 8 As indicated by the dashed lines in , the current diffusion ion implantation may be performed on both sides of the spiked field plate trench 110 using a dual mode tilted implantation.

[0067] exist Figure 9 In the embodiment, the current diffusion region 130 is defined by the contact groove 900, and the contact groove 900 is parallel to the strip-shaped gate structure 112 ( Figure 9 The current diffusion region 130 is formed by etching contact grooves 900 into the semiconductor substrate 100, each of which has unetched strip regions 902 ( Figure 9 and injecting a first conductivity type dopant material into the contact groove 900.

[0068] Relatively low energy ion implantation can be used to form the current diffusion region 130 because the implantation is performed through the contact groove 900. No additional photolithography steps are required, and only the subsequent thermal budget for activating the highly doped body contact region acts on the current diffusion implantation, thereby allowing the implanted ion depth to be precisely defined. The contact groove 900 has a stripe shape with a stem 902 to facilitate filling with a metal, metal alloy, etc. to form the source / body contact 904. The current diffusion region 130 is formed using a 0° or tilted implantation into the contact groove 900. The current diffusion region 130 is not formed in the Figure 9 , but the implantation process for the current diffusion region 130 is performed by Figure 9 By maintaining an unetched strip region 902 in each contact recess 900, there are no contact edges, which is better for photolithography processing because the same opening area across the entire chip (die) provides better control. Current diffusion ion implantation can be performed on both sides of the contact recess 900 using dual-mode tilted implantation.

[0069] In general, the rows of spiked field plate structures 110 can be shifted relative to one another so that the power transistor cells can have, for example, a hexagonal grid layout when viewed from above, and some gate connections can be omitted so that, in a top layout view, the strip-shaped gate structures 112 extend in a zigzag pattern over the chip. Thus, the strip-shaped gate structures 112 can extend longitudinally in a straight line or in a zigzag pattern.

[0070] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc., and are not intended to be limiting. Throughout the description, like terms refer to like elements.

[0071] As used herein, the terms "having," "comprising," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0072] It is to be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0073] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device comprising: a semiconductor substrate comprising a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; A plurality of rows of thorn-shaped field plate structures are formed in the semiconductor substrate, wherein the thorn-shaped field plate structures extend into the drift region through the source region and the body region; a stripe-shaped gate structure formed in the semiconductor substrate and separating adjacent stab-shaped field plate structures; as well as a current diffusion region of a first conductivity type formed below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region includes a strip extending longitudinally between adjacent thorn-shaped field plate structures in the thorn-shaped field plate structure and intersecting with an adjacent strip-shaped gate structure in the strip-shaped gate structure. 2 . The semiconductor device according to claim 1 , wherein the thorn-shaped field plate structures each include a field electrode disposed in the trench and a field dielectric insulating the field electrode from the semiconductor substrate.

3. The semiconductor device according to claim 2 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode is positioned deeper in the trench than the connection region, and wherein the current diffusion region is formed adjacent to the connection region of the thorn-shaped field plate structure. 4 . The semiconductor device according to claim 1 , wherein the current diffusion region has a peak doping concentration at a depth shallower than a bottom of the stripe-shaped gate structure in the semiconductor substrate.

5. The semiconductor device of claim 1 , wherein each strip-shaped gate structure comprises a gate electrode disposed in a trench and a gate dielectric insulating the gate electrode from a semiconductor substrate, wherein the current diffusion region has a longitudinal extension below the gate trench, and wherein the gate oxide is thicker at the bottom of the gate trench.

6. A semiconductor device comprising: a semiconductor substrate comprising a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; A plurality of rows of thorn-shaped field plate structures are formed in the semiconductor substrate, wherein the thorn-shaped field plate structures extend into the drift region through the source region and the body region; a stripe-shaped gate structure formed in the semiconductor substrate and separating adjacent stab-shaped field plate structures; as well as a current diffusion region of a first conductivity type formed below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region is adjacent to the sidewall of the thorn-shaped field plate structure.

7. The semiconductor device according to claim 6, wherein The current diffusion region is defined by adjacent strip-shaped gate structures among the strip-shaped gate structures. 8 . The semiconductor device according to claim 6 , wherein the current diffusion region extends laterally from a sidewall of each thorn-shaped field plate structure to a sidewall of an adjacent strip-shaped gate structure. 9 . The semiconductor device according to claim 6 , wherein the thorn-shaped field plate structures each include a field electrode disposed in the trench and a field dielectric insulating the field electrode from the semiconductor substrate.

10. The semiconductor device of claim 9 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein the current diffusion region is formed adjacent to the connection region of the thorn-shaped field plate structures. 11 . The semiconductor device according to claim 6 , wherein the current diffusion region has a peak doping concentration at a depth shallower than a bottom of the stripe-shaped gate structure in the semiconductor substrate.

12. The semiconductor device of claim 6 , wherein each strip-shaped gate structure comprises a gate electrode disposed in a trench and a gate dielectric insulating the gate electrode from a semiconductor substrate, wherein the current diffusion region has a longitudinal extension below the gate trench, and wherein the gate oxide is thicker at the bottom of the gate trench.

13. A semiconductor device comprising: a semiconductor substrate comprising a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; A plurality of rows of thorn-shaped field plate structures are formed in the semiconductor substrate, wherein the thorn-shaped field plate structures extend into the drift region through the source region and the body region; a stripe-shaped gate structure formed in the semiconductor substrate and separating adjacent stab-shaped field plate structures; as well as a current diffusion region of a first conductivity type formed below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The strip gate structure has a longitudinal extension portion, which partially extends between adjacent thorn-shaped field plate structures in the thorn-shaped field plate structure, so that there is a gap between each longitudinal extension portion and an adjacent strip gate structure, and the current diffusion region is defined to the gap between the longitudinal extension portion of the strip gate structure and the adjacent strip gate structure. 14 . The semiconductor device according to claim 13 , wherein the thorn-shaped field plate structures each include a field electrode disposed in the trench and a field dielectric insulating the field electrode from the semiconductor substrate.

15. The semiconductor device of claim 14 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein the current diffusion region is formed adjacent to the connection region of the thorn-shaped field plate structures. 16 . The semiconductor device according to claim 13 , wherein the current diffusion region has a peak doping concentration at a depth shallower than a bottom of the stripe-shaped gate structure in the semiconductor substrate.

17. A semiconductor device according to claim 13, wherein each strip-shaped gate structure includes a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region has a longitudinal extension below the gate trench, and wherein the gate oxide is thicker at the bottom of the gate trench.

18. A semiconductor device comprising: a semiconductor substrate comprising a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; A plurality of rows of thorn-shaped field plate structures are formed in the semiconductor substrate, wherein the thorn-shaped field plate structures extend into the drift region through the source region and the body region; a stripe-shaped gate structure formed in the semiconductor substrate and separating adjacent stab-shaped field plate structures; as well as a current diffusion region of a first conductivity type formed below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current spreading region includes a strip, which extends longitudinally between adjacent ones of the thorn-shaped field plate structures and terminates before reaching an adjacent one of the strip-shaped gate structures. 19 . The semiconductor device of claim 18 , wherein the thorn-shaped field plate structures each include a field electrode disposed in the trench and a field dielectric insulating the field electrode from the semiconductor substrate.

20. The semiconductor device of claim 19, wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein the current diffusion region is formed adjacent to the connection region of the thorn-shaped field plate structures. 21 . The semiconductor device according to claim 18 , wherein the current diffusion region has a peak doping concentration at a depth shallower than a bottom of the stripe-shaped gate structure in the semiconductor substrate.

22. A semiconductor device according to claim 18, wherein each strip-shaped gate structure includes a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region has a longitudinal extension below the gate trench, and wherein the gate oxide is thicker at the bottom of the gate trench.

23. A semiconductor device comprising: a semiconductor substrate comprising a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; A plurality of rows of thorn-shaped field plate structures are formed in the semiconductor substrate, wherein the thorn-shaped field plate structures extend into the drift region through the source region and the body region; a stripe-shaped gate structure formed in the semiconductor substrate and separating adjacent stab-shaped field plate structures; as well as a current diffusion region of a first conductivity type formed below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region is defined by a contact groove, which extends parallel to the stripe-shaped gate structure and is aligned with the multiple rows of thorn-shaped field plate structures. 24 . The semiconductor device of claim 23 , wherein the thorn-shaped field plate structures each include a field electrode disposed in the trench and a field dielectric insulating the field electrode from the semiconductor substrate.

25. The semiconductor device of claim 24, wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein the current diffusion region is formed adjacent to the connection region of the thorn-shaped field plate structures. 26 . The semiconductor device according to claim 23 , wherein the current diffusion region has a peak doping concentration at a depth shallower than a bottom of the stripe-shaped gate structure in the semiconductor substrate.

27. A semiconductor device according to claim 23, wherein each strip-shaped gate structure includes a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region has a longitudinal extension below the gate trench, and wherein the gate oxide is thicker at the bottom of the gate trench.

28. A method of producing a semiconductor device, the method comprising: forming a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region in a semiconductor substrate; forming a plurality of rows of thorn-shaped field plate structures in a semiconductor substrate, wherein the thorn-shaped field plate structures extend into a drift region through a source region and a body region; forming a strip-shaped gate structure in a semiconductor substrate and separating adjacent thorn-shaped field plate structures; as well as forming a current diffusion region of a first conductivity type below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region is formed by: After forming the source region, forming a photolithography mask on the semiconductor substrate, wherein the photolithography mask has a stripe-shaped opening extending longitudinally between adjacent ones of the thorn-shaped field plate structures and intersecting with adjacent ones of the stripe-shaped gate structures; as well as Dopant species of the first conductivity type are implanted through the body region using a photolithographic mask having stripe-shaped openings.

29. The method of claim 28, wherein forming the current spreading region comprises implanting a dopant species of the first conductivity type through the body region using a same photolithography mask used to form the source region.

30. The method of claim 28, wherein forming a plurality of rows of spiked field plate structures comprises: etching a plurality of rows of trenches in a semiconductor substrate; as well as A field electrode and a field dielectric insulating the field electrode from the semiconductor substrate are formed in each trench.

31. The method of claim 30 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein forming the current diffusion region includes forming the current diffusion region adjacent to the connection region of the thorn-shaped field plate structures.

32. A method according to claim 28, wherein each strip-shaped gate structure is formed to include a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region is formed to have a longitudinal extension below the gate trench, and wherein the gate oxide is formed thicker at the bottom of the gate trench.

33. A method of producing a semiconductor device, the method comprising: forming a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region in a semiconductor substrate; forming a plurality of rows of thorn-shaped field plate structures in a semiconductor substrate, wherein the thorn-shaped field plate structures extend into a drift region through a source region and a body region; forming a strip-shaped gate structure in a semiconductor substrate and separating adjacent thorn-shaped field plate structures; as well as forming a current diffusion region of a first conductivity type below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The strip-shaped gate structure has a longitudinal extension portion, wherein the longitudinal extension portion partially extends between adjacent ones of the thorn-shaped field plate structures, such that a gap exists between each longitudinal extension portion and an adjacent strip-shaped gate structure, and wherein forming the current diffusion region comprises: After forming the source region, forming a photolithography mask on the semiconductor substrate, wherein the photolithography mask has an opening above the gap between the longitudinal extension of the strip-shaped gate structure and the adjacent strip-shaped gate structure; as well as A dopant species of the first conductivity type is implanted through the body region using a photolithographic mask having openings over the gaps.

34. The method of claim 33, wherein forming a plurality of rows of spiked field plate structures comprises: etching a plurality of rows of trenches in a semiconductor substrate; as well as A field electrode and a field dielectric insulating the field electrode from the semiconductor substrate are formed in each trench.

35. The method of claim 34 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein forming the current diffusion region includes forming the current diffusion region adjacent to the connection region of the thorn-shaped field plate structures.

36. A method according to claim 33, wherein each strip-shaped gate structure is formed to include a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region is formed to have a longitudinal extension below the gate trench, and wherein the gate oxide is formed thicker at the bottom of the gate trench.

37. A method of producing a semiconductor device, the method comprising: forming a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region in a semiconductor substrate; forming a plurality of rows of thorn-shaped field plate structures in a semiconductor substrate, wherein the thorn-shaped field plate structures extend into a drift region through a source region and a body region; forming a strip-shaped gate structure in a semiconductor substrate and separating adjacent thorn-shaped field plate structures; as well as forming a current diffusion region of a first conductivity type below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region is formed by: forming a stripe-shaped groove in the semiconductor substrate, the stripe-shaped groove extending longitudinally between adjacent ones of the thorn-shaped field plate structures and terminating before reaching an adjacent one of the stripe-shaped gate structures; and Dopant species of the first conductivity type are implanted into the stripe-shaped grooves.

38. The method of claim 37, wherein forming a plurality of rows of spiked field plate structures comprises: etching a plurality of rows of trenches in a semiconductor substrate; as well as A field electrode and a field dielectric insulating the field electrode from the semiconductor substrate are formed in each trench.

39. The method of claim 38 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein forming the current diffusion region includes forming the current diffusion region adjacent to the connection region of the thorn-shaped field plate structures.

40. A method according to claim 37, wherein each strip-shaped gate structure is formed to include a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region is formed to have a longitudinal extension below the gate trench, and wherein the gate oxide is formed thicker at the bottom of the gate trench.

41. A method of producing a semiconductor device, the method comprising: forming a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region in a semiconductor substrate; forming a plurality of rows of thorn-shaped field plate structures in a semiconductor substrate, wherein the thorn-shaped field plate structures extend into a drift region through a source region and a body region; forming a strip-shaped gate structure in a semiconductor substrate and separating adjacent thorn-shaped field plate structures; as well as forming a current diffusion region of a first conductivity type below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region is formed by: Etching contact grooves into the semiconductor substrate, the contact grooves extending parallel to the stripe-shaped gate structures and aligned with the multiple rows of thorn-shaped field plate structures, each contact groove having unetched stripe regions parallel to each other; as well as A dopant species of the first conductivity type is implanted into the contact recess.

42. The method of claim 41 , wherein forming multiple rows of spiked field plate structures comprises: etching a plurality of rows of trenches in a semiconductor substrate; as well as A field electrode and a field dielectric insulating the field electrode from the semiconductor substrate are formed in each trench.

43. The method of claim 42 , wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode being positioned deeper in the trench than the connection region, and wherein forming the current diffusion region includes forming the current diffusion region adjacent to the connection region of the thorn-shaped field plate structures.

44. A method of producing a semiconductor device, the method comprising: forming a drift region of a first conductivity type, a body region of a second conductivity type formed above the drift region, and a source region of the first conductivity type separated from the drift region by the body region in a semiconductor substrate; forming a plurality of rows of thorn-shaped field plate structures in a semiconductor substrate, wherein the thorn-shaped field plate structures extend into a drift region through a source region and a body region; forming a strip-shaped gate structure in a semiconductor substrate and separating adjacent thorn-shaped field plate structures; as well as forming a current diffusion region of a first conductivity type below the body region in a semiconductor mesa between adjacent ones of the thorn-shaped field plate structures and without a stripe-shaped gate structure, the current diffusion region being configured to increase channel current distribution in the semiconductor mesa; The current diffusion region is formed so as to extend laterally from a sidewall of each thorn-shaped field plate structure to a sidewall of an adjacent strip-shaped gate structure.

45. The method of claim 44, wherein forming multiple rows of spiked field plate structures comprises: etching a plurality of rows of trenches in a semiconductor substrate; as well as A field electrode and a field dielectric insulating the field electrode from the semiconductor substrate are formed in each trench.

46. ​​A method according to claim 45, wherein the thorn-shaped field plate structures each include a connection region connected to the field electrode and narrower than the field electrode, the field electrode is positioned deeper in the trench than the connection region, and wherein forming the current diffusion region includes forming the current diffusion region adjacent to the connection region of the thorn-shaped field plate structure.

47. A method according to claim 44, wherein each strip-shaped gate structure is formed to include a gate electrode arranged in a trench and a gate dielectric that insulates the gate electrode from the semiconductor substrate, wherein the current diffusion region is formed to have a longitudinal extension below the gate trench, and wherein the gate oxide is formed thicker at the bottom of the gate trench.

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