Display device

Abstract

The present disclosure relates to a display device, which may include a substrate, a pixel, a transistor, a data line, a connecting line, a pad, and an electrostatic discharge protection circuit. The substrate may include a display area and a pad area. The pad area may overlap with the display area. The pixel may be supported by the display area and may include a pixel electrode. The data line may be electrically connected to the pixel electrode through the transistor. The connecting line may be supported by the display area and may be electrically connected to the transistor through the data line. The pad may be supported by the pad area and may be electrically connected to the data line through the connecting line. The display area and the pad area may be positioned between the connecting line and the pad. The electrostatic discharge protection circuit may be electrically connected to the connecting line.

Description

[0001] The technical field relates to display devices. Background Art

[0002] Display devices can present visual information. Display devices are generally expected to be thin, lightweight, and energy-efficient. Display devices are also generally expected to have a minimal non-display area and a maximal display area. Summary of the invention

[0003] One or more embodiments may be directed to a display device having a minimum non-display area. The display device can be prevented from being damaged by static electricity.

[0004] According to one or more embodiments, a display device includes: a substrate, including a display area, a peripheral area outside the display area, and a pad area within the peripheral area; a plurality of data lines arranged in the display area; and a plurality of connecting lines connected to the plurality of data lines and configured to transmit signals from a plurality of pads arranged in the pad area to the plurality of data lines, wherein the plurality of connecting lines are all connected to an ESD protection circuit.

[0005] Each of the connection lines may include a plurality of sections separated from each other in an extending direction, and the ESD protection circuit may include at least one bridge configured to electrically connect the plurality of sections of the connection line to each other.

[0006] A plurality of pixels are arranged in the display area and connected to the plurality of data lines, each of the plurality of pixels includes a capacitor and a display element, and the connecting line can be arranged in a layer between the capacitor and the display element, and the data line can be arranged in a layer between the connecting line and the capacitor.

[0007] In the display area, the bridge may be positioned on the same layer as the electrode of the display element, or on the same layer as the data line.

[0008] Each of the connecting lines may include an extension portion extending from the display area to the peripheral area, and each of the connecting lines may include a plurality of sections separated from each other, and the ESD protection circuit may include a bridge configured to connect a first section of the plurality of sections of each of the connecting lines that is in the display area and includes the extension portion to a second section in the peripheral area.

[0009] A plurality of pixels may be arranged in the display area and may be connected to the plurality of data lines, the plurality of pixels each including a capacitor and a display element, and the connecting line may be arranged in a layer between the capacitor and the display element, and the data line may be arranged in a layer between the connecting line and the capacitor.

[0010] In the display area, the bridge may be positioned on the same layer as the electrode of the display element, or on the same layer as the data line.

[0011] According to one or more embodiments, a display device includes: a substrate, including a display area, a peripheral area outside the display area, and a pad area within the peripheral area; a plurality of data lines arranged in the display area; and a plurality of connecting lines arranged between the plurality of data lines and a plurality of pads arranged in the pad area, wherein the plurality of connecting lines include: a first connecting line positioned in the display area, one end of the first connecting line being connected to one of the plurality of data lines; and a second connecting line positioned in the peripheral area and connected to the other end of the first connecting line and one of the plurality of pads, and an ESD protection circuit can be connected to the first connecting line or the second connecting line.

[0012] A plurality of pixels may be arranged in the display area and may be connected to the plurality of data lines, the plurality of pixels each including a capacitor and a display element, and the first connecting line may be positioned in a layer between the capacitor and the display element, and the data line may be positioned in a layer between the first connecting line and the capacitor.

[0013] The first connection line may include a plurality of sections separated from each other in an extending direction, and the ESD protection circuit may include at least one bridge configured to electrically connect the plurality of sections of the first connection line to each other.

[0014] In the display area, the bridge may be positioned on the same layer as the electrode of the display element.

[0015] In the display area, the bridge may be positioned on the same layer as the data line.

[0016] The first connecting line may include an extension portion extending from the display area to the peripheral area, the first connecting line may include a plurality of sections separated from each other, and the ESD protection circuit may include a bridge configured to connect a first section of the plurality of sections of the first connecting line that is positioned in the display area and includes the extension portion to a second section in the peripheral area.

[0017] In the peripheral region, the bridges may be positioned on the same layer as the electrodes of the display element.

[0018] In the peripheral region, the bridge may be positioned on the same layer as the data line.

[0019] The second connection line may include a plurality of sections separated from each other in an extending direction, and the ESD protection circuit may include at least one bridge configured to electrically connect the plurality of sections of the second connection line to each other.

[0020] In the peripheral region, the at least one bridge may be positioned between the display region and the pad region.

[0021] The second connection line may be positioned on the same layer as an electrode of the capacitor, and in the peripheral region, the at least one bridge may be positioned on the same layer as one electrode of the display element.

[0022] The second connection line may be positioned on the same layer as one electrode of the capacitor, and, in the peripheral region, the at least one bridge may be positioned on the same layer as the data line.

[0023] The display area may include a first area in which the first connection line extends in a first direction, a second area in which the first connection line extends in a second direction perpendicular to the first direction, and a third area different from the first area and the second area.

[0024] Embodiments may relate to a display device. The display device may include a substrate, a pixel, a transistor, a data line, a connecting line, a pad, and an electrostatic discharge protection circuit. The substrate may include a display area and a pad area. The pad area may overlap with the display area. The pixel may be supported by the display area and may include a pixel electrode. The data line may be electrically connected to the pixel electrode through the transistor. The connecting line may be supported by the display area and may be electrically connected to the transistor through the data line. The pad may be supported by the pad area and may be electrically connected to the data line through the connecting line. The display area and the pad area may be positioned between the connecting line and the pad. The electrostatic discharge protection circuit may be electrically connected to the connecting line.

[0025] The connecting line may include a first subsection and a second subsection. The electrostatic discharge protection circuit may include a bridge. The first subsection may be separated from the second subsection in the extending direction of the connecting line and may be electrically connected to the second subsection through the bridge.

[0026] The pixel may include a capacitor. The connection line may be arranged between the capacitor and the pixel electrode. The data line may be arranged between the connection line and the capacitor.

[0027] The display device may include an insulating layer. The bridge may directly contact a surface of the insulating layer. The pixel electrode or the data line may directly contact the surface of the insulating layer.

[0028] The first section may include an extension portion, and the extension portion may extend toward the pad region and out of the display region.

[0029] The pixel may include a capacitor. The connection line may be arranged between the capacitor and the pixel electrode. The data line may be arranged between the connection line and the capacitor.

[0030] The display device may include an insulating layer. The bridge may overlap the display area. The bridge may directly contact a surface of the insulating layer. The pixel electrode or the data line may directly contact the surface of the insulating layer.

[0031] Embodiments may relate to a display device. The display device may include the following elements: a substrate including a display area and a peripheral area, wherein the peripheral area may be positioned outside the display area and may include a pad area, and wherein the pad area may overlap the display area; a pixel supported by the display area and including a pixel electrode; a transistor; a data line electrically connected to the pixel electrode through the transistor; a first connection line supported by the display area and electrically connected to the transistor through the data line; a second connection line supported by the peripheral area and electrically connected to the data line through the first connection line; a pad supported by the pad area and electrically connected to the first connection line through the second connection line, wherein the display area and the pad area may be positioned between the first connection line and the pad; and an electrostatic discharge protection circuit electrically connected to at least one of the first connection line and the second connection line.

[0032] The pixel may include a capacitor. The first connection line may be positioned between the capacitor and the pixel electrode. The data line may be positioned between the first connection line and the capacitor.

[0033] The first connection line may include a first subsection and a second subsection. The electrostatic discharge protection circuit may include a bridge. The first subsection may be separated from the second subsection in an extending direction of the first connection line and may be electrically connected to the second subsection through the bridge.

[0034] The display device may include an insulating layer. The bridge may overlap the display area. A surface of the insulating layer may directly contact each of the bridge and the pixel electrode.

[0035] The display device may include an insulating layer. The bridge may overlap the display area. A surface of the insulating layer may directly contact each of the bridge and the data line.

[0036] The first connection line may include a first subsection and a second subsection separated from the first subsection. The first subsection may extend from the display area toward the pad area to the peripheral area. The electrostatic discharge protection circuit may include a bridge. The first subsection may be arranged on the display area and may be electrically connected to the second subsection via the bridge.

[0037] The display device may include an insulating layer. The bridge may overlap the peripheral region. A surface of the insulating layer may directly contact each of the bridge and the pixel electrode.

[0038] The display device may include an insulating layer. The bridge may overlap the peripheral area. A surface of the insulating layer may directly contact each of the bridge and the data line.

[0039] The second connection line may include two sections spaced apart from each other in an extending direction of the second connection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a perspective view showing a part of a display device according to an embodiment.

[0041] Figure 2 is a diagram showing a Figure 1 A plan view of a display device.

[0042] Figure 3 According to the embodiment Figure 2 An enlarged view of a portion of a display device.

[0043] Figure 4 According to the embodiment Figure 2 An enlarged view of a portion of a display device.

[0044] Figure 5A is a diagram showing a Figure 3 Floor plan of Section A.

[0045] Figure 5B is a diagram showing a Figure 3 Floor plan of Section A.

[0046] Fig. 6A According to the embodiment along Figure 5B A cross-sectional view taken along line II'.

[0047] Figure 6B According to the embodiment along Figure 5B A cross-sectional view taken along line II'.

[0048] Figure 7 According to the embodiment Figure 2 The equivalent circuit diagram of a pixel is shown in FIG.

[0049] Figure 8 is a diagram showing a layout of pixels of a display device according to an embodiment.

[0050] Fig. 9 is a diagram showing a layout of a pixel according to an embodiment.

[0051] Fig.10 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0052] Fig.11 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0053] Fig.12 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0054] Fig.13 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0055] Fig.14 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0056] Fig.15 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0057] Fig.16 is a diagram showing the layers in accordance with an embodiment Fig. 9 Layout diagram of the components of a pixel.

[0058] Fig.17 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A cross-sectional view of a portion of a display device.

[0059] Fig.18 is a diagram showing a layout of pixels of a display device according to an embodiment.

[0060] Fig.19 is a diagram showing the layers in accordance with an embodiment Fig.18 Layout diagram of the components of a pixel.

[0061] Fig. 20is a diagram showing the layers in accordance with an embodiment Fig.18 Layout diagram of the components of a pixel.

[0062] Fig.21 is a diagram showing the layers in accordance with an embodiment Fig.18 Layout diagram of the components of a pixel.

[0063] Fig. 22 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A cross-sectional view of a portion of a display device.

[0064] Fig.23 is a diagram showing a method according to an embodiment of the present invention. Figure 3 Plan view of section B.

[0065] Fig.24A According to the embodiment along Fig.23 A cross-sectional view taken along line IV-IV'.

[0066] Fig. 24B According to the embodiment along Fig.23 A cross-sectional view taken along line IV-IV'.

[0067] Fig.25 is a diagram showing a method according to an embodiment of the present invention. Figure 3 Floor plan of Section E.

[0068] Fig.26A According to the embodiment along Fig.25 A cross-sectional view taken along line V-V' and line VI-VI'.

[0069] Fig.26B According to the embodiment along Fig.25 A cross-sectional view taken along line V-V' and line VI-VI'.

[0070] Fig. 27 is a diagram showing a method according to an embodiment of the present invention. Figure 3 Plan view of section D.

[0071] Fig.28A According to the embodiment along Fig. 27 Cross-sectional views taken along line VII-VII' and line VIII-VIII'.

[0072] Fig.28B According to the embodiment along Fig. 27 Cross-sectional views taken along line VII-VII' and line VIII-VIII'.

[0073] Fig.29 is a plan view showing a part of a display device according to an embodiment. DETAILED DESCRIPTION

[0074] Example embodiments are described with reference to the drawings, wherein like reference numerals may refer to like elements.

[0075] Although the terms "first", "second", etc. can be used to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Without departing from the teachings of one or more embodiments, the first component can be referred to as the second component. The component described as the "first" component may not require or imply the existence of a second component or other components. The terms "first", "second", etc. can be used to distinguish components of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first type (or first group)", "second type (or second group)", etc.

[0076] The singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise.

[0077] When a first element is referred to as being “on” a second element, the first element may be directly on the second element or indirectly on the second element. One or more intervening elements may be present between the first element and the second element.

[0078] The sizes of elements in the drawings may be exaggerated for convenience of explanation.

[0079] The term “connected” may refer to “electrically connected”. The term “positioned between” may refer to “substantially positioned between”. The term “positioned on the same layer” may refer to “positioned on the same layer and made of the same material”. The term “supported” may refer to “mechanically supported”.

[0080] Figure 1 is a perspective view showing a part of a display device according to an embodiment. Figure 2 is a plan view showing a display device according to the embodiment. Figure 3 and Figure 4 Each is an enlarged view of a portion of a display device according to an embodiment.

[0081] Reference Figure 1 and Figure 2 The display device 10 includes a display area DA for displaying an image, and includes a peripheral area PA outside the display area DA. The substrate 100 of the display device 10 includes a display area DA and a peripheral area PA corresponding to the display area DA and the peripheral area PA, respectively.

[0082] In an electronic device including the display device 10 , a portion of the substrate 100 may be bent so as to minimize the area of ​​the peripheral area PA visible to a user.

[0083] The display area DA may include a first display unit 111 , and a second display unit 112 , a third display unit 113 , a fourth display unit 114 , and a fifth display unit 115 surrounding the first display unit 111 .

[0084] The first display unit 111 may be positioned at the center of the substrate 100, may be substantially flat, and may have a polygonal shape. For example, the first display unit 111 may have a rectangular shape including two sides extending in a first direction (X direction) and two sides extending in a second direction (Y direction).

[0085] The second display unit 112, the third display unit 113, the fourth display unit 114, and the fifth display unit 115 may extend from the first display unit 111. The second display unit 112, the third display unit 113, the fourth display unit 114, and the fifth display unit 115 may have curved surfaces each having a predetermined radius of curvature. The second display unit 112 may be positioned in a first curved area BA1 that is bent at a first side (lower side) of the first display unit 111 with reference to a first curved line BL1 extending in a second direction. The second display unit 112 may include an edge display unit 112' that is bent at a specific curvature and a side display unit 112" that is oriented substantially perpendicular to the first display unit 111. The third display unit 113 may be positioned in a second curved area BA2 that is bent at a second side (right side) of the first display unit 111 with reference to a second curved line BL2 extending in the first direction. The third display unit 113 may include an edge display unit 113' that is bent at a specific curvature and a side display unit 113" that is oriented substantially perpendicular to the first display unit 111. The fourth display unit 114 may be positioned in a third bending area BA3 that is bent at a third side (left side) of the first display unit 111 with reference to a third bending line BL3 extending in the first direction. The fourth display unit 114 may include an edge display unit 114' that is bent with a specific curvature and a side display unit 114" that is oriented substantially perpendicular to the first display unit 111. The fifth display unit 115 may be positioned in a fourth bending area BA4 that is bent at a fourth side (upper side) of the first display unit 111 with reference to a fourth bending line BL4 extending in the second direction. The fifth display unit 115 may include an edge display unit 115' that is bent with a specific curvature and a side display unit 115" that is oriented substantially perpendicular to the first display unit 111.

[0086] The display area DA may include rounded corners 116. The rounded corners 116 may be positioned between the second display unit 112 and the third display unit 113, between the third display unit 113 and the fifth display unit 115, between the second display unit 112 and the fourth display unit 114, and between the fourth display unit 114 and the fifth display unit 115, respectively.

[0087] In the front view, there is no bezel in the edge of the display device 10 , and the display area DA in the front view may be maximized.

[0088] The pad area PADA may be in the peripheral area PA. The pad area PADA may accommodate electronic components and / or a printed circuit board (PCB). For example, a driving circuit unit that supplies signals to the pixels PX in the display area DA may be located in the pad area PADA. The driving circuit unit may include a data driving unit for applying data signals to a plurality of data lines DL. The driving circuit unit may be implemented in the form of an integrated circuit chip and may be mounted on the substrate 100. A plurality of pads PAD (see Figure 3 ) can be positioned in the pad area PADA. The driving circuit unit can supply signals to the display area DA via the plurality of pads PAD. The substrate 100 can be bent in the first bending area BA1, and the driving circuit unit in the pad area PADA can overlap with the display area DA. The bending direction of the pad area PADA is set so that the pad area PADA can be located behind the display area DA. Therefore, from the user's perspective, the display area DA occupies most of the display device 10.

[0089] The pixels PX and the wires for applying electrical signals to the pixels PX may be positioned in the display area DA. Each pixel PX may include a display element and a circuit unit for driving the display element. In an example, the display element may include an organic light emitting diode, and the circuit unit may include a plurality of transistors and a capacitor.

[0090] Conductive lines for applying electrical signals to the pixels PX may include scan lines SL and data lines DL. The scan lines SL may be arranged in rows and may transmit scan signals to the pixels PX, and the data lines DL may be arranged in columns and may transmit data signals to the pixels PX. The pixels PX may be positioned at / near intersections of the scan lines SL and the data lines DL.

[0091] Reference Figure 3 and Figure 4 , a connection line 200 for transmitting an electrical signal supplied from the pad PAD to a conductive line connected to the pixel PX may be positioned on the substrate 100. For example, the connection line 200 may be positioned (and connected) between the data line DL and the pad PAD, and may transmit a data signal supplied from the pad PAD to the data line DL.

[0092] The connection line 200 may include a first connection line 210, a second connection line 220, and a third connection line 230. The first connection line 210 may be substantially positioned in the display area DA, and the second and third connection lines 220 and 230 may be positioned in the peripheral area PA. The second and third connection lines 220 and 230 may be positioned in the first bending area BA1.

[0093] One end of the first connection line 210 may be connected to the corresponding data line DL via the first contact portion CNT1, and the other end of the first connection line 210 may be connected to the corresponding second connection line 220 via the second contact portion CNT2. The first connection line 210 may extend in a first direction (+X direction), may be bent to extend in a second direction (Y direction) perpendicular to the first direction, and may be bent again to extend in the first direction (-X direction). One end of the second connection line 220 may be connected to the first connection line 210 via the second contact portion CNT2, and the other end of the second connection line 220 may be connected to the corresponding pad PAD among the pads PAD. One end of the third connection line 230 may be connected to the corresponding data line DL via the third contact portion CNT3, and the other end of the third connection line 230 may be connected to the corresponding pad PAD among the pads PAD.

[0094] The first connection line 210 and the second connection line 220 may connect the data line DL arranged in the third display unit 113 (in the second bending area BA2) and the fourth display unit 114 (in the fourth bending area BA4) to the pad PAD in the pad area PADA. The second connection line 220 may be positioned in the peripheral area PA and may be indirectly connected to the data line DL through the first connection line 210. Therefore, the display area DA of the rounded corner portion 116 between the second bending area BA2 and the first bending area BA1 and the display area DA of the rounded corner portion 116 between the third bending area BA3 and the first bending area BA1 are not reduced, and the peripheral area PA is not expanded. The non-display area can be minimized.

[0095] The display area DA may be divided into a plurality of areas according to the extending direction of the first connection line 210. For example, the display area DA may include a first area S1 in which (a plurality of first segments of) the first connection line 210 extends in a first direction (+X direction and -X direction), a second area S2 in which (a plurality of second segments of) the first connection line 210 extends in a second direction (Y direction), and a third area S3 other than the first area S1 and the second area S2. The third area S3 may not accommodate the first connection line 210. The display device 10 may include a plurality of first areas S1 and a plurality of second areas S2.

[0096] The peripheral area PA may surround the display area DA. The peripheral area PA may not accommodate the pixels PX, may include a pad area PADA, and may accommodate a voltage line for supplying power for driving the display element.

[0097] The connection line 200 located in the peripheral area PA may be susceptible to static electricity introduced by entities outside the display device 10. To prevent damage, the connection line 200 may be connected to an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may be located at Figure 3 In at least one of the portion A, portion B, portion E, and portion D of the display device 10 indicated in FIG. The portion A may be in the display area DA. The portion B, portion E, and portion D may be in the peripheral area PA.

[0098] Figure 5A and Figure 5B is a diagram showing a method according to an embodiment of the present invention. Figure 3 Floor plan of section A. Fig. 6A and Figure 6B According to the embodiment along Figure 5B A cross-sectional view taken along line II'.

[0099] In an embodiment, the ESD protection circuit may be located in the first region S1 of the display area DA. Figure 3 , Figure 4 , Figure 5A and Figure 5B In the first region S1, the first connection line 210 may extend in the first direction and may include first subdivisions 212 spaced apart from each other in the first direction. The first connection line 210 may be connected to a corresponding ESD protection circuit. The ESD protection circuit may include a bridge 250 electrically connecting the first subdivisions 212. The number of the first subdivisions 212 and the number of the bridges 250 may be configured according to the length of the first connection line 210. Figure 5A A bridge 250 is shown connecting the two first subsections 212 of each first connection line 210, and Figure 5B Two bridges 250 are shown connecting three first subdivisions 212 of each first connection line 210. The bridges 250 connect the first subdivisions 212 at contact holes C, the number of which may be configured according to the embodiment.

[0100] Reference Fig. 6A and Figure 6B , the bridge 250 may be disposed on a layer different from a layer on which the first subdivision 212 is positioned, and may be electrically connected to the first subdivision 212 via a contact hole C.

[0101] like Fig. 6AAs shown in FIG. 1 , the bridge 250 may overlap the first subsection 212 of the first connection line 210 using at least one intermediate insulating layer IL. The first connection line 210 may be positioned on the insulating surface 120 and may be positioned between the insulating surface 120 and the bridge 250. The insulating surface 120 may be a top surface of an insulating layer between the substrate 100 and the first connection line 210.

[0102] like Figure 6B As shown in , the bridge 250 may be positioned between the insulating surface 120 and each of the two first subdivisions 212 of the first connection line 210. At least one insulating layer IL may be positioned between the bridge 250 and each of the first subdivisions 212. The bridge 250 may be positioned on the insulating surface 120. The insulating surface 120 may be a top surface of the insulating layer between the substrate 100 and the bridge 250.

[0103] Figure 7 According to the embodiment Figure 2 The equivalent circuit diagram of a pixel is shown in FIG.

[0104] Reference Figure 7 , the pixel PX includes a display element and a pixel circuit that drives the display element by receiving a signal from a wire. Hereinafter, as an example, a pixel PX in which an OLED is used as a display element will be described.

[0105] Figure 7 The case where signal lines 121, 122, 123 and 171, initialization voltage line 141 and power supply voltage line 172 are provided in each pixel PX is shown. In another embodiment, at least one of the signal lines 121, 122, 123 and 171, initialization voltage line 141 and power supply voltage line 172 may be shared in adjacent pixels.

[0106] The signal lines 121, 122, 123, and 171 include a first scan line 121 for transmitting a first scan signal GW, a second scan line 122 for transmitting a second scan signal GI, an emission control line 123 for transmitting an emission control signal EM, and a data line 171 that crosses the first scan line 121 and transmits a data signal DATA. The second scan line 122 may be connected to the first scan line 121 of a next or previous row, and the second scan signal GI may be the first scan signal GW of the next or previous row.

[0107] The power supply voltage line 172 may transmit a first power supply voltage ELVDD to the first transistor T1 , and the initialization voltage line 141 may transmit an initialization voltage VINT for initializing the first transistor T1 and a pixel electrode to each pixel PX.

[0108] The pixel circuit of each pixel PX may include transistors T1 to T7 and a capacitor Cst. Depending on the type of transistor (p-type or n-type) and its operating conditions, Figure 7 The first electrodes E11 to E71 and the second electrodes E12 to E72 may be source electrodes (source regions) or drain electrodes (drain regions). The first to seventh transistors T1 to T7 may be thin film transistors (TFTs).

[0109] The first transistor T1 may include a gate electrode G1 connected to a first electrode Cst1 of the capacitor Cst, a first electrode E11 connected to a power supply voltage line 172 via a fifth transistor T5, and a second electrode E12 electrically connected to a pixel electrode of the OLED via a sixth transistor T6. The first transistor T1 functions as a driving transistor and supplies current to the OLED by receiving a data signal DATA according to a switching operation of the second transistor T2.

[0110] The second transistor T2 may include a gate electrode G2 connected to the first scan line 121, a first electrode E21 connected to the data line 171, and a second electrode E22 connected to the first electrode E11 of the first transistor T1. The second transistor T2 may be turned on according to the first scan signal GW received via the first scan line 121, and may perform a switching operation of transmitting a data signal DATA transmitted to the data line 171 to the first electrode E11 of the first transistor T1.

[0111] The third transistor T3 may include a gate electrode G3 connected to the first scan line 121, a first electrode E31 connected to the second electrode E12 of the first transistor T1, and a first electrode Cst1 of the capacitor Cst, a second electrode E42 of the fourth transistor T4, and a second electrode E32 of the gate electrode G1 of the first transistor T1. The first electrode E31 is connected to the pixel electrode of the OLED via the sixth transistor T6. The third transistor T3 may be turned on according to the first scan signal GW received via the first scan line 121, thereby connecting the first transistor T1 in a diode manner.

[0112] The fourth transistor T4 may include a gate electrode G4 connected to the second scan line 122, a first electrode E41 connected to the initialization voltage line 141, and a second electrode E42 connected to the first electrode Cst1 of the capacitor Cst, the second electrode E32 of the third transistor T3, and the gate electrode G1 of the first transistor T1. The fourth transistor T4 may be turned on according to the second scan signal GI received via the second scan line 122, and may transmit the initialization voltage VINT to the gate electrode G1 of the first transistor T1, thereby initializing the gate voltage of the first transistor T1.

[0113] The fifth transistor T5 may include a gate electrode G5 connected to the emission control line 123, a first electrode E51 connected to the power supply voltage line 172, and a second electrode E52 connected to the first electrode E11 of the first transistor T1 and the second electrode E22 of the second transistor T2.

[0114] The sixth transistor T6 may include a gate electrode G6 connected to the emission control line 123 , a first electrode E61 connected to the second electrode E12 of the first transistor T1 and the first electrode E31 of the third transistor T3 , and a second electrode E62 connected to a pixel electrode of the OLED.

[0115] The fifth transistor T5 and the sixth transistor T6 may be simultaneously turned on according to the emission control signal EM transmitted through the emission control line 123, and thus, current may flow through the OLED.

[0116] The seventh transistor T7 may include a gate electrode G7 connected to the second scan line 122, a first electrode E71 connected to the second electrode E62 of the sixth transistor T6 and the pixel electrode of the OLED, and a second electrode E72 connected to the initialization voltage line 141. The seventh transistor T7 may be turned on according to the second scan signal GI transmitted via the second scan line 122, thereby initializing the voltage of the pixel electrode of the OLED. The seventh transistor T7 may be omitted.

[0117] exist Figure 7 , the fourth transistor T4 and the seventh transistor T7 are connected to the second scan line 122. In an embodiment, the fourth transistor T4 may be connected to the second scan line 122, and the seventh transistor T7 may be connected to an additional wiring, and thus may be driven according to a signal to be transmitted to the wiring.

[0118] The capacitor Cst may include a first electrode Cst1 connected to the gate electrode G1 of the first transistor T1 and a second electrode Cst2 connected to the power supply voltage line 172. The first electrode Cst1 of the capacitor Cst may be connected to the second electrode E32 of the third transistor T3 and the second electrode E42 of the fourth transistor T4.

[0119] The OLED may include a pixel electrode and a common electrode facing the pixel electrode. A second power voltage ELVSS may be applied to the common electrode. The OLED may emit light by receiving a current Ioled from the first transistor T1, thereby displaying an image.

[0120] Figure 8 is a diagram showing a layout of pixels of the display device 10 according to the embodiment. Figure 8 The transistor shown in FIG. 1 may be a TFT and may be used in conjunction with the reference Figure 7 The transistors described are similar.

[0121] Figure 8 Shows Figure 3 The pixels PXa and PXb in the first region S1 are Figure 3 The pixel PXb in the second region S2.

[0122] The pixel PXa and the pixel PXb may include a conductive line extending in a first direction (X direction) and a conductive line extending in a second direction (Y direction). The first scan line 121, the second scan line 122, the emission control line 123, and the initialization voltage line 141 may extend in the second direction. The data line 171 and the power supply voltage line 172 may extend in the first direction.

[0123] Each of the pixels PXa and PXb may include first to seventh TFTs T1 to T7 and may include a capacitor Cst. Each of the first to seventh TFTs T1 to T7 may include a semiconductor layer and a gate electrode, the semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region, and the gate electrode is positioned to correspond to the channel region and is insulated from the semiconductor layer. Figure 7 The first electrode and the second electrode of each transistor may be a source electrode (source region) or a drain electrode (drain region).

[0124] The first connection line 210 having a first segment extending in a first direction (X direction) may be positioned in a pixel PXa in the first region S1. The first connection line 210 having a second segment extending in a second direction (Y direction) may be positioned in a pixel PXb in the second region S2. The first connection line 210 may be positioned in an upper layer of the data line 171 and the power supply voltage line 172. The first connection line 210 may be positioned in a layer between the data line 171, the power supply voltage line 172, and the pixel electrode.

[0125] Fig. 9 is a diagram showing a layout of a pixel according to an embodiment. Figures 10 to 16 is a diagram showing the different layers according to one or more embodiments. Fig. 9 Layout diagram of the components of a pixel. Fig.17 It shows Figure 2 A cross-sectional view of a portion of a display device. Fig.17 Shown along the Fig.15 A cross section of the pixel electrode taken along line II-II'.

[0126] Fig. 9 Shown is located Figure 3 in the first region S1 or with Figure 3The first pixel PX1 and the second pixel PX2 are adjacent to the first region S1. The first pixel PX1 and the second pixel PX2 are a pair of pixels arranged in the same row of adjacent columns. The structure of the first pixel PX1 may be similar to that of the second pixel PX2. Figures 10 to 17 The structure of the first pixel PX1 is described.

[0127] like Fig.17 As shown in , a display device (eg, display device 10 ) includes a substrate 100 .

[0128] The substrate 100 may include one or more flexible or bendable materials. For example, the substrate 100 may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 may have a multilayer structure including two polymer resin layers, and may include an inorganic material layer (such as silicon oxide, silicon nitride, or silicon oxynitride layer) positioned between the two polymer resin layers.

[0129] The first pixel PX1 and the second pixel PX2 may be positioned on the substrate 100. If necessary, a buffer layer 101 may be positioned on the substrate 100. The buffer layer 101 may planarize the surface of the substrate 100 or prevent impurities from penetrating into a semiconductor layer on the substrate 100. The buffer layer 101 may have a single layer / multilayer structure including an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The buffer layer 101 may be omitted.

[0130] The semiconductor layer may be positioned on the buffer layer 101. The semiconductor layer may have various curved shapes, such as Fig. 9 As shown in . The first pixel PX1 and the second pixel PX2 may each include a semiconductor layer having the same shape. Hereinafter, when each layer of the first pixel PX1 and the second pixel PX2 has the same shape, it will not be described differently. The semiconductor layer of each of the first to seventh TFTs T1 to T7 may include a channel region, a source region, and a drain region, wherein the channel region is located between the source region and the drain region.

[0131] The semiconductor layer may include a channel region 131a of the first TFT T1, a channel region 131b of the second TFT T2, channel regions 131c1 and 131c2 of the third TFT T3, channel regions 131d1 and 131d2 of the fourth TFT T4, a channel region 131e of the fifth TFT T5, a channel region 131f of the sixth TFT T6, and a channel region 131g of the seventh TFT T7. That is, it will be understood that each channel region of the first to seventh TFTs T1 to T7 is some semiconductor layer, such as Fig.10 As shown in . The channel region 131a of the first TFT T1 may have a bend and thus may be formed long. Therefore, the driving range of the gate voltage applied to the gate electrode G1 may be increased. The shape of the channel region 131a of the first TFT T1 may have various embodiments, including shape, shape, "S" shape, "M" shape, and "W" shape.

[0132] The semiconductor layer may include polysilicon. The semiconductor layer may include a source region and a drain region, with a channel region therebetween. Both the source region and the drain region may be regions into which impurities are doped. The impurities may vary depending on the type of the TFT and may include N-type impurities or P-type impurities. The channel region, the source region on one side of the channel region, and the drain region on the other side of the channel region may be referred to as an active layer. That is, the TFT has an active layer, and the active layer includes a channel region, a source region, and a drain region.

[0133] like Fig.10 As shown in , the semiconductor layer may include a source region 176a and a drain region 177a of a first transistor T1, a source region 176b and a drain region 177b of a second transistor T2, a source region 176c and a drain region 177c of a third transistor T3, a source region 176d and a drain region 177d of a fourth transistor T4, a source region 176e and a drain region 177e of a fifth transistor T5, a source region 176f and a drain region 177f of a sixth transistor T6, and a source region 176g and a drain region 177g of a seventh transistor T7. In some cases, the source region or the drain region may be interpreted as a source electrode or a drain electrode of a TFT. That is, for example, the source electrode and the drain electrode of the first TFT T1 may each be in Fig.10 Impurities near the channel region 131a in the semiconductor layer shown in FIG. 1 are doped into the source region 176a and the drain region 177a therein.

[0134] A first insulating layer 320 including an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride may be located on the semiconductor layer.

[0135] The first insulating layer 320 may be positioned under the gate electrode 125a of the first TFT, the gate electrode 125b of the second TFT T2, the gate electrodes 125c1 and 125c2 of the third TFT T3, the gate electrodes 125d1 and 125d2 of the fourth TFT T4, the gate electrode 125e of the fifth TFT T5, the gate electrode 125f of the sixth TFT T6, and the gate electrode 125g of the seventh TFT T7. The first scan line 121, the second scan line 122, and the emission control line 123 each include the same material as that used to form the gate electrodes of the first to seventh TFTs T1 to T7 and are positioned on the same layer, and the first scan line 121, the second scan line 122, and the emission control line 123 may be positioned on the first insulating layer 320 and extend in the second direction.

[0136] like Fig.11 As shown in FIG. 1 , the gate electrode 125b of the second TFT T2 and the gate electrodes 125c1 and 125c2 of the third TFT T3 may be part of the first scan line 121 crossing the semiconductor layer or protrude from the first scan line 121, the gate electrodes 125d1 and 125d2 of the fourth TFT T4 and the gate electrode 125g of the seventh TFT T7 may be part of the second scan line 122 crossing the semiconductor layer or protrude from the second scan line 122, and the gate electrode 125e of the fifth TFT T5 and the gate electrode 125f of the sixth TFT T6 may be part of the emission control line 123 crossing the semiconductor layer or protrude from the emission control line 123. The gate electrode 125a of the first TFT T1 may be an island type.

[0137] exist Fig. 9 and Fig.11 In the embodiment, the third TFT T3 and the fourth TFT T4 each have a dual gate electrode. In the embodiment, the third TFT T3 and the fourth TFT T4 each may have one gate electrode. There may be various modifications, in which at least one of the other TFTs T1, T2, T5, T6, and T7 other than the third TFT T3 and the fourth TFT T4 may have a dual gate electrode.

[0138] The capacitor Cst may overlap with the first TFT T1. The first electrode as the lower electrode of the capacitor Cst may be the gate electrode 125a of the first TFT T1. In an embodiment, the capacitor Cst may not overlap with the first TFT T1, and the first electrode 125a of the capacitor Cst may be a separate component independent of the gate electrode 125a of the first TFT T1.

[0139] The second insulating layer 331 may be positioned on the gate electrodes 125a, 125b, 125c, 125d, 125e, 125f, and 125g of the first to seventh TFTs T1 to T7. The second insulating layer 331 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0140] The second electrode 127 as the upper electrode of the capacitor Cst may be positioned on the second insulating layer 331. Fig.12 As shown in FIG. 2 , an opening 27 may be formed in the second electrode 127 of the capacitor Cst. A connecting member 174 may be used to electrically connect the first electrode 125a of the capacitor Cst to the drain region 177c of the third TFT T3 via the opening 27. The initialization voltage line 141 may be positioned on the same layer as the second electrode 127 of the capacitor Cst on the second insulating layer 331.

[0141] The third insulating layer 332 may be positioned on the second electrode 127 of the capacitor Cst. The third insulating layer 332 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0142] The data line 171 and the power supply voltage line 172 may be positioned on the third insulating layer 332. The data line 171 may be connected to the source region 176b of the second TFT T2 via a contact hole 164 formed in the first insulating layer 320, the second insulating layer 331, and the third insulating layer 332. The power supply voltage line 172 may be connected to the second electrode 127 of the capacitor Cst via a contact hole 168 formed in the third insulating layer 332, and may be connected to the lower semiconductor layer via contact holes 165 and 169 formed in the first insulating layer 320, the second insulating layer 331, and the third insulating layer 332.

[0143] The conductive layer may be further positioned on the third insulating layer 332. For example, the connection members 173, 174, and 175 may be formed on the third insulating layer 332, such as Fig.13. One end of the connection member 173 may be connected to the initialization voltage line 141 via a contact hole 161 formed in the second insulating layer 331 and the third insulating layer 332, and the other end of the connection member 173 may be connected to the source region 176d of the fourth TFT T4 via a contact hole 162 formed in the first insulating layer 320, the second insulating layer 331, and the third insulating layer 332. One end of the connection member 174 may be connected to the drain region 177c of the third TFT T3 via a contact hole 166 formed in the first insulating layer 320, the second insulating layer 331, and the third insulating layer 332, and the other end of the connection member 174 may be connected to the gate electrode 125a of the first TFT T1 via a contact hole 167 formed in the second insulating layer 331 and the third insulating layer 332. In this case, the other end of the connection member 174 may be connected to the gate electrode 125a of the first TFT T1 (or the first electrode 125a of the capacitor Cst) via an opening 27 formed in the second electrode 127 of the capacitor Cst. The connection member 175 may be connected to the drain region 177 f of the sixth TFT T6 via a contact hole 163 formed in the first insulating layer 320 , the second insulating layer 331 , and the third insulating layer 332 . The connection member 175 may be electrically connected to the pixel electrode 410 .

[0144] The fourth insulating layer 341 may be positioned on the data line 171 and the power supply voltage line 172. The first connection line 210 may be positioned on the fourth insulating layer 341, such as Fig.14 As shown in . In the first region S1, the first connection line 210 may include first subdivisions 212 separated from each other. The first connection line 210 may have a single-layer or multi-layer structure, and the single-layer or multi-layer structure includes at least one of aluminum (Al), copper (Cu), titanium (Ti) and alloys of some such metals. The first connection line 210 may extend in the first direction. The first connection line 210 may overlap with at least some of the power supply voltage lines 172. The position of the gap GAP1 of the first subdivision 212 of the first connection line 210 in the first pixel PX1 and the position of the gap GAP2 of the first subdivision 212 of the first connection line 210 in the second pixel PX2 may be different from each other. The fifth insulating layer 342 may be positioned on the first connection line 210.

[0145] The fourth insulating layer 341 and the fifth insulating layer 342 may both include general polymers, such as imide polymers, polymethyl methacrylate (PMMA), polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, aromatic ether polymers, amide polymers, fluorine polymers, paraxylene polymers, vinyl alcohol polymers, and blends of some such polymers.

[0146] The OLED 400 may be positioned on the fifth insulating layer 342. The OLED 400 may include a pixel electrode 410, an opposite electrode 430, and an intermediate layer 420 between the pixel electrode 410 and the opposite electrode 430.

[0147] The pixel electrode 410 may be a (semi) transparent electrode or a reflective electrode. When the pixel electrode 410 is a (semi) transparent electrode, the pixel electrode 410 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), In 2 O 3 , indium gallium oxide (IGO) or aluminum zinc oxide (AZO). When the pixel electrode 410 is a reflective electrode, the pixel electrode 410 may have a reflective layer including silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) and compounds thereof, and a reflective layer including ITO, IZO, ZnO, In 2 O 3 The pixel electrode 410 may have a single-layer or multi-layer structure.

[0148] The shielding member 450 may be further positioned on the fifth insulating layer 342. The shielding member 450 may extend in the second direction along some edges of the pixel electrode 410 so as not to overlap with the pixel electrode 410 in a plan view, and may be positioned at the upper or lower side of each row. The shielding member 450 may have a straight line shape extending in the second direction, or may have a zigzag shape according to the arrangement of the pixel electrode 410 in the same row. The shielding member 450 may include a light shielding metal. For example, the shielding member 450 may include molybdenum (Mo), Al, Cu, Ti, etc., and may have a multilayer or single-layer structure including the above-mentioned materials. In an embodiment, the shielding member 450 may have a multilayer structure of Ti / Al / Ti. The shielding member 450 may include the same material as the material used to form the pixel electrode 410. The shielding member 450 may be spaced apart from each other and independently arranged in each row. The shielding member 450 may be floating, and may be electrically connected to a constant voltage wiring, and a constant voltage may be applied to the shielding member 450. The constant voltage may be an initialization voltage VINT.

[0149] like Fig.15 , Fig.16 and Fig.17As shown in , the bridge 250 electrically connecting the first subdivision 212 of the first connection line 210 may be positioned on the fifth insulating layer 342. The bridge 250 may include the same material as the material used to form the pixel electrode 410, and may be positioned on the same layer as the pixel electrode 410. The bridge 250 may electrically connect the first subdivision 212 of the first connection line 210 arranged in the lower layer via a contact hole C formed in the fifth insulating layer 342. In a direction perpendicular to the substrate 100, the bridge 250 may not overlap with the pixel electrode 410 and the shielding member 450. As shown in FIG. Fig.16 As shown in , the bridges 250 arranged in the same row may be positioned in a zigzag manner in the second direction according to the arrangement of the pixel electrodes 410. The dotted line IL1 connecting the centers of the bridges 250 in the same row may not be parallel to the first direction or the second direction. The centers of the bridges 250 may not be aligned. The position of the gap GAP1 of the first division 212 of the first connection line 210 arranged in the first pixel PX1 and the position of the gap GAP2 of the first division 212 of the first connection line 210 arranged in the second pixel PX2 may be determined according to the position of the bridge 250.

[0150] The sixth insulating layer 350 covering the end of the pixel electrode 410 may be positioned on the fifth insulating layer 342. The sixth insulating layer 350 may have an opening OP for exposing a portion of the pixel electrode 410, thereby defining a pixel. The sixth insulating layer 350 may include an organic material such as benzocyclobutene (BCB), polyimide or hexamethyldisiloxane (HMDSO). Alternatively, the sixth insulating layer 350 may include one or more inorganic materials.

[0151] The intermediate layer 420 may be formed on the pixel electrode 410 exposed by the opening OP of the sixth insulating layer 350. The intermediate layer 420 may include at least an emission layer (EML), and may also include at least one functional layer of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). In an embodiment, the intermediate layer 420 may include a first functional layer arranged below the EML and / or a second functional layer arranged on the EML. The first functional layer and / or the second functional layer may include an entire layer in all pixel electrodes 410, or may be patterned as a layer corresponding to each pixel electrode 410. The EML may include a red emission layer, a green emission layer, or a blue emission layer. Alternatively, the EML may have a multilayer structure in which a red emission layer, a green emission layer, and a blue emission layer are stacked one on another to emit white light, or may have a single-layer structure including a red emission material, a green emission material, and a blue emission material.

[0152] The counter electrode 430 may cover the display area (see Figure 2The counter electrode 430 may cover some peripheral areas (see Figure 2 The opposite electrode 430 may include a semi-transmissive reflective layer including at least one selected from the group consisting of lithium (Li), calcium (Ca), lithium fluoride (LiF), Al, Mg, and Ag, or a light-transmitting metal oxide such as ITO, IZO, or ZnO, and may have a single-layer or multi-layer structure.

[0153] Fig.18 is a diagram showing a layout of pixels of the display device 10 according to the embodiment. Figures 19 to 21 is a layout diagram showing elements of a pixel in different layers according to one or more embodiments. Fig. 22 It shows Figure 2 A cross-sectional view of a portion of a display device. Fig. 22 According to an embodiment, a Fig.21 A cross section of the pixel electrode taken along line III-III'. Figures 19 to 21 Some structures shown in one or more of the figures may be compared with those shown in the reference Figures 9 to 17 Some structures described in one or more figures are the same or similar, and the relevant description may not be repeated.

[0154] like Fig.18 and Fig. 22 As shown in FIG. 1 , a pixel (eg, a first pixel PX1 or a second pixel PX2) may be positioned on a substrate 100. Each of the first pixel PX1 and the second pixel PX2 may include first to seventh TFTs T1 to T7 and a capacitor Cst. Each of the first to seventh TFTs T1 to T7 may include a semiconductor layer and a gate electrode.

[0155] like Fig.10 , Fig.17 and Fig. 22 As shown in FIG. 1 , the semiconductor layer of each of the first to seventh TFTs T1 to T7 may be positioned on the buffer layer 101. The semiconductor layer may include a source region, a drain region, and a channel region between the source region and the drain region of each of the first to seventh TFTs T1 to T7. A first insulating layer 320 may be positioned on the semiconductor layer.

[0156] like Fig.11 , Fig.17 and Fig. 22As shown in FIG. 1 , the gate electrodes 125a, 125b, 125c, 125d, 125e, 125f, and 125g of the first to seventh TFTs T1 to T7, the first scan line 121, the second scan line 122, and the emission control line 123 may be positioned on the first insulating layer 320. The first electrode as the lower electrode of the capacitor Cst may be the gate electrode 125a of the first TFT T1. The second insulating layer 331 may be positioned on the gate electrodes of the first to seventh TFTs T1 to T7.

[0157] like Fig.12 , Fig.17 and Fig. 22 As shown in FIG. 1 , the second electrode 127 as the upper electrode of the capacitor Cst may be positioned on the second insulating layer 331. An opening 27 may be formed in the second electrode 127 of the capacitor Cst. A third insulating layer 332 may be positioned on the second electrode 127 of the capacitor Cst. An initialization voltage line 141 may be positioned on the same layer as the second electrode 127 of the capacitor Cst.

[0158] like Fig.19 and Fig. 22 As shown in , the data line 171 and the power supply voltage line 172 may be positioned on the third insulating layer 332. The connecting members 173, 174 and 175 may be further positioned on the third insulating layer 332. The bridge 250 electrically connecting the first subsection 212 of the first connection line 210 may be further positioned on the third insulating layer 332. The bridge 250 may include the same material as the material used to form the data line 171, and may be formed on the same layer as the data line 171. In a direction perpendicular to the substrate 100, the bridge 250 may not overlap with the data line 171, the power supply voltage line 172, and the connecting members 173, 174 and 175. The relative position of the bridge 250 in the first pixel PX1 and the relative position of the bridge 250 in the second pixel PX2 may be substantially the same. The dotted line IL2 connecting the centers of the bridges 250 arranged in the same row may be parallel to the second direction. The centers of the bridges 250 arranged in the same row may be aligned in the second direction. The fourth insulating layer 341 may be positioned on the data line 171 and the power supply voltage line 172 .

[0159] like Fig. 20 and Fig. 22As shown in , the first subdivision 212 of the first connection line 210 may be positioned on the fourth insulating layer 341. The first subdivision 212 of the first connection line 210 extends in the first direction. The first connection line 210 may overlap at least some portions extending in the first direction of the semiconductor layer. The position of the gap GAP1 of the first subdivision 212 of the first connection line 210 arranged in the first pixel PX1 and the position of the gap GAP2 of the first subdivision 212 of the first connection line 210 arranged in the second pixel PX2 may both correspond to the position of the bridge 250 below. The first subdivision 212 of the first connection line 210 may be electrically connected to the corresponding bridge 250 arranged in the lower layer via the contact hole C formed in the fourth insulating layer 341. The fifth insulating layer 342 may be positioned on the first connection line 210.

[0160] like Fig.21 and Fig. 22 As shown in FIG. 3 , the OLED 400 may be positioned on the fifth insulating layer 342. The OLED 400 may include a pixel electrode 410, an opposing electrode 430, and an intermediate layer 420 between the pixel electrode 410 and the opposing electrode 430. A shielding member 450 may be further positioned on the fifth insulating layer 342.

[0161] The sixth insulating layer 350 covering the pixel electrode 410 and the shielding member 450 may be positioned on the fifth insulating layer 342. An opening OP for exposing a portion of the pixel electrode 410 may be formed in the sixth insulating layer 350. The intermediate layer 420 may be formed on the pixel electrode 410 exposed by the opening OP of the sixth insulating layer 350.

[0162] Fig.23 is a diagram showing a Figure 3 Plan view of section B. Fig.24A and Fig. 24B According to the embodiment along Fig.23 A cross-sectional view taken along line IV-IV'.

[0163] In an embodiment, the ESD protection circuit may be disposed in the peripheral area PA, may be located adjacent to a boundary between the display area DA and the peripheral area PA, and may be connected to the first connection line 210. Fig.23, the first connection line 210 can be electrically connected to the corresponding data line 171 (or data line DL) at the first contact portion CNT1. The first connection line 210 can extend from the display area DA to the peripheral area PA. The first connection line 210 may include a first subdivision 212 positioned in both the display area DA and the peripheral area PA, and may include a second subdivision 213 separated from the first subdivision 212 and positioned in the peripheral area PA. That is, the first subdivision 212 includes an extension, and the extension extends outside the display area DA toward the pad area PADA. Each subdivision of the first connection line 210 can be connected to a corresponding ESD protection circuit. The ESD protection circuit may be / include a bridge 250a that electrically connects the first subdivision 212 to the second subdivision 213 near the boundary between the display area DA and the peripheral area PA.

[0164] Reference Fig.24A and Fig. 24B The bridge 250 a may be positioned on a layer different from a layer on which the first and second subdivisions 212 and 213 are positioned, and may be electrically connected to the first and second subdivisions 212 and 213 via contact holes C.

[0165] In an embodiment, Fig.24A As shown in , the first subdivision 212 and the second subdivision 213 of the first connection line 210 may be substantially positioned between the fourth insulating layer 341 and the fifth insulating layer 342. The bridge 250a may be positioned on the fifth insulating layer 342. The bridge 250a may be positioned on the same layer as the pixel electrode 410. The bridge 250a may connect the first subdivision 212 to the second subdivision 213 via the contact hole C. The second subdivision 213 may be electrically connected to the corresponding data line 171 lower than the second subdivision 213 via the contact hole C at the first contact portion CNT1. The data line 171 may be positioned on the third insulating layer 332 (at Fig.17 or Fig. 22 The first contact portion CNT1 and the bridge 250a may be located on the insulating surface 120 of the display area DA and may be located between the second sub-portion 213 and the third insulating layer 332. The first contact portion CNT1 and the bridge 250a may be located in the peripheral area PA and may be located adjacent to a boundary between the display area DA and the peripheral area PA.

[0166] In an embodiment, Fig. 24B As shown in FIG. 1 , the first subsection 212 and the second subsection 213 of the first connection line 210 may be positioned on the fourth insulating layer 341. The bridge 250a may be positioned on the third insulating layer 332 (in Fig.17 or Fig. 22The bridge 250a may be located on the insulating surface 120 of the display area 210 (shown in FIG. 1 ), and may be located between the first connection line 210 and the third insulating layer 332. The bridge 250a may be located on the same layer as the data line 171. The bridge 250a may connect the first subdivision 212 to the second subdivision 213 via the contact hole C. The second subdivision 213 may be electrically connected to the corresponding data line 171 (located between the second subdivision 213 and the third insulating layer 332) via the contact hole C at the first contact portion CNT1. The first contact portion CNT1 and the bridge 250a may be located in the peripheral area PA, and may be adjacent to the boundary between the display area DA and the peripheral area PA.

[0167] Fig.25 is a diagram showing a Figure 3 Floor plan of Section E. Fig.26A and Fig.26B According to the embodiment along Fig.25 A cross-sectional view taken along line V-V' and line VI-VI'.

[0168] In an embodiment, the ESD protection circuit may be disposed in the peripheral area PA, may be located adjacent to a boundary between the display area DA and the peripheral area PA, and may be connected to the second connection line 220 and / or the third connection line 230 (in Figure 3 and Figure 4 ). Figure 3 , Figure 4 and Fig.25 , the second connection line 220 may include subdivisions 222 spaced apart from each other along the first direction in the peripheral area PA. Each subdivision 222 of the second connection line 220 may be connected to a corresponding ESD protection circuit. The ESD protection circuit may be / include a bridge 250b that electrically connects the subdivisions 222. Similarly, the third connection line 230 may include subdivisions 232 spaced apart from each other along the first direction in the peripheral area PA. Each subdivision 232 of the third connection line 230 may be connected to a corresponding ESD protection circuit. The ESD protection circuit may be / include a bridge 250c that electrically connects the subdivisions 232.

[0169] Reference Fig.26A and Fig.26B The bridge 250b may be positioned on a layer different from the layer on which the subsection 222 of the second connection line 220 is positioned, and may be electrically connected to the subsection 222 of the second connection line 220 via the contact hole C. The bridge 250c may be positioned on a layer different from the layer on which the subsection 232 of the third connection line 230 is positioned, and may be electrically connected to the subsection 232 of the third connection line 230 via the contact hole C.

[0170] In an embodiment, Fig.26AAs shown in FIG. 1 , the portion 222 of the second connection line 220 and the portion 232 of the third connection line 230 may be positioned on the first insulating layer 320 or the second insulating layer 331 (in Fig.17 or Fig. 22 The third insulating layer 332 (and the second insulating layer 331) may be substantially positioned between the second connection line 220 and the data line 171 and between the third connection line 230 and the data line 171. The data line 171 may be positioned between the third insulating layer 332 and the fourth insulating layer 341. The first connection line 210 may be positioned between the fourth insulating layer 341 and the fifth insulating layer 342. The bridges 250b and 250c may be positioned on the fifth insulating layer 342. The bridges 250b and 250c may be aligned with the pixel electrode 410 (in Fig.17 or Fig. 22 3 and the fourth insulating layer 341). The bridge 250b may be connected to the subsection 222 of the second connection line 220 (positioned between the bridge 250b and the substrate 100) via the contact hole C. The subsection 222 of the second connection line 220 may be electrically connected to the corresponding first connection line 210 (positioned between the subsection 222 and the fifth insulating layer 342) via the contact hole C at the second contact portion CNT2. The bridge 250c may be connected to the subsection 232 of the third connection line 230 (positioned between the bridge 250c and the substrate 100) via the contact hole C. The subsection 232 of the third connection line 230 may be electrically connected to the data line 171 (positioned between the subsection 232 and the fourth insulating layer 341) via the contact hole C at the third contact portion CNT3. The second contact portion CNT2, the third contact portion CNT3, and the bridges 250b and 250c may be positioned in the peripheral area PA, and may be positioned adjacent to the boundary between the display area DA and the peripheral area PA.

[0171] In an embodiment, Fig.26BAs shown in , the bridges 250b and 250c may be positioned on the third insulating layer 332. The bridges 250b and 250c may be positioned on the same layer as the data line 171. The bridge 250b may be connected to the subsection 222 of the second connection line 220 (positioned between the bridge 250b and the substrate 100) via the contact hole C. The subsection 222 of the second connection line 220 may be electrically connected to the corresponding first connection line 210 via the contact hole C at the second contact portion CNT2. The bridge 250c may be connected to the subsection 232 of the third connection line 230 (positioned between the bridge 250c and the substrate 100) via the contact hole C. The subsection 232 of the third connection line 230 may be electrically connected to the corresponding data line 171 (positioned between the subsection 232 and the fourth insulating layer 341) via the contact hole C at the third contact portion CNT3. The second contact portion CNT2, the third contact portion CNT3, and the bridges 250b and 250c may be positioned in the peripheral area PA and positioned adjacent to a boundary between the display area DA and the peripheral area PA.

[0172] Fig. 27 is a diagram showing a Figure 3 Plan view of section D. Fig.28A and Fig.28B According to the embodiment along Fig. 27 Cross-sectional views taken along line VII-VII' and line VIII-VIII'.

[0173] In an embodiment, the ESD protection circuit may be disposed adjacent to the pad area PADA of the peripheral area PA and may be connected to the second connection line 220 and / or the third connection line 230 (in Figure 3 and Figure 4 ). Figure 3 , Figure 4 and Fig. 27 , the second connection line 220 may include subdivisions 222 spaced apart from each other along the first direction in the peripheral area PA. Each subdivision 222 of the second connection line 220 may be connected to an ESD protection circuit. The ESD protection circuit may be / include a bridge 250d that electrically connects the subdivisions 222. Similarly, the third connection line 230 may include subdivisions 232 spaced apart from each other along the first direction in the peripheral area PA. Each subdivision 232 of the third connection line 230 may be connected to an ESD protection circuit. The ESD protection circuit may be / include a bridge 250e that electrically connects the subdivisions 232.

[0174] Reference Fig.28A and Fig.28BThe bridge 250d may be positioned on a layer different from the layer on which the subsection 222 of the second connection line 220 is positioned, and may be electrically connected to the subsection 222 of the second connection line 220 via the contact hole C. The bridge 250e may be positioned on a layer different from the layer on which the subsection 232 of the third connection line 230 is positioned, and may be electrically connected to the subsection 232 of the third connection line 230 via the contact hole C.

[0175] In an embodiment, Fig.28A As shown in FIG. 1 , the portion 222 of the second connection line 220 and the portion 232 of the third connection line 230 may be positioned on the first insulating layer 320 or the second insulating layer 331 (in Fig.17 or Fig. 22 2 and 3. The bridge 250 d and 250 e may be positioned on the insulating surface 120 of the substrate 100 (shown in FIG. 2 ). The bridges 250 d and 250 e may be positioned on the fifth insulating layer 342. The third insulating layer 332, the fourth insulating layer 341 and the fifth insulating layer 342 (and the second insulating layer 331) may be positioned between the second connection line 220 and the bridge 250 d and between the third connection line 230 and the bridge 250 e. The bridges 250 d and 250 e may be positioned on the same layer as the pixel electrode 410. The bridge 250 d may be connected to the subdivision 222 of the second connection line 220 (positioned between the bridge 250 d and the substrate 100) via the contact hole C. The bridge 250 e may be connected to the subdivision 232 of the third connection line 230 (positioned between the bridge 250 e and the substrate 100) via the contact hole C.

[0176] In an embodiment, Fig.28B As shown in FIG. 1 , the portion 222 of the second connection line 220 and the portion 232 of the third connection line 230 may be positioned on the first insulating layer 320 or the second insulating layer 331 (in Fig.17 or Fig. 22 100). The bridges 250d and 250e may be positioned on the third insulating layer 332. The bridges 250d and 250e may be positioned on the same layer as the data line 171. The third insulating layer 332 (and the second insulating layer 331) may be positioned between the second connection line 220 and the bridge 250d and between the third connection line 230 and the bridge 250e. The bridge 250d may be connected to the subsection 222 of the second connection line 220 (positioned between the bridge 250d and the substrate 100) via the contact hole C. The bridge 250e may be connected to the subsection 232 of the third connection line 230 (positioned between the bridge 250e and the substrate 100) via the contact hole C.

[0177] Fig.29 is a plan view showing a part of a display device according to an embodiment.

[0178] Fig.29The display device 10' shown in FIG. 1 has a first bending area BA1, a second bending area BA2, and a third bending area BA3. The display device 10' may include features similar to or identical to some of the features described above. The third display unit 113 and the fourth display unit 114 may extend from the first display unit 111. The third display unit 113 and the fourth display unit 114 may each include an edge display unit and a side display unit. Figure 3 and Figure 4 , the first connection line 210 may be positioned in the display area DA of the display device 10', and the second connection line 220 and the third connection line 230 may be positioned in the peripheral area PA of the first bending area BA1 of the display device 10'. Similar to the above features, the first connection line 210, the second connection line 220, and the third connection line 230 may be connected to at least one ESD protection circuit.

[0179] In an embodiment, an ESD protection circuit may be connected to a connection line between a data line and a pad, thereby preventing the connection line and / or the data line from being damaged by the static electricity of the connection line and / or the data line. An ESD protection circuit may be / includes a bridge electrically connecting the subdivisions of the connection line. In an embodiment, an ESD protection circuit may be positioned in a display area. In an embodiment, an ESD protection circuit may be arranged in a peripheral region P and may be positioned near a boundary between a display area and a peripheral region. In an embodiment, an ESD protection circuit may be arranged in a peripheral region and may be positioned near a pad region.

[0180] In an embodiment, a connection line for transmitting a data signal to a data line is arranged in a display area of ​​a display device, so that a non-display area of ​​the display device can be minimized. An ESD protection circuit can be connected to the connection line, so that the connection line and / or the data line can be prevented from being damaged by static electricity introduced from an entity outside the display device.

[0181] The described example embodiments should be considered in an illustrative sense, not for limiting purposes. The description of features or aspects in the embodiments should generally be considered applicable to other embodiments. Although the example embodiments have been described with reference to the accompanying drawings, various changes may be made to the embodiments without departing from the scope defined by the present disclosure.

Claims

1. A display device, in, The display device comprises: A substrate comprising a display area and a peripheral area, wherein a display element is located on the display area, and the peripheral area is located outside the display area and comprises a pad area, A data line, located on the display area; A pad, located on the pad area; a connection line located on the display area, the connection line being positioned on a layer different from a layer on which the data line is positioned, the connection line being electrically connected to the data line and the pad, and the connection line being configured to transmit a signal from the pad to the data line; and The electrostatic discharge protection circuit is electrically connected to the connection line.

2. The display device according to claim 1, in, The connecting line includes a first section and a second section, The electrostatic discharge protection circuit includes a bridge, and The first subsection is spaced apart from the second subsection in the extending direction of the connection line, and is electrically connected to the second subsection through the bridge.

3. The display device according to claim 2, in, The display element includes a pixel electrode and a capacitor, The connecting line is arranged between the capacitor and the pixel electrode, and The data line is arranged between the connection line and the capacitor.

4. The display device according to claim 3, in, The bridge is located on the same layer as the pixel electrode or the data line.

5. The display device according to claim 2, in, The first subsection includes an extension, and The extension portion extends toward the pad region and out of the display region.

6. The display device according to claim 5, in, The display element includes a pixel electrode and a capacitor, The connecting line is arranged between the capacitor and the pixel electrode, and The data line is arranged between the connection line and the capacitor.

7. The display device according to claim 6, in, The bridge is located on the same layer as the pixel electrode or the data line.

8. A display device, in, The display device comprises: A substrate, comprising a display area and a peripheral area, wherein the peripheral area is located outside the display area and comprises a pad area; A data line, located on the display area; A pad, located on the pad area; a first connection line located on the display area, the first connection line being located on a layer different from a layer where the data line is located, and the first connection line being electrically connected to the data line; a second connection line located on the peripheral area and electrically connected to the first connection line and the pad; and The electrostatic discharge protection circuit is electrically connected to at least one of the first connection line and the second connection line.

9. The display device according to claim 8, in, The display device further includes a display element, wherein the display element includes a pixel electrode and a capacitor. The first connecting line is positioned between the capacitor and the pixel electrode, and The data line is positioned between the first connection line and the capacitor.

10. The display device according to claim 9, in, The first connecting line includes a first section and a second section, The electrostatic discharge protection circuit includes a bridge, and The first subsection is spaced apart from the second subsection in an extending direction of the first connecting line, and is electrically connected to the second subsection through the bridge.

11. The display device according to claim 10, in, The bridge is located on the same layer as the pixel electrode.

12. The display device according to claim 10, in, The bridge is located on the same layer as the data line.

13. The display device according to claim 9, in, The first connecting line includes a first section and a second section separated from the first section, The first section extends from the display area toward the pad area to the peripheral area, The electrostatic discharge protection circuit includes a bridge, and The first division is arranged on the display area and is electrically connected to the second division through the bridge.

14. The display device according to claim 13, in, The bridge is located on the same layer as the pixel electrode.

15. The display device according to claim 13, in, The bridge is located on the same layer as the data line.

16. The display device according to claim 9, in, The second connecting line includes two sections spaced apart from each other in an extending direction of the second connecting line, and The electrostatic discharge protection circuit includes a bridge electrically connecting the two sections of the second connection line to each other.

17. The display device according to claim 16, in, The bridge is located on the peripheral area and positioned between the display area and the pad area.

18. The display device according to claim 16, in, The second connecting line and the electrode of the capacitor are located on the same layer, The bridge is located on the peripheral area and on the same layer as the pixel electrode.

19. The display device according to claim 16, in, The second connecting line and the electrode of the capacitor are located on the same layer, The bridge is located on the peripheral area and on the same layer as the data line.

20. The display device according to claim 8, in, The first connecting line includes a first section and a second section, The first section extends in a first direction, The second segment is directly connected to the first segment and extends in a second direction perpendicular to the first direction, and The first segment and the second segment are both located on the display area.

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