Display device and display panel

Abstract

The present disclosure relates to a display device and a display panel, and pertains to the field of display technologies. The display panel includes a substrate, a driving layer, a light-emitting device layer, a first barrier rib, a plurality of drainage bars, and a packaging layer. The driving layer is disposed on one side of the substrate and has a pixel circuit region, a peripheral circuit region, and an edge region. The light-emitting device layer is disposed on the side of the pixel circuit region facing away from the substrate. The first barrier rib is disposed in the edge region and surrounds the peripheral circuit region. The drainage bars are disposed on the side of the edge region facing away from the substrate and are located within the area surrounded by the first barrier rib. Each drainage bar extends from the edge region to the peripheral circuit region. The packaging layer includes a first inorganic layer, an organic layer, and a second inorganic layer. The first inorganic layer covers the light-emitting device layer, the first barrier rib, and the drainage bars and bulges in the regions corresponding to the first barrier rib and the drainage bars. The organic layer is disposed on the surface of the first inorganic layer facing away from the substrate and is confined within the range surrounded by the first barrier rib. The second inorganic layer covers the organic layer and the first inorganic layer.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a display device and a display panel. Background Art

[0002] In an OLED (Organic Light-Emitting Diode) display panel, a Thin-Film Encapsulation (TFE) process is usually adopted for encapsulation. However, the optical uniformity of the encapsulation layer of the existing display panel is relatively low, and the effect of still blocking water and oxygen needs to be improved.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a display device and a display panel, which can improve the optical uniformity and reduce the risk of encapsulation failure.

[0005] According to one aspect of the present disclosure, a display panel is provided, including:

[0006] A substrate;

[0007] A driving layer, disposed on one side of the substrate, and having a pixel circuit region, a peripheral circuit region surrounding the pixel circuit region, and an edge region surrounding the peripheral circuit region;

[0008] A light-emitting device layer, disposed on the side of the pixel circuit region away from the substrate;

[0009] A first barrier rib, disposed on the side of the edge region away from the substrate, the first barrier rib being an annular structure surrounding the peripheral circuit region;

[0010] A plurality of drainage strips, disposed on the side of the edge region away from the substrate and within the range surrounded by the first barrier rib; the drainage strips are spaced apart from each other, and each drainage strip extends from the edge region to the peripheral circuit region;

[0011] An encapsulation layer, including a first inorganic layer, an organic layer, and a second inorganic layer, the first inorganic layer covering the light-emitting device layer, the first barrier rib, and the drainage strips, and protruding in the regions corresponding to the first barrier rib and the drainage strips; the organic layer is disposed on the surface of the first inorganic layer away from the substrate and is limited within the range surrounded by the first barrier rib; the second inorganic layer covers the organic layer and the first inorganic layer.

[0012] In an exemplary embodiment of the present disclosure, the drain bar is connected to the inner side wall of the first blocking dam; in a direction perpendicular to the substrate, the thickness of the drain bar is less than the thickness of the first blocking dam.

[0013] In an exemplary embodiment of the present disclosure, the first blocking dam includes a first layer and a second layer stacked in sequence along a direction away from the substrate, the inner sidewall of the second layer surrounds the inner sidewall of the first layer; the drain bar is connected to the first layer and is made of the same material.

[0014] In an exemplary embodiment of the present disclosure, there is a gap between the inner side wall of the first barrier dam and the guide bar.

[0015] In an exemplary embodiment of the present disclosure, the orthographic projection of the edge region on the substrate is a polygon and includes a plurality of side regions and arc regions, and two adjacent side regions are transitionally connected by an arc region;

[0016] The width of the drain strip located in the arc-shaped area increases in a direction away from the pixel circuit area.

[0017] In an exemplary embodiment of the present disclosure, the driving layer includes:

[0018] An active layer, disposed on one side of the substrate and located in the pixel circuit area and the peripheral circuit area;

[0019] a first gate insulating layer, covering the active layer and located in the pixel circuit area, the peripheral circuit area and the edge area;

[0020] A gate layer, provided on a surface of the first gate insulating layer away from the substrate, and located in the pixel circuit area and the peripheral circuit area;

[0021] a second gate insulating layer, covering the gate layer and the first gate insulating layer, and located in the pixel circuit area, the peripheral circuit area and the edge area;

[0022] a dielectric layer, covering the second gate insulating layer and located in the pixel circuit area, the peripheral circuit area and the edge area;

[0023] A source-drain layer, disposed on a surface of the dielectric layer away from the substrate, and located in the pixel circuit area and the peripheral circuit area;

[0024] A planar layer, covering the source / drain layer and the dielectric layer, and located in the pixel circuit area and the peripheral circuit area;

[0025] A power line is provided on the surface of the dielectric layer away from the substrate and located in the edge area, and the material and thickness of the power line are the same as those of the source and drain layer;

[0026] The first blocking dam and the drain bar at least cover a partial area of ​​the power line.

[0027] In an exemplary embodiment of the present disclosure, the light emitting device layer includes:

[0028] A first electrode layer is provided on a surface of the planar layer away from the substrate and located in the pixel circuit area, the first electrode layer comprising a plurality of first electrodes distributed in an array;

[0029] a pixel definition layer, covering the first electrode layer and the planar layer, and exposing each of the first electrodes;

[0030] a light-emitting functional layer, at least covering a surface of the first electrode facing away from the substrate;

[0031] A second electrode layer, covering the light-emitting functional layer;

[0032] The display panel further includes:

[0033] A bonding layer is provided on the surface of the flat layer away from the substrate and extends to the surface of the power line away from the substrate, and a plurality of exhaust holes distributed in an array are provided in the bonding layer in an area corresponding to the flat layer; the bonding layer and the first electrode layer have the same material and thickness;

[0034] A protective layer is provided on the surface of the overlapping layer away from the substrate, covers the exhaust hole, and exposes a part of the overlapping layer; the protective layer is made of the same material and has the same thickness as the drain bar;

[0035] The drain bar is located on a side of the protective layer away from the pixel circuit area, and covers a portion of the overlap layer corresponding to the power line;

[0036] The second electrode layer extends toward the edge region to a surface of the protection layer facing away from the substrate, and is connected to the overlapping layer.

[0037] In an exemplary embodiment of the present disclosure, the protective layer includes a plurality of protective strips, and the exhaust holes are distributed in the area of ​​the overlapping layer covered by the protective strips; each of the protective strips is connected to each of the drainage strips in a one-to-one correspondence.

[0038] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0039] A support column is provided on a surface of the pixel definition layer facing away from the substrate;

[0040] One of the support pillars and the pixel definition layer is made of the same material as the drain bar.

[0041] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0042] The second blocking dam is disposed on a side of the edge region away from the substrate and surrounds the first blocking dam. The first inorganic layer covers the second blocking dam.

[0043] In an exemplary embodiment of the present disclosure, a distance between an inner sidewall of the second layer and an inner sidewall of the first layer is not less than 3 μm.

[0044] In an exemplary embodiment of the present disclosure, the width of the gap between the drain strip and the inner sidewall of the first barrier dam is 3 μm-30 μm.

[0045] In an exemplary embodiment of the present disclosure, the length of the drain strip is 50 μm-500 μm, the width of the drain strip is 5 μm-50 μm, and the interval between two adjacent drain strips is 5 μm-100 μm.

[0046] In an exemplary embodiment of the present disclosure, the guide strips are distributed at intervals along an annular track.

[0047] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0048] The display device and display panel disclosed in the present invention are provided with a drain strip extending from the edge area to the peripheral circuit area on the inner side of the first barrier layer, and the first inorganic layer is raised in the area corresponding to the first barrier dam and the drain strip; when the organic layer is formed, the protrusion corresponding to the drain strip will destroy the equilibrium state of the surface tension of the liquid organic material, and under the action of the capillary effect, the organic material diffuses along the protrusion corresponding to the drain strip toward the first barrier dam until it is blocked by the protrusion corresponding to the first barrier dam. The problem of insufficient coverage or overflow (over the first barrier dam) of the organic material caused by the inability to accurately control the leveling boundary of the organic material can be prevented; and the insufficient coverage of the organic material in the edge area is likely to cause the accumulation of organic materials in the peripheral circuit area or the pixel circuit area, increasing the risk of subsequent processes and causing insufficient luminescence uniformity; the overflow of organic materials can cause the organic material to contact with external water and oxygen, resulting in packaging failure. In summary, the display panel disclosed in the present invention can improve luminescence uniformity, reduce process risks, and prevent packaging failure.

[0049] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments in accordance with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0051] Figure 1 It is a schematic diagram of the encapsulation of a display panel in the related art.

[0052] Figure 2 It is a partial cross-sectional view of the distribution of organic materials in the encapsulation layer of a display panel in the related art.

[0053] Figure 3 It is a partial top view of the distribution of organic materials in the encapsulation layer of a display panel in the related art.

[0054] Figure 4 It is a top view of the display panel of the present disclosure.

[0055] Figure 5 It is Figure 4 the A-A cross-sectional view of the display panel in

[0056] Figure 6 It is Figure 4 the B-B cross-sectional view of an embodiment of the display panel in

[0057] Figure 7 It is corresponding to Figure 6 the schematic diagram of the distribution of drain bars of the embodiment of the display panel in

[0058] Figure 8 It is Figure 4 the B-B cross-sectional view of another embodiment of the display panel in

[0059] Figure 9 It is corresponding to Figure 8 the schematic diagram of the distribution of drain bars of the embodiment of the display panel in

[0060] Figure 10 It is Figure 4 the B-B cross-sectional view of yet another embodiment of the display panel in

[0061] Figure 11 It is corresponding to Figure 10 the schematic diagram of the distribution of drain bars of the embodiment of the display panel in

[0062] Figure 12 It is the schematic diagram of the distribution of drain bars in the side area and the arc area of the display panel of the present disclosure.

[0063] Figure 13This is a flowchart of an embodiment of the manufacturing method of the present disclosure.

[0064] Description of reference numerals:

[0065] Figures 1 - 3 Among them: 001, driving backplane; 002, light-emitting device layer; 003, encapsulation layer; 0031, first inorganic layer; 0032, organic layer; 0033, second inorganic layer; 004, barrier dam.

[0066] Figures 4 - 12 Among them: 1, substrate; 2, driving layer; 201, pixel circuit region; 202, peripheral circuit region; 203, edge region; 2031, side region; 2032, arc region; 21, active layer; 211, active part; 22, first gate insulating layer; 23, gate layer; 231, gate; 24, second gate insulating layer; 25, dielectric layer; 26, source-drain layer; 261, source electrode; 262, drain electrode; 27, planarization layer; 28, power line; 291, first electrode plate; 292, second electrode plate; 293, third electrode plate; 294, fourth electrode plate; 3, light-emitting device layer; 31, first electrode layer; 311, first electrode; 32, pixel definition layer; 33, light-emitting functional layer; 331, organic common layer; 332, light-emitting material layer; 34, second electrode layer; 4, first barrier dam; 41, first layer of the first barrier dam; 42, second layer of the first barrier dam; 5, drainage strip; 6, encapsulation layer; 61, first inorganic layer; 62, organic layer; 63, second inorganic layer; 7, overlapping layer; 71, exhaust hole; 8, protective layer; 81, protection strip; 9, support pillar; 10, second barrier dam; 101, first layer of the second barrier dam; 102, second layer of the second barrier dam; 103, third layer of the second barrier dam; 11, buffer layer. Detailed implementation manners

[0067] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0068] The terms "a", "one", "the", "said" and "at least one" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are only used as labels and are not a limitation on the quantity of their objects.

[0069] In the related art, as Figure 1 shown, an OLED display panel may include a driving backplane 001, an optical device layer 002, and a packaging layer 003. A plurality of annular barrier ribs 004 arranged concentrically are provided on one side of the driving backplane 001; the light-emitting device layer 002 is disposed on the driving backplane 001 and within the range surrounded by the barrier ribs 004, and the light-emitting devices in the light-emitting device layer 002 can be driven by the circuit in the driving backplane 001 to emit light, thereby displaying an image.

[0070] The packaging layer 003 may include a first inorganic layer 0031, an organic layer 0032, and a second inorganic layer 0033. Among them, the first inorganic layer 0031 covers the barrier ribs 004 and the light-emitting device layer 002, the organic layer 0032 is disposed on the surface of the first inorganic layer 0031 facing away from the driving backplane 001, and is limited within the range surrounded by the barrier rib 004 (the one closest to the light-emitting device layer 002 among the barrier ribs 004); the second inorganic layer 0033 covers the organic layer 0032 and the first inorganic layer 0031, thereby encapsulating the organic layer 0032 between the first inorganic layer 0031 and the second inorganic layer 0033. The first inorganic layer 0031 and the second inorganic layer 0033 are inorganic materials and can be used for water blocking; while the material of the organic layer 0032 is an organic material, which can play a role in flattening the interface, encapsulating defects, and releasing stress.

[0071] During packaging, the organic material can be formed on the first inorganic layer 0031 by an inkjet-printed (IJP) process, and the barrier ribs 004 are used to prevent the organic material from overflowing outside the barrier ribs 004, preventing the organic material from contacting water and oxygen in the outside world. During this process, the liquid organic material freely levels on the first inorganic layer 0031. Affected by local wettability and liquid surface tension fluctuations, the actual stopping positions of the organic material in different regions vary greatly, that is, the edge linearity is poor; that is to say, it is difficult for the boundaries of the organic layer 0032 in different regions to match the range defined by the barrier ribs 004.

[0072] As Figure 2 and Figure 3 shown, the ideal edge of the organic layer 0032 is the II region, that is, the inside of the barrier rib 004 is filled with the organic material and there is no overflow. However, since the actual stopping position of the organic material is difficult to control, problems such as insufficient coverage or overflow are likely to occur. Specifically, in Figure 2 and Figure 3In the [description], in the area where the leveling distance in Region I is insufficient, that is, the boundary of the organic material does not reach the barrier dam 004, resulting in some areas inside the barrier dam 004 not being covered by the organic layer 0032. In Region I, a large slope is likely to occur, causing subsequent process risks and pressing the internal organic material to form a bulge on the light-emitting device layer 002, affecting optical uniformity. In Region III, the organic material overflows the barrier dam 004, exposing the organic layer 0032, which is easily in contact with water and oxygen, leading to packaging failure.

[0073] Embodiments of the present disclosure provide a display panel, which may be an OLED display panel. For example, Figures 4 - 7 As shown, the display panel may include a substrate 1, a driving layer 2, a light-emitting device layer 3, a first barrier dam 4, a drainage strip 5, and a packaging layer 6, where:

[0074] The driving layer 2 is disposed on one side of the substrate 1 and has a pixel circuit region 201, a peripheral circuit region 202 surrounding the pixel circuit region 201, and an edge region 203 surrounding the peripheral circuit region 202.

[0075] The light-emitting device layer 3 is disposed on the side of the pixel circuit region 201 facing away from the substrate 1.

[0076] The first barrier dam 4 is disposed on the side of the edge region 203 facing away from the substrate 1, and the first barrier dam 4 is an annular structure surrounding the pixel circuit region 201.

[0077] A plurality of drainage strips 5 are disposed on the side of the edge region 203 facing away from the substrate 1 and are located within the range surrounded by the first barrier dam 4; the drainage strips 5 are spaced apart, and each drainage strip 5 extends from the edge region 203 to the peripheral circuit region 202.

[0078] For example, the drainage strips 5 are spaced apart along an annular trajectory.

[0079] The packaging layer 6 includes a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63. The first inorganic layer 61 covers the light-emitting device layer 3, the first barrier dam 4, and the drainage strip 5, and bulges in the regions corresponding to the first barrier dam 4 and the drainage strip 5; the organic layer 62 is disposed on the surface of the first inorganic layer 61 facing away from the substrate 1 and is limited within the range surrounded by the first barrier dam 4; the second inorganic layer 63 covers the organic layer 62 and the first inorganic layer 61.

[0080] In the display panel of the embodiment of the present disclosure, when the organic layer 62 is formed, the protrusion corresponding to the drain bar 5 will destroy the equilibrium state of the surface tension of the liquid organic material. Under the action of the capillary effect, the organic material diffuses along the protrusion corresponding to the drain bar 5 toward the first barrier dam 4 until it is blocked by the protrusion corresponding to the first barrier dam 4, so that the boundary of the organic layer 62 matches the range defined by the first barrier dam 4, and there will be no problems of insufficient coverage and overflow (over the first barrier dam 4) of the organic material. Insufficient coverage of the organic material in the edge area 203 can easily cause accumulation of organic material in the peripheral circuit area 202 or the pixel circuit area 201, increasing the risk of subsequent processes and causing insufficient uniformity of luminescence; overflow of organic material can cause the organic material to contact with external water and oxygen, resulting in packaging failure. In summary, the display panel can improve luminescence uniformity, reduce process risks, and prevent packaging failure.

[0081] The following is a detailed description of each part of the display panel in the embodiment of the present disclosure:

[0082] The substrate 1 may be a transparent plate-like structure, and its material may be a flexible material such as PI (polyimide). Accordingly, the display panel is a flexible display panel. Of course, the material of the substrate 1 may also be a hard material such as glass.

[0083] The driving layer 2 is disposed on one side of the substrate 1 , and in order to prevent impurities in the substrate 1 from affecting the driving layer 2 , a buffer layer 11 may be disposed on the substrate 1 . The driving layer 2 is disposed on the surface of the buffer layer 11 away from the substrate 1 .

[0084] The driving layer 2 has a pixel circuit area 201, a peripheral circuit area 202 surrounding the pixel circuit area 201, and an edge area 203 surrounding the peripheral circuit area 202. Among them, a pixel circuit is arranged in the pixel circuit area 201, and the specific structure of the pixel circuit is not particularly limited here, as long as it can be used to drive the light-emitting device of the light-emitting device layer 3 to emit light. A peripheral circuit is arranged in the peripheral circuit area 202, and a driving signal can be input to the pixel circuit through the peripheral circuit to make the light-emitting device of the light-emitting device layer 3 emit light. The peripheral circuit may include a light-emitting control circuit (EM-GOA), a gate driving circuit (Gate-GOA), etc., and the specific structure of the peripheral circuit is not particularly limited here.

[0085] In some embodiments of the present disclosure, the pixel circuit and the peripheral circuit of the driving layer 2 both include a plurality of thin film transistors, such as Figure 5 , Figure 6 , Figure 8 and Figure 10 As shown, Figure 5 Only the driving transistor of the pixel circuit is shown. Figure 6 , Figure 8 and Figure 10Only one thin film transistor in the light emission control circuit of the peripheral circuit is also shown. Taking all thin film transistors as the top gate type structure as an example, as Figure 5 shown, in the direction perpendicular to the driving layer 2, the driving layer 2 may include an active layer 21, a first gate insulating layer 22, a gate layer 23, a second gate insulating layer 24, a dielectric layer 25, a source-drain layer 26, and a planar layer 27, where:

[0086] The active layer 21 is disposed on one side of the substrate 1. For example, the active layer 21 is disposed on the surface of the buffer layer 11 facing away from the substrate 1. The active layer 21 is a semiconductor material such as amorphous silicon, polycrystalline silicon, or metal oxide. The active layer 21 may include a plurality of independent active portions 211, and active portions 211 are formed in the regions corresponding to the respective thin film transistors in the pixel circuit region 201 and the peripheral circuit region 202.

[0087] The first gate insulating layer 22 covers the active layer 21. For example, it covers the active layer 21 and the buffer layer 11 not covered by the active layer 21. At the same time, the first gate insulating layer 22 extends to the pixel circuit region 201, the peripheral circuit region 202, and the edge region 203, that is, the positive projection of the first gate insulating layer 22 on the substrate 1 may coincide with the boundary of the substrate 1.

[0088] The gate layer 23 may be disposed on the surface of the first gate insulating layer 22 facing away from the substrate 1 and is located in the pixel circuit region 201 and the peripheral circuit region 202. The gate layer 23 may include a plurality of independent gates 231, and gates 231 are formed in the regions corresponding to the respective thin film transistors in the pixel circuit region 201 and the peripheral circuit region 202, and the gate 231 and the active portion 211 of the same thin film transistor are disposed opposite to each other in the direction perpendicular to the substrate 1.

[0089] The second gate insulating layer 24 covers the gate layer 23 and the region of the first gate insulating layer 22 not covered by the gate layer 23. The pixel circuit region 201, the peripheral circuit region 202, and the edge region 203 all have the second gate insulating layer 24, that is, the positive projection of the second gate insulating layer 24 on the substrate 1 may coincide with the boundary of the substrate 1.

[0090] The dielectric layer 25 covers the second gate insulating layer 24, and the pixel circuit region 201, the peripheral circuit region 202, and the edge region 203 all have the dielectric layer 25, that is, the positive projection of the dielectric layer 25 on the substrate 1 may coincide with the boundary of the substrate 1.

[0091] The source-drain layer 26 is disposed on the surface of the dielectric layer 25 facing away from the substrate 1. The source-drain layer 26 includes multiple sets of independent source electrodes 261 and drain electrodes 262. A set of source electrode 261 and drain electrode 262 are formed in the pixel circuit region 201 and the peripheral circuit region 202 corresponding to each thin film transistor. Each set of source electrode 261 and drain electrode 262 includes a source electrode 261 and a drain electrode 262. The same thin film transistor includes a set of source electrode 261 and drain electrode 262, and the source electrode 261 and the drain electrode 262 are connected to both ends of the corresponding active part 211.

[0092] The material of the planarization layer 27 can be an organic insulating material. It can cover the source-drain layer 26 and the region of the dielectric layer 25 not covered by the source-drain layer 26. And the planarization layer 27 is continuously located in the pixel circuit region 201 and the peripheral circuit region 202, while in the edge region 203, there is at most only a part of the planarization layer 27. That is to say, the boundary of the planarization layer 27 coincides with the boundary of the peripheral circuit region 202; or, the boundary of the planarization layer 27 can be located within the edge region 203.

[0093] In addition, as Figure 5 and Figure 6 shown, the driving layer 2 may further include a power line 28. The power line 28 can be disposed on the surface of the dielectric layer 25 facing away from the substrate 1 and is located in the edge region 203. That is to say, the power line 28 is disposed on the surface of the dielectric layer 25 not covered by the planarization layer 27. The power line 28 has the same material and thickness as the source-drain layer 26, so that they can be formed simultaneously by the same patterning process, and this patterning process can be a lithography process. At the same time, the power line 28 is separated from the peripheral circuit in the peripheral circuit region 202 by a partial region of the planarization layer 27, so that the power line 28 is not directly connected to the peripheral circuit.

[0094] The planarization layer 27 can also extend into the edge region 203 and cover a partial region of the power line 28. The power line 28 can be connected to the driving circuit board in the bonding region bonded to the edge region 203 to receive the driving signal from the driving circuit board, so as to drive the light-emitting device in the light-emitting device layer 3 to emit light.

[0095] As Figure 5 shown, the pixel circuit in the pixel circuit region 201 may further include a first capacitor. The first capacitor includes a first electrode plate 291 and a second electrode plate 292. Among them, the first electrode plate 291 can be disposed on the surface of the first gate insulating layer 22 facing away from the substrate 1, is covered by the second gate insulating layer 24, and has the same material and thickness as the gate layer 21, so that the gate layer 21 and the first electrode plate 291 can be formed simultaneously by one patterning process. The second electrode plate 292 can be disposed on the surface of the second gate insulating layer 25 facing away from the substrate 1 and is covered by the dielectric layer 25.

[0096] As Figure 6 、 Figure 8 and Figure 10As shown, the peripheral circuit of the peripheral circuit region 202 includes a second capacitor. The second capacitor may include a third electrode plate 293 and a fourth electrode plate 294. Among them, the third electrode plate 293 may be disposed on the surface of the first gate insulating layer 22 facing away from the substrate 1, covered by the second gate insulating layer 24, and have the same material and thickness as the gate electrode layer 21, so that the gate electrode layer 21 and the third electrode plate 293 can be formed simultaneously through a single patterning process. The fourth electrode plate 294 may be disposed on the surface of the second gate insulating layer 25 facing away from the substrate 1 and covered by the dielectric layer 25. The fourth electrode plate 294 and the second electrode plate 292 have the same material and thickness, so as to be formed through a single patterning process.

[0097] It should be noted that Figure 5 the first capacitor shown in is only for illustrating the structure of the first capacitor and does not refer to a specific capacitor in the pixel circuit. Figure 6 、 Figure 8 and Figure 10 the second capacitor in is only for illustrating the structure of the second capacitor and does not refer to a specific capacitor in the peripheral circuit.

[0098] As Figure 5 shown, the light-emitting device layer 3 may include a plurality of light-emitting devices. Taking the light-emitting device as an OLED light-emitting device as an example, as Figure 5 shown, in some embodiments of the present disclosure, the light-emitting device layer 3 may include a first electrode layer 31, a pixel definition layer 32, a light-emitting functional layer 33, and a second electrode layer 34, where:

[0099] The first electrode layer 31 is disposed on the surface of the planarization layer 27 facing away from the substrate 1 and is located in the pixel circuit region 201. The first electrode layer 31 includes a plurality of first electrodes 311 distributed in an array. Each first electrode 311 can serve as the anode of an OLED light-emitting device and can be connected to the pixel circuit in the pixel circuit region 201 to receive a signal for driving the light-emitting device to emit light. For example, the pixel circuit may include pixel circuit units corresponding to each light-emitting device one by one. Each pixel circuit unit includes a driving transistor, and the source electrode 261 or the drain electrode 262 of the driving transistor is connected to the first electrode 311 of the corresponding light-emitting device through a via hole passing through the planarization layer 27.

[0100] The pixel definition layer 32 covers the first electrode layer 31 and the planarization layer 27, and the pixel definition layer 32 is provided with a plurality of openings, and each opening exposes each first electrode 311 one by one, so that the ranges of the respective light-emitting devices can be defined through the pixel definition layer 32.

[0101] The light-emitting functional layer 33 covers at least the surface of the first electrode 311 facing away from the substrate 1. For example, it may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in sequence in a direction away from the substrate 1. Among them, different-color OLED light-emitting devices may share at least the same electron transport layer and the same hole transport layer, while the light-emitting material layers of different-color OLED light-emitting devices are different. Therefore, for all OLED light-emitting devices, the light-emitting functional layer 33 may at least include an organic common layer 331 and a light-emitting material layer 332, where: the organic common layer 331 is used to represent the film layer shared by each OLED light-emitting device, and the number of light-emitting material layers 332 is multiple and distributed in an array, and each light-emitting material layer 332 is arranged in one-to-one correspondence with each first electrode 311 to limit the light-emitting color of each OLED light-emitting device.

[0102] It should be noted that although Figure 5 the organic common layer 331 in is depicted as the film layer located between the first electrode layer 31 and the light-emitting material layer 332, it does not represent a certain actual film layer in the light-emitting functional layer 33, but is used to represent all the shared film layers. If the organic common layer 331 is depicted as the multiple film layers it actually contains, for example, the organic common layer 331 includes an electron transport layer and a hole transport layer; then the light-emitting material layer 332 may be located between the electron transport layer and the hole transport layer. That is to say, Figure 5 the organic common layer 331 and the light-emitting material layer 332 in do not constitute a limitation on the stacking relationship of the actual film layers in the OLED light-emitting device.

[0103] The second electrode layer 34 covers the light-emitting functional layer 33, and it can be used as the cathode of each light-emitting device, that is, each light-emitting device can share the second electrode layer 34. Each first electrode 311 and its corresponding light-emitting functional layer 33 and second electrode layer 34 can form an OLED light-emitting device. By applying a driving signal to the first electrode layer 31 and the second electrode layer 34, the light-emitting functional layer 33 can be made to emit light.

[0104] Furthermore, the light-emitting functional layer 33 may further include an optical adjustment layer (not shown in the figure), which can be disposed on the surface of the second electrode layer 34 facing away from the substrate 1. By reasonably setting the refractive index of the optical adjustment layer, the reflection effect of the second electrode layer 34 on the light emitted by the light-emitting material layer 332 can be reduced, and the light extraction efficiency can be improved.

[0105] Furthermore, as Figure 6 、 Figure 8 and Figure 10 shown, in order to facilitate the connection of the second electrode layer 34 to the power line 28 to input a signal to the second electrode layer 34, the display panel may further include a lamination layer 7 and a protective layer 8, where:

[0106] The overlapping layer 7 is made of a conductive material and is disposed on the surface of the flat layer 27 facing away from the substrate 1 and extends to the surface of the power supply line 28 facing away from the substrate 1. However, it is not limited to completely covering the power supply line 28, as long as it can be connected to the power supply line 28. The overlapping layer 7 and the first electrode layer 31 have the same material and thickness, so the overlapping layer 7 and the first electrode layer 31 can be formed simultaneously through the same patterning process, but they are not directly connected. In the direction perpendicular to the substrate 1, the peripheral circuit of the peripheral circuit region 202 can be opposite to the overlapping layer 7. For example, the overlapping layer 7 can be directly opposite to the light-emitting control circuit. Figure 6 、 Figure 8 and Figure 10 only shows a thin-film transistor of the light-emitting control circuit of the peripheral circuit, which is directly opposite to the overlapping layer 7.

[0107] The flat layer 27 is made of an organic material and is prone to absorbing water. The light-emitting functional layer 33 of the light-emitting device layer 3 can be formed by an evaporation process. In order to discharge water vapor, baking can be performed after forming the overlapping layer 7 and the first electrode layer 31 and before forming the light-emitting device layer 3. A plurality of exhaust holes 71 are arranged in an array in the region of the overlapping layer 7 corresponding to the flat layer 27 to prevent the overlapping layer 7 from blocking the release of water vapor.

[0108] In order to avoid the burrs at the edges of the exhaust holes 71 from damaging the upper film layer, the exhaust holes 71 can be covered with a protective layer 8 so that the edges of the exhaust holes 71 are within the range covered by the protective layer 8, thereby preventing the burrs from damaging the upper film layer. Specifically, the protective layer 8 is disposed on the surface of the overlapping layer 7 facing away from the substrate 1, covers each exhaust hole 71, and exposes a part of the overlapping layer 7. The second electrode layer 34 can extend to the surface of the protective layer 8 facing away from the substrate 1 in the edge region 203 and is connected to the overlapping layer 7 not covered by the protective layer 8, so that the second electrode layer 33 is connected to the power supply line 28 through the overlapping layer 7 to input a signal to the second electrode layer 34.

[0109] For example, the protective layer 8 can include a plurality of protective units arranged in an array, and each protective unit covers each exhaust hole 71 one by one. The edge of each exhaust hole 71 is within the range of the orthographic projection of the corresponding protective unit on the overlapping layer 7, and the protective unit fills the corresponding exhaust hole 71.

[0110] As Figures 6 - 11 shown, the first barrier dam 4 is disposed on the side of the edge region 203 of the driving layer 2 facing away from the substrate 1. For example, the first barrier dam 4 can be disposed on the surface of the dielectric layer 25 facing away from the substrate 1 and is located in the edge region 203. The first barrier dam 4 can cover the region of the power supply line 28 not covered by the overlapping layer 7 and a part of the overlapping layer 7. The first barrier dam 4 is an annular structure surrounding the peripheral circuit region 202 and is used to limit the organic layer 62 of the encapsulation layer 6.

[0111] The first barrier dam 4 is a single-layer or multi-layer structure. In some embodiments of the present disclosure, the first barrier dam 4 may include a first layer 41 and a second layer 42, where:

[0112] The first layer 41 of the first barrier dam 4 may be disposed on the surface of the dielectric layer 25 facing away from the substrate 1 and located in the edge region 203. The first layer 41 may cover the region of the power line 28 not covered by the overlapping layer 7 and a partial region of the overlapping layer 7. Further, the first layer 41 may be made of the same material as the pixel definition layer 32 so as to be formed simultaneously through the same patterning process.

[0113] The second layer 42 is disposed on the surface of the first layer 41 facing away from the substrate 1. For example, the display panel of the present disclosure may further include support posts 9. The support posts 9 may be disposed on the surface of the pixel definition layer 32 facing away from the substrate 1 and do not block the openings of the pixel definition layer 32. The second layer 42 may be made of the same material as the support posts 9, so that they can be formed through one patterning process to simplify the process. Of course, if the support posts 9 and the pixel definition layer 32 are made of the same material, the support posts 9, the pixel definition layer 32, the first layer 41, and the second layer 42 can be formed simultaneously through one gray-scale mask process.

[0114] As Figures 6 - 11 shown, the drain bar 5 may be disposed on the side of the edge region 203 of the driving layer 2 facing away from the substrate 1 and extend from the edge region 203 to the peripheral circuit region 202. For example: the drain bar 5 may be disposed on the surface of the dielectric layer 25 facing away from the substrate 1 and may cover at least a partial region of the power line 28, and extend from the edge region 203 to the surface of the overlapping layer 7 facing away from the substrate 1. At the same time, the drain bar 5 is located within the range surrounded by the first barrier dam 4, and the drain bars 5 are distributed at intervals along an annular track, and can guide the organic material to flow towards the first barrier dam 4 under the action of capillary effect.

[0115] The drain bar 5 and the protective layer 8 may be made of the same material, so that the drain bar 5 can be formed simultaneously through the same patterning process to simplify the process. In addition, the drain bar 5 may also be made of the same material as the support posts 9 or the pixel definition layer 32, so that it can be formed simultaneously with the support posts 9 or the pixel definition layer 32. Of course, if the material of the protective layer 8 is the same as that of the pixel definition layer 32, the drain bar 5 can be formed simultaneously with the protective layer 8 and the pixel definition layer 32. Further, the drain bar 5 may be made of the same material as the first layer 41 of the first barrier dam 4 and formed simultaneously.

[0116] In some embodiments of the present disclosure, as Figure 6 and Figure 7 shown, the drain bar 5 is connected to the inner sidewall of the first barrier dam 4 and may be an integral structure, that is, one end of the drain bar 5 is connected to the inner sidewall of the first barrier dam 4, and the other end extends towards the pixel driving region 201. At the same time, in the direction perpendicular to the substrate 1, the thickness of the drain bar 5 is less than the thickness of the first barrier dam 4.

[0117] Furthermore, the inner sidewall of the second layer 42 of the first barrier dam 4 surrounds the inner sidewall of the first layer 41, that is, the inner sidewall of the second layer 42 of the first barrier dam 4 is located on the side of the inner sidewall of the first layer 41 away from the pixel circuit area 201, so that the second layer 42 exposes a part of the first layer 41 to form a step, and the drain bar 5 is connected to the first layer 41, which is conducive to the organic material of the encapsulation layer 6 being terminated on the inner side of the first barrier dam 4. At the same time, the drain bar 5 is made of the same material as the first layer 41, so it can be formed at the same time as the first layer 41.

[0118] Furthermore, the distance K between the inner sidewall of the second layer 42 and the inner sidewall of the first layer 41 is not less than 3 μm, so that the organic material is not easy to overflow the first blocking dam 4. In addition, the drain bar 5 can extend in a straight line toward the pixel driving area 201, and the length L of the drain bar 5 is 50 μm-500 μm, and the width D of the drain bar 5 is 5 μm-50 μm; the spacing W2 between two adjacent drain bars 5 can be 5 μm-100 μm. The width of the drain bar 5 is the distance between the two side walls of the drain bar 5; the spacing between two adjacent drain bars 5 is the width of the gap between two adjacent drain bars 5.

[0119] In other embodiments of the present disclosure, Figure 8 and Figure 9 As shown, there is a gap between the inner side wall of the first barrier dam 4 and the drain bar 5, which can prevent the organic material of the encapsulation layer 6 from overflowing the first barrier dam 4. The gap between the inner side wall of the first barrier dam 4 and the drain bar 5 is: the distance between the orthographic projection of the first layer 41 on the substrate 1 close to one end of the first barrier dam 4 and the orthographic projection of the first barrier dam 4 on the substrate 1. Further, the width W1 of the gap between the drain bar 5 and the inner side wall of the first barrier dam 4 can be 3μm-30μm.

[0120] In some further embodiments of the present disclosure, Figure 10 and Figure 11 As shown, the protective layer 8 includes a plurality of protective strips 81, and the exhaust holes 71 are distributed in the area of ​​the overlapping layer 7 covered by the protective strips 81. For example, the exhaust holes 71 can be distributed in an array, and each protective strip 81 can cover a row of exhaust holes 71. Each protective strip 81 is connected to each drain strip 5 in a one-to-one correspondence, so as to extend the path for guiding the organic material to flow toward the first blocking dam 4. Among them, the protective strip 81 and the drain strip 5 can be an integral structure with the same width, and the two can be formed simultaneously through the same patterning process, that is, the protective strip 81 can be regarded as a strip structure formed by at least part of the drain strip 5 extending toward the pixel circuit area 201, as long as it can cover each exhaust hole 71.

[0121] exist Figure 9 and Figure 10In the illustrated embodiment, there is a gap between the drain bar 5 and the inner sidewall of the first barrier dam 4. Of course, the drain bar 5 may also be connected to the inner sidewall of the first barrier dam 4.

[0122] In some embodiments of the present disclosure, as Figure 4 and Figure 12 shown, the orthographic projection of the edge region 203 on the substrate 1 is a polygon, and the edge region 203 may include a plurality of side regions 2301 and an arc region 2032. Two adjacent side regions 2031 are connected by an arc region 2032 in a transitional manner. Correspondingly, the shape of the display panel is a rectangle with four arc-shaped corners. The first barrier dam 4 connects the side regions 2031 and the arc region 2032 in series, and drain bars 5 are distributed in each of the side regions 2031 and the arc region 2032.

[0123] Within the arc region 2032, during the process of the organic material of the organic layer 62 for forming the encapsulation layer 6 flowing outward, the organic material needs to diffuse to both sides, causing the area to be filled to gradually increase outward. However, the amount of organic material does not increase compared to the side region 2031. Therefore, there will be a problem that the flow distance of the organic material in the arc region 2032 is insufficient. Thus, the width of the drain bar 5 located in the arc region 2032 can be increased in the direction away from the pixel circuit region 201, such that the drain bar 5 in the arc region 2032 is a fan-shaped structure that expands in the direction away from the pixel circuit region 201, thereby reducing the area of the region to be filled, enabling the organic material in the arc region 2032 to flow to contact the first barrier dam 4, avoiding the situation of insufficient coverage, improving the uniformity of light emission at the corners of the display panel, and reducing the process risk.

[0124] Furthermore, the sidewalls of the drain bars 5 on both sides of the gap between two adjacent drain bars 5 in the arc region 2032 are parallel, such that the orthographic projection of the gap between two adjacent drain bars 5 in the arc region 2032 on the substrate 1 is a rectangle. The distance W3 between two adjacent drain bars 5 in the arc region 2032 can be made not greater than the distance W2 between two adjacent drain bars 5 in the side region 2031, such that the region to be filled between two adjacent drain bars 5 in the arc region 2032 is not greater than the region to be filled between two adjacent drain bars 5 in the side region 2031.

[0125] In Figure 12 the illustrated embodiment, there is a gap between the drain bar 5 and the inner sidewall of the first barrier dam 4. Of course, the drain bar 5 may also be connected to the inner sidewall of the first barrier dam 4.

[0126] As Figures 6 - 12 shown, the encapsulation layer 6 includes a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63, wherein:

[0127] The first inorganic layer 61 covers the light-emitting device layer 3, the first dam 4, and the drain bar 5. The thickness of the first inorganic layer 61 is less than that of the drain bar 5, and it conforms to the first dam 4 and the drain bar 5, that is, it protrudes in the areas corresponding to the first dam 4 and the drain bar 5.

[0128] The organic layer 62 is disposed on the surface of the first inorganic layer 61 facing away from the substrate 1 and is limited within the range surrounded by the first dam 4. The organic material can be printed on the surface of the first inorganic layer 61 facing away from the substrate 1 by inkjet printing to obtain the organic layer 62. During this process, the protrusion of the first inorganic layer 61 corresponding to the drain bar 5 can generate a capillary effect, thereby guiding the organic material to flow towards the first dam 4, avoiding insufficient coverage and overflow of the organic layer 62.

[0129] The second inorganic layer 63 can cover the organic layer 62 and the first inorganic layer 61, thereby wrapping the organic layer 62 between the first inorganic layer 61 and the second inorganic layer 63. The boundaries of the orthographic projections of the first inorganic layer 61 and the second inorganic layer 63 on the substrate 1 coincide with the boundaries of the substrate 1, which can be used for water resistance. The organic layer 62 is used for flattening the interface, covering defects, and releasing stress.

[0130] As Figures 6 - 12 shown, the display panel further includes a second dam 10. The second dam 10 is disposed on the side of the edge region 203 facing away from the substrate 1. For example, it is disposed on the surface of the dielectric layer 25 facing away from the substrate 1. At the same time, the second dam 10 surrounds the first dam 4, and the first inorganic layer 61 covers the second dam 10.

[0131] In some embodiments of the present disclosure, as Figure 6 、 Figure 8 and Figure 10 shown, the second dam 10 can cover a partial area of the power line 28. For example, the second dam 10 covers the edge of the power line 28 on the side facing away from the pixel circuit region 201, can cover the burrs on the edge of the power line 28, and prevent the power line 28 from warping.

[0132] The second barrier dam 10 can be a single-layer or multi-layer structure. In some embodiments of the present disclosure, the height of the second barrier dam 10 can be greater than that of the first barrier dam 4. It can include a first layer 101, a second layer 102, and a third layer 103. Among them, the first layer 101 can be made of the same material as the flat layer 27 and can be formed by the same patterning process. The second layer 102 can be made of the same material as the pixel definition layer 32 and can be formed simultaneously by the same patterning process. The third layer 103 can be made of the same material as the support pillar 9 and can be formed simultaneously by the same patterning process. In addition, the edge of the overlap layer 7 facing away from the pixel circuit region 201 can extend between the first layer 101 and the second layer 102 to prevent the overlap layer 7 from warping, and the overlap layer 7 can protect the first layer 101 to prevent the first layer 101 from peeling off from the dielectric layer 25 during other processes after the formation of the first layer 101.

[0133] Embodiments of the present disclosure also provide a manufacturing method of a display panel. The display panel can be the display panel of any of the above embodiments, and its specific structure can refer to the embodiments of the display panel in the above text, which will not be elaborated here. As Figure 13 described, the manufacturing method can include step S110-step S160, where:

[0134] Step S110: Form a driving layer on one side of the substrate. The driving layer has a pixel circuit region, a peripheral circuit region surrounding the pixel circuit region, and an edge region surrounding the peripheral circuit region.

[0135] Step S120: Form a light-emitting device layer on the side of the pixel circuit region layer facing away from the substrate.

[0136] Step S130: Form a first barrier dam and a plurality of drainage strips on the side of the edge region facing away from the substrate. The first barrier dam is an annular structure surrounding the peripheral circuit region; the drainage strips are located within the range surrounded by the first barrier dam; the drainage strips are spaced apart from each other, and each drainage strip extends from the edge region to the peripheral circuit region.

[0137] Step S140: Form a first inorganic layer covering the light-emitting device layer, the first barrier dam, and the drainage strips, and the first inorganic layer bulges in the regions corresponding to the first barrier dam and the drainage strips.

[0138] Step S150: Form an organic layer on the surface of the first inorganic layer facing away from the substrate, and the organic layer is defined within the range surrounded by the first barrier dam.

[0139] Step S160: Form a second inorganic layer covering the organic layer and the first inorganic layer.

[0140] Details of the structures corresponding to the steps of the manufacturing method according to the embodiments of the present disclosure have been described in the embodiments of the display panel above, and will not be repeated here.

[0141] Embodiments of the present disclosure also provide a display device, which may include the display panel according to any of the above embodiments. The structure of the display panel may refer to the embodiments of the display panel above, and its specific structure and beneficial effects will not be repeated here. The display device of the present disclosure may be an electronic device with a display function such as a mobile phone, a tablet computer, a television, etc., and will not be listed one by one here.

[0142] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate; A driving layer, which is disposed on one side of the substrate and comprises a pixel circuit area, a peripheral circuit area surrounding the pixel circuit area, and an edge area surrounding the peripheral circuit area; The pixel circuit area has a pixel circuit, the peripheral circuit area has a peripheral circuit, and the peripheral circuit includes a gate drive circuit; A light emitting device layer is provided on a side of the pixel circuit region away from the substrate; A first blocking dam is provided on a side of the edge region away from the substrate, the first blocking dam being an annular structure surrounding the peripheral circuit region; A plurality of drain bars are provided on a side of the edge region away from the substrate and within a range surrounded by the first blocking dam; the drain bars are spaced apart and each of the drain bars extends from the edge region to the peripheral circuit region; and a spacing between two adjacent drain bars is 5 μm-100 μm; an encapsulation layer, comprising a first inorganic layer, an organic layer and a second inorganic layer, wherein the first inorganic layer covers the light-emitting device layer, the first barrier dam and the drain bar, and is raised in a region corresponding to the first barrier dam and the drain bar; The organic layer is disposed on a surface of the first inorganic layer facing away from the substrate and is confined within a range surrounded by the first blocking dam; The second inorganic layer covers the organic layer and the first inorganic layer; The driving layer includes: An active layer, disposed on one side of the substrate and located in the pixel circuit area and the peripheral circuit area; a first gate insulating layer, covering the active layer and located in the pixel circuit area, the peripheral circuit area and the edge area; A gate layer, provided on a surface of the first gate insulating layer away from the substrate, and located in the pixel circuit area and the peripheral circuit area; a second gate insulating layer, covering the gate layer and the first gate insulating layer, and located in the pixel circuit area, the peripheral circuit area and the edge area; a dielectric layer, covering the second gate insulating layer and located in the pixel circuit area, the peripheral circuit area and the edge area; A source-drain layer, disposed on a surface of the dielectric layer away from the substrate, and located in the pixel circuit area and the peripheral circuit area; A planar layer, covering the source / drain layer and the dielectric layer, and located in the pixel circuit area and the peripheral circuit area; A power line is provided on the surface of the dielectric layer away from the substrate and located in the edge area, and the material and thickness of the power line are the same as those of the source and drain layer; The first barrier dam and the drain strip at least cover a portion of the power line; The light emitting device layer comprises: A first electrode layer is provided on a surface of the planar layer away from the substrate and located in the pixel circuit area, the first electrode layer comprising a plurality of first electrodes distributed in an array; a pixel definition layer, covering the first electrode layer and the planar layer, and exposing each of the first electrodes; a light-emitting functional layer, at least covering a surface of the first electrode facing away from the substrate; A second electrode layer, covering the light-emitting functional layer; The display panel further includes: The overlapping layer is disposed on the surface of the flat layer facing away from the substrate, extends to the surface of the power line facing away from the substrate, and a plurality of exhaust holes distributed in an array are provided in the area of the overlapping layer corresponding to the flat layer; The protective layer is disposed on the surface of the overlapping layer facing away from the substrate, covers the exhaust holes, and exposes a partial area of the overlapping layer; The drainage strip is located on the side of the protective layer facing away from the pixel circuit region and covers a partial area of the overlapping layer corresponding to the power line; The second electrode layer extends to the surface of the protective layer facing away from the substrate in the edge region and is connected to the overlapping layer.

2. The display panel according to claim 1, characterized in that, The drainage strip is connected to the inner sidewall of the first dam; in the direction perpendicular to the substrate, the thickness of the drainage strip is less than the thickness of the first dam.

3. The display panel according to claim 2, characterized in that, The first dam includes a first layer and a second layer stacked in sequence in the direction away from the substrate, and the inner sidewall of the second layer surrounds the inner sidewall of the first layer; the drainage strip is connected to the first layer and has the same material.

4. The display panel according to claim 1, characterized in that, There is a gap between the inner sidewall of the first dam and the drainage strip.

5. The display panel according to claim 1, characterized in that, The orthographic projection of the edge region on the substrate is a polygon and includes a plurality of side regions and arc regions, and two adjacent side regions are transitionally connected through one arc region; The width of the drainage strip located in the arc region increases in the direction away from the pixel circuit region.

6. The display panel according to claim 1, wherein The overlapping layer and the first electrode layer have the same material and thickness; the protective layer and the drainage strip have the same material and thickness.

7. The display panel according to claim 6, wherein The protective layer includes a plurality of protection strips, and the exhaust holes are distributed in the area of the overlapping layer covered by the protection strips; each protection strip is correspondingly butted with each drainage strip.

8. The display panel according to claim 1, wherein The display panel further includes: Support pillars are disposed on the surface of the pixel definition layer facing away from the substrate; One of the support pillars and the pixel definition layer has the same material as the drainage strip.

9. The display panel according to claim 1, wherein The display panel further includes: A second dam is disposed on the side of the edge region facing away from the substrate and is disposed around the first dam, and the first inorganic layer covers the second dam.

10. The display panel according to claim 3, wherein The distance between the inner sidewall of the second layer and the inner sidewall of the first layer is not less than 3 μm.

11. The display panel according to claim 4, wherein The width of the gap between the drainage strip and the inner sidewall of the first dam is 3 μm - 30 μm.

12. The display panel according to claim 1, wherein The length of the drainage strip is 50 μm - 500 μm, and the width of the drainage strip is 5 μm - 50 μm.

13. The display panel according to claim 1, wherein Each drainage strip is distributed at intervals along an annular track.

14. A display device, wherein Including the display panel according to any one of claims 1 - 13.

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