Display devices

Abstract

A display device includes: a panel comprising pixels, each pixel comprising: an LED; a capacitor between a first voltage line and a node; a first transistor between the first voltage line and a first electrode of the LED; a second transistor between a data line and the source of the first transistor; a third transistor between a node and the drain of the first transistor; a fourth transistor between a node and a second voltage line; a fifth transistor between the first voltage line and the source of the first transistor; a sixth transistor between the first electrode of the LED and the drain of the first transistor; and a seventh transistor between a second voltage line and the first electrode of the LED. The third and fourth transistors each include: an active region comprising a metal oxide; a first gate and a second gate above the active region; and a pattern below the active region.

Description

Technical Field

[0001] This invention relates to a display device. More specifically, this invention relates to a display device having two types of transistors. Background Art

[0002] A display device is an output device used to present information in a visual form. A display device includes multiple pixels and driving circuitry for controlling the pixels. The driving circuitry includes, for example, scan driving circuitry and data driving circuitry. Each pixel includes a display element and pixel driving circuitry for controlling the display element. The pixel driving circuitry includes multiple transistors.

[0003] The scan drive circuit and / or data drive circuit are formed using the same process as the pixel. Therefore, the drive circuit also includes multiple transistors. Summary of the Invention

[0004] An exemplary embodiment of the present invention provides a display device, comprising: a display panel including a plurality of pixels, wherein a first pixel includes: a light-emitting diode; a capacitor connected between a first voltage line and a reference node; a first transistor connected between the first voltage line and a first electrode of the light-emitting diode; a second transistor connected between a data line and the source of the first transistor; a third transistor connected between the reference node and the drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line; a fifth transistor connected between the first voltage line and the source of the first transistor; a sixth transistor connected between the first electrode of the light-emitting diode and the drain of the first transistor; and a seventh transistor connected between the second voltage line and the first electrode of the light-emitting diode, each of the third and fourth transistors including: an active region comprising a metal oxide; a first gate and a second gate disposed on a first side of the active region and overlapping the active region; and a pattern disposed on a second side of the active region and overlapping the active region.

[0005] Each of the first, second, fifth, and sixth transistors is a P-type transistor, and each of the third and fourth transistors is an N-type transistor.

[0006] The active region of each of the first, second, fifth, and sixth transistors comprises polysilicon.

[0007] The source of the first transistor extends from the active region of the first transistor.

[0008] The patterns of each of the third and fourth transistors include metal.

[0009] The pattern of each of the third and fourth transistors comprises polycrystalline silicon.

[0010] The pattern of each of the third and fourth transistors includes a conductive material, and the source of the third transistor is electrically connected to the pattern of the third transistor or the source of the fourth transistor is electrically connected to the pattern of the fourth transistor.

[0011] The pattern of each of the third and fourth transistors includes a conductive material, and the first gate and the second gate of the third transistor are electrically connected to the pattern of the third transistor or the first gate and the second gate of the fourth transistor are electrically connected to the pattern of the fourth transistor.

[0012] The display device further includes: a semiconductor pattern disposed below the pattern of each of the third and fourth transistors and overlapping the active region of the third transistor.

[0013] The active region of the first transistor includes polysilicon, and a semiconductor pattern extends from the active region of the first transistor.

[0014] The seventh transistor includes: an active region comprising a metal oxide; a gate disposed on a first side of the active region of the seventh transistor and overlapping the active region of the seventh transistor; and a pattern disposed on a second side of the active region of the seventh transistor and overlapping the active region of the seventh transistor.

[0015] Each of the first, second, fifth, and sixth transistors is a P-type transistor, and each of the third, fourth, and seventh transistors is an N-type transistor.

[0016] The patterns of the second voltage line, as well as each of the third and fourth transistors, are set on the same layer and comprise the same material.

[0017] An exemplary embodiment of the present invention provides a display device comprising: a display panel including pixels, each pixel including: a light-emitting diode (LED); a capacitor connected between a first voltage line and a reference node; a first transistor connected between the first voltage line and a first electrode of the LED; a second transistor connected between a data line and the source of the first transistor; a third transistor connected between the reference node and the drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line; a fifth transistor connected between the first voltage line and the source of the first transistor; a sixth transistor connected between the first electrode of the LED and the drain of the first transistor; and a seventh transistor connected between the second voltage line and the first electrode of the LED, each of the third and fourth transistors including: an active region comprising a metal oxide; a gate disposed above the active region; and a first pattern comprising polysilicon disposed below the active region and overlapping the active region when viewed in a plan view, wherein the first pattern of the fourth transistor extends from the first pattern of the third transistor.

[0018] The first pattern of the third transistor extends from the active region of the first transistor.

[0019] The active region of the fourth transistor extends from the active region of the third transistor.

[0020] Each of the third and fourth transistors further includes a second pattern disposed between its active region and its first pattern.

[0021] The second voltage line and the second pattern are placed on the same layer and include the same metal.

[0022] When viewed in a planar diagram, the second pattern of the third transistor at least overlaps with the first pattern of the third transistor.

[0023] Each of the first, second, fifth, and sixth transistors is a P-type transistor, and each of the third and fourth transistors is an N-type transistor.

[0024] An exemplary embodiment of the present invention provides a display device comprising: a display panel including pixels, each pixel including: a light-emitting diode (LED); a capacitor connected between a first voltage line receiving a first power supply voltage and a reference node; a first transistor connected between the first voltage line and a first electrode of the LED; a second transistor connected between a data line and the source of the first transistor; a third transistor connected between the reference node and the drain of the first transistor; a fourth transistor connected between the reference node and a second voltage line receiving an initialization voltage; a fifth transistor connected between the first voltage line and the source of the first transistor; a sixth transistor connected between the first electrode of the LED and the drain of the first transistor; and a seventh transistor connected between the second voltage line and the first electrode of the LED, each of the third and fourth transistors including: an active layer comprising a metal oxide; a gate disposed above the active layer; and a pattern disposed below the active layer and overlapping the active layer when viewed in a plan view; the first transistor including: an active layer comprising polysilicon; and a gate disposed above the active layer of the first transistor, wherein the active layer of the first transistor is configured to be lower than the active layers of each of the third and fourth transistors. Attached Figure Description

[0025] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the invention with reference to the accompanying drawings, in which:

[0026] Figure 1 This is a block diagram illustrating an exemplary display device according to a concept of the present invention;

[0027] Figure 2 This is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the concept of the present invention;

[0028] Figure 3 This shows the drive. Figure 2 The waveform diagram of the driving signal of the pixel shown;

[0029] Figure 4A and Figure 4B This is a cross-sectional view showing a display panel corresponding to pixels of an exemplary embodiment of the present invention;

[0030] Figure 5A This is a plan view illustrating an exemplary embodiment of a third transistor according to a concept of the present invention;

[0031] Figure 5B , Figure 5C and Figure 5D It is along Figure 5A The line I-I' in the diagram is shown. Figure 5A A cross-sectional view of the third transistor shown;

[0032] Figure 6A This is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the concept of the present invention;

[0033] Figure 6B This is a cross-sectional view illustrating an exemplary embodiment of the fourth transistor according to the concept of the present invention;

[0034] Figure 7A This is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the concept of the present invention;

[0035] Figure 7B This is a cross-sectional view illustrating an exemplary embodiment of the fourth transistor according to the concept of the present invention;

[0036] Figure 8A This is an equivalent circuit diagram illustrating a pixel according to an exemplary embodiment of the concept of the present invention;

[0037] Figure 8B This is a cross-sectional view illustrating an exemplary embodiment of the seventh transistor according to the concept of the present invention;

[0038] Figure 9 This is a plan view illustrating pixels according to an exemplary embodiment of the concept according to the present invention;

[0039] Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 10G , Figure 10H , Figure 10I , Figure 10J and Figure 10K It is a plan view illustrating the stacking order of pixel patterns according to an exemplary embodiment of the present invention; and

[0040] Figure 11 This is a cross-sectional view showing a display panel corresponding to the first and third transistors according to an exemplary embodiment of the present invention. Detailed Implementation

[0041] In this specification, it will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, the element or layer may be directly on or directly connected to or coupled to the other element or layer, or there may be an intermediate element or layer.

[0042] Throughout the accompanying drawings, the same reference numerals may refer to the same elements. For clarity, the thickness of layers, films, and regions may be enlarged in the drawings.

[0043] The singular forms “one” and “the” used in this article are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0044] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0045] Figure 1 This is a block diagram illustrating a display device DD according to an exemplary embodiment of the present invention. The display device DD includes a timing controller TC, a scan drive circuit SDC, a data drive circuit DDC, and a display panel DP. In this exemplary embodiment, the display panel DP will be described as a light-emitting display panel. The light-emitting display panel may include an organic light-emitting display panel or a quantum dot light-emitting display panel.

[0046] The timing controller TC receives the input image signal, converts the data format of the input image signal into a data format suitable for the interface between the timing controller TC and the data drive circuit DDC, and generates image data D-RGB. The timing controller TC outputs the image data D-RGB as well as various control signals DCS and SCS.

[0047] The scan driver circuit SDC receives the scan control signal SCS from the timing controller TC. The scan control signal SCS includes a vertical start signal to initiate the operation of the scan driver circuit SDC and a clock signal to determine the output timing of the signals output from the scan driver circuit SDC. The scan driver circuit SDC generates multiple scan signals and outputs them sequentially to the corresponding signal lines SL1 to SLn and GL1 to GLn. Additionally, in response to the scan control signal SCS, the scan driver circuit SDC generates multiple light emission control signals and outputs them to the corresponding signal lines EL1 to ELn.

[0048] exist Figure 1 In this embodiment, the scan signal and the light emission control signal are output from a single scan driver circuit SDC; however, the present invention is not limited thereto. For example, multiple scan driver circuits can generate and output the scan signal after dividing the scan signal, and can generate and output the light emission control signal after dividing the light emission control signal. Furthermore, in an exemplary embodiment of the present invention, the scan driver circuit that generates and outputs the scan signal can be provided separately from the scan driver circuit that generates and outputs the light emission control signal.

[0049] The data drive circuit (DDC) receives the data control signal (DCS) and image data (D-RGB) from the timing controller (TC). The DDC converts the D-RGB image data into a data signal and outputs it to multiple data lines DL1 to DLm. The data signal is an analog voltage corresponding to the grayscale value of the D-RGB image data.

[0050] The light-emitting display panel DP includes a first group of scan lines SL1 to SLn, a second group of scan lines GL1 to GLn, a third group of scan lines HL1 to HLn, light-emitting lines EL1 to ELn, data lines DL1 to DLm, a first voltage line PL, a second voltage line RL, and multiple pixels PX. The first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the light-emitting lines EL1 to ELn extend along a first direction DR1 and are arranged along a second direction DR2.

[0051] Data lines DL1 to DLm are insulated from the first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the light-emitting lines EL1 to ELn, while also intersecting with these lines. Each pixel PX is connected to a corresponding signal line in the signal lines. The connection relationship between pixels PX and signal lines can be changed according to the configuration of the pixel driving circuit of the pixel PX.

[0052] The first voltage line PL receives the first power supply voltage ELVDD. The second voltage line RL receives the initialization voltage Vint. The initialization voltage Vint has a lower level than the first power supply voltage ELVDD. The display panel DP receives the second power supply voltage ELVSS. The second power supply voltage ELVSS has a lower level than the first power supply voltage ELVDD.

[0053] In the above description, refer to Figure 1 The display device DD according to this embodiment has been described; however, the display device DD is not limited thereto. For example, signal lines may be added or omitted depending on the configuration of the pixel driving circuit. Furthermore, the connection relationship between a pixel PX and the signal lines may be changed.

[0054] A pixel PX may include multiple groups that produce light of different colors from each other. For example, a pixel PX may include red pixels for producing red light, green pixels for producing green light, and blue pixels for producing blue light. The light-emitting diodes (LEDs) of the red pixels, the green pixels, and the blue pixels may include light-emitting layers comprising different materials from each other.

[0055] The pixel driving circuit may include multiple transistors and capacitors electrically connected to the transistors. At least one of the scan driving circuit SDC and the data driving circuit DDC may include multiple transistors formed using the same process as the pixel driving circuit.

[0056] The aforementioned signal lines, pixels (PX), scan drive circuit (SDC), and data drive circuit (DDC) can be formed on the substrate through multiple photolithography processes. Multiple insulating layers can be formed on the substrate through multiple deposition or coating processes. The insulating layers can be thin layers corresponding to the pixels (PX), and a portion of the insulating layer can include an insulating pattern that overlaps only with a specific conductive pattern. The insulating layers can include organic layers and / or inorganic layers.

[0057] Figure 2 This is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the concept of the present invention. Figure 3 This shows the drive. Figure 2 The waveform diagram of the driving signal for pixel PXij is shown.

[0058] As a representative example Figure 2 The pixel PXij is shown as being connected to the i-th scan line SLi in the first group of scan lines SL1 to SLn and to the j-th data line DLj in the data lines DL1 to DLm.

[0059] In this exemplary embodiment, the pixel driving circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a capacitor Cst. In this exemplary embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors, and the third transistor T3 and the fourth transistor T4 are N-type transistors. However, the first to seventh transistors T1 to T7 are not limited to this, and the first to seventh transistors T1 to T7 may be implemented as either P-type transistors or N-type transistors. Furthermore, in this exemplary embodiment, at least one of the first to seventh transistors T1 to T7 may be omitted.

[0060] In this exemplary embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. A capacitor Cst is connected between a first voltage line PL that receives the first power supply voltage ELVDD and a reference node RD. The capacitor Cst includes a first electrode Cst1 connected to the reference node RD and a second electrode Cst2 connected to the first voltage line PL.

[0061] A first transistor T1 is connected between a first voltage line PL and a first electrode (e.g., anode) of a light-emitting diode (OLED). The source S1 of the first transistor T1 is electrically connected to the first voltage line PL. In the following description, the phrase "transistor electrically connected to a signal line" may mean that the source, drain, or gate of the transistor is integrally provided with the signal line or connected to the signal line via a connecting electrode. Alternatively, the phrase "transistor electrically connected to another transistor" may mean that the source, drain, or gate of one transistor is integrally provided with the source, drain, or gate of another transistor, or connected to the source, drain, or gate of another transistor via a connecting electrode. Another transistor may be provided or omitted between the source S1 of the first transistor T1 and the first voltage line PL.

[0062] The drain D1 of the first transistor T1 is electrically connected to the anode of the light-emitting diode (OLED). Another transistor can be placed between the drain D1 of the first transistor T1 and the anode of the OLED, or this can be omitted. The gate G1 of the first transistor T1 is electrically connected to the reference node RD.

[0063] The second transistor T2 is connected between the j-th data line DLj and the source S1 of the first transistor T1. The source S2 of the second transistor T2 is electrically connected to the j-th data line DLj, and the drain D2 of the second transistor T2 is electrically connected to the source S1 of the first transistor T1. In this exemplary embodiment, the gate G2 of the second transistor T2 may be electrically connected to the i-th scan line SLi in the first group.

[0064] A third transistor T3 is connected between a reference node RD and the drain D1 of a first transistor T1. The drain D3 of the third transistor T3 is electrically connected to the drain D1 of the first transistor T1, and the source S3 of the third transistor T3 is electrically connected to the reference node RD. The third transistor T3 may include a plurality of gates G3. In this exemplary embodiment, the two gates G3-1 and G3-2 of the third transistor T3 may be electrically connected to the i-th scan line GLi in the second group. In another exemplary embodiment of the inventive concept, the third transistor T3 may include a single gate.

[0065] A fourth transistor T4 is connected between the reference node RD and the second voltage line RL. The drain D4 of the fourth transistor T4 is electrically connected to the reference node RD, and the source S4 of the fourth transistor T4 is electrically connected to the second voltage line RL. The fourth transistor T4 may include a plurality of gates G4. In another exemplary embodiment of the present invention, the fourth transistor T4 may include a single gate.

[0066] In this exemplary embodiment, the two gates G4-1 and G4-2 of the fourth transistor T4 can be electrically connected to the i-th scan line HLi in the third group. Since the third transistor T3 and the fourth transistor T4 include multiple gates, the leakage current of pixel PXij can be reduced.

[0067] The fifth transistor T5 is connected between the first voltage line PL and the source S1 of the first transistor T1. The source S5 of the fifth transistor T5 is electrically connected to the first voltage line PL, and the drain D5 of the fifth transistor T5 is electrically connected to the source S1 of the first transistor T1. The gate G5 of the fifth transistor T5 can be electrically connected to the i-th light-emitting line ELi.

[0068] A sixth transistor T6 is connected between the drain D1 of the first transistor T1 and the light-emitting diode OLED. The source S6 of the sixth transistor T6 is electrically connected to the drain D1 of the first transistor T1, and the drain D6 of the sixth transistor T6 is electrically connected to the anode of the light-emitting diode OLED. The gate G6 of the sixth transistor T6 can be electrically connected to the i-th light-emitting line ELi. In an exemplary embodiment of the present invention, the gate G6 of the sixth transistor T6 can be connected to a signal line different from the signal line to which the gate G5 of the fifth transistor T5 is connected.

[0069] The seventh transistor T7 is connected between the drain D6 of the sixth transistor T6 and the second voltage line RL. The source S7 of the seventh transistor T7 is electrically connected to the drain D6 of the sixth transistor T6, and the drain D7 of the seventh transistor T7 is electrically connected to the second voltage line RL. The gate G7 of the seventh transistor T7 can be electrically connected to the (i+1)th scan line SLi+1 in the first group.

[0070] Reference Figure 2 and Figure 3 A more detailed description of the operation of pixel PXij. Display device DD (reference) Figure 1 The image is displayed for each frame period. During each frame period, the signal lines of each of the following groups are scanned sequentially: the first group of scan lines SL1 to SLn, the second group of scan lines GL1 to GLn, the third group of scan lines HL1 to HLn, and the light emission lines EL1 to ELn. Figure 3 This shows a portion of a frame period.

[0071] refer to Figure 3 Each of the signals Ei, GIi, GWPi, GWNi, and GWPi+1 can have a high level V-HIGH for a portion of the time period and a low level V-LOW for another portion of the time period. When the corresponding signal has a high level V-HIGH, the N-type transistor is turned on, and when the corresponding signal has a low level V-LOW, the P-type transistor is turned on.

[0072] When the light-emitting control signal Ei has a high level V-HIGH, the fifth transistor T5 and the sixth transistor T6 are turned off. When the fifth transistor T5 and the sixth transistor T6 are turned off, no current path is formed between the first voltage line PL and the light-emitting diode OLED. Therefore, the period during which no current path is formed can be a non-light-emitting period.

[0073] When the first scan signal GIi applied to the i-th scan line HLi in the third group has a high level V-HIGH, the fourth transistor T4 is turned on. When the fourth transistor T4 is turned on, the reference node RD is initialized by the initialization voltage Vint.

[0074] When the second scan signal GWPi applied to the i-th scan line SLi in the first group has a low level V-LOW and the third scan signal GWNi applied to the i-th scan line GLi in the second group has a high level V-HIGH, the second transistor T2 and the third transistor T3 are turned on.

[0075] Since the reference node RD is initialized to the initialization voltage Vint, the first transistor T1 is in the on state. When the first transistor T1 is on, it is in the same state as the data signal Dj (reference). Figure 2 The voltage corresponding to the data signal Dj is applied to the reference node RD. In this case, the capacitor Cst is charged with the voltage corresponding to the data signal Dj.

[0076] When the fourth scan signal GWPi+1 applied to the (i+1)th scan line SL1+1 in the first group has a low level V-LOW, the seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the anode of the light-emitting diode (OLED) is initialized to the initialization voltage Vint. The parasitic capacitance of the OLED can then be discharged.

[0077] When the light emission control signal Ei is at a low level (V-LOW), the fifth transistor T5 and the sixth transistor T6 are turned on. When the fifth transistor T5 is turned on, the first power supply voltage ELVDD is applied to the first transistor T1. When the sixth transistor T6 is turned on, the first transistor T1 and the light-emitting diode (OLED) are electrically connected to each other. The OLED produces light with a brightness corresponding to the amount of current applied to it.

[0078] Figure 4A and Figure 4B This is a cross-sectional view of a display panel DP corresponding to pixels of an exemplary embodiment of the present invention. Figure 4A and Figure 4B It shows the relationship with Figure 2 The cross-sections of the portions corresponding to the first transistor T1 and the third transistor T3 shown in the figure.

[0079] refer to Figure 4A and Figure 4B The display panel DP may include a substrate layer BL, a circuit element layer DP-CL disposed on the substrate layer BL on a third-direction DR3, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. The display panel DP may further include functional layers, such as an anti-reflective layer and a refractive index control layer. The circuit element layer DP-CL includes at least circuit elements and multiple insulating layers. In the following, the insulating layers may include organic layers and / or inorganic layers.

[0080] An insulating layer, a semiconductor layer, and a conductive layer are formed through coating and deposition processes. Then, the insulating layer, semiconductor layer, and conductive layer are selectively patterned using a photolithography process. At least one of the semiconductor pattern, the conductive pattern, and the signal line is formed using the above method.

[0081] The substrate layer BL may include a synthetic resin film. The synthetic resin film may include a thermosetting resin. Specifically, the synthetic resin film (or synthetic resin layer) may be a polyimide resin layer, but is not limited thereto. The synthetic resin layer may include at least one of acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and dinaphthalene-based resins. Furthermore, the substrate layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0082] At least one inorganic layer is formed on the upper surface of the substrate layer BL. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Multiple inorganic layers may be provided. The inorganic layer may form a barrier layer BRL and / or a buffer layer BFL. The barrier layer BRL and the buffer layer BFL may be selectively disposed. For example, the barrier layer BRL may be disposed between the buffer layer BFL and the substrate layer BL.

[0083] A barrier layer (BRL) prevents foreign objects from entering from the outside. The BRL may include a silicon oxide layer and a silicon nitride layer. Multiple copies of each of the silicon oxide and silicon nitride layers may be provided, and the silicon oxide and silicon nitride layers may be stacked alternately on top of each other.

[0084] A buffer layer (BFL) can be disposed on the barrier layer (BRL). The buffer layer (BFL) can increase the coupling force between the substrate layer (BL) and the semiconductor pattern and / or conductive pattern. The buffer layer (BFL) may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer can be stacked alternately on top of each other.

[0085] A semiconductor pattern is disposed on a buffer layer BFL. The semiconductor pattern directly disposed on the buffer layer BFL can be a first semiconductor pattern. The first semiconductor pattern can include silicon semiconductors. The first semiconductor pattern can include polycrystalline silicon, but is not limited thereto. The first semiconductor pattern can include amorphous silicon.

[0086] Figure 4A and Figure 4B Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern can be further set in pixel PXij (reference). Figure 2 In another region of the semiconductor pattern, the first semiconductor pattern may have different electrical properties depending on whether it is doped. The first semiconductor pattern may include doped and undoped regions. In other words, the first semiconductor pattern may include a first region and a second region. The doped regions may be doped with N-type or P-type dopant. A P-type transistor includes a doped region doped with P-type dopant. An N-type transistor includes a doped region doped with N-type dopant.

[0087] The doped region has a higher conductivity than the undoped region and is used as an electrode or signal line. The undoped region corresponds to the active region (or channel) of the transistor. In other words, a first portion of the first semiconductor pattern can be the active region of the transistor, a second portion of the first semiconductor pattern can be the source or drain of the transistor, and a third portion of the first semiconductor pattern can be a connecting signal line (or connecting electrode).

[0088] like Figure 4A and Figure 4B As shown, the source S1, active region A1, and drain D1 of the first transistor T1 are formed by a first semiconductor pattern. The source S1 and drain D1 of the first transistor T1 extend from the active region A1 in directions opposite to each other.

[0089] Figure 4A and Figure 4B A portion of the connection signal line SCL, formed by a semiconductor pattern, is shown. When viewed in a planar view, the connection signal line SCL can be connected to the drain D6 of the sixth transistor T6 (reference). Figure 2 ).

[0090] The first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is commonly grounded with each pixel PX (reference). Figure 1The first insulating layer 10 overlaps and covers the first semiconductor pattern. The first insulating layer 10 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In this exemplary embodiment, the first insulating layer 10 may be a silicon oxide layer with a single-layer structure. The insulating layer of the circuit element layer DP-CL, described later, may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure as well as the first insulating layer 10. The inorganic layer may include at least one of the materials described above.

[0091] The gate G1 of the first transistor T1 is disposed on the first insulating layer 10. The gate G1 may be part of a metal pattern. The gate G1 of the first transistor T1 overlaps with the active region A1 of the first transistor T1. In the doping process of the first semiconductor pattern, the gate G1 of the first transistor T1 is used as a mask.

[0092] A second insulating layer 20 is disposed on the first insulating layer 10 to cover the gate G1. The second insulating layer 20 is commonly grounded with each pixel PX (reference). Figure 1 The second insulating layer 20 may include an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In this exemplary embodiment, the second insulating layer 20 may be a silicon oxide layer with a single-layer structure.

[0093] The upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G1. The upper electrode UE can be part of a metal pattern or a doped semiconductor pattern. A portion of the gate G1 and the upper electrode UE overlapping this portion of the gate G1 can be a capacitor Cst (refer to...). Figure 2 In an exemplary embodiment of the present invention, the upper electrode UE may be omitted.

[0094] In an exemplary embodiment of the present invention, the second insulating layer 20 may be replaced by an insulating pattern. An upper electrode UE is disposed on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0095] The first electrode Cst1 and the second electrode Cst2 of capacitor Cst (reference) Figure 2 The first electrode Cst1 can be formed with the gate G1 and the upper electrode UE using the same process. The first electrode Cst1 can be disposed on the first insulating layer 10. The first electrode Cst1 can be electrically connected to the gate G1. The first electrode Cst1 can be provided integrally with the gate G1.

[0096] The second electrode Cst2 can be disposed on the second insulating layer 20. The second electrode Cst2 can be electrically connected to the upper electrode UE. The second electrode Cst2 can be provided integrally with the upper electrode UE.

[0097] A third insulating layer 30 is disposed on the second insulating layer 20 to cover the upper electrode UE. In this exemplary embodiment, the third insulating layer 30 may be a silicon oxide layer with a single-layer structure. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 (see reference) Figure 2 The source electrodes S2, S5, S6, and S7 (reference) Figure 2 ), drains D2, D5, D6 and D7 (reference) Figure 2 ) and gates G2, G5, G6 and G7 (reference) Figure 2 They can be formed with the source S1, drain D1 and gate G1 of the first transistor T1 through the same process.

[0098] A semiconductor pattern is disposed on the third insulating layer 30. Hereinafter, the semiconductor pattern directly disposed on the third insulating layer 30 is referred to as the "second semiconductor pattern". The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include crystalline oxide semiconductors or amorphous oxide semiconductors. For example, the oxide semiconductor may include metal oxides of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or mixtures of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), or zinc tin oxide (ZTO).

[0099] Figure 4A and Figure 4B Only a portion of the second semiconductor pattern is shown, and the second semiconductor pattern can be further set in pixel PXij (reference). Figure 2 In another region of the second semiconductor pattern. The second semiconductor pattern may include multiple regions that are distinguished from each other based on whether the metal oxide is reduced. The regions where the metal oxide is reduced (hereinafter referred to as "reduced regions") have a higher conductivity than the regions where the metal oxide is not reduced (hereinafter referred to as "unreduced regions"). The reduced regions serve as electrodes or signal lines. The unreduced regions correspond to the active regions (or channels) of the transistor. In other words, a first portion of the second semiconductor pattern may be the active region of the transistor, a second portion of the second semiconductor pattern may be the source or drain of the transistor, and a third portion of the second semiconductor pattern may be a connection electrode or a connection signal line.

[0100] like Figure 4A and Figure 4BAs shown, the source S3, active region A3, and drain D3 of the third transistor T3 are formed from a second semiconductor pattern. The source S3 and drain D3 of the third transistor T3 comprise metal reduced from a metal-oxide-semiconductor. The source S3 and drain D3 may comprise a metal layer having a predetermined thickness from the upper surface of the second semiconductor pattern and comprising the reduced metal.

[0101] A fourth insulating layer 40 is disposed on the third insulating layer 30 to cover the second semiconductor pattern. In this exemplary embodiment, the fourth insulating layer 40 may be a silicon oxide layer with a monolayer structure. The gate G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The gate G3 may be part of a metal pattern. The gate G3 of the third transistor T3 overlaps with the active region A3 of the third transistor T3.

[0102] In an exemplary embodiment of the present invention, the fourth insulating layer 40 can be replaced by an insulating pattern. The gate G3 of the third transistor T3 is disposed on the insulating pattern. In this exemplary embodiment, when viewed in a plan view, the gate G3 may have a shape substantially the same as the insulating pattern. In this exemplary embodiment, for ease of explanation, only one gate G3 is shown; however, the third transistor T3 may include, for example, Figure 2 The two gates G3-1 and G3-2 are shown in the figure.

[0103] A fifth insulating layer 50 is disposed on the fourth insulating layer 40 to cover the gate G3. In this exemplary embodiment, the fifth insulating layer 50 may include a silicon oxide layer and a silicon nitride layer. The fifth insulating layer 50 may include a silicon oxide layer and silicon nitride layers stacked alternately with the silicon oxide layer.

[0104] Fourth transistor T4 (reference) Figure 2 The source S4 (reference) Figure 2 ), Drain D4 (reference) Figure 2 ) and gate G4 (reference) Figure 2 They can be formed together with the source S3, drain D3 and gate G3 of the third transistor T3 through the same process.

[0105] At least one insulating layer is further disposed on the fifth insulating layer 50. In this exemplary embodiment, a sixth insulating layer 60 and a seventh insulating layer 70 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 and the seventh insulating layer 70 may be organic layers and may have a single-layer or multi-layer structure. The sixth insulating layer 60 and the seventh insulating layer 70 may be polyimide resin layers with a single-layer structure, but they are not limited thereto. The sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyamide resins, and dinaphthalene-containing resins.

[0106] like Figure 4A As shown, the first connection electrode CNE1 can be disposed on the sixth insulating layer 60. The first connection electrode CNE1 can be connected to the connection signal line SCL (or connection electrode) through the first contact hole CH1 passing through the first to sixth insulating layers 10 to 60. The light-emitting diode OLED is disposed on the seventh insulating layer 70. The anode AE ​​of the light-emitting diode OLED is disposed on the seventh insulating layer 70. The pixel defining layer PDL is disposed on the seventh insulating layer 70. The anode AE ​​is connected to the first connection electrode CNE1 through the contact hole CH-70 passing through the seventh insulating layer 70.

[0107] exist Figure 4A In this configuration, the first connection electrode CNE1 is directly connected to the connection signal line SCL, but this is not the only possibility. (See reference...) Figure 4B The first connection electrode CNE10 can be disposed on the fifth insulating layer 50. The first connection electrode CNE10 can be connected to the connection signal line SCL through a first contact hole CH1 passing through the first to fifth insulating layers 10 to 50, and the second connection electrode CNE20 can be connected to the first connection electrode CNE10 through a contact hole CH-60 passing through the sixth insulating layer 60. In an exemplary embodiment of the present invention, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 can be omitted.

[0108] At least a portion of the anode AE ​​is exposed through an opening OP in the pixel-defining layer PDL. The opening OP in the pixel-defining layer PDL can define a light-emitting region PXA. For example, pixel PX (reference) Figure 1 ) can be regularly arranged on the display panel DP (reference) Figure 1 On a plane, the area where pixels PX are arranged can be called a pixel region, and a pixel region can include a light-emitting region PXA and a non-light-emitting region NPXA adjacent to the light-emitting region PXA. The non-light-emitting region NPXA can surround the light-emitting region PXA.

[0109] A hole control layer (HCL) can be commonly disposed in the emitting region PXA and the non-emitting region NPXA. Common layers such as the hole control layer HCL can be commonly formed in each pixel PX. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer.

[0110] The emissive layer EML can be set on the hole control layer HCL. The emissive layer EML can be set in the region corresponding to the opening OP. The emissive layer EML can be formed in each of the individual pixels PX after being divided into multiple parts.

[0111] In this exemplary embodiment, a patterned emissive layer EML is shown as a representative example; however, the emissive layer EML can be commonly disposed in each pixel PX. In this case, the emissive layer EML can generate white light or blue light. Furthermore, the emissive layer EML can have a multi-layer structure.

[0112] An electronic control layer (ECL) can be disposed on the light-emitting layer (EML). The ECL may include an electron transport layer and an electron injection layer. A cathode (CE) can be disposed on the ECL. The ECL and CE can be commonly disposed in each pixel (PX).

[0113] A thin-film encapsulation layer (TFE) is disposed on the cathode (CE). The TFE is commonly disposed in each pixel (PX). In this exemplary embodiment, the TFE directly covers the cathode (CE). In an exemplary embodiment of the present invention, a capping layer directly covering the cathode (CE) may be further provided. In an exemplary embodiment of the present invention, the stacked structure of the light-emitting diode (OLED) may have the same characteristics as... Figure 4A and Figure 4B The structure shown is a comparison with a vertically inverted (e.g., flipped upside down) structure.

[0114] The thin-film encapsulation layer (TFE) comprises at least an inorganic layer or an organic layer. In an exemplary embodiment of the present invention, the thin-film encapsulation layer (TFE) may include two inorganic layers and an organic layer disposed between the two inorganic layers. In an exemplary embodiment of the present invention, the thin-film encapsulation layer (TFE) may include a plurality of inorganic layers and a plurality of organic layers stacked alternately with the inorganic layers.

[0115] The inorganic layer of the thin-film encapsulation layer (TFE) protects the OLED from moisture and oxygen, while the organic layer protects it from foreign matter such as dust particles. The inorganic layer of the TFE can include, but is not limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer of the TFE can include, but is not limited to, an acrylic organic layer.

[0116] Figure 5A This is a plan view illustrating a third transistor T3 according to an exemplary embodiment of the concept of the present invention. Figures 5B to 5D It is along Figure 5A The line I-I' in the diagram is shown. Figure 5A The cross-sectional view of the third transistor T3 shown is illustrated below. (Referring to the reference...) Figures 1 to 4B Detailed descriptions of the same components as those described can be omitted.

[0117] refer to Figures 5A to 5D The third transistor T3 may further include a patterned LSP. The patterned LSP may comprise a material with high absorbance or high reflectivity. The patterned LSP is positioned below the second semiconductor pattern SCP2 to block light incident from the outside onto the second semiconductor pattern SCP2 (specifically, the active region A3 of the third transistor T3). In other words, the patterned LSP can be a light-blocking pattern. For example, the patterned LSP can prevent external light from altering the voltage-current characteristics of the active region A3 of the third transistor T3 and prevent leakage current.

[0118] refer to Figure 5A The source S3, active region A3, and drain D3 of the third transistor T3 correspond to different portions of the second semiconductor pattern SCP2. The gate G3 of the third transistor T3 corresponds to a portion of the i-th scan line GLi in the second group.

[0119] like Figure 5B As shown, a patterned LSP can be disposed on the buffer layer BFL. The patterned LSP may include the source S1 and drain D1 of the first transistor T1 (reference). Figure 4A The same material. Patterned LSPs include metals.

[0120] Pattern LSP and source S1 and drain D1 of the first transistor T1 (reference) Figure 4A The patterned LSP can be formed from a first semiconductor pattern. For example, the patterned LSP can include doped polysilicon. In other words, the patterned LSP can be a semiconductor pattern different from the active region A3 of the third transistor T3. The patterned LSP includes at least polysilicon.

[0121] like Figure 5A and Figure 5BAs shown, the third transistor T3 may include a first gate G3-1 and a second gate G3-2, as well as a first active region A3-1 and a second active region A3-2 corresponding to the first gate G3-1 and the second gate G3-2, respectively. For example, the first gate G3-1 may overlap with the first active region A3-1, and the second gate G3-2 may overlap with the second active region A3-2. The region between the first active region A3-1 and the second active region A3-2 corresponds to the drain / source DS3 of the second semiconductor pattern SCP2. Figure 5A In the diagram, the drain / source DS3 is shown as having an elliptical shape, but is not limited thereto. Figure 5A and Figure 5B The third transistor T3 shown has a circuit configuration in which two of the transistors are connected in series in an equivalent circuit.

[0122] like Figure 5C As shown, a patterned LSP can be disposed on the first insulating layer 10. The patterned LSP may include the gate G1 of the first transistor T1 (reference). Figure 4A The same material. For example... Figure 5D As shown, a patterned LSP can be disposed on the second insulating layer 20. The patterned LSP may comprise the same material as the upper electrode UE. For example, the second voltage line RL (reference) Figure 2 Some signal lines can be placed on the same layer as the upper electrode UE.

[0123] exist Figures 5A to 5D In this design, the patterned LSP can correspond to a floating electrode. The patterned LSP is electrically isolated and not electrically connected to other electrodes or other signal lines. However, the inventive concept is not limited thereto. For example, the patterned LSP can be electrically connected to the gate or source of a corresponding transistor.

[0124] Figure 6A This is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the concept of the present invention. Figure 6B This is a cross-sectional view showing a fourth transistor T4 according to an exemplary embodiment of the present invention. Figure 7A This is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the concept of the present invention. Figure 7B This is a cross-sectional view illustrating a fourth transistor T4 according to an exemplary embodiment of the concept according to the present invention. In the following, it will be referred to as a reference. Figures 1 to 5B Detailed descriptions of the same components as those described can be omitted.

[0125] refer to Figure 6A and Figure 6BThe patterned LSP may include a conductive material, and the source S4 of the fourth transistor T4 may be electrically connected to the patterned LSP. In this case, the patterned LSP may correspond to a gate disposed below the fourth transistor T4. When an initialization voltage Vint is applied to the lower gate (e.g., the patterned LSP), the fourth transistor T4 has the same voltage-current characteristics as a dual-gate transistor in which a bias voltage is applied to its lower gate. The fourth transistor T4 corresponds to a single-channel transistor that turns on in response to a voltage applied to the upper gate. The voltage-current characteristics of the fourth transistor T4 can be controlled by adjusting the level of the initialization voltage Vint.

[0126] The source S4 of the fourth transistor T4 and the patterned LSP can be connected to each other via the connecting electrode CNE. The connecting electrode CNE is disposed on the sixth insulating layer 60, connected to the source S4 of the fourth transistor T4 through the contact hole CH100 passing through the fourth to sixth insulating layers 40 to 60, and connected to the patterned LSP through the contact hole CH200 passing through the first to sixth insulating layers 10 to 60.

[0127] The cross-sectional structure of the third transistor T3 can correspond to the cross-sectional structure of the fourth transistor T4. The gate G3 of the third transistor T3 can be disposed on the same layer as the gate G4 of the fourth transistor T4, and the source S3 and drain D3 of the third transistor T3 can be disposed on the same layer as the source S4 and drain D4 of the fourth transistor T4. The patterned LSP of the third transistor T3 can be disposed on the same layer as the patterned LSP of the fourth transistor T4.

[0128] In this exemplary embodiment, the patterned LSP is applied to each of the third transistor T3 and the fourth transistor T4, but it is not limited thereto. For example, the patterned LSP may be applied to only one transistor.

[0129] exist Figure 6A and Figure 6B In the diagram, DS4 can correspond to the drain / source of the fourth transistor T4, G4-1 and G4-2 can correspond to the first gate and the second gate of the fourth transistor T4, and A3-1 and A3-2 can correspond to the first active region and the second active region of the fourth transistor T4.

[0130] refer to Figure 7A and Figure 7BThe patterned LSP may include a conductive material, and at least one of the gates G3 of the third transistor T3 and G4 of the fourth transistor T4 may be electrically connected to the corresponding patterned LSP. In this case, the patterned LSP may correspond to the gates disposed below the third transistor T3 and the fourth transistor T4. When the first scan signal GIi is applied to the lower gate of the fourth transistor T4, and the third scan signal GWNi is applied to the lower gate of the third transistor T3, dual channels may be formed in the third transistor T3 and the fourth transistor T4, which are in the on state. The third transistor T3 and the fourth transistor T4 may each correspond to two transistors.

[0131] Figure 7B A cross-section of the fourth transistor T4 is shown as a representative example. The gate G4 of the fourth transistor T4 and the patterned LSP can be connected to each other via a connection electrode CNE. The connection electrode CNE is disposed on the sixth insulating layer 60, connected to the gates G4-1 and G4-2 of the fourth transistor T4 through contact holes CH101 passing through the fifth insulating layer 50 and the sixth insulating layer 60, and connected to the patterned LSP through contact holes CH200 passing through the first to sixth insulating layers 10 to 60. Figure 7B In this configuration, multiple contact holes CH101 are provided. Figure 7B In the diagram, contact hole CH101 overlaps with the first active region A4-1 and the second active region A4-2; however, this is merely exemplary. When viewed in a plan view, contact hole CH101 may not overlap with the first active region A4-1 and the second active region A4-2.

[0132] Figure 8A This is an equivalent circuit diagram illustrating a pixel PXij according to an exemplary embodiment of the concept of the present invention. Figure 8B This is a cross-sectional view illustrating a seventh transistor T7 according to an exemplary embodiment of the concept according to the present invention. In the following, it is referred to as... Figures 1 to 7B Detailed descriptions of the same components as those described can be omitted.

[0133] like Figure 8A and Figure 8B As shown, the seventh transistor T7 can be an N-type transistor. The active region A7 of the seventh transistor T7 can include a metal-oxide-semiconductor (MODS). The seventh transistor T7 can include two gates G7-1 and G7-2. Additionally, the seventh transistor T7 can include two active regions A7-1 and A7-2 corresponding to the two gates G7-1 and G7-2 respectively, and a drain / source DS7. The seventh transistor T7 can include a patterned LSP.

[0134] Figure 8B Showing with Figure 5BThe seventh transistor T7 has the same structure as the third transistor T3 shown, however, the structure of the seventh transistor T7 is not limited to this. The seventh transistor T7 can be modified to have... Figure 5C and Figure 5D The structure of the third transistor T3 shown or Figures 6A to 7B The structure of the fourth transistor T4 is shown in the figure.

[0135] Reference Figures 5A to 8B In the embodiments of the described inventive concept, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 include active regions of metal-oxide-semiconductor (MOS) semiconductors, but they are not limited thereto. Some of the first to seventh transistors T1 to T7 may include active regions of MOS semiconductors, while the other transistors may include active regions of polysilicon. Among the first to seventh transistors T1 to T7, the transistor having an active region of MOS semiconductor may include a reference... Figures 5A to 7B The pattern LSP is described.

[0136] Figure 9 This is a plan view illustrating a pixel PXij according to an exemplary embodiment of the concept according to the present invention. Figures 10A to 10K This is a plan view illustrating the stacking order of the patterns of pixels PXij according to an exemplary embodiment of the present invention. In the following, with reference to... Figures 1 to 8B Detailed descriptions of the same components as those described can be omitted.

[0137] Figure 9 Showing has Figure 2 A planar diagram of pixel PXij in the equivalent circuit. (Reference) Figure 9 The first to seventh transistors T1 to T7 of pixel PXij are shown. Additionally, the i-th scan line SLi in the first group, the (i+1)-th scan line SLi+1 in the first group, the i-th scan line GLi in the second group, the i-th scan line HLi in the third group, and the i-th light-emitting line ELi are shown. Figure 2 The equivalent circuits are different; each of the third transistor T3 and the fourth transistor T4 includes a gate, such as G3 and G4.

[0138] refer to Figure 10A The first semiconductor pattern SCP1 is disposed on the substrate layer BL (reference). Figure 4A The first semiconductor pattern SCP1 may include multiple regions with different doping concentrations. The first semiconductor pattern SCP1 may include a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7 (see reference). Figure 9The first semiconductor pattern SCP1 may include source electrodes S1, S2, S5, S6 and S7, active regions A1, A2, A5, A6 and A7, and drain electrodes D1, D2, D5, D6 and D7. The first semiconductor pattern SCP1 may include connection signal lines SCL.

[0139] The first semiconductor pattern SCP1 can be a portion of transistor patterns LSP-3P and LSP-4P. The first portion of the first semiconductor pattern SCP1 can be the LSP-3P pattern of the third transistor T3, and the second portion of the first semiconductor pattern SCP1 can be the LSP-4P pattern of the fourth transistor T4. The first and second portions corresponding to patterns LSP-3P and LSP-4P can be... Figure 10D The patterns LSP-3 and LSP-4 shown overlap. Figure 10A The patterns LSP-3P and LSP-4P and Figure 10D The patterns LSP-3 and LSP-4 correspond to a double pattern.

[0140] The pattern LSP-3P of the third transistor T3 and the pattern LSP-4P of the fourth transistor T4 have larger areas than the active regions A2, A5, A6 and A7 of the transistors T2, T5, T6 and T7 other than the first transistor T1. Figure 10A The reason why patterns LSP-3P and LSP-4P have such areas is to make them cover Figure 10D The patterns shown are LSP-3 and LSP-4, and Figure 10F The active regions A3 and A4 of the third transistor T3 and the fourth transistor T4 are shown in the diagram. This is because the areas of the active regions A3 and A4 of the third transistor T3 and the fourth transistor T4 are larger than the areas of the active regions A2, A5, A6 and A7 of the second transistor A2, the fifth transistor A5, the sixth transistor A6 and the seventh transistor A7.

[0141] Refer again Figure 10A A pattern LSP-4P or LSP-3P can extend from another pattern LSP-3P or LSP-4P. Pattern LSP-3P extends from the active region A1 of the first transistor T1. In this exemplary embodiment, the first semiconductor pattern SCP1 corresponding to pixel PXij has an integral shape, but is not limited thereto. Patterns LSP-4P and LSP-3P can be separated from each other, and pattern LSP-3P can be separated from the active region A1 of the first transistor T1.

[0142] Figure 10B A plan view of a first semiconductor pattern SCP1 is shown, illustrating another exemplary embodiment of the concept according to the present invention. Figure 10B As shown, with Figure 10AThe portions corresponding to patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1 can be omitted.

[0143] Figure 10C Showing based on Figure 10A The pattern. (Reference) Figure 10C The first metallic pattern MP1 is disposed in the first insulating layer 10 (reference). Figure 4A The first metal pattern MP1 may include the gate G1 of the first transistor T1, the i-th scan line SLi in the first group, the (i+1)-th scan line SLi+1 in the first group, and the i-th light-emitting line ELi. A portion of the i-th scan line SLi in the first group may be the gate G2 of the second transistor T2, and a portion of the (i+1)-th scan line SLi+1 in the first group may be the gate G7 of the seventh transistor T7. A portion of the i-th light-emitting line ELi may be the gate G5 of the fifth transistor T5, and another portion of the i-th light-emitting line ELi may be the gate G6 of the sixth transistor T6.

[0144] refer to Figure 10D The second metallic pattern MP2 is disposed on the second insulating layer 20 (reference). Figure 4A The second metal pattern MP2 may include an upper electrode UE, a second voltage line RL, and dummy lines DL-H and DL-G. The upper electrode UE, the second voltage line RL, and the dummy lines DL-H and DL-G may include the same metal and the same layer structure. The upper electrode UE may be provided with an opening UE-OP passing through it.

[0145] The first dummy line DL-H overlaps with the i-th scan line HLi in the third group, which will be described later. The second dummy line DL-G overlaps with the i-th scan line GLi in the second group, which will be described later. A portion of the first dummy line DL-H may be the pattern LSP-4 of the fourth transistor T4, and a portion of the second dummy line DL-G may be the pattern LSP-3 of the third transistor T3.

[0146] Figure 10D The patterns LSP-3 and LSP-4 shown overlap with patterns LSP-3P and LSP-4P to form a reference. Figure 10AThe double pattern is described. In the case of forming a double pattern, the areas of patterns LSP-3 and LSP-4 of the second metal pattern MP2 can be adjusted. The areas of patterns LSP-3 and LSP-4 of the second metal pattern MP2 can be smaller than the areas of patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1. The regions of patterns LSP-3 and LSP-4 of the second metal pattern MP2 can at least overlap with the patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1. Patterns LSP-3 and LSP-4 of the second metal pattern MP2 can have widths corresponding to the width of the line portion DL-HL to reduce the parasitic capacitance between patterns LSP-3 and LSP-4 of the second metal pattern MP2 and patterns LSP-3P and LSP-4P of the first semiconductor pattern SCP1. In an exemplary embodiment of the inventive concept, dummy lines DL-H and DL-G can be omitted, and only patterns LSP-3 and LSP-4 of the second metal pattern MP2 can be provided. In an exemplary embodiment of the inventive concept, Figure 10A The patterns LSP-3P and LSP-4P shown can be omitted, and can be provided Figure 10D The patterns shown are LSP-3 and LSP-4 or Figure 10D The dummy lines DL-H and DL-G are shown in the diagram.

[0147] In an exemplary embodiment of the present invention, the dummy lines DL-H and DL-G can be omitted. This structure is shown in... Figure 10E In this case, the portion of the first semiconductor pattern SCP1 corresponding to patterns LSP-3P and LSP-4P can be the light-blocking patterns of the third transistor T3 and the fourth transistor T4.

[0148] refer to Figure 10F The second semiconductor pattern SCP2 is disposed in the third insulating layer 30 (reference). Figure 4A The second semiconductor pattern SCP2 may include regions that are distinct from each other based on whether the metal oxide is reduced. The second semiconductor pattern SCP2 may include a third transistor T3 and a fourth transistor T4 (see reference). Figure 9 The fourth transistor T4 has sources S3 and S4, active regions A3 and A4, and drains D3 and D4. The active region A4 of the fourth transistor T4 extends from the active region A3 of the third transistor T3. The second semiconductor pattern SCP2 includes a connection signal line SCL.

[0149] A connection signal line SCL extends from the source S3 of the third transistor T3 and / or the drain D4 of the fourth transistor T4. The connection signal line SCL is connected to the gate G1 of the first transistor T1 through contact hole CH10. (Reference) Figure 4A , Figure 4B , Figure 5A and Figure 5B The contact hole CH10 passes through the second insulating layer 20 and the third insulating layer 30.

[0150] refer to Figure 10A and Figure 10F The drain D3 of the third transistor T3 is connected to the connection signal line SCL of the first semiconductor pattern SCP1 through contact hole CH20. (Reference) Figure 10A and Figure 10F The drain D3 of the third transistor T3 is connected to the source S6 of the sixth transistor T6. (Reference) Figure 10D and Figure 10F The source S4 of the fourth transistor T4 is connected to the second voltage line RL through the contact hole CH30. The connection signal line SCL extending from the source S4 of the fourth transistor T4 can overlap with the contact hole CH30.

[0151] refer to Figure 10G The third metallic pattern MP3 is set in the fourth insulating layer 40 (reference). Figure 4A The third metal pattern MP3 may include the i-th scan line GLi in the second group and the i-th scan line HLi in the third group. A portion of the i-th scan line GLi in the second group may be the gate G3 of the third transistor T3, and a portion of the i-th scan line HLi in the third group may be the gate G4 of the fourth transistor T4.

[0152] refer to Figure 10H The fourth metal pattern MP4 is set in the sixth insulating layer 60 (reference). Figure 4A The fourth metal pattern MP4 may include a first connecting electrode CNE1, a second connecting electrode CNE2, a data line DLj, and a first voltage line PL. Figure 10H This shows a portion of the data line DLj and a portion of the first voltage line PL. (Reference) Figure 10A and Figure 10H The first connection electrode CNE1 is connected to the connection signal line SCL through the contact hole CH1. The first connection electrode CNE1 can be... Figure 4A The first connection electrode is CNE1. The second connection electrode CNE2 connects the drain D7 of the seventh transistor T7 to the second voltage line RL through contact holes CH2 and CH3. The data line DLj is connected to the source S2 of the second transistor T2 through contact hole CH4. The first voltage line PL is connected to the source S5 of the fifth transistor T5 through contact hole CH5.

[0153] in addition, Figure 10HThe diagram illustrates a structure where one pixel overlaps with a data line DLj; however, the inventive concept is not limited thereto. For example, a pixel may overlap with two data lines. One data line may connect to pixels arranged in a pixel row, while the other data line may connect to pixels arranged in a pixel row adjacent to the pixel row. The pixel row may be an odd-numbered pixel row or an even-numbered pixel row.

[0154] Figures 10I to 10K A plan view of pixel PXij is shown, illustrating another exemplary embodiment of the concept according to the present invention, the plan view being consistent with... Figures 10A to 10H The planar diagram of pixel PXij shown is different. Figure 10I Corresponding to Figure 10F . refer to Figure 10I ,and Figure 10F Unlike other semiconductor patterns, contact holes CH10, CH20, and CH30 are not formed. In other words, the second semiconductor pattern SCP2 can be non-directly connected to... Figures 10A to 10E The first semiconductor pattern SCP1, the first metal pattern MP1, or the second metal pattern MP2 shown are illustrated. Additionally, refer to... Figure 10I ,and Figure 10F Unlike other transistors, the connection signal line SCL, which overlaps with the first transistor T1, is omitted.

[0155] According to this exemplary embodiment, with Figures 10A to 10H The pixels PXij shown are different, and the fourth metal pattern MP4 and the fifth metal pattern MP5 are set on the third metal pattern MP3. Figure 10J The fourth metal pattern MP4 is shown, while Figure 10K The fifth metal pattern, MP5, is shown.

[0156] refer to Figure 10J ,refer to Figure 10G The described third metal pattern MP3 is additionally provided. The third metal pattern MP3 may include the i-th scan line GLi in the second group, the i-th scan line HLi in the third group, and the (i+1)-th scan line HLi+1 in the third group.

[0157] refer to Figure 10JThe third connecting electrode CNE3, fourth connecting electrode CNE4, fifth connecting electrode CNE5, sixth connecting electrode CNE6, and seventh connecting electrode CNE7, formed by the fourth metal pattern MP4, and the connecting electrodes CNE3 to CNE7 are shown connected to the second contact hole CH2, third contact hole CH3, fourth contact hole CH4, fifth contact hole CH5, sixth contact hole CH6, seventh contact hole CH7, eighth contact hole CH8, and ninth contact hole CH9 through which the connecting electrodes CNE3 to CNE7 are connected to the first semiconductor pattern SCP1, the first metal pattern MP1, or the second metal pattern MP2. The third connecting electrode CNE3 connects the second voltage line RL to the seventh transistor T7 through the third contact hole CH3 and the fourth contact hole CH4. The fourth connecting electrode CNE4 connects the third transistor T3 to the sixth transistor T6 through the fifth contact hole CH5 and the sixth contact hole CH6. The fifth connecting electrode CNE5 connects the third transistor T3 to the first transistor T1 and the fourth transistor T4 to the first transistor T1 through the seventh contact hole CH7 and the eighth contact hole CH8. The sixth connecting electrode CNE6 connects to the second transistor T2 through the ninth contact hole CH9. The seventh connection electrode CNE7 is connected to the fifth transistor T5 through the second contact hole CH2. The first connection electrode CNE10 is electrically connected to the sixth transistor T6 through the first contact hole CH1.

[0158] refer to Figure 10K The connection electrode CNE20, data lines DLj-E and DLj-O, and the first voltage line PL, formed by the fifth metal pattern MP5, are shown. Additionally, the connection electrode CNE20, data lines DLj-E and DLj-O, and the first voltage line PL are shown connected to the contact holes CH-60, CH40, and CH50 of the fourth metal pattern MP4 via contact hole CH-60. Connection electrode CNE20 is connected to connection electrode CNE10 via contact hole CH-60. The first voltage line PL is connected to the seventh connection electrode CNE7 via contact hole CH40, and is also electrically connected to the fifth transistor T5. Data line DLj-O is connected to the sixth connection electrode CNE6 via contact hole CH50, and is also electrically connected to the second transistor T2. Two data lines DLj-E and DLj-O overlap with a pixel; however, one data line DLj-O is connected to a pixel, and the other data line DLj-E is connected to a pixel adjacent to that pixel. When one data line DLj-O is connected to the odd-numbered pixel rows, the other data line DLj-E is connected to the even-numbered pixel rows.

[0159] Figure 11 This is a cross-sectional view showing a display panel corresponding to the first transistor T1 and the third transistor T3 according to an exemplary embodiment of the present invention. In the following, with reference to... Figures 1 to 10K Detailed descriptions of the same components as those described can be omitted.

[0160] Figure 11 A third transistor T3 with two gates G3-1 and G3-2 is shown. Furthermore, the third transistor T3 has a dual-pattern structure. The first pattern LSP-3P extends from the active region A1 of the first transistor T1. The second pattern LSP-3 is disposed on the same layer as the upper electrode UE.

[0161] refer to Figure 10D The areas of the first pattern LSP-3P and the second pattern LSP-3 on the plane can be compared with each other. The second pattern LSP-3 has a smaller area than the first pattern LSP-3P and is disposed inside the first pattern LSP-3P. The second pattern LSP-3 at least overlaps with the first pattern LSP-3P.

[0162] According to embodiments of the inventive concept described above, the display device includes two types of transistors, and therefore, the pixel leakage current can be reduced, and the response speed of the light-emitting diode can be improved. The pixel leakage current can be reduced using transistors comprising metal-oxide-semiconductor (MODS), and the response speed of the light-emitting diode can be improved using transistors comprising polysilicon (PSS). The pixel leakage current can also be reduced using transistors comprising multiple gates.

[0163] A pattern formed beneath the metal-oxide-semiconductor (MOS) blocks external light from reaching the MOS. Therefore, the current-voltage characteristics of the MOS are prevented from shifting due to external light. The pattern can be used as another gate. The characteristics of a transistor incorporating the MOS can be controlled based on the voltage applied to the pattern.

[0164] Although the concept of the invention has been described with reference to exemplary embodiments thereof, it should be understood that various changes and modifications may be made thereto by those skilled in the art without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels, wherein the first pixel of the pixels includes: Light-emitting diode; A capacitor is connected between the first voltage line and the reference node; A first transistor is connected between the first voltage line and the first electrode of the light-emitting diode. The first transistor includes a gate and a first semiconductor pattern. The first semiconductor pattern includes an active region, a source, and a drain. The second transistor is connected between the data line and the source of the first transistor; A third transistor is connected between the reference node and the drain of the first transistor; A fourth transistor is connected between the reference node and the second voltage line; A fifth transistor is connected between the first voltage line and the source of the first transistor; A sixth transistor is connected between the first electrode of the light-emitting diode and the drain of the first transistor; and A seventh transistor is connected between the second voltage line and the first electrode of the light-emitting diode, and each of the third and fourth transistors includes: Active regions include metal oxides; A first gate and a second gate are disposed on a first side of the active region and overlap with the active region; and A pattern is disposed on the second side of the active region and overlaps with the active region. The pattern of the third transistor and the pattern of the first semiconductor are disposed on the same layer, the pattern of the third transistor and the pattern of the first semiconductor have an integral shape in a planar view, and the pattern of the third transistor and the pattern of the first semiconductor include silicon semiconductor.

2. The display device according to claim 1, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is an N-type transistor.

3. The display device according to claim 1, wherein, The active region of the first transistor comprises polysilicon.

4. The display device of claim 3, wherein the source of the first transistor extends from the active region of the first transistor.

5. The display device according to claim 1, wherein the second transistor includes a second semiconductor pattern, the second semiconductor pattern including an active region, a source, and a drain.

6. The display device according to claim 5, wherein the first semiconductor pattern and the second semiconductor pattern are disposed on the same layer, and the first semiconductor pattern and the second semiconductor pattern have an integral shape in a plan view.

7. The display device of claim 1, wherein each of the third transistor and the fourth transistor further comprises another pattern, the other pattern comprising a conductive material.

8. The display device according to claim 1, wherein, The pattern of the third transistor and the source of the first semiconductor pattern have the same material.

9. The display device according to claim 1, wherein, The pattern of the third transistor and the first semiconductor pattern comprise polycrystalline silicon.

10. The display device of claim 1, wherein the seventh transistor comprises: Active regions include metal oxides; The gate is disposed on the first side of the active region of the seventh transistor and overlaps with the active region of the seventh transistor; as well as A pattern is disposed on the second side of the active region of the seventh transistor and overlaps with the active region of the seventh transistor.

11. The display device according to claim 10, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor, the fourth transistor, and the seventh transistor is an N-type transistor.

12. The display device according to claim 1, wherein, The pattern of the third transistor extends from the pattern of the fourth transistor.

13. A display device, comprising: A display panel, comprising pixels, wherein the pixels include; Light-emitting diode; A capacitor is connected between the first voltage line and the reference node; The first transistor is connected between the first voltage line and the first electrode of the light-emitting diode; The second transistor is connected between the data line and the source of the first transistor; A third transistor is connected between the reference node and the drain of the first transistor; A fourth transistor is connected between the reference node and the second voltage line; A fifth transistor is connected between the first voltage line and the source of the first transistor; A sixth transistor is connected between the first electrode of the light-emitting diode and the drain of the first transistor; as well as A seventh transistor is connected between the second voltage line and the first electrode of the light-emitting diode, and each of the third and fourth transistors includes: Active regions include metal oxides; A gate is disposed above the active region; and A first pattern, comprising polysilicon, is disposed below the active region and overlaps with the active region when viewed in a plan view, wherein the first pattern of the fourth transistor extends from the first pattern of the third transistor.

14. The display device of claim 13, wherein the first pattern of the third transistor extends from the active region of the first transistor.

15. The display device of claim 13, wherein the active region of the fourth transistor extends from the active region of the third transistor.

16. The display device according to claim 13, wherein, Each of the third transistor and the fourth transistor further includes a second pattern disposed between its active region and its first pattern.

17. The display device according to claim 16, wherein, The second voltage line and the second pattern are disposed on the same layer and comprise the same metal.

18. The display device according to claim 16, wherein, When viewed in the plan view, the second pattern of the third transistor at least overlaps with the first pattern of the third transistor.

19. The display device according to claim 13, wherein, Each of the first transistor, the second transistor, the fifth transistor, and the sixth transistor is a P-type transistor, and each of the third transistor and the fourth transistor is an N-type transistor.

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