Display device

Abstract

A display device is provided. The display device includes: a substrate including a display area having multiple pixel areas and a non-display area surrounding at least one side of the display area; a light-blocking layer disposed on a first surface of the substrate and including a light-transmitting area to allow incident light to pass through the light-transmitting area; a circuit element layer disposed on the light-blocking layer and including multiple conductive layers; a light-emitting element layer disposed on the circuit element layer and including a light-emitting element; and a sensor layer disposed on a second surface of the substrate opposite the first surface to sense light passing through the light-transmitting area. The light-blocking layer is electrically coupled to at least one of the multiple conductive layers.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0068940, filed on Jun. 11, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention relate generally to a display device, and more particularly, to a display device including a photosensor for detecting light. Background Art

[0003] Recently, with the use of display devices (such as smartphones or tablet PCs) in various fields, schemes for authenticating biometric information using a user's fingerprint, etc. have become widely used. In order to provide a fingerprint sensing function, a fingerprint sensor may be provided in a form in which the fingerprint sensor is included in the display device or attached to the display device.

[0004] The fingerprint sensor can be implemented as a light-sensing type, for example. A light-sensing fingerprint sensor may include a light source, a lens, and a photosensor array. To transmit light reflected from the fingerprint to the photosensor array, light-transmitting holes may be formed extensively across a wide area in the circuit element layer of the display panel. Furthermore, when such a fingerprint sensor is attached to a display panel, the thickness of the display device and its manufacturing cost may increase.

[0005] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute the prior art. Summary of the Invention

[0006] The applicant has discovered that when light-transmitting holes are formed extensively across a wide area in the circuit element layer of a display panel with an integrated fingerprint sensor, the load acting on the lines formed on the circuit element layer (e.g., scan lines, data lines, etc.) may increase. This increase in load may increase the power consumption of the display device. In addition, when light-transmitting holes are formed extensively across a wide area in the circuit element layer, crosstalk with the elements (e.g., transistors) of the corresponding pixels occurs, thereby degrading the quality of the display panel.

[0007] A display device constructed in accordance with the principles and exemplary embodiments of the invention can sense light and / or fingerprints with improved accuracy and / or efficiency. For example, a display device can include a conductive photoresist layer electrically coupled to a component in a pixel so that power applied to the component in the pixel can be transferred to the photoresist layer, which can cause the light-emitting element in the pixel to receive an increased and / or desired amount of current. As a result, the light-emitting element can emit an increased and / or desired amount of light, and the photosensor of the display device can effectively sense light reflected by an object such as a fingerprint.

[0008] According to other aspects and exemplary embodiments of the invention, fingerprint sensing capability may be improved by assigning a function of selectively blocking light of a specific wavelength to an insulating layer or the like included in a display device.

[0009] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0010] According to one aspect of the invention, a display device includes: a substrate including a display area having multiple pixel areas and a non-display area surrounding at least one side of the display area; a light-blocking layer disposed on a first surface of the substrate and including a light-transmitting area to allow incident light to pass through the light-transmitting area; a circuit element layer disposed on the light-blocking layer and including multiple conductive layers; a light-emitting element layer disposed on the circuit element layer and including a light-emitting element; and a sensor layer disposed on a second surface of the substrate opposite to the first surface to sense light passing through the light-transmitting area, wherein the light-blocking layer is electrically coupled to at least one of the multiple conductive layers.

[0011] The light blocking layer may be configured to receive power through at least one of the plurality of conductive layers.

[0012] The plurality of conductive layers may include power lines extending in one direction and configured to receive power.

[0013] The light blocking layer may be electrically coupled to the power line through at least one contact hole in the non-display area.

[0014] The light blocking layer may include at least one extending portion in the non-display area, the at least one extending portion extending from at least a portion of a periphery of the light blocking layer toward a circumference of the substrate and disposed adjacent to the electric force line.

[0015] The at least one extension portion may be electrically coupled to the power line through the at least one contact hole in the non-display area.

[0016] The multiple conductive layers may further include a connector placed between at least one extension and the power line, the at least one extension may be electrically coupled to the connector through at least one first contact hole, and the connector may be electrically coupled to the power line through at least one second contact hole, and the connector may include a bridging pattern.

[0017] The at least one extension portion may include a protrusion pattern configured to protrude from the at least one extension portion toward the power line to overlap the power line, and the protrusion pattern may be electrically coupled to the power line through the at least one contact hole.

[0018] The power line may include a protrusion pattern configured to protrude toward the at least one extension portion of the light blocking layer to overlap the at least one extension portion, and the protrusion pattern may be electrically coupled to the at least one extension portion through the at least one contact hole.

[0019] The non-display area may include: a pad area including a pad for coupling to an external controller; a bending area adjacent to the pad area and bendable about a bending axis; and a wiring area positioned between the bending area and the display area, and wherein the plurality of conductive layers include a plurality of lines located in the wiring area, and the plurality of lines and power lines extend from the pad to the display area.

[0020] The at least one extension portion may be electrically coupled to the power line through the at least one contact hole in the wiring region.

[0021] In the wiring region, the power line may have a width greater than that of the plurality of lines.

[0022] The non-display area may further include a dummy area adjacent to the display area, the display area being disposed between the dummy area and the wiring area, and the at least one extension may be disposed in at least one of the wiring area and the dummy area.

[0023] The light blocking layer may be electrically coupled to the power line through the contact hole in the display area.

[0024] The multiple conductive layers may include in the display area: a semiconductor layer including an active pattern forming at least one transistor; a first gate layer including a gate electrode overlapping the active pattern; a second gate layer including at least one capacitor electrode; and a source / drain layer including a power line and a conductive line coupled to the active pattern.

[0025] The contact hole may include a first contact hole and a second contact hole, and the second gate layer may further include a connector electrically coupled to the light blocking layer through the first contact hole and electrically coupled to the power line through the second contact hole.

[0026] The connection member may be a bridge pattern including a first region extending parallel to the power line and a second region extending from a first end of the first region in a direction perpendicular to the first region.

[0027] The first region may overlap the power line and be electrically coupled to the light blocking layer through the first contact hole and electrically coupled to the power line through the second contact hole.

[0028] The plurality of conductive layers may include light-transmitting holes overlapping the light-transmitting regions.

[0029] The light-transmitting region may include a pinhole.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept. The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0032] Figures 1A to 1C is a schematic plan view of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0033] Figure 2 is a plan view of an exemplary embodiment of a light blocking layer constructed according to the principles of the invention.

[0034] Figures 3A to 3D is a plan view of an exemplary embodiment of an array structure of pixels, pinholes, and photosensors constructed according to the principles of the invention.

[0035] Figure 4 is a cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0036] Figure 5 is a cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention.

[0037] Figures 6 to 9 are cross-sectional views of further exemplary embodiments of display devices constructed according to the principles of the invention.

[0038] Figure 10A yes Figure 1B An enlarged plan view of an exemplary embodiment of portion EA1 is shown.

[0039] Figure 10B It is along Figure 10A A cross-sectional view taken along line II'.

[0040] Figure 11A yes Figure 1B FIG. 1 is an enlarged plan view of another exemplary embodiment of portion EA1 .

[0041] Figure 11B It is along Figure 11A A sectional view taken along line II-II'.

[0042] Figure 12A yes Figure 1B FIG. 1 is an enlarged plan view of yet another exemplary embodiment of portion EA1 .

[0043] Figure 12B It is along Figure 12AA cross-sectional view taken along line III-III'.

[0044] 13A to 13D This is a graph for explaining changes in characteristics of transistors in the circuit element layer due to voltage applied to the light-blocking layer.

[0045] Figure 14 is a circuit diagram of an exemplary embodiment of a representative pixel constructed according to the principles of the invention.

[0046] Figure 15 is included Figure 14 1 is a plan view of an exemplary embodiment of a layout of pixels and a light blocking layer constructed according to the principles of the invention.

[0047] Figure 16 It is along Figure 15 A sectional view taken along line IV-IV'.

[0048] Figure 17 is included Figure 14 1 is a plan view of another exemplary embodiment of a layout of pixels and a light-blocking layer constructed according to the principles of the invention.

[0049] Figure 18 It is along Figure 17 A cross-sectional view taken along line V-V'. DETAILED DESCRIPTION

[0050] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various exemplary embodiments or implementations of the invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of devices or methods that employ one or more of the inventive concepts disclosed herein. However, it is apparent that the various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, in order to avoid making the various exemplary embodiments unnecessarily vague, well-known structures and devices are shown in block diagram form. In addition, the various exemplary embodiments may be different, but do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0051] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise indicated, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as "elements" or "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0052] The use of cross hatching and / or shading is generally provided in the accompanying drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or demand for the specific material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two continuously described processes can be performed substantially simultaneously or in an order opposite to the described order. In addition, the same reference numerals represent the same elements.

[0053] When an element or layer is referred to as being "on" another element or layer, "connected to" or "bound to" another element or layer, the element or layer may be directly on, directly connected to or directly bound to the other element or layer, or there may be an intermediate element or intermediate layer. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly bound to" another element or layer, there are no intermediate elements or intermediate layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without intermediate elements. In addition, the D1 axis, the D2 axis and the D3 axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, the y-axis and the z-axis) and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0054] Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be named a second element without departing from the teachings of the disclosure.

[0055] For descriptive purposes, spatially relative terms such as "below," "beneath," "under," "down," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, an element described as "below" or "beneath" other elements or features would subsequently be positioned "above" the other elements or features. Thus, the exemplary term "below" can include both above and below orientations. Furthermore, the device can be positioned otherwise (e.g., rotated 90 degrees or at other orientations), with the spatially relative descriptors used herein interpreted accordingly.

[0056] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular "one", "one (kind / person)" and "said (the)" are also intended to include plural forms. In addition, when using the terms "comprise" and / or "include" and their variations in this manual, it is explained that there are stated features, integral bodies, steps, operations, elements, components and / or their groups, but it is not excluded that there are or add one or more other features, integral bodies, steps, operations, elements, components and / or their groups. It is also noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, and are so used to explain the inherent deviation of measured values, calculated values ​​and / or provided values ​​that those of ordinary skill in the art will recognize.

[0057] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views that are schematic diagrams of idealized exemplary embodiments and / or intermediate structures. As such, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as being limited to the specific illustrated shapes of the regions, but rather are to include deviations in shapes due to, for example, manufacturing. In this manner, the regions illustrated in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and as such, are not necessarily intended to be limiting.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0059] Figures 1A to 1C is a schematic plan view of an exemplary embodiment of a display device constructed according to the principles of the invention. Figures 1A to 1C Schematically shows a display panel and a driving circuit for driving the display panel provided in a display device. Figures 1A to 1C 1 and 2 show a display panel and a driving circuit separately, but the exemplary embodiments are not limited thereto. For example, all or part of the driving circuit may be integrated into the display panel.

[0060] The display device 10 can be configured in various shapes. For example, the display device 10 can be configured in the shape of a substantially rectangular plate having two pairs of parallel sides. The display device 10 can display any visual information, such as text, video, pictures, and two-dimensional (2D) or three-dimensional (3D) images.

[0061] The entire display device 10 or at least a portion thereof may have flexibility. For example, the display device 10 may have flexibility in the entire region, or may have flexibility in a local region corresponding to the flexible region.

[0062] Reference Figures 1A to 1C The display device 10 may include a display panel 110 and a driving circuit 200 for driving the display panel 110 .

[0063] The display panel 110 may include a display area AA and a non-display area NA. The display area AA may be a region in which a plurality of pixels PXL (or also referred to as "sub-pixels") are disposed and may be designated as an active area. In an exemplary embodiment, each of the pixels PXL may include at least one light-emitting element. The light-emitting element may be, but is not limited to, an organic light-emitting diode or a micro-inorganic light-emitting diode having a size falling within the micrometer or nanometer range. The display device 10 displays an image in the display area AA by driving the pixels PXL according to externally applied image data.

[0064] The non-display area NA may be an area surrounding the display area AA and may be designated as a non-active area. In an exemplary embodiment, the non-display area NA may inclusively refer to the remaining area of ​​the display panel 110 except for the display area AA.

[0065] In an exemplary embodiment, the non-display area NA may include a bending area BA, a wiring area WA, a pad (or "pad") area PA and various types of dummy areas, wherein the display area AA may be disposed adjacent to the dummy area and between the dummy area and the wiring area WA.

[0066] The bending area BA may be bent around a bending axis BAX. The bending area BA may refer to an area having a curvature radius after being bent. In an exemplary embodiment, the bending area BA may be formed between the display area AA and the pad area PA and may form, for example, a portion of the wiring area WA.

[0067] The pad area PA is arranged at one end of the non-display area NA and includes a plurality of pads P. The pad area PA may be exposed without being covered by an insulating layer and may then be electrically coupled to a controller and / or driver circuit 200, such as a flexible printed circuit board and a driver integrated circuit (IC), which will be described later. The controller and / or driver circuit 200 may provide data signals, scan signals, a first power (hereinafter also referred to as a first power source) ELVDD, a second power (hereinafter also referred to as a second power source) ELVSS, and the like.

[0068] The wiring area WA may include a plurality of lines (wiring) for coupling the pad P to the display area AA. The lines may be coupled to the pad P, and then electrical signals may be supplied to the pixels PXL arranged in the display area AA. The lines may include, for example, scan lines, data lines, power lines PL, and the like. For example, the power lines PL may be coupled to a controller through at least some of the pads P, and may supply a first power ELVDD provided from the controller to the pixels PXL. In an exemplary embodiment, at least two power lines PL may be provided, but the exemplary embodiment is not limited thereto. In addition, as Figure 1A As shown in , the power lines PL may be formed to have a width much greater than that of other lines (eg, scan lines, data lines, etc.) (here, the width is the length in a direction perpendicular to the longitudinal direction of elongation).

[0069] The wire may extend across the bending axis BAX. In an exemplary embodiment, the wire may extend obliquely at a predetermined angle relative to the bending axis BAX. In addition, the wire may have various shapes, such as a curved shape or a zigzag shape, rather than a linear shape.

[0070] In an exemplary embodiment, the display device 10 may further include a plurality of photosensors (or "light sensors") PHS disposed in the display area AA. In an exemplary embodiment, the photosensors PHS may detect that light emitted from a light source is reflected by a user's finger, analyze the reflected light, and then detect the user's fingerprint. Hereinafter, although an example will be described in which the photosensors PHS are used to detect fingerprints, the photosensors PHS may be used to perform various functions, as in the case of a touch sensor or scanner in various exemplary embodiments.

[0071] In an exemplary embodiment, the photosensor PHS may be arranged in the display area AA. Here, the photosensor PHS may be arranged to overlap at least some or all of the pixels PXL arranged in the display area AA, or may be arranged near the pixels PXL. For example, at least some or all of the photosensors PHS may be arranged between the pixels PXL. This will be referred to later. Figures 3A to 3D An exemplary embodiment of an arrangement relationship between the photosensor PHS and the pixel PXL is described in detail.

[0072] In an exemplary embodiment in which the photosensor PHS is arranged adjacent to the pixel PXL, the photosensor PHS may use a light-emitting element as a light source, which is provided in at least one pixel PXL arranged in the display area AA. In this embodiment, the photosensor PHS, together with the pixel PXL in the display area AA (specifically, the light-emitting element provided in the pixel PXL), may constitute a light-sensing fingerprint sensor. In this manner, when a display device embedded with a fingerprint sensor is configured to use the pixel PXL as a light source without requiring a separate external light source, the module thickness of the display device equipped with the light-sensing fingerprint sensor can be reduced, and its manufacturing cost can be reduced.

[0073] In an exemplary embodiment, the photosensor PHS may be disposed on a second surface (eg, rear surface) opposite to a first surface (eg, front surface) on which an image is displayed, between two surfaces of the display panel 110. However, exemplary embodiments are not limited thereto.

[0074] In an exemplary embodiment, the display device 10 may further include a light-blocking layer PHL. The light-blocking layer PHL may be disposed within the display panel 110 or between the display panel 110 and the photosensor PHS, thereby blocking a portion of light from being incident on the photosensor PHS. For example, the light-blocking layer PHL may selectively block light (hereinafter referred to as "reflected light") reflected from an object (e.g., a finger) in contact with the top of the display panel 110 and selectively allow the reflected light to pass through. A portion of the light incident on the light-blocking layer PHL may be blocked, and the remaining portion of the incident light may reach the photosensor PHS below the light-blocking layer PHL after passing through the light-transmitting region of the light-blocking layer PHL.

[0075] More specifically, the light-transmitting region of the light-blocking layer PHL may be formed of any structure or material that allows light to pass therethrough, such as a plurality of pinholes PIH, which are described in detail herein. The pinholes PIH are optical holes or openings in the light-blocking layer PHL that allow light to pass therethrough. In an exemplary embodiment, some layers in the display device 10 may include pinholes PIH that overlap one another on the path of reflected light that passes through the display panel 110 in a diagonal or vertical direction and then is incident on the photosensor PHS.

[0076] In an exemplary embodiment, the light blocking layer PHL may be arranged to correspond to the display area AA. Figure 1A As shown in FIG, the light-blocking layer PHL has a size larger than that of the display area AA, and thus a portion of the light-blocking layer PHL may overlap with the non-display area NA. However, exemplary embodiments are not limited thereto, and in other embodiments, the light-blocking layer PHL may have a size smaller than that of the display area AA or a size equal to that of the display area AA.

[0077] The light-blocking layer PHL may include a conductive material and be electrically coupled to at least one of the conductive layers provided in the display panel 110. For example, the light-blocking layer PHL may be electrically coupled to the power line PL provided in the display panel 110. Then, power (e.g., the first power ELVDD) applied to the pixel PXL through the power line PL may be supplied to the light-blocking layer PHL.

[0078] In an exemplary embodiment, as Figure 1A As shown in FIG, when the light blocking layer PHL overlaps the power line PL in the display area AA, the light blocking layer PHL may be electrically coupled to the power line PL through the contact hole in the display area AA. Figures 15 to 18 This is described in detail.

[0079] In an exemplary embodiment, one end of the light blocking layer PHL may include one or more extension portions EP1, EP2, EP3, and EP4 extending toward the periphery of the display device 10. For example, the light blocking layer PHL may have a Figure 1B As shown in FIG, one or more extension portions EP1 and EP2 extend outward from the first end facing the wiring area WA, and the one or more extension portions EP1 and EP2 may be provided in the wiring area WA. Figure 1C As shown in FIG, one or more extension portions EP3 and EP4 extending outward from a second end opposite to a first end facing the wiring area WA, the one or more extension portions EP3 and EP4 may be provided in the dummy area. However, exemplary embodiments are not limited thereto, and the light blocking layer PHL may include only Figure 1B and Figure 1C , or may include one of the extensions EP1 , EP2 , EP3 and EP4 shown in FIG.

[0080] The extension portions EP1, EP2, EP3, and EP4 may be formed to overlap at least one power line PL or be arranged adjacent to at least one power line PL, and then may be electrically coupled to the power line PL in the non-display area NA. For example, the extension portions EP1, EP2, EP3, and EP4 may be directly coupled to the power line PL, or may be indirectly coupled to the power line PL via a bridge or the like.

[0081] The width of the extensions EP1, EP2, EP3, and EP4 may be equal to or different from the width of the power line PL. When each of the extensions EP1, EP2, EP3, and EP4 has a width at least approximately equal to the considerable width of the power line PL, the extensions EP1, EP2, EP3, and EP4 may be electrically coupled to the power line PL through a plurality of contact holes.

[0082] Will refer to it later 10A to 12B An example of a coupling relationship between the extending portion EP1 , EP2 , EP3 , or EP4 and the power line PL is described in detail.

[0083] The driving circuit 200 can drive the display panel 110. For example, the driving circuit 200 can output a data signal corresponding to image data to the display panel 110 or output a driving signal for the photosensor PHS, and can receive a sensing signal from the photosensor PHS. The driving circuit 200 that has received the sensing signal can use the sensing signal to detect the shape of the user's fingerprint.

[0084] In an exemplary embodiment, the driving circuit 200 may include a panel driver 210 and a fingerprint detector 220. For ease of description, although Figures 1A to 1C2. The panel driver 210 and the fingerprint detector 220 are shown separately in FIG. 2, but the exemplary embodiment is not limited thereto. For example, at least a portion of the fingerprint detector 220 may be integrated with the panel driver 210 or may operate in conjunction with the panel driver 210.

[0085] The panel driver 210 may supply data signals corresponding to image data to the pixels PXL while sequentially scanning the pixels PXL in the display area AA, and then the display panel 110 may display an image corresponding to the image data.

[0086] In an exemplary embodiment, the panel driver 210 may supply a driving signal for fingerprint sensing to the pixel PXL. The driving signal may be provided so that the pixel PXL emits light to serve as a light source for the photosensor PHS. In this embodiment, the driving signal for fingerprint sensing may be provided to the pixel PXL disposed in a specific area (e.g., in the display area AA) of the display panel 110. In an exemplary embodiment, the driving signal for fingerprint sensing may be provided by the fingerprint detector 220.

[0087] The fingerprint detector 220 may transfer a driving signal to the photosensor PHS to drive the photosensor PHS, and may detect the fingerprint of the user based on a sensing signal received from the photosensor PHS.

[0088] Although the pinhole PIH and photoelectric sensor PHS Figures 1A to 1C , but the exemplary embodiment is not limited thereto. For example, at least a portion of the display area AA may be set as a sensing area, and the pinhole PIH and the photosensor PHS may be arranged in the sensing area. In this embodiment, the size of the light-blocking layer PHL may be equal to or larger than the size of the sensing area. In the case where the size of the light-blocking layer PHL is larger than the size of the sensing area, the light-blocking layer PHL may have a size smaller than the size of the display area AA or a size equal to the size of the display area AA, or may be as shown. Figures 1A to 1C , shown in , to have a size larger than that of the display area AA.

[0089] Figure 2 is a plan view of an exemplary embodiment of a light-blocking layer constructed according to the principles of the invention. Figure 2 Shown with Figure 1A The light blocking layer PHL is shaped as shown in FIG. Figure 2 shown in, but Figure 1B and Figure 1C At least one of the extension portions EP1, EP2, EP3, and EP4 shown in FIG. 5 may be formed on the light blocking layer PHL.

[0090] Reference Figure 2, the light blocking layer PHL may include a light blocking mask LBM and a plurality of pinholes PIH distributed throughout the light blocking mask LBM.

[0091] The light blocking mask LBM can be formed of a light blocking and / or light absorbing material. For example, the light blocking mask LBM can be formed of an opaque metal layer that is partially open in the area where the pinholes PIH are arranged. However, the material forming the light blocking mask LBM is not limited to such a metal material, and the light blocking mask LBM can be formed of various types of materials that can block the transmission of light. For example, the light blocking mask LBM can be formed of a currently known black matrix material.

[0092] The pinholes PIH may be optical openings distributed throughout the light-blocking mask LBM. For example, the pinholes PIH may be empty spaces that eliminate at least one region of the light-blocking mask LBM, or may be through-holes formed through the light-blocking mask LBM. Alternatively, the pinholes PIH may be optical apertures formed transparently or translucently so as to selectively transmit only a portion of the incident light.

[0093] The pinholes PIH can be distributed throughout the light-blocking mask LBM in a regular or irregular pattern to have a predetermined size and spacing. The pinholes PIH can be formed with a suitable size and spacing to prevent diffraction of the incident light while detecting a clearer fingerprint shape. For example, the width of the pinholes PIH can be set to a value greater than ten times the wavelength of the incident light to prevent diffraction of the light. In addition, the spacing between the pinholes PIH can be determined based on the distance between the light-blocking layer PHL and the photosensor PHS, the wavelength of the incident light, and the field of view (FOV) (or viewing angle) required for the pinholes PIH.

[0094] exist Figure 2 In the embodiment of FIG. 1 , although the pinhole PIH is shown as having a rectangular shape, the exemplary embodiment is not limited thereto. That is, in the exemplary embodiment, the pinhole PIH may have various shapes, such as a circular shape, an elliptical shape, or a polygonal shape other than a rectangular shape. However, the exemplary embodiment is not limited thereto, and the size, shape, number, resolution, and / or array structure of the pinhole PIH may be varied in various ways.

[0095] The light-blocking layer PHL can constitute an optical system for selectively transmitting only a portion of light and blocking the rest. Such a light-blocking layer PHL, together with the above-mentioned photosensor PHS, can constitute a fingerprint sensor. In addition, the light-blocking layer PHL can be integrated with the circuit element layer of the display panel 110. In this case, the module thickness of the display device equipped with the light-sensing fingerprint sensor can be reduced or minimized.

[0096] Figures 3A to 3Dis a plan view of an exemplary embodiment of an array structure of pixels, pinholes, and photosensors constructed according to the principles of the invention. Figures 3A to 3D Shown with the arrangement in Figures 1A to 1C Different embodiments are related to the relative size, resolution and / or array relationship of the pixels PXL, the pinholes PIH and the photosensors PHS in the display area AA.

[0097] Reference Figure 3A The display area AA may include a smaller number of pinholes PIH and photosensors PHS than the number of pixels PXL. For example, the pinholes PIH and photosensors PHS may have a size smaller than that of the pixels PXL and may be distributed throughout the display area AA at a lower resolution than that of the pixels PXL.

[0098] Despite Figure 3A , the number of pinholes PIH and photosensors PHS is shown as being smaller than the number of pixels PXL, but exemplary embodiments are not limited thereto. For example, in other exemplary embodiments, the number of pinholes PIH and photosensors PHS distributed throughout the display area AA is substantially equal to one another, and the spacing between the pinholes PIH and the spacing between the photosensors PHS are substantially equal to one another, so that the pinholes PIH and photosensors PHS are arranged in a one-to-one correspondence. For example, the pinholes PIH and photosensors PHS may be arranged to overlap one another, while forming corresponding pairs in a one-to-one correspondence. In exemplary embodiments, a pair of pinholes PIH and photosensors PHS may be arranged to overlap any one pixel PXL arranged in the display area AA, but exemplary embodiments are not limited thereto. For example, the pinholes PIH and photosensors PHS may be alternately arranged so as not to overlap one another, or may be arranged so as not to overlap a pixel PXL.

[0099] The pinhole PIH and the photosensor PHS may have equal or different sizes. That is, the relative sizes or resolutions of the pinhole PIH and the photosensor PHS are not particularly limited to specific values.

[0100] Reference Figure 3B , the display area AA may include a smaller number of pinholes PIH than the number of pixels PXL and a larger number of photosensors PHS than the number of pixels PXL. For example, the pinholes PIH and the photosensors PHS may have a size smaller than that of the pixels PXL, but the pinholes PIH may be distributed throughout the display area AA at a resolution lower than that of the pixels PXL, and the photosensors PHS may be densely distributed throughout the display area AA at a resolution higher than that of the pixels PXL.

[0101] At least some of the photosensors PHS may overlap with any one of the pinholes PIH and / or any one of the pixels PXL, but exemplary embodiments are not limited thereto. For example, some of the photosensors PHS may be arranged to overlap with the pinholes PIH and / or the pixels PXL, and the other photosensors PHS may be arranged in the gaps between the pixels PXL.

[0102] Reference Figure 3C and Figure 3D , the photosensors PHS can be distributed throughout the display area AA so that they have a Figure 3B The size of the embodiment is smaller than the size of Figure 3B The resolution in the embodiment is high resolution. For example, the photosensors PHS can be distributed throughout the display area AA at shorter intervals (e.g., 50 μm in each of the horizontal and vertical directions) of about 1 / 10 to 1 / 100 of the intervals between the pinholes PIH (e.g., 450 μm in each of the horizontal and vertical directions), and can be densely distributed throughout the display area AA at a resolution higher than the resolution of the pixels PXL. In this case, the photosensors PHS can be densely arranged in the display area AA to the extent that a one-to-one correspondence is not required between the pixels PXL and / or between the pinholes PIH, and thus Moire can be prevented or minimized regardless of whether the pixels PXL and / or the pinholes PIH are aligned with each other.

[0103] The pinholes PIH may be distributed over the display area AA at a resolution that is the same as or different from the resolution of the pixels PXL. Figure 3C The pixels PXL are distributed throughout the display area AA at the same density as shown in FIG. 1 , or may be distributed as shown in FIG. Figure 3D As shown in FIG, the pixels are distributed throughout the display area AA at a density lower than that of the pixels PXL.

[0104] exist Figures 3A to 3D In the embodiment described above, the pinholes PIH and the photosensors PHS are arranged in a regular array in the display area AA, but the exemplary embodiments are not limited thereto. That is, the pinholes PIH and / or the photosensors PHS may be irregularly dispersed throughout the display area AA, or may be distributed with different densities or array structures according to each area or each segment of the display area AA.

[0105] The array structure of the pixels PXL, pinholes PIH and photosensors PHS is not limited to Figures 3A to 3DFor example, the shape, array form, relative size, number, resolution and / or mutual arrangement relationship of the pixels PXL, pinholes PIH and / or photosensors PHS arranged in the display area AA may be changed in various ways.

[0106] Figure 4 is a cross-sectional view of an exemplary embodiment of a display device constructed according to the principles of the invention.

[0107] Reference Figure 4 , the display device 10 may include a display panel 110 and a sensor layer PSL disposed on one surface of the display panel 110 .

[0108] The display panel 110 may be operable to display an image. The type of the display panel 110 is not particularly limited to a specific type, as long as the display panel 110 can display an image. The display panel 110 may be a self-emissive display panel, such as an organic light emitting diode (OLED) display panel. In addition, the display panel 110 may be a non-emissive display panel, such as a liquid crystal display (LCD) panel, an electrophoretic display (EPD) panel, or an electrowetting display (EWD) panel. When the display panel 110 is configured as a non-emissive display panel, the display device 10 may be provided with a backlight assembly for supplying light to the display panel 110.

[0109] The display panel 110 may include a first substrate SUB1, and a circuit element layer BPL, a light emitting element layer LDL, a first protective layer PTL1, a first adhesive layer ADL1, and a window WIN sequentially disposed on a first surface (e.g., top surface) of the first substrate SUB1. Furthermore, the display device 10 may include a second adhesive layer ADL2 and a second protective layer PTL2 sequentially disposed on a second surface (e.g., bottom surface) of the first substrate SUB1.

[0110] The first substrate SUB1, which is the base material of the display panel 110, may be a substantially transparent light-transmitting substrate. The first substrate SUB1 may be a rigid substrate including glass or reinforced glass, or a flexible substrate made of a plastic material. However, the material of the first substrate SUB1 is not limited thereto, and the first substrate SUB1 may be made of various materials.

[0111] The first substrate SUB1 may include a display area AA and a non-display area NA such as Figures 1A to 1C In addition, the display area AA may include a plurality of pixel areas PXA in which corresponding pixels PXL are arranged and / or formed.

[0112] The circuit element layer BPL may be arranged on the first surface of the first substrate SUB1 and may include at least one conductive layer. For example, the circuit element layer BPL may include a plurality of circuit elements constituting the pixel circuit of the pixel PXL and lines for supplying various types of power and signals required to drive the pixel PXL. In this case, the circuit element layer BPL may include a plurality of conductive layers for forming various types of circuit elements (such as at least one transistor and at least one capacitor) and lines coupled to the circuit elements. In addition, the circuit element layer BPL may include at least one insulating layer disposed between the plurality of conductive layers. In addition, the circuit element layer BPL may include a wiring unit arranged in the non-display area NA of the first substrate SUB1 to supply power and signals corresponding to the lines coupled to the pixel PXL.

[0113] The light-emitting element layer LDL may be disposed on the first surface of the circuit element layer BPL. The light-emitting element layer LDL may include a plurality of light-emitting elements LD coupled to circuit elements and / or wires of the circuit element layer BPL via contact holes, etc. The light-emitting elements LD may be organic light-emitting diodes or micro-light-emitting elements using an inorganic crystal growth structure. In an exemplary embodiment, at least one of the plurality of light-emitting elements LD may be disposed in each pixel area PXA.

[0114] Each of the pixels PXL may include circuit elements provided in the circuit element layer BPL and at least one light emitting element LD provided in the light emitting element layer LDL provided on top of the circuit element layer BPL. The structure of each pixel PXL will be described in detail later.

[0115] The first protective layer PTL1 may be disposed on top of the light emitting element layer LDL to cover the display area AA. The first protective layer PTL1 may include a sealing member such as a thin film encapsulation (TFE) layer or an encapsulation substrate, and may further include a protective film or the like in addition to the sealing member.

[0116] The first adhesive layer ADL1 may be interposed between the first protection layer PTL1 and the window WIN to bond the first protection layer PTL1 to the window WIN. The first adhesive layer ADL1 may include a transparent adhesive such as an optically clear adhesive (OCA), and may additionally include various types of adhesive materials.

[0117] The window WIN may be a protective element provided in the uppermost portion of the module including the display panel 110 of the display device 10, and may be a substantially transparent light-transmitting substrate. Such a window WIN may have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. The window WIN may include a rigid or flexible material, and the material forming the window WIN is not particularly limited.

[0118] In an exemplary embodiment, the display device 10 may further include a polarizing plate and / or a touch sensor layer (touch electrode layer). For example, the display device 10 may further include a polarizing plate and / or a touch sensor layer interposed between the first protection layer PTL1 and the window WIN.

[0119] The second protection layer PTL 2 may be disposed on the second surface of the first substrate SUB 1. The second protection layer PTL 2 may be bonded to the first substrate SUB 1 through a second adhesive layer ADL 2.

[0120] The second adhesive layer ADL2 may firmly bond (or attach) the first substrate SUB1 and the second protective layer PTL2 to each other. The second adhesive layer ADL2 may include a transparent adhesive such as OCA. The second adhesive layer ADL2 may include a pressure-sensitive adhesive (PSA) that acts when an adhesive material is applied thereto to bond the second adhesive layer ADL2 to the bonding end. When the second adhesive layer ADL2 includes a pressure-sensitive adhesive, the second adhesive layer ADL2 may be attached to the bonding end using only pressure without the need for a separate heat treatment or UV treatment.

[0121] In an exemplary embodiment, the second adhesive layer ADL2 may include a material that absorbs light of a specific wavelength or a material that blocks light of a specific wavelength. For example, the second adhesive layer ADL2 may include an infrared absorbing material that absorbs infrared light with high energy density or an infrared shielding material that blocks infrared light.

[0122] The infrared absorbing material may include an inorganic oxide containing antimony tin oxide (ATO), indium tin oxide (ITO), tungsten oxide or carbon black, and a metal material such as Ag. The inorganic oxide can selectively transmit light in the visible light band and can absorb infrared light. In addition, the infrared absorbing material may include, for example, an organic dye. The organic dye may be a dye used for, for example, a color filter provided in the display panel 110.

[0123] The infrared shielding material may include one or more selected from the group consisting of, for example, borate mixtures, carbonate mixtures, aluminate mixtures, nitrate mixtures, and nitrite mixtures. For example, the infrared shielding material may include one or more selected from the group consisting of lithium borate, sodium borate (e.g., Na2B4O x), potassium borate, magnesium borate, calcium borate, strontium borate, barium borate, colemanite, lithium carbonate, sodium carbonate, potassium carbonate, calcium carbonate (e.g., CaCO 3 or calcite), dolomite and magnesite. In addition, the infrared shielding material may be at least one of the dyes selected from the group consisting of nickel dithiol, dithiol metal complexes, anthocyanin, squaric acid, ketoic acid, diammonium, ammonium, phthalocyanine, naphthalocyanine, anthraquinone, naphthoquinone, condensation polymerazo-based pyrrole, polymethine and acrylic compounds.

[0124] When the user's finger reaches (or is positioned on) the display surface of the display device 10 (e.g., the surface on which an image is displayed), the display device 10 can perform a function of sensing the user's fingerprint through the photosensor PHS, which will be described later. When external light flows into the display device 10 while sensing the user's fingerprint, the external light in the visible light band may be blocked by the user's hand, but infrared light may pass through the user's hand and then be incident on the photosensor PHS. The infrared light incident on the photosensor PHS acts as noise, thereby reducing the accuracy of recognition of the light reflected from the user's hand.

[0125] As in the illustrated embodiment, when the second adhesive layer ADL2 contains an infrared absorbing material and / or an infrared shielding material, even if the infrared light of the external light passes through the user's hand, the infrared light of the external light is absorbed and / or blocked by the second adhesive layer ADL2 and is not incident on the photosensor PHS, thereby improving the accuracy of fingerprint recognition.

[0126] The second protective layer PTL2 can prevent oxygen and moisture from penetrating from the outside and can be provided in a single layer or a multilayer form. The second protective layer PTL2 can be formed in the shape of a film and can further ensure the flexibility of the display panel 110. The second protective layer PTL2 can be bonded to the sensor layer PSL through an additional adhesive layer containing a transparent adhesive such as OCA.

[0127] In an exemplary embodiment, a selective light-shielding film may be further provided on the bottom of the second protective layer PTL2. The selective light-shielding film may block light of a specific frequency (or wavelength) band (for example, an infrared light band) contained in the external light that flows into the display device 10, thereby preventing the corresponding infrared light from being incident on the photosensor PHS of the sensor layer PSL. Although the selective light-shielding film is described as being further provided on the bottom of the second protective layer PTL2, exemplary embodiments are not limited thereto. For example, the selective light-shielding film may be freely provided on any layer of the display device 10 as long as the selective light-shielding film can be arranged on top of the sensor layer PSL. In addition, when a component for blocking infrared light (such as a second adhesive layer ADL2) is included in the display panel 110, the selective light-shielding film may be omitted.

[0128] The light blocking layer PHL may be placed between the light emitting element layer LDL and the sensor layer PSL. Figure 4 As shown in FIG, the light blocking layer PHL may be placed between the first substrate SUB1 and the circuit element layer BPL. Figure 2 As described, the light blocking layer PHL may include a plurality of pinholes PIH.

[0129] The display panel 110 may be transparently formed in the region where the pinholes PIH are provided so that light reflected from a fingerprint of a finger or the like can pass through each pinhole PIH. In addition, the display panel 110 may be configured so that light satisfying a field of view (FOV) (also referred to as a "viewing angle") falling within a predetermined angle range can pass through each pinhole PIH to reduce the loss of reflected light required for fingerprint sensing.

[0130] For example, the display panel 110 may be transparently formed in a region overlapping each pinhole PIH while having an area larger than that of the pinhole PIH. Hereinafter, a region transparently formed to allow reflected light to pass therethrough is referred to as an 'optical aperture OPA'.

[0131] Assuming that the field of view (FOV) within a desired range relative to the center of each pinhole PIH is θ, the thickness of the circuit element layer BPL is q, and the width of the optical aperture OPA formed at the interface between the circuit element layer BPL and the light emitting element layer LDL is 2p, 2p = 2 × (q × tanθ) may be satisfied. In an exemplary embodiment, the field of view may be within an angular range of approximately 30° to 60°, but is not limited thereto.

[0132] The pinhole PIH may have a predetermined width w, for example, a width w ranging from 5 μm to 20 μm, and the width of the optical aperture OPA may be 2p + w. In this way, the width of the optical aperture OPA to be ensured by each layer of the display device 10 may gradually increase in a direction away from the light-blocking layer PHL (i.e., toward the top and bottom of the light-blocking layer PHL).

[0133] The width w (or diameter) of the pinhole PIH can be set to a value approximately ten times greater than the wavelength of the reflected light (e.g., 4 μm or 5 μm or greater) to prevent light diffraction. Furthermore, the width w of the pinhole PIH can be set to a size sufficient to prevent image blur and more clearly sense the shape of the fingerprint. For example, the width w of the pinhole PIH can be set to a value less than or equal to approximately 15 μm. However, exemplary embodiments are not limited thereto, and the width w of the pinhole PIH can vary depending on the wavelength band of the reflected light and / or the thickness of each layer of the module.

[0134] The spacing (or pitch) between adjacent pinholes PIH can be set taking into account the distance between the light-blocking layer PHL and the sensor layer PSL and the wavelength range of the reflected light. For example, when it is desired to ensure a field of view (FOV) of approximately 45° for the reflected light, the spacing between adjacent pinholes PIH can be set to a value twice or greater than the distance between the light-blocking layer PHL and the sensor layer PSL, and can also be set to a value equal to or greater than the value obtained by adding a predetermined error range to the distance. In this case, the images observed by the corresponding photosensors PHS can be prevented from overlapping each other, thereby preventing image blur.

[0135] The sensor layer PSL may be attached to the second surface (e.g., rear surface) of the display panel 110 so as to overlap at least one area of ​​the display panel 110. The sensor layer PSL may be arranged to overlap the display panel 110 at least in the display area AA. Such a sensor layer PSL may include a plurality of photosensors PHS distributed at a predetermined resolution and / or at predetermined intervals. The intervals between the photosensors PHS may be densely set so that light reflected from a specific area of ​​an observation target (e.g., a finger, such as a fingerprint area) is incident on at least two adjacent photosensors PHS.

[0136] The photosensor PHS of the sensor layer PSL can output an electrical signal corresponding to the reflected light received after passing through the pinhole PIH as a sensing signal. The reflected light component received by the corresponding photosensor PHS can have different optical characteristics (e.g., frequency, wavelength, intensity, etc.) depending on whether the corresponding reflected light is generated by a valley or a ridge of a fingerprint formed on the user's finger. Therefore, the photosensor PHS can output a sensing signal with different electrical characteristics depending on the optical characteristics of the corresponding reflected light component. The sensing signal output from the photosensor PHS can be converted into image data and can be used to identify the user's fingerprint.

[0137] As described above, the display device 10 may include a fingerprint sensor including a light-emitting element layer LDL, a sensor layer PSL, and a light-blocking layer PHL. The light-emitting element layer LDL may include a light-emitting element LD that can also function as a light source for a light-sensing sensor. The sensor layer PSL may include a photosensor PHS that receives light reflected from an object (e.g., a fingerprint area of ​​a finger) located on top of the display device 10 after being emitted from the light-emitting element layer LDL. The light-blocking layer PHL, disposed between the light-emitting element layer LDL and the sensor layer PSL, may include a pinhole PIH to selectively transmit reflected light.

[0138] The display device 10 may utilize the light emitting element LD of the pixel PXL as a light source of the fingerprint sensor, but the exemplary embodiment is not limited thereto. For example, the display device 10 may include a separate light source for fingerprint sensing.

[0139] The following briefly describes a fingerprint sensing method using the display device 10 according to the illustrated embodiment. During a fingerprint sensing period in which the photosensor PHS is activated, the pixels PXL in the display area AA (specifically, the light-emitting elements LD provided in the pixels PXL) can emit light when a user brings their finger (e.g., fingerprint area) into contact with the display area AA or when the user moves their finger close to the display area AA. For example, during the fingerprint sensing period, all pixels PXL in the display area AA can emit light simultaneously or sequentially. Alternatively, among the pixels PXL in the display area AA, only some pixels PXL can emit light at predetermined intervals, or alternatively, only some pixels PXL configured to emit light of a specific color (e.g., light having a short wavelength, such as blue light) can selectively emit light.

[0140] A portion of the light emitted from the pixel PXL may be incident on the photosensor PHS after being reflected from the user's finger and passing through the optical aperture OPA and the pinhole PIH formed in each layer of the display device 10. Here, the shape (fingerprint pattern) of the user's fingerprint may be detected based on the difference between the amount of light reflected from the ridges and valleys of the fingerprint and / or the waveform of the reflected light.

[0141] Figure 5 is a cross-sectional view of another exemplary embodiment of a display device constructed according to the principles of the invention. Figure 4 The same or similar components are described in detail to avoid redundancy.

[0142] Reference Figure 5 , the display panel 110 may include a second protective layer PTL2. The second protective layer PTL2 may include a base layer BSL and first and second coating layers COL1 and COL2 formed on the bottom and top surfaces of the base layer BSL, respectively.

[0143] The base layer (BSL) may be implemented in the form of a plastic film including at least one organic layer. The plastic film may be manufactured to include, for example, at least one of a thermoplastic polymer resin having high transparency and excellent heat dissipation performance (such as polyimide (PI), polyethersulfone (PES), polyarylate (PAR), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), cyclic olefin copolymer, polycarbonate (PC), etc.) and a thermosetting polymer resin (such as epoxy resin, unsaturated polyester, phenol (PF), polysilicone, or polyurethane).

[0144] In an exemplary embodiment, the material of the base layer BSL is not limited to the above examples. As the material of the base layer BSL, a suitable material can be selected from materials that can protect the layers disposed on top of the base layer BSL according to the design conditions of the display panel 110, etc. In an exemplary embodiment, the base layer BSL may also include the same material as the infrared absorbing material and / or infrared shielding material included in the second adhesive layer ADL2 of the display device 10.

[0145] Either the first coating layer COL1 or the second coating layer COL2 may be coated with an infrared shielding material that reflects and blocks infrared light, and the other may be coated with an infrared absorbing material that absorbs infrared light. For example, the first coating layer COL1 may be a layer having a mixture of materials that absorb infrared light applied (or coated) thereon, and the second coating layer COL2 may be a layer having a mixture of materials that reflect and block infrared light applied (or coated) thereon. For example, the material that reflects and blocks infrared light may include, but is not limited to, titanium oxide (TiO2) or magnesium fluoride (MgF2).

[0146] As described above, when the second protective layer PTL2 includes an infrared shielding material that reflects and / or blocks infrared light and an infrared absorbing material that absorbs infrared light, even if infrared light from external light passes through the user's hand, the infrared light is prevented from being incident on the sensor layer PSL by virtue of the second protective layer PTL2 located on top of the sensor layer PSL. Therefore, the photosensor PHS can more accurately recognize the user's fingerprint without interference from external light.

[0147] In an exemplary embodiment, some components of the display panel 110 (e.g., the second adhesive layer ADL2 and / or the second protective layer PTL2) are configured to include an infrared absorbing material and / or an infrared shielding material, without requiring a separate component such as an infrared shielding film, thereby blocking infrared light. Therefore, the manufacturing cost of the display device 10 can be reduced, and the thickness of the display device 10 can be further reduced.

[0148] Figures 6 to 9 are cross-sectional views of some further exemplary embodiments of display devices constructed according to the principles of the invention. Figure 4 The same or similar components are described in detail to avoid redundancy.

[0149] Reference Figure 6 The display panel 110 may further include a second substrate SUB2 disposed on a second surface (e.g., bottom surface) of the first substrate SUB1. The second substrate SUB2 may be disposed between the first substrate SUB1 and the sensor layer PSL. In this embodiment, a barrier layer BRL may be disposed between the first substrate SUB1 and the second substrate SUB2.

[0150] The second substrate SUB2 may be formed of a material that is the same as or different from that of the first substrate SUB1. For example, the first substrate SUB1 and the second substrate SUB2 may be thin film substrates both made of polyimide (PI) material. Alternatively, the first substrate SUB1 and the second substrate SUB2 may be heterogeneous substrates having different materials. Such a second substrate SUB2 may include at least one of the materials described as components of the first substrate SUB1, and may be formed to additionally include various types of materials.

[0151] The barrier layer BRL may be provided in the form of a single layer structure or a multi-layer structure. For example, the barrier layer BRL may be formed in a structure in which at least 10 inorganic insulating layers are stacked.

[0152] Reference Figure 7 and Figure 8The circuit element layer BPL may include a light-transmitting layer LTHL including a plurality of light-transmitting holes LTH. Furthermore, a light-blocking layer PHL including a plurality of pinholes PIH may be disposed between the first substrate SUB1 and the circuit element layer BPL. Each light-transmitting hole LTH and each pinhole PIH may be arranged to at least partially overlap each other.

[0153] In an exemplary embodiment, the light transmission hole LTH and the pinhole PIH may have the same or different sizes. Figure 7 As shown in , the light transmission hole LTH may have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH. For example, the pinhole PIH and the light transmission hole LTH may have a width (or diameter) ranging from 5 μm to 20 μm, and the light transmission hole LTH may both have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH.

[0154] When the light-transmitting hole LTH has a size smaller than that of the pinhole PIH, the light-transmitting layer LTHL can perform the function of the light-controlling layer LBL for controlling the light path (for example, the function of limiting the field of view of the reflected light to a predetermined angle range), and the light-blocking layer PHL can perform the light-blocking function of selectively transmitting light.

[0155] like Figure 8 As shown in , the light transmitting hole LTH may have a width (or diameter) greater than that of the pinhole PIH. In this embodiment, the light transmitting layer LTHL may perform a light blocking function, and the light blocking layer PHL may perform a function of a light control layer LBL for controlling a light path.

[0156] Reference Figure 9 , the circuit element layer BPL may include a light-transmitting layer LTHL, and the light-transmitting layer LTHL includes a plurality of light-transmitting holes LTH. Figure 6 As described, a second substrate SUB2 may be further provided, and a light blocking layer PHL including a plurality of pinholes PIH may be interposed between the first substrate SUB1 and the second substrate SUB2.

[0157] In an exemplary embodiment, the light-transmitting hole LTH and the pinhole PIH may have the same or different sizes. For example, the light-transmitting hole LTH may have a width (or diameter) smaller than the width (or diameter) of the pinhole PIH. In this embodiment, the light-transmitting layer LTHL may function as a light-controlling layer LBL for controlling a light path, and the light-blocking layer PHL may function as a light-blocking layer for selectively transmitting light.

[0158] As described above, when the light-transmitting holes LTH are widely formed over a wide area in the circuit element layer BPL of the display panel 110, the load acting on the lines (e.g., scan lines, data lines, etc.) formed on the circuit element layer BPL may increase. This increase in load may increase the power consumption of the display device 10. In addition, when the light-transmitting holes LTH are widely formed over a wide area in the circuit element layer BPL of the display panel 110, crosstalk with the elements (e.g., transistors) of the corresponding pixels PXL occurs, thereby deteriorating the quality of the display panel 110.

[0159] These problems can be solved by applying power to the light-blocking layer PHL disposed adjacent to the circuit element layer BPL and by varying the characteristics of adjacent transistors according to the electric field effect of the light-blocking layer PHL. Hereinafter, this aspect of the disclosure will be described in detail.

[0160] Figure 10A yes Figure 1B An enlarged plan view of an exemplary embodiment of portion EA1 is shown. Figure 10B It is along Figure 10A A cross-sectional view taken along line II'. Figure 10A and Figure 10B In order to more easily explain the coupling relationship between the light blocking layer PHL and the power lines PL, only some components included in the non-display area NA are schematically illustrated.

[0161] exist Figure 10A and Figure 10B Although we will use it by way of example Figure 1B and Figure 1C The first extension portion EP1 among the extension portions EP1, EP2, EP3 and EP4 of the light-blocking layer PHL shown in the figure is used to describe the coupling relationship with the power line PL, but the following embodiments can be equally applied to the second to fourth extension portions EP2, EP3 and EP4 and the power line PL adjacent thereto.

[0162] The first substrate SUB1 may be divided into a display area AA and a non-display area NA, and the pixels PXL may be arranged in the display area AA. The non-display area NA may include a wiring area WA in which the power lines PL are arranged.

[0163] Reference Figure 10A and Figure 10B In the display device 10 , a first substrate SUB1 and a buffer layer 112 , a gate insulating layer 113 , first to third interlayer insulating layers 114 , 115 - 1 and 115 - 2 , and a protective layer 116 sequentially stacked on the first substrate SUB1 may be provided.

[0164] The first substrate SUB1, which is the base material of the display panel 110, may be a substantially transparent light-transmitting substrate. The first substrate SUB1 may be a rigid substrate including glass or reinforced glass, or a flexible substrate made of a plastic material. However, the material of the first substrate SUB1 is not limited thereto, and the first substrate SUB1 may be made of various materials.

[0165] The buffer layer 112 can prevent the phenomenon in which metal atoms or impurities diffuse (for example, degassing) from the first substrate SUB1. In addition, when the first substrate SUB1 has an irregular surface flatness, the buffer layer 112 can play a role in improving the surface flatness of the first substrate SUB1. The buffer layer 112 may include an inorganic material (such as an oxide or a nitride), an organic material, or an organic / inorganic compound, and may be formed of a single layer or a multilayer structure of an organic material and an inorganic material. For example, the buffer layer 112 may have a three-layer or more layer structure formed of silicon oxide, silicon nitride, and silicon oxide. In the non-display area NA, the buffer layer 112 may be formed only of an inorganic material, but exemplary embodiments are not limited thereto.

[0166] The gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2 are sequentially stacked on the buffer layer 112. Each of the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2 may include an inorganic layer and / or an organic layer. In an example, each of the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2 may be made of a material including SiO x or SiN x For example, each of the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2 may include an inorganic insulating material (such as SiO x 、SiN x , SiON, SiOF or AlO x ) or an organic insulating material, and may have a single-layer structure or a multi-layer structure including at least one of these materials. In the non-display area NA, each of the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2 may be formed only of an inorganic material, but is not limited thereto.

[0167] Each of the buffer layer 112, the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2 may be formed of only an inorganic material in the non-display area NA, thereby forming an inorganic insulating layer. Such an inorganic insulating layer can provide robustness against external forces applied due to bending in the non-display area NA (particularly in the bending area BA and areas adjacent thereto).

[0168] In an exemplary embodiment, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer may be disposed on the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2, respectively. In an exemplary embodiment, the first conductive layer may be a first gate layer, the second conductive layer may be a second gate layer, the third conductive layer may be a third gate layer, and the fourth conductive layer may be a source / drain layer.

[0169] In an exemplary embodiment, a connector, such as a bridge pattern (BRP), may be provided on the third conductive layer to electrically connect the elements together. The bridge pattern (BRP) may extend approximately perpendicular to the power line (PL) and the first extension (EP1) in the non-display area (NA). The bridge pattern (BRP) may be coupled to the power line (PL) via first and second contact holes (CT1, CT2) formed through the third interlayer insulating layer (115-2), and may be coupled to the light-blocking layer (PHL) via third and fourth contact holes (CT3, CT4). The first and second contact holes (CT1, CT2) may be formed through the third interlayer insulating layer (115-2), and the third and fourth contact holes (CT3, CT4) may be formed through the buffer layer (112), the gate insulating layer (113), the first interlayer insulating layer (114), and the second interlayer insulating layer (115-1).

[0170] In an exemplary embodiment, a power line PL may be disposed on the fourth conductive layer. The power line PL may extend approximately along the second direction DR2 in the non-display area NA, but is not limited thereto. Such a power line PL may receive the first power ELVDD from the pad P disposed in the pad area PA. The power line PL may be coupled to the bridge pattern BRP via the first and second contact holes CT1 and CT2 formed through the third interlayer insulating layer 115-2. Since the bridge pattern BRP is coupled to the light-blocking layer PHL via the third and fourth contact holes CT3 and CT4, the power line PL may be electrically coupled to the light-blocking layer PHL.

[0171] A protective layer 116 may be disposed on the third interlayer insulating layer 115-2. In an exemplary embodiment, the protective layer 116 may include a passivation layer and / or a planarization layer. Such a protective layer 116 may have a top surface that may be approximately flat and may be formed as a single layer or a multilayer structure.

[0172] The first protective layer PTL1 may be disposed on the protective layer 116. The first protective layer PTL1 may be formed of a thin film encapsulation layer. In an exemplary embodiment, the thin film encapsulation layer may be replaced with another type of encapsulation layer or an encapsulation substrate or at least one protective layer.

[0173] The thin film encapsulation layer can prevent oxygen and moisture from penetrating from the outside. For this operation, the thin film encapsulation layer may include an inorganic layer. The inorganic layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0174] The light-blocking layer PHL may be disposed between the first substrate SUB1 and the buffer layer 112 and may be configured to selectively transmit incident light. In the non-display area NA, the light-blocking layer PHL may include a first extension portion EP1 adjacent to and extending approximately parallel to the power line PL. The width of the first extension portion EP1 may be less than or equal to the width of the power line PL.

[0175] The width of the bridge pattern BRP may be equal to or different from the width of the power line PL. When the bridge pattern BRP has a width at least approximately the same as the considerable width of the power line PL, the bridge pattern BRP may electrically couple the first extension portion EP1 to the power line PL through a plurality of contact holes such as the first to fourth contact holes CT1 to CT4.

[0176] The additional component coupled to the power line PL can act as a parallel resistor that receives the voltage of the power (e.g., the first power ELVDD) supplied through the power line PL. As described above, when the first extension portion EP1 and the power line PL are electrically coupled to each other over a large area, the power line PL and the light-blocking layer PHL can be coupled to each other through a larger number of contact holes. In this case, the contact holes and the light-blocking layer PHL coupled to the power line PL through the corresponding contact holes can act as corresponding parallel resistors. Since the increase in the number of parallel resistors leads to a decrease in the total resistance coupled to the power line PL, the power supply through the power line PL can be efficiently performed, and as a result, the IR drop and / or voltage drop occurring in the display panel 110 can be improved or reduced. Therefore, the display device 10 can supply power through the power line PL with improved reliability, and the light-emitting element LD can emit light as needed. Therefore, the photosensor PHS can receive a desired amount of light to sense the fingerprint with improved accuracy.

[0177] Despite Figure 10A and Figure 10BThe power line PL and the bridge pattern BRP are shown as being coupled to each other via four contact holes, and the bridge pattern BRP and the first extension portion EP1 are shown as being coupled to each other via four contact holes, but exemplary embodiments are not limited thereto. In exemplary embodiments, the power line PL and the bridge pattern BRP and / or the bridge pattern BRP and the first extension portion EP1 may be coupled to each other via a greater number of contact holes or a smaller number of contact holes, respectively. In exemplary embodiments, the number of contact holes coupling the power line PL to the bridge pattern BRP and the number of contact holes coupling the bridge pattern BRP to the first extension portion EP1 may be equal to or different from each other.

[0178] Figure 11A yes Figure 1B FIG. 1 is an enlarged plan view of another exemplary embodiment of portion EA1 . Figure 11B It is along Figure 11A A sectional view taken along line II-II'. Figure 11A and Figure 11B In the description of Figure 10A and Figure 10B The components in the embodiments are the same as those in the embodiments, and their detailed descriptions will be omitted to avoid redundancy.

[0179] exist Figure 11A and Figure 11B In an embodiment, the power line PL and the first extension portion EP1 may be coupled to each other without passing through the bridge pattern BRP. To this end, the power line PL may include a protrusion pattern PP protruding toward the first extension portion EP1.

[0180] The protrusion pattern PP may extend from the power line PL toward the first extension portion EP1 in a direction perpendicular to the power line PL. The width of the protrusion pattern PP in the second direction DR2 may be substantially the same as the width of the power line PL. When the width of the protrusion pattern PP is substantially the same as the relatively large width of the power line PL, the protrusion pattern PP and the first extension portion EP1 may be electrically coupled to each other over a large area via a large number of contact holes CT1 to CT4. For example, the protrusion pattern PP and the first extension portion EP1 may be electrically coupled to each other via a plurality of contact holes CT1 to CT4 formed through the buffer layer 112, the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2.

[0181] exist Figure 11A and Figure 11B , an example is shown in which the protrusion pattern PP and the first extension portion EP1 are coupled to each other through four contact holes CT1 to CT4, but exemplary embodiments are not limited thereto. For example, the protrusion pattern PP and the first extension portion EP1 may be coupled to each other through a greater or smaller number of contact holes.

[0182] Figure 12A yes Figure 1B FIG. 1 is an enlarged plan view of yet another exemplary embodiment of portion EA1 . Figure 12B It is along Figure 12A A cross-sectional view taken along line III-III'. Figure 12A and Figure 12B In the description of Figure 10A and Figure 10B The components in the embodiments are the same as those in the embodiments, and their detailed descriptions will be omitted to avoid redundancy.

[0183] Reference Figure 12A and Figure 12B , the power line PL and the first extension portion EP1 may be coupled to each other without passing through the bridge pattern BRP. To this end, the first extension portion EP1 may include a protrusion pattern PP protruding toward the power line PL.

[0184] The protrusion pattern PP may extend from the first extension portion EP1 to the power line PL in a direction perpendicular to the first extension portion EP1. The width of the protrusion pattern PP in the second direction DR2 may be substantially the same as the width of the power line PL or the first extension portion EP1. When the width of the protrusion pattern PP is substantially the same as the relatively large width of the power line PL or the first extension portion EP1, the protrusion pattern PP and the power line PL can be electrically coupled to each other over a large area via a large number of contact holes CT1 to CT4. For example, the protrusion pattern PP and the first extension portion EP1 can be electrically coupled to each other via a plurality of contact holes CT1 to CT4 formed through the buffer layer 112, the gate insulating layer 113, the first interlayer insulating layer 114, the second interlayer insulating layer 115-1, and the third interlayer insulating layer 115-2.

[0185] Although Figure 12A and Figure 12B The protrusion pattern PP and the power line PL are shown to be coupled to each other through four contact holes CT1 to CT4, but exemplary embodiments are not limited thereto. The protrusion pattern PP and the power line PL may be coupled to each other through a greater or smaller number of contact holes.

[0186] 13A to 13D This is a graph for explaining changes in characteristics of transistors in the circuit element layer due to voltage applied to the light-blocking layer.

[0187] As above 10A to 12B As described, when the first power ELVDD of the power line PL is applied to the light-blocking layer PHL, electrical characteristics of at least one circuit element (eg, a transistor of the pixel PXL) provided in the circuit element layer BPL may be changed.

[0188] Reference Figure 13A Depending on the level of the voltage Vbg (e.g., the first power ELVDD) applied to the light-blocking layer PHL, the field effect of the light-blocking layer PHL may vary, and the hysteresis characteristics of the transistors provided in the circuit element layer BPL may change. For example, when the level of the voltage Vbg applied to the light-blocking layer PHL increases, the hysteresis characteristics of the corresponding transistors may decrease.

[0189] For details, refer to Figure 13B Depending on the level of the voltage Vbg applied to the light-blocking layer PHL, the field effect of the light-blocking layer PHL may change, and the threshold voltage characteristics of the transistors provided in the circuit element layer BPL may change. For example, when the level of the voltage Vbg applied to the light-blocking layer PHL increases, the threshold voltage of the corresponding transistor may decrease.

[0190] Reference Figure 13C and Figure 13D According to the level of the voltage Vbg applied to the light-blocking layer PHL, the gate drive range characteristics of the corresponding transistors provided in the circuit element layer BPL may change. For example, when the level of the voltage Vbg applied to the light-blocking layer PHL increases, the gate drive range of the corresponding transistors may decrease.

[0191] As described above, when the electrical characteristics of the transistor change according to the voltage level of the voltage Vbg applied to the light-blocking layer PHL, the amount of current flowing through the light-emitting element LD coupled to the transistor may change. When the amount of current flowing through the light-emitting element LD changes, the amount (or intensity) of light emitted from the light-emitting element LD may change. For example, when the voltage Vbg applied to the light-blocking layer PHL increases, the electrical characteristics of the transistor may change as follows. 13A to 13D , and this can cause the light-emitting element LD to receive more current. When the amount (or intensity) of light emitted from the light-emitting element LD increases, the amount (or intensity) of reflected light incident on the pinhole PIH in the light-blocking layer PHL can be increased. As a result, the amount (or intensity) of light that reaches the photosensor PHS of the sensor layer PSL after passing through the pinhole PIH can also be increased. Due to this, the photosensor PHS can output a sensing signal based on the optical characteristics of the larger amount of reflected light, thereby improving the accuracy of fingerprint sensing based on the sensing signal.

[0192] Figure 14 is a circuit diagram of an exemplary embodiment of a representative pixel constructed according to the principles of the invention. For ease of description, Figure 14An effective pixel PXL is shown that includes seven transistors and is coupled to an i-th scan line Si, an i-th emission control line Ei, and a j-th data line Dj. Here, the i-th scan line Si is arranged in the i-th horizontal pixel line (or referred to as the i-th horizontal pixel row), and the j-th data line Dj is arranged in the j-th vertical pixel line (or referred to as the j-th vertical pixel column) (where i and j are natural numbers). However, exemplary embodiments of the structure of the pixel PXL are not limited thereto.

[0193] Reference Figure 14 , the pixel PXL may include first to seventh transistors M1 to M7, a storage capacitor Cst, and a light emitting element LD.

[0194] A first electrode of the first transistor (driving transistor) M1 may be coupled to the first power supply ELVDD via the fifth transistor M5, and a second electrode of the first transistor M1 may be coupled to the anode electrode of the light-emitting element LD via the sixth transistor M6. Furthermore, a gate electrode of the first transistor M1 may be coupled to the first node N1. The first transistor M1 may control the amount of current flowing from the first power supply ELVDD to the second power supply ELVSS via the light-emitting element LD in response to the voltage of the first node N1.

[0195] A second transistor (switching transistor) M2 may be coupled between the jth data line Dj and the first electrode of the first transistor M1. Furthermore, a gate electrode of the second transistor M2 may be coupled to the i-th scan line Si. When a scan signal is supplied to the i-th scan line Si, the second transistor M2 is turned on, thereby electrically coupling the j-th data line Dj to the first electrode of the first transistor M1.

[0196] The third transistor M3 may be coupled between the second electrode of the first transistor M1 and the first node N1. Furthermore, the gate electrode of the third transistor M3 may be coupled to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the third transistor M3 is turned on, thereby electrically coupling the second electrode of the first transistor M1 to the first node N1. Therefore, when the third transistor M3 is turned on, the first transistor M1 may be coupled in the form of a diode.

[0197] A fourth transistor (initialization transistor) M4 may be coupled between the first node N1 and the initialization power supply Vint. Furthermore, a gate electrode of the fourth transistor M4 may be coupled to the (i-1)th scan line Si-1. The fourth transistor M4 is turned on when a scan signal is supplied to the (i-1)th scan line Si-1, thereby supplying the voltage of the initialization power supply Vint to the first node N1.

[0198] Figure 14An embodiment is shown in which the (i-1)th scan line Si-1 is used as an initialization control line for initializing the gate electrode (i.e., the first node N1) of the first transistor M1. However, exemplary embodiments are not limited thereto. For example, another control line such as the (i-2)th scan line Si-2 may be used as an initialization control line for initializing the gate electrode of the first transistor M1.

[0199] The fifth transistor M5 may be coupled between the first power source ELVDD and the first transistor M1. Furthermore, a gate electrode of the fifth transistor M5 may be coupled to the i-th emission control line Ei. When an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, the fifth transistor M5 may be turned off. Otherwise, the fifth transistor M5 may be turned on.

[0200] The sixth transistor M6 may be coupled between the first transistor M1 and the light-emitting element LD. Furthermore, a gate electrode of the sixth transistor M6 may be coupled to the i-th emission control line Ei. When an emission control signal having a gate-off voltage (e.g., a high-level voltage) is supplied to the i-th emission control line Ei, the sixth transistor M6 may be turned off. Otherwise, the sixth transistor M6 may be turned on.

[0201] The seventh transistor M7 can be coupled between the initialization power supply Vint and the first electrode of the light-emitting element LD (e.g., the anode electrode of the light-emitting element LD). In addition, the gate electrode of the seventh transistor M7 can be coupled to the i+1th scan line Si+1. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied to the i+1th scan line Si+1, the seventh transistor M7 is turned on, thereby supplying the voltage of the initialization power supply Vint to the anode electrode of the light-emitting element LD. Here, the voltage of the initialization power supply Vint can be set to be lower than the voltage of the data signal. In other words, the voltage of the initialization power supply Vint can be set to be equal to or lower than the lowest voltage of the data signal.

[0202] Figure 14 An example is shown in which the anode initialization control line coupled to the gate electrode of the seventh transistor M7 is the (i+1)th scan line Si+1. However, exemplary embodiments are not limited to this example. For example, the gate electrode of the seventh transistor M7 may be coupled to the (i)th scan line Si. In this case, when a scan signal having a gate-on voltage is supplied to the (i)th scan line Si, the voltage of the initialization power supply Vint may be supplied to the anode electrode of the light-emitting element LD via the seventh transistor M7.

[0203] The storage capacitor Cst may be coupled between the first power source ELVDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to the data signal and the threshold voltage of the first transistor M1.

[0204] The anode electrode of the light-emitting element LD may be coupled to the first transistor M1 via the sixth transistor M6, and the cathode electrode of the light-emitting element LD may be coupled to the second power supply ELVSS. The light-emitting element LD generates light having a predetermined brightness in response to the amount of current supplied from the first transistor M1. To enable current to flow into the light-emitting element LD, the voltage of the first power supply ELVDD may be set to be higher than the voltage of the second power supply ELVSS.

[0205] The structure of the pixel PXL is not limited to Figure 14 For example, a pixel circuit having any one of various currently known structures may be applied to the pixel PXL.

[0206] Figure 14 An example is shown in which the transistors M1 to M7 are P-type transistors, but the exemplary embodiment is not limited thereto. For example, at least one of the transistors M1 to M7 may be replaced with an N-type transistor.

[0207] Figure 15 is included Figure 14 1 is a plan view of an exemplary embodiment of a layout of pixels and a light blocking layer constructed according to the principles of the invention. Figure 16 It is along Figure 15 Specifically, Figure 15 Shows the settings Figures 1A to 1C A layout of the pixel PXL including the light transmission hole LTH overlapping the pinhole PIH of the light blocking layer PHL among any pixels PXL in the display area AA.

[0208] exist Figure 15 and Figure 16 In the figure, for the convenience of description, the scan line of the i-1th row is referred to as the i-1th scan line Si-1, the scan line of the i-th row is referred to as the i-th scan line Si, the scan line of the i+1th row is referred to as the i+1th scan line Si+1, the emission control line of the i-th row is referred to as the emission control line Ei, the data line of the j-th column is referred to as the data line Dj, and the power line of the j-th column (for example, the power line of the j-th column to which the power of the first power supply ELVDD is applied) is referred to as the power line PL.

[0209] Reference Figure 15 and Figure 16 The display device 10 may include pixels PXL disposed in the display area AA and lines for supplying drive signals and / or power to the pixels PXL. The lines may include scan lines Si-1, Si, and Si+1, data lines Dj, emission control lines Ei, power lines PL, and initialization power lines IPL.

[0210] The scan lines Si-1, Si, and Si+1 may extend along a first direction DR1 in the display area AA. The scan lines Si-1, Si, and Si+1 may include an i-1th scan line Si-1, an i-th scan line Si, and an i+1th scan line Si+1 sequentially arranged along a second direction DR2 intersecting the first direction DR1. The scan lines Si-1, Si, and Si+1 may receive scan signals applied thereto. For example, the i-1th scan line Si-1 may receive an i-1th scan signal applied thereto, the i-th scan line Si may receive an i-th scan signal applied thereto, and the i+1th scan line Si+1 may receive an i+1th scan signal applied thereto.

[0211] The emission control line Ei may extend in the first direction DR1 in the display area AA to be parallel to the scan lines Si-1, Si, and Si+1. The emission control line Ei may receive an emission control signal applied thereto.

[0212] The data line Dj may extend along the second direction DR2 in the display area AA. That is, the data line Dj may extend in a direction intersecting the control lines Si-1, Si, Si+1, and Ei (including the scan lines Si-1, Si, and Si+1 and the emission control line Ei). The data line Dj may receive a data signal applied thereto.

[0213] The power line PL may extend along the second direction DR2 in the display area AA, but is not limited thereto. The power line PL may be disposed to be spaced apart from the data line Dj and may receive power of the first power source ELVDD applied thereto.

[0214] The initialization power line IPL may extend along the first direction DR1 in the display area AA, but is not limited thereto. The initialization power line IPL may receive power of an initialization power source Vint applied thereto.

[0215] In an exemplary embodiment, the pixel PXL may include first to seventh transistors M1 to M7 , a storage capacitor Cst, and a light emitting element LD.

[0216] The first transistor M1 may include a first gate electrode GE1 , a first source electrode SE1 , and a first drain electrode DE1 .

[0217] In an exemplary embodiment, the first gate electrode GE1 may be disposed to overlap the first channel CH1 of the active pattern with at least one insulating layer (e.g., the gate insulating layer 113) interposed therebetween. The first gate electrode GE1 may be coupled to the third drain electrode DE3 (including DE3a and DE3b) of the third transistor M3 and the fourth source electrode SE4 (including SE4a and SE4b) of the fourth transistor M4.

[0218] The first gate electrode GE1 may be coupled to the third drain electrode DE3 and the fourth source electrode SE4 through a connection wire CNL. One end of the connection wire CNL may be coupled to the first gate electrode GE1 through a first contact hole CT1, and the other end of the connection wire CNL may be coupled to the third drain electrode DE3 and the fourth source electrode SE4 through a second contact hole CT2.

[0219] In an exemplary embodiment, the first channel CH1, the first source electrode SE1, and the first drain electrode DE1 may be formed of a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the first source electrode SE1 and the first drain electrode DE1 may be formed of a semiconductor pattern doped with impurities, and the first channel CH1 may be formed of a semiconductor pattern that is not doped with impurities.

[0220] The first channel CH1 has a shape extending in any direction and may have a shape that bends multiple times along the direction in which the first channel CH1 extends. When viewed from a plan view, the first channel CH1 may overlap the first gate electrode GE1. The first channel CH1 is formed longitudinally, thereby allowing the channel region of the first transistor M1 to be formed longitudinally. Therefore, the driving range of the gate voltage applied to the first transistor M1 is increased. Therefore, the grayscale of the light emitted from the light-emitting element LD can be finely controlled.

[0221] The first source electrode SE1 may be coupled to one end of the first channel CH1. The first source electrode SE1 may be coupled to the second drain electrode DE2 of the second transistor M2 and the fifth drain electrode DE5 of the fifth transistor M5. In an exemplary embodiment, the first drain electrode DE1 may be coupled to the other end of the first channel CH1. The first drain electrode DE1 may be coupled to the third source electrode SE3 of the third transistor M3 and the sixth source electrode SE6 of the sixth transistor M6.

[0222] The second transistor M2 may include a second gate electrode GE2 , a second channel CH2 , a second source electrode SE2 , and a second drain electrode DE2 .

[0223] The second gate electrode GE2 may be disposed to overlap the second channel CH2 while interposing at least one insulating layer (eg, the gate insulating layer 113 ) therebetween. The second gate electrode GE2 may be coupled to the i-th scan line Si.

[0224] The second channel CH2, the second source electrode SE2, and the second drain electrode DE2 may be formed of a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the second source electrode SE2 and the second drain electrode DE2 may be formed of a semiconductor pattern doped with impurities, and the second channel CH2 may be formed of a semiconductor pattern that is not doped with impurities. The second channel CH2 may be a portion overlapping the second gate electrode GE2.

[0225] One end of the second source electrode SE2 may be coupled to the second channel CH2, and the other end of the second source electrode SE2 may be coupled to the data line Dj through the sixth contact hole CT6. In an exemplary embodiment, one end of the second drain electrode DE2 may be coupled to the second channel CH2, and the other end of the second drain electrode DE2 may be coupled to the first source electrode SE1 of the first transistor M1 and the fifth drain electrode DE5 of the fifth transistor M5.

[0226] The third transistor M3 may be configured such that the third transistor M3 has a dual-gate structure to prevent leakage current. That is, the third transistor M3 may include a 3a-th transistor M3a and a 3b-th transistor M3b. The 3a-th transistor M3a may include a 3a-th gate electrode GE3a, a 3a-th active pattern (or 3a-th channel) CH3a, a 3a-th source electrode SE3a, and a 3a-th drain electrode DE3a. The 3b-th transistor M3b may include a 3b-th gate electrode GE3b, a 3b-th active pattern (or 3b-th channel) CH3b, a 3b-th source electrode SE3b, and a 3b-th drain electrode DE3b. Hereinafter, the 3a gate electrode GE3a and the 3b gate electrode GE3b are referred to as the third gate electrode GE3, the 3a active pattern CH3a and the 3b active pattern CH3b are referred to as the third channel CH3, the 3a source electrode SE3a and the 3b source electrode SE3b are referred to as the third source electrode SE3, and the 3a drain electrode DE3a and the 3b drain electrode DE3b are referred to as the third drain electrode DE3.

[0227] The third gate electrode GE3 may be disposed to overlap the third channel CH3 while having at least one insulating layer (eg, the gate insulating layer 113 ) interposed therebetween. The third gate electrode GE3 may be coupled to the i-th scan line Si.

[0228] The third channel CH3, the third source electrode SE3, and the third drain electrode DE3 may be formed of a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the third source electrode SE3 and the third drain electrode DE3 may be formed of a semiconductor pattern doped with impurities, and the third channel CH3 may be formed of a semiconductor pattern that is not doped with impurities. The third channel CH3 is a portion that overlaps the third gate electrode GE3.

[0229] One end of the third source electrode SE3 may be coupled to the third channel CH3, and the other end of the third source electrode SE3 may be coupled to the first drain electrode DE1 of the first transistor M1 and the sixth source electrode SE6 of the sixth transistor M6. In an exemplary embodiment, one end of the third drain electrode DE3 may be coupled to the third channel CH3, and the other end of the third drain electrode DE3 may be coupled to the fourth source electrode SE4 of the fourth transistor M4. In addition, the third drain electrode DE3 may be coupled to the connection line CNL and may be coupled to the first gate electrode GE1 of the first transistor M1 through the second contact hole CT2 and the first contact hole CT1.

[0230] The fourth transistor M4 may be configured such that the fourth transistor M4 has a dual-gate structure to prevent leakage current. That is, the fourth transistor M4 may include a 4a-th transistor M4a and a 4b-th transistor M4b. The 4a-th transistor M4a may include a 4a-th gate electrode GE4a, a 4a-th active pattern (or a 4a-th channel) CH4a, a 4a-th source electrode SE4a, and a 4a-th drain electrode DE4a. The 4b-th transistor M4b may include a 4b-th gate electrode GE4b, a 4b-th active pattern (or a 4b-th channel) CH4b, a 4b-th source electrode SE4b, and a 4b-th drain electrode DE4b. Hereinafter, the 4a-th gate electrode GE4a and the 4b-th gate electrode GE4b are referred to as the fourth gate electrode GE4, the 4a-th active pattern CH4a and the 4b-th active pattern CH4b are referred to as the fourth channel CH4, the 4a-th source electrode SE4a and the 4b-th source electrode SE4b are referred to as the fourth source electrode SE4, and the 4a-th drain electrode DE4a and the 4b-th drain electrode DE4b are referred to as the fourth drain electrode DE4.

[0231] The fourth gate electrode GE4 may be disposed to overlap the fourth channel CH4 while interposing at least one insulating layer (eg, the gate insulating layer 113 ) therebetween. The fourth gate electrode GE4 may be coupled to the (i-1)th scan line Si-1.

[0232] The fourth channel CH4, the fourth source electrode SE4, and the fourth drain electrode DE4 may be formed of a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the fourth source electrode SE4 and the fourth drain electrode DE4 may be formed of a semiconductor pattern doped with impurities, and the fourth channel CH4 may be formed of a semiconductor pattern that is not doped with impurities. The fourth channel CH4 is a portion that overlaps the fourth gate electrode GE4.

[0233] One end of the fourth source electrode SE4 may be coupled to the fourth channel CH4, and the other end of the fourth source electrode SE4 may be coupled to the third drain electrode DE3 of the third transistor M3. Furthermore, the fourth source electrode SE4 may be coupled to the connection line CNL and may be coupled to the first gate electrode GE1 of the first transistor M1 through the second contact hole CT2 and the first contact hole CT1. One end of the fourth drain electrode DE4 may be coupled to the fourth channel CH4, and the other end of the fourth drain electrode DE4 may be coupled to the seventh drain electrode DE7 of the seventh transistor M7 of the pixel PXL in the (i-1)th row. The fourth drain electrode DE4 may be coupled to the auxiliary connection line AUX and may be coupled to the initialization power line IPL through the ninth contact hole CT9 and the eighth contact hole CT8.

[0234] The fifth transistor M5 may include a fifth gate electrode GE5 , a fifth channel CH5 , a fifth source electrode SE5 , and a fifth drain electrode DE5 .

[0235] The fifth gate electrode GE5 may be disposed to overlap the fifth channel CH5 while having at least one insulating layer (eg, the gate insulating layer 113 ) interposed therebetween. The fifth gate electrode GE5 may be coupled to the emission control line Ei.

[0236] The fifth channel CH5, the fifth source electrode SE5, and the fifth drain electrode DE5 may be formed of a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the fifth source electrode SE5 and the fifth drain electrode DE5 may be formed of a semiconductor pattern doped with impurities, and the fifth channel CH5 may be formed of a semiconductor pattern that is not doped with impurities. The fifth channel CH5 is a portion that overlaps the fifth gate electrode GE5.

[0237] One end of the fifth source electrode SE5 may be coupled to the fifth channel CH5, and the other end of the fifth source electrode SE5 may be coupled to the power line PL through the fifth contact hole CT5. In an exemplary embodiment, one end of the fifth drain electrode DE5 may be coupled to the fifth channel CH5, and the other end of the fifth drain electrode DE5 may be coupled to the first source electrode SE1 of the first transistor M1 and the second drain electrode DE2 of the second transistor M2.

[0238] The sixth transistor M6 may include a sixth gate electrode GE6 , a sixth channel CH6 , a sixth source electrode SE6 , and a sixth drain electrode DE6 .

[0239] The sixth gate electrode GE6 may be disposed to overlap the sixth channel CH6 while having at least one insulating layer (eg, the gate insulating layer 113 ) interposed therebetween. The sixth gate electrode GE6 may be coupled to the emission control line Ei.

[0240] The sixth channel CH6, the sixth source electrode SE6, and the sixth drain electrode DE6 may be formed from a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the sixth source electrode SE6 and the sixth drain electrode DE6 may be formed from a semiconductor pattern doped with impurities, and the sixth channel CH6 may be formed from a semiconductor pattern that is not doped with impurities. The sixth channel CH6 is a portion that overlaps the sixth gate electrode GE6.

[0241] One end of the sixth source electrode SE6 may be coupled to the sixth channel CH6, and the other end of the sixth source electrode SE6 may be coupled to the first drain electrode DE1 of the first transistor M1 and the third source electrode SE3 of the third transistor M3. In an exemplary embodiment, one end of the sixth drain electrode DE6 may be coupled to the sixth channel CH6, and the other end of the sixth drain electrode DE6 may be coupled to the seventh source electrode SE7 of the seventh transistor M7.

[0242] The seventh transistor M7 may include a seventh gate electrode GE7 , a seventh channel CH7 , a seventh source electrode SE7 , and a seventh drain electrode DE7 .

[0243] The seventh gate electrode GE7 may be disposed to overlap the seventh channel CH7 while having at least one insulating layer (eg, the gate insulating layer 113 ) interposed therebetween. The seventh gate electrode GE7 may be coupled to the (i+1)th scan line Si+1.

[0244] The seventh channel CH7, the seventh source electrode SE7, and the seventh drain electrode DE7 may be formed of a semiconductor pattern that is not doped with impurities or is doped with impurities. For example, the seventh source electrode SE7 and the seventh drain electrode DE7 may be formed of a semiconductor pattern doped with impurities, and the seventh channel CH7 may be formed of a semiconductor pattern that is not doped with impurities. The seventh channel CH7 is a portion that overlaps the seventh gate electrode GE7.

[0245] One end of the seventh source electrode SE7 may be coupled to the seventh channel CH7, and the other end of the seventh source electrode SE7 may be coupled to the sixth drain electrode DE6 of the sixth transistor M6. In an exemplary embodiment, one end of the seventh drain electrode DE7 may be coupled to the seventh channel CH7, and the other end of the seventh drain electrode DE7 may be coupled to the auxiliary connection line AUX and may be coupled to the initialization power line IPL through the ninth contact hole CT9 and the eighth contact hole CT8.

[0246] The storage capacitor Cst may include a first capacitor electrode LE and a second capacitor electrode UE. In an exemplary embodiment, the first capacitor electrode LE may be a lower electrode of the storage capacitor Cst and may be integrated with the first gate electrode GE1 of the first transistor M1. In an exemplary embodiment, the second capacitor electrode UE may be an upper electrode of the storage capacitor Cst and may overlap with the first gate electrode GE1. Furthermore, when viewed from a plan view, the second capacitor electrode UE may cover at least one area of ​​the first capacitor electrode LE. The capacitance of the storage capacitor Cst may be increased by expanding the area where the first capacitor electrode LE and the second capacitor electrode UE overlap each other.

[0247] The second capacitor electrode UE may extend in the first direction DR1. In an exemplary embodiment, a voltage having the same level as the voltage of the first power source ELVDD may be applied to the second capacitor electrode UE. The second capacitor electrode UE may include an opening OPN in a region where a first contact hole CT1 is formed, and the first gate electrode GE1 contacts the connection line CNL in the first contact hole CT1.

[0248] The light-emitting element LD may include a first electrode (e.g., an anode electrode) AD, a second electrode (e.g., a cathode electrode) CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD. In an exemplary embodiment, the first electrode AD and the second electrode CD may be disposed so as to overlap each other in the emission region of the light-emitting element layer LDL, and the emission layer EML may be disposed in the emission region. That is, the emission region of each pixel PXL may be a region in which the first electrode AD of the light-emitting element LD, the emission layer EML of the light-emitting element LD, and the second electrode CD of the light-emitting element LD are disposed so as to overlap each other.

[0249] The first electrode AD may be disposed in a predetermined emission region. The first electrode AD may be coupled to the seventh source electrode SE7 of the seventh transistor M7 and the sixth drain electrode DE6 of the sixth transistor M6 through the fourth contact hole CT4 and the seventh contact hole CT7. A first bridge pattern BRP1 may be disposed between the fourth contact hole CT4 and the seventh contact hole CT7. The first bridge pattern BRP1 may couple the sixth drain electrode DE6, the seventh source electrode SE7, and the first electrode AD.

[0250] Hereinafter, a stack structure (cross-sectional structure) of the pixel PXL and the display area AA including the pixel PXL will be described.

[0251] First, a buffer layer 112 may be provided on the first surface of the first substrate SUB1. Thus, a phenomenon in which metal atoms or impurities diffuse from the first substrate SUB1 (e.g., degassing) may be prevented. In addition, when the first substrate SUB1 has an irregular surface flatness, the buffer layer 112 may be used to improve the surface flatness of the first substrate SUB1. The buffer layer 112 may include an inorganic material (such as an oxide or nitride), an organic material, or an inorganic / organic compound, and may be formed of a single layer or a multilayer structure of an inorganic material and an organic material. For example, the buffer layer 112 may have a three-layer or more layer structure formed of silicon oxide, silicon nitride, and silicon oxide.

[0252] The active pattern may be disposed on the buffer layer 112. In an exemplary embodiment, the active pattern may include first to seventh channels CH1 to CH7. The first to seventh channels CH1 to CH7 may be formed of a semiconductor material.

[0253] The gate insulating layer 113 may be disposed on the buffer layer 112 on which the first to seventh channels CH1 to CH7 are disposed. In an exemplary embodiment, the gate insulating layer 113 may be a gate insulating layer interposed between the active patterns of the first to seventh transistors M1 to M7 disposed in the pixel PXL and the gate electrodes GE1 to GE7.

[0254] The gate insulating layer 113 may include one or more inorganic layers and / or organic layers. For example, the gate insulating layer 113 may be made of a material including SiO x 、SiN x For example, the gate insulating layer 113 may include an inorganic insulating material (such as SiO x 、SiN x 、SiON、SiOF、AlO x etc.) or an organic insulating material, and may have a single-layer or multi-layer structure including at least one of these materials.

[0255] In an exemplary embodiment, the gate insulating layer 113 may have a limited thickness falling within a predetermined range to easily drive the transistors M1 to M7. For example, the thickness of the gate insulating layer 113 may be in the range from to In the range of, for example, about However, the thickness of the gate insulating layer 113 is not limited thereto.

[0256] The first conductive layer may be provided on the gate insulating layer 113. In an exemplary embodiment, the first conductive layer may be a first gate layer. The control lines Si-1, Si, Si+1, and Ei and the gate electrodes GE1 to GE7 may be provided on the first conductive layer. In addition, one electrode of the storage capacitor Cst (e.g., the first capacitor electrode LE) may be provided on the first conductive layer. Specifically, the i-1th scan line Si-1, the i-th scan line Si, the i+1th scan line Si+1, the emission control line Ei, and the first gate electrode GE1 to the seventh gate electrode GE7 may be provided on the first conductive layer on the gate insulating layer 113. In an exemplary embodiment, the first gate electrode GE1 may become the first capacitor electrode LE of the storage capacitor Cst. That is, the first gate electrode GE1 and the first capacitor electrode LE may be integrated with each other.

[0257] The control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE serving as the lower electrode of the storage capacitor Cst disposed in (or on) the first conductive layer may be formed of the same material. For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE serving as the lower electrode of the storage capacitor Cst may be formed of a predetermined first gate metal.

[0258] Examples of materials for the first gate metal include Ti, Cu, Mo, Al, Au, Cr, TiN, Ag, Pt, Pd, Ni, Sn, Co, Rh, Ir, Fe, Ru, Os, Mn, W, Nb, Ta, Bi, Sb, and Pb, and various metals may be used. Examples of alloys for forming the first gate metal include MoTi, AlNiLa, and various alloys may be used. Examples of multilayer structures for forming the first gate metal include Ti / Cu, Ti / Au, Mo / Al / Mo, ITO / Ag / ITO, TiN / Ti / Al / Ti, and TiN / Ti / Cu / Ti, and various conductive materials having a multilayer structure may be used.

[0259] The material forming the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE provided on the first conductive layer is not necessarily limited to metal. That is, any type of material may be used as the material forming the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE, as long as the material can provide sufficient conductivity to smoothly drive the pixel PXL.

[0260] For example, the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE can be formed from a conductive polymer or a conductive metal oxide. Examples of conductive polymers used to form the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE include polythiophene compounds, polypyrrole compounds, polyaniline compounds, polyacetylene compounds, polyphenylene compounds, and composites thereof. Specifically, among the polythiophene compounds, PEDOT / PSS can be used. Examples of conductive metal oxides used to form the control lines Si-1, Si, Si+1, and Ei, the gate electrodes GE1 to GE7, and / or the first capacitor electrode LE include ITO, IZO, AZO, ITZO, ZnO, SnO2, and the like.

[0261] The first interlayer insulating layer 114 may be disposed on the first conductive layer. In an exemplary embodiment, the first interlayer insulating layer 114 may be a first interlayer insulating layer disposed between the first capacitor electrode LE and the second capacitor electrode UE. In an exemplary embodiment, the first interlayer insulating layer 114 may have a limited thickness falling within a predetermined range to ensure sufficient capacitance of the storage capacitor Cst in a limited area. In an exemplary embodiment, the first interlayer insulating layer 114 may have a thickness similar to that of the gate insulating layer 113. For example, the thickness of the first interlayer insulating layer 114 may be between 100 nm and 100 nm. to In the range of, for example, about However, the thickness of the first interlayer insulating layer 114 is not limited thereto.

[0262] The first interlayer insulating layer 114 may include one or more inorganic layers and / or organic layers. For example, the first interlayer insulating layer 114 may be made of a material including SiO x 、SiN x For example, the first interlayer insulating layer 114 may include an inorganic insulating material (such as SiO x 、SiN x 、SiON、SiOF、AlO x etc.) or an organic insulating material, and may have a single-layer or multi-layer structure including at least one of these materials.

[0263] A second conductive layer may be disposed on the first interlayer insulating layer 114. In exemplary embodiments, the second conductive layer may be a second gate layer.

[0264] The second capacitor electrode UE, the initialization power line IPL, and the second bridge pattern BRP2 may be disposed on the second conductive layer.

[0265] In an exemplary embodiment, the second capacitor electrode UE may cover the first capacitor electrode LE. The second capacitor electrode UE overlaps the first capacitor electrode LE with the first interlayer insulating layer 114 interposed therebetween, whereby the second capacitor electrode UE and the first capacitor electrode LE may form a storage capacitor Cst.

[0266] The initialization power line IPL may extend in the first direction DR1 in the display area AA, but is not limited thereto. The initialization power line IPL may receive power of an initialization power source Vint applied thereto.

[0267] The second bridge pattern BRP2 may include a first region extending parallel to the first direction DR1 in the display area AA and a second region extending parallel to the second direction DR2 from one end of the first region, but the form of the second bridge pattern BRP2 is not limited thereto. The second bridge pattern BRP2 may be a pattern configured as a medium for electrically coupling the light-blocking layer PHL and the power line PL to each other. The second bridge pattern BRP2 (such as the second region of the second bridge pattern BRP2) may be coupled to the power line PL via a tenth contact hole CT10 formed through the second interlayer insulating layer 115, and may be coupled to the light-blocking layer PHL via an eleventh contact hole CT11 formed through the buffer layer 112, the gate insulating layer 113, and the first interlayer insulating layer 114.

[0268] The second capacitor electrode UE, the initialization power line IPL, and the second bridge pattern BRP2 provided on the second conductive layer can be formed of the same material. For example, the second capacitor electrode UE, the initialization power line IPL, and the second bridge pattern BRP2 can be formed of a predetermined second gate metal. In an exemplary embodiment, the second gate metal can be one of the metal materials described as examples of the first gate metal, but the second gate metal is not limited thereto. In addition, the material of the second capacitor electrode UE, the initialization power line IPL, and the second bridge pattern BRP2 provided on the second conductive layer is not necessarily limited to metal. That is, any material that can provide sufficient conductivity to smoothly drive the pixel PXL can be used as the material of the second capacitor electrode UE, the initialization power line IPL, and the second bridge pattern BRP2. For example, the second capacitor electrode UE, the initialization power line IPL, and the second bridge pattern BRP2 provided on the second conductive layer can be formed of a conductive polymer or a conductive metal oxide.

[0269] The second interlayer insulating layer 115 may be disposed on the second conductive layer. In an exemplary embodiment, the second interlayer insulating layer 115 may be a second interlayer insulating layer. The second interlayer insulating layer 115 may have a thickness greater than that of the gate insulating layer 113 and the first interlayer insulating layer 114. For example, the thickness of the second interlayer insulating layer 115 may be equal to or greater than the sum of the thickness of the gate insulating layer 113 and the thickness of the first interlayer insulating layer 114. For example, the second interlayer insulating layer 115 may have a thickness of approximately The thickness of the second interlayer insulating layer 115 is not limited thereto. When the second interlayer insulating layer 115 is formed to have a thickness greater than the sum of the thickness of the gate insulating layer 113 and the thickness of the first interlayer insulating layer 114, electrical stability can be ensured between components disposed below the second interlayer insulating layer 115 and components disposed above the second interlayer insulating layer 115. Therefore, short-circuit defects can be effectively prevented.

[0270] The second interlayer insulating layer 115 may include one or more inorganic layers and / or organic layers. For example, the second interlayer insulating layer 115 may be made of a material including SiO x 、SiN x For example, the second interlayer insulating layer 115 may include an inorganic insulating material (such as SiO x 、SiN x 、SiON、SiOF、AlO x etc.) or an organic insulating material, and may have a single-layer or multi-layer structure including at least one of these materials.

[0271] A third conductive layer may be disposed on the second interlayer insulating layer 115. In exemplary embodiments, the third conductive layer may be a source drain layer.

[0272] The data line Dj, the power line PL, the connection line CNL, the first bridge pattern BRP1, and the auxiliary connection line AUX may be disposed on the third conductive layer.

[0273] The data line Dj may be coupled to the second source electrode SE2 through a sixth contact hole CT6 formed through the gate insulating layer 113 , the first interlayer insulating layer 114 , and the second interlayer insulating layer 115 .

[0274] The power line PL may be coupled to the second capacitor electrode UE, which is the upper electrode of the storage capacitor Cst, through a third contact hole CT3 formed through the second interlayer insulating layer 115. In addition, the power line PL may be coupled to the fifth source electrode SE5 through a fifth contact hole CT5 formed through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0275] The power line PL may be further coupled to the second bridge pattern BRP2 through a tenth contact hole CT10 formed through the second interlayer insulating layer 115. Since the second bridge pattern BRP2 is coupled to the light blocking layer PHL through the eleventh contact hole CT11, the power line PL may be electrically coupled to the light blocking layer PHL.

[0276] The connection line CNL may be coupled to the first gate electrode GE1 through a first contact hole CT1 formed through the first interlayer insulating layer 114 and the second interlayer insulating layer 115. In addition, the connection line CNL may be coupled to the third drain electrode DE3 and the fourth source electrode SE4 through a second contact hole CT2 formed through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0277] The first bridge pattern BRP1 may be a pattern provided as a medium for coupling the sixth drain electrode DE6 and the first electrode AD between the sixth drain electrode DE6 and the first electrode AD. Such a first bridge pattern BRP1 may be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through a fourth contact hole CT4 formed through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0278] The auxiliary connection line AUX may be coupled to the initialization power line IPL through an eighth contact hole CT8 formed through the second interlayer insulating layer 115. In addition, the auxiliary connection line AUX may be coupled to the seventh drain electrode DE7 through a ninth contact hole CT9 formed through the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115.

[0279] The data line Dj, the power line PL, the connection line CNL, the first bridge pattern BRP1, and / or the auxiliary connection line AUX arranged on the third conductive layer may be formed of the same material. For example, the data line Dj, the power line PL, the connection line CNL, the first bridge pattern BRP1, and / or the auxiliary connection line AUX may be formed of a predetermined source / drain metal.

[0280] The source / drain metal may be, but is not limited to, one of the metal materials described above as examples of the first gate metal and / or the second gate metal. Furthermore, the material forming the data line Dj, the power line PL, the connection line CNL, the first bridge pattern BRP1, and / or the auxiliary connection line AUX arranged on the third conductive layer need not be limited to metal. That is, any type of material may be used as the material forming the data line Dj, the power line PL, the connection line CNL, the first bridge pattern BRP1, and / or the auxiliary connection line AUX, as long as the material can provide sufficient conductivity to smoothly drive the pixel PXL. For example, the data line Dj, the power line PL, the connection line CNL, the first bridge pattern BRP1, and / or the auxiliary connection line AUX may be formed of a conductive polymer or a conductive metal oxide.

[0281] At least two of the first gate metal, the second gate metal, and the source / drain metal may be made of the same material. For example, even if the first gate metal and the second gate metal are arranged on different layers, the first gate metal and the second gate metal may be made of the same material. However, exemplary embodiments are not limited thereto. For example, in other embodiments, the first gate metal, the second gate metal, and the source / drain metal may be made of different materials.

[0282] The protective layer 116 may be disposed on the third conductive layer. In an exemplary embodiment, the protective layer 116 may include a passivation layer and / or a planarization layer. The protective layer 116 may include a seventh contact hole CT7 for exposing a portion of the first bridge pattern BRP1.

[0283] The light emitting element LD may be disposed on the protective layer 116. The light emitting element LD may include a first electrode AD, a second electrode CD, and an emission layer EML disposed between the first electrode AD and the second electrode CD.

[0284] In an exemplary embodiment, the protective layer 116 may have to The thickness, for example, is about However, the thickness of the protective layer 116 is not limited thereto.

[0285] At least one of the first electrode AD and the second electrode CD may be a transmissive electrode. For example, when the light-emitting element LD is a bottom-emitting organic light-emitting element, the first electrode AD may be a transmissive electrode, and the second electrode CD may be a reflective electrode. When the light-emitting element LD is a top-emitting organic light-emitting element, the first electrode AD may be a reflective electrode, and the second electrode CD may be a transmissive electrode. Furthermore, when the light-emitting element LD is a double-sided emitting organic light-emitting element, both the first electrode AD and the second electrode CD may be transmissive electrodes. Hereinafter, the case where the light-emitting element LD is a top-emitting organic light-emitting element and the first electrode AD is an anode electrode will be described by way of example. Furthermore, in the illustrated embodiment, the light-emitting element LD is used as a light source, but exemplary embodiments are not limited thereto. For example, the light-emitting element LD may be replaced with another type of light-emitting element.

[0286] The first electrode AD may be disposed on the protective layer 116. The first electrode AD may be coupled to the first bridge pattern BRP1 through the seventh contact hole CT7 formed through the protective layer 116. Since the first bridge pattern BRP1 is coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through the fourth contact hole CT4, the first electrode AD may be ultimately coupled to the sixth drain electrode DE6 and the seventh source electrode SE7 through the first bridge pattern BRP1.

[0287] The first electrode AD may include a reflective layer capable of reflecting light and a transparent conductive layer disposed on the top or bottom of the reflective layer. At least one of the transparent conductive layer and the reflective layer may be coupled to the sixth drain electrode DE6 and the seventh source electrode SE7.

[0288] The reflective layer may include a material capable of reflecting light. For example, the reflective layer may include at least one of aluminum (Al), silver (Ag), chromium (Cr), molybdenum (Mo), platinum (Pt), nickel (Ni), and alloys thereof.

[0289] The transparent conductive layer may include a transparent conductive oxide. For example, the transparent conductive layer may include at least one transparent conductive oxide selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium-doped zinc oxide (GZO), zinc tin oxide (ZTO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0290] The emission layer EML can be provided on the exposed surface of the first electrode AD. The emission layer EML can have a multilayer thin film structure including at least a light generating layer (LGL). For example, the emission layer EML can include a hole injection layer (HIL), a hole transport layer (HTL), a light generating layer, a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL), holes are injected into the hole injection layer (HIL), the hole transport layer (HTL) has excellent hole transport performance and limits the movement of electrons in the light generating layer that have not yet been combined with holes, thereby increasing the chance of recombination between holes and electrons, the light generating layer emits light through the recombination between the injected electrons and holes, the hole blocking layer (HBL) limits the movement of holes in the light generating layer that have not yet been combined with electrons, the electron transport layer (ETL) is configured to smoothly transfer electrons to the light generating layer, and the electron injection layer (EIL) is injected with electrons.

[0291] The color of the light generated from the light generation layer may be, but is not limited to, one of red, green, blue, and white. For example, the color of the light generated from the light generation layer of the emission layer EML may be one of magenta, cyan, and yellow.

[0292] The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may be common layers coupled between adjacent emission regions.

[0293] The second electrode CD may be a semi-transmissive reflective layer. For example, the second electrode CD may be a thin-film metal layer having a thickness that allows light emitted from the emission layer EML to pass through the second electrode CD. The second electrode CD may allow a portion of light generated from the emission layer EML to pass through the second electrode CD, while reflecting the remaining portion of the light generated from the emission layer EML.

[0294] In an exemplary embodiment, the second electrode CD may include a material having a lower work function than that of the transparent conductive layer. For example, the second electrode CD may include at least one of molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), and alloys thereof.

[0295] A portion of the light emitted from the emission layer EML may not pass through the second electrode CD, and the light reflected from the second electrode CD may be reflected again from the reflective layer. In other words, the light emitted from the emission layer EML may resonate between the reflective layer and the second electrode CD. Due to the resonance of light, the light extraction efficiency of the light emitting element LD can be enhanced.

[0296] A pixel defining layer (or bank layer) 117 for defining an emission region of each pixel PXL may be disposed on the first substrate SUB1 on which the first electrode AD is disposed. The pixel defining layer 117 may expose a top surface of the first electrode AD and protrude from the first substrate SUB1 along the periphery of each emission region.

[0297] The emission layer EML may be provided in an emission region of each pixel PXL surrounded by the pixel defining layer 117. The second electrode CD may be provided on the emission layer EML. Any one of the first electrode AD and the second electrode CD may be an anode electrode, and the other may be a cathode electrode. For example, the first electrode AD may be an anode electrode, and the second electrode CD may be a cathode electrode.

[0298] The pixel defining layer 117 may include an organic insulating material. For example, the pixel defining layer 117 may include at least one of polystyrene, polymethyl methacrylate (PMMA), polyacrylonitrile (PAN), polyamide (PA), polyimide (PI), polyarylene ether (PAE), heterocyclic polymer, parylene, epoxy resin, benzocyclobutene (BCB), siloxane-based resin, and silane-based resin.

[0299] A first protective layer PTL1 covering the second electrode CD may be provided on the second electrode CD. The first protective layer PTL1 may be formed of a thin film encapsulation layer. In an exemplary embodiment, the thin film encapsulation layer may be replaced with another type of encapsulation layer or an encapsulation substrate or at least one protective layer.

[0300] The thin film encapsulation layer can prevent the penetration of oxygen and moisture. For this operation, the thin film encapsulation layer can include an inorganic layer. The inorganic layer can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, zirconium oxide, and tin oxide.

[0301] The corresponding circuit elements and lines arranged on the first surface of the first substrate SUB1 within the range from the buffer layer 112 to the protective layer 116 may constitute a circuit element layer BPL of the display device 10 and / or the fingerprint sensor. The light-emitting elements LD arranged in the corresponding pixels PXL within the range from the first electrode AD to the second electrode CD and the pixel defining layer 117 arranged therebetween may constitute a light-emitting element layer LDL of the display device 10 and / or the fingerprint sensor.

[0302] Further references Figure 15 and Figure 16 The pixel PXL may include a light-transmitting hole LTH formed in at least one conductive layer of the circuit element layer BPL. The display area AA may include a plurality of pixels PXL, each pixel PXL including the light-transmitting hole LTH.

[0303] The light-transmitting hole LTH may be formed as a region overlapping the light-transmitting region defined by the corresponding conductive layer of the circuit element layer BPL. For example, the light-transmitting hole LTH may be formed by a light-transmitting region of multiple layers, the multiple layers including at least two of a semiconductor layer in which the active pattern of the circuit element layer BPL is arranged, a first conductive layer in which the gate electrodes GE1 to GE7 are arranged, a second conductive layer in which the second capacitor electrode UE and the second bridge pattern BRP2 are arranged, and a third conductive layer in which the power line PL and the like are arranged.

[0304] According to the illustrated embodiment, a light-transmitting hole array for receiving reflected light can be formed to be integrated with the light-emitting element layer LDL and the circuit element layer BPL without forming an additional layer in the circuit element layer BPL. Therefore, the module thickness of the display device 10 can be reduced.

[0305] The arrangement and shape of the light transmission hole LTH are not limited to Figure 15 and Figure 16 In an exemplary embodiment, each light-transmitting hole LTH may be formed in another region, for example, a region including the opening OPN formed in the second capacitor electrode UE. In such an exemplary embodiment, the layout structure may be modified in various ways so that the conductive layer is not provided in the light-transmitting hole LTH.

[0306] The size (width or diameter) of the light transmission hole LTH may be determined according to the size of the light transmission area. For example, the width of the light transmission hole LTH may be determined as the minimum width among the widths of the light transmission area.

[0307] The light transmission area forming the light transmission hole LTH may be formed such that it at least partially overlaps the pinhole PIH of the light blocking layer PHL. In exemplary embodiments, the width of the light transmission hole LTH may be equal to or different from the width of the pinhole PIH.

[0308] The light-transmitting hole LTH may be formed in all or at least some of the pixels PXL arranged in the display area AA. For example, the light-transmitting hole LTH may be formed in the pixel PXL arranged in the display area AA that overlaps the pinhole PIH formed in the light-blocking layer PHL. In an exemplary embodiment, in the pixel PXL in which the light-transmitting hole LTH is not formed, the distance between the emission control line Ei and the initialization power line IPL and / or the distance between the fifth source electrode SE5 and the sixth drain electrode DE6 may be shorter than those distances in the pixel PXL in which the light-transmitting hole LTH is formed.

[0309] A light blocking layer PHL may be interposed between the first substrate SUB1 and the buffer layer 112 to selectively transmit incident light. The light blocking layer PHL may be an opaque metal layer including one or more pinholes PIH.

[0310] The light-blocking layer PHL can be coupled to the second bridge pattern BRP2 via an eleventh contact hole CT11 formed through the buffer layer 112, the gate insulating layer 113, and the first interlayer insulating layer 114. Since the second bridge pattern BRP2 can be coupled to the power line PL via the tenth contact hole CT10, the light-blocking layer PHL can be electrically coupled to the power line PL. Therefore, power applied through the power line PL (e.g., power from the first power source ELVDD) can be supplied to the light-blocking layer PHL. The power applied to the light-blocking layer PHL can change the characteristics of the transistors arranged in the circuit element layer BPL, and the light-emitting element layer LDL can receive increased current, thereby increasing the intensity of light emitted from the emission layer EML. The intensity of light that has reached the photosensor PHS disposed under the first substrate SUB1 after passing through the light-transmitting hole LTH and the pinhole PIH can then be increased, thereby improving the accuracy of fingerprint sensing performed by the photosensor PHS.

[0311] In an exemplary embodiment, the pinholes PIH in the light-blocking layer PHL may be arranged at intervals lower than the intervals between the pixels PXL arranged in the display area AA. In this case, some of the pixels PXL arranged in the display area AA may include light-transmitting holes LTH overlapping the corresponding pinholes PIH, while other pixels PXL may not overlap the pinholes PIH and may not include light-transmitting holes LTH. In this embodiment, the second bridge pattern BRP2 may be provided in all pixels PXL. That is, even in pixels PXL that do not overlap the pinholes PIH, the power line PL can be electrically coupled to the light-blocking layer PHL through the second bridge pattern BRP2. Therefore, power supply to the light-blocking layer PHL can be performed more efficiently. However, exemplary embodiments are not limited to this, and the second bridge pattern BRP2 may not be provided in some pixels PXL (for example, pixels PXL in which the light-transmitting holes LTH are not formed).

[0312] Figure 17 is included Figure 14 1 is a plan view of another exemplary embodiment of a layout of pixels and a light-blocking layer constructed according to the principles of the invention. Figure 18 It is along Figure 17 In detail, Figure 17 Shown is the layout Figures 1A to 1C A layout of the pixel PXL including the light transmission hole LTH overlapping the pinhole PIH of the light blocking layer PHL among any pixels PXL in the display area AA.

[0313] exist Figure 17 and Figure 18In the description of the embodiment, for the convenience of description, the scan line in the i-1th row is referred to as the i-1th scan line Si-1, the emission control line in the i-th row is referred to as the emission control line Ei, the data line in the j-th column is referred to as the data line Dj, and the power line in the j-th column (for example, the power line in the j-th column to which the first power ELVDD is applied) is referred to as the power line PL.

[0314] In addition to the light blocking layer PHL being coupled to the power line PL without passing through the second bridge pattern BRP2, Figure 17 and Figure 18 The Pixel PXL with Figure 15 and Figure 16 Therefore, the same reference numerals are assigned to the Figure 15 and Figure 16 , and thus their detailed descriptions will be omitted to avoid redundancy.

[0315] Reference Figure 17 and Figure 18 , the power line PL and the light-blocking layer PHL may be electrically coupled to each other through a twelfth contact hole CT12 formed through the buffer layer 112, the gate insulating layer 113, the first interlayer insulating layer 114, and the second interlayer insulating layer 115. Therefore, power (e.g., the first power ELVDD) applied through the power line PL may be applied to the light-blocking layer PHL.

[0316] The position of the twelfth contact hole CT12 is not limited to Figure 17 and Figure 18 The twelfth contact hole CT12 may be formed in any region as long as the power line PL and the light blocking layer PHL overlap each other in the region.

[0317] The display device can change the element characteristics of the transistor in the pixel by transferring the voltage applied to a component in the pixel to the light-blocking layer, thereby improving the light-emitting efficiency of the light-emitting element.

[0318] Furthermore, the display device can be implemented as a thin film structure while reducing manufacturing costs by allocating a function of blocking specific light to a certain component of the display panel.

[0319] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, comprising: The substrate comprises a display area and a non-display area, wherein the display area has a plurality of pixel areas, and the non-display area surrounds at least one side of the display area; a light-blocking layer disposed on the first surface of the substrate and comprising a light-transmitting region to allow incident light to pass through the light-transmitting region; a circuit element layer, disposed on the light-blocking layer and comprising a plurality of conductive layers; a light emitting element layer, disposed on the circuit element layer and comprising a light emitting element; as well as a sensor layer disposed on a second surface of the substrate opposite to the first surface to sense the light passing through the light-transmitting area; wherein the light blocking layer is electrically coupled to at least one conductive layer of the plurality of conductive layers in the display area, and The light-blocking layer includes at least one extension portion in the non-display area, the at least one extension portion extends from at least a portion of the periphery of the light-blocking layer toward the periphery of the substrate, and is arranged to be adjacent to the at least one conductive layer, and the at least one extension portion is electrically coupled to the at least one conductive layer in the non-display area.

2. The display device according to claim 1, wherein The light blocking layer is configured to receive power through the at least one conductive layer of the plurality of conductive layers.

3. The display device according to claim 2, wherein: The plurality of conductive layers include power lines extending in one direction and configured to receive the power.

4. The display device according to claim 3, wherein The at least one extending portion is disposed adjacent to the power line in the non-display area.

5. The display device according to claim 4, wherein The at least one extension is electrically coupled to the power line through at least one contact hole in the non-display area.

6. The display device according to claim 5, wherein: The plurality of conductive layers further include a connector disposed between the at least one extension and the power line. The at least one extension portion is electrically coupled to the connection member through at least one first contact hole, The connection member is electrically coupled to the power line through at least one second contact hole, and The connecting member includes a bridge pattern.

7. The display device according to claim 5, wherein: The at least one extending portion includes a protrusion pattern configured to protrude from the at least one extending portion toward the power line to overlap with the power line, and The protrusion pattern is electrically coupled to the power line through the at least one contact hole.

8. The display device according to claim 5, wherein: The electric force line includes a protrusion pattern configured to protrude toward the at least one extension portion of the light blocking layer to overlap the at least one extension portion, and The protrusion pattern is electrically coupled to the at least one extension through the at least one contact hole.

9. The display device according to claim 4, wherein: The non-display area includes: a pad area including pads for coupling to an external controller; a flexure region adjacent to the pad region and bendable about a flexure axis; and a wiring area disposed between the bending area and the display area, and The plurality of conductive layers further include a plurality of lines located in the wiring region, and the plurality of lines and the power lines extend from the pad to the display region.

10. The display device according to claim 9, wherein The at least one extension is electrically coupled to the power line through at least one contact hole in the wiring region.

11. The display device according to claim 9, wherein In the wiring region, the power line has a width greater than a width of the plurality of lines.

12. The display device according to claim 9, wherein The non-display area further includes a dummy area adjacent to the display area, the display area is arranged between the dummy area and the wiring area, and The at least one extension portion is provided in at least one of the wiring region and the dummy region.

13. The display device according to claim 3, wherein: The light blocking layer is electrically coupled to the power line through a contact hole in the display area.

14. The display device according to claim 13, wherein: The plurality of conductive layers in the display area include: a semiconductor layer including an active pattern forming at least one transistor; a first gate layer comprising a gate electrode overlapping the active pattern; a second gate layer comprising at least one capacitor electrode; and The source and drain electrode layer includes the power lines and the conductive lines coupled to the active pattern.

15. The display device according to claim 14, wherein The contact holes include a first contact hole and a second contact hole, and the second gate layer further includes a connector electrically coupled to the light blocking layer through the first contact hole and electrically coupled to the power line through the second contact hole.

16. The display device according to claim 15, wherein The connecting member is a bridge pattern, and the bridge pattern includes: a first region extending parallel to the electric field lines; and The second region extends from the first end of the first region in a direction perpendicular to the first region.

17. The display device according to claim 16, wherein: The first region overlaps the power line and is electrically coupled to the light blocking layer through the first contact hole and electrically coupled to the power line through the second contact hole.

18. The display device according to claim 1, wherein The plurality of conductive layers include light-transmitting holes overlapping the light-transmitting regions.

19. The display device according to claim 1, wherein The light-transmitting area includes a pinhole.

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