Data parallel processing method, electronic device and computer readable storage medium

Abstract

The present invention discloses a method for parallel data processing, an electronic device and a computer-readable storage medium, comprising obtaining input data, wherein the input data includes second data; splitting the second data according to the number of enabled cores to determine multiple groups of split data; and transmitting the split data to at least one enabled core of a multi-core processor respectively, so that at least one of the enabled cores can execute the split data in parallel, which can greatly improve the efficiency of data processing, avoid the waste of idle cores, and improve the utilization rate.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a method, device, electronic device and computer-readable storage medium for parallel data processing. Background Art

[0002] With the development of computer technology, the amount of data calculation in the processing of image, audio, video and other data is increasing. In order to improve the speed and amount of data processing, parallel processing is often used when processing data. However, some parallel methods (such as parallel methods determined by the batch size of data) may not fully utilize the processor, resulting in a waste of processor computing resources. How to ensure the correctness of the operation while avoiding the waste of resources is a problem that needs to be solved urgently. Summary of the invention

[0003] Based on this, it is necessary to provide a method, device, equipment and computer-readable storage medium for parallel data processing in order to solve the above technical problems.

[0004] According to a first aspect of the present disclosure, a method for parallel data processing is provided, the method comprising:

[0005] Acquire input data, wherein the input data includes second data;

[0006] Splitting the second data according to the number of enabled cores to determine multiple groups of split data;

[0007] The split data are transmitted to at least one enabled core of a processor respectively, so that at least one enabled core can execute the split data in parallel; wherein the processor includes at least one enabled core.

[0008] According to a second aspect of the present disclosure, a data processing device is provided, the device comprising:

[0009] An acquisition module, used for acquiring input data, wherein the input data includes second data;

[0010] A splitting module, used for splitting the second data according to the number of enabled cores to determine multiple groups of split data;

[0011] A transmission module is used to transmit the split data to at least one enabled core of a processor respectively, so that at least one enabled core can execute the split data in parallel; wherein, the processor includes at least one enabled core.

[0012] According to a third aspect of the present disclosure, an electronic device is provided, comprising a processor and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above-mentioned data processing method.

[0013] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored, and the computer program instructions are executed by a processor to perform the above-mentioned data parallel processing method.

[0014] By splitting the input data according to the number of enabled cores, multiple groups of split data are obtained, and each enabled core runs a group of split data, ensuring that each enabled core can run the input data normally, avoiding the waste of enabled core resources. Multiple enabled cores run multiple groups of split data in parallel, which improves the data processing speed.

[0015] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 A schematic diagram showing a processor of a data processing method according to an embodiment of the present disclosure;

[0018] Figure 2 A flow chart showing a data processing method according to an embodiment of the present disclosure;

[0019] Figure 3 Another flow chart showing a data processing method according to an embodiment of the present disclosure;

[0020] Figure 4 A schematic diagram showing the method of processing input data by the RoiPooling operator;

[0021] Figure 5 A block diagram showing a data processing device according to an embodiment of the present disclosure;

[0022] Figure 6 A schematic diagram showing the structure of a combined processing device according to an embodiment of the present disclosure is shown;

[0023] Figure 7 A schematic diagram of the structure of a board according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0025] It should be understood that the terms "including" and "comprising" used in the specification and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections. It should also be understood that the terms used in this disclosure specification are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in the disclosure specification and claims, the singular forms of "one", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in the disclosure specification and claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0027] As computer architecture develops, parallel architecture becomes more and more popular. Parallel architecture achieves higher task processing performance by increasing the parallelism of chips. Applications usually have two parallel methods: data-level parallelism and task-level parallelism. Data-level parallelism can operate on multiple data items at the same time, while task-level parallelism creates some work tasks that can be executed individually but can be processed in a large-scale parallel manner.

[0028] In data parallelism, the present disclosure does not impose any restrictions on the scenarios for executing data parallelism. It can be data parallelism during operator calculation or data parallelism in other scenarios. The input data of the present disclosure includes first data and second data, wherein each input data includes four dimensions of N, C, H, and W, wherein N can be the number of batches, C can be the number of channels, H can be the height, and W can be the width. Optionally, the first data can be feature map data, and the second data can be data that can be split and parallelized according to the enabling core, such as representing roi frame data. This is only used as an example and is not intended to be specifically limited. For example, taking the RoiPooling operator as an example, the first data can be feature map data, and the second data can represent roi frame data. When the operator is calculated, there is no limitation on the type of operator, and there is no limitation on the first data and the second data.

[0029] In the traditional technology, in the process of data parallel processing, an optional way is to split the N dimension of the first data, that is, to split the data according to the number of images. Another optional way is to split the C dimension of the first data according to the alignment of the processor, and segment the data according to the value of the C dimension of the first data and the alignment of the processor. For the splitting of the N dimension of the first data, the result of the splitting is limited by the size of N, which may cause a waste of enabled core resources. If N is very small, assuming N = 2, and the number of enabled cores is 4, then the data can only be split into 2 parts of data, resulting in 2 enabled cores being idle, resulting in a waste of enabled core resources. When splitting the data according to the value of the C dimension of the first data and the processor alignment, the minimum splitting unit is determined by the alignment of the processor, and the advantages of multi-core cannot be well utilized.

[0030] In order to better utilize the advantages of multi-core and process data in parallel, the present invention discloses a data parallel processing method. The method can be used for a processor, which can be a general-purpose processor, such as a CPU (Central Processing Unit), or an artificial intelligence processor (IPU) for performing artificial intelligence operations. Artificial intelligence operations may include machine learning operations, brain-like operations, etc. Among them, machine learning operations include neural network operations, k-means operations, support vector machine operations, etc. The artificial intelligence processor may, for example, include one or a combination of GPU (Graphics Processing Unit), NPU (Neural-Network Processing Unit), DSP (Digital Signal Process), and Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) chips. The present disclosure does not limit the specific type of processor. Optionally, the processor mentioned in the present disclosure may include multiple processing units, or the chip may include multiple cores. Each processing unit can independently run various tasks assigned to it, such as: convolution operation tasks, pooling tasks (such as RoiPooling, etc.) or fully connected tasks. Multiple processing units can process multiple parallel tasks in parallel, and the present disclosure does not limit the processing units and the tasks executed by the processing units. Figure 1 A schematic diagram of a processor of a data processing method according to an embodiment of the present disclosure is shown. Figure 1 As shown, the processor 100 includes a plurality of processing units 101 and a storage unit 102. The plurality of processing units 101 are used to execute instruction sequences, and the storage unit 102 is used to store input data, and may include a random access memory (RAM) and a register file. The plurality of processing units 101 in the processor 100 may share part of the storage space, such as sharing part of the RAM storage space and the register file, or may have their own storage space at the same time. The processing unit 101 processes the input data obtained from the storage unit 102. The processing unit 101 may process the data individually or a plurality of processing units may process the input data in parallel, and the present disclosure does not specifically limit this.

[0031] Figure 2 A schematic diagram of a data processing method according to an embodiment of the present disclosure is shown, wherein the method is applied to Figure 1 The processor shown, the method includes:

[0032] S210: The processor obtains input data, wherein the input data includes second data;

[0033] S220. The processor splits the second data according to the number of enabled cores to determine multiple sets of split data;

[0034] Optionally, the processor may determine the size of each set of split data according to the number of enabled cores and the value of the C dimension of the second data.

[0035] S230. The processor respectively transmits the split data to at least one enabled core of the processor, so that at least one of the enabled cores can execute the split data in parallel; wherein, the processor includes at least one enabled core. Herein, the number of enabled cores refers to the number of idle cores, and the processor can send the input data to the currently idle cores for processing. Multiple enabled cores can process multiple input data in parallel.

[0036] In an optional embodiment, when the value of the N dimension of the input data is less than or equal to a preset threshold, the second data is split according to the number of enabled cores to determine multiple sets of split data. Optionally, the preset threshold is the number of enabled cores. When the N dimension of the input data is less than or equal to the number of enabled cores, all enabled cores cannot be fully utilized, resulting in waste of the resources of the enabled cores. When the value of the N dimension of the input data satisfies being less than the number of enabled cores, the roi box can be split according to the number of enabled cores to achieve better operation efficiency and reflect the advantages of multiple cores. Optionally, the preset threshold data can also be other values, and the present disclosure does not make any limitation thereto.

[0037] In an optional embodiment, when the N dimension of the input data is greater than the preset threshold, that is, when the N dimension of the input data is greater than the number of enabled cores, the input data is split according to the value of the N dimension of the input data. The input data can be split into N parts, and the N parts of data are distributed to multiple cores of multiple processors or distributed to multiple cores of the same processor for parallel operation to achieve parallel operation of the N parts of data. Assuming that the split is performed according to the number M of enabled cores by the above method, at most it can be split into M parts to achieve parallel operation of M parts of data, and M < N. Therefore, when the N dimension of the input data is greater than the preset threshold (enabled core), the operation efficiency of splitting according to the N dimension of the input data is higher than that according to the number of enabled cores.

[0038] Optionally, the input data also includes first data, wherein the first data is feature map data, representing featuremap data. There is a mapping relationship between the first data and the second data, and the mapping relationship between the first data and the second data can be obtained according to the data information of the first information or the second information, and then the other input data can be obtained according to the mapping relationship between the first data and the second data, and one of the input data. According to this method, when loading data, only part of the input data can be loaded, and other input data can be obtained by obtaining the loaded part of the input data, so as to complete the operation of the input data, thereby reducing the time of data loading and improving the operation efficiency. Based on this, the processor can obtain input data in the following way.

[0039] Optionally, the processor may directly obtain the first data and the second data for calculation.

[0040] Optionally, the processor only obtains the first data; and obtains the second data according to the data information of the first data. The data information of the first data includes the batch number information of the data, and the processor can obtain the second data according to the batch number information of the first data. Specifically, the processor obtains the mapping relationship according to the batch number information of the first data, and obtains the second data according to the mapping relationship.

[0041] Optionally, when the processor only obtains the second data; the first data is obtained according to the data information of the second data. The data information of the second data includes W-dimensional information, and the processor can obtain the second data according to the W-dimensional information of the second data. Specifically, the processor can obtain the mapping relationship according to the W-dimensional information of the second data, and obtain the first data according to the mapping relationship.

[0042] Optionally, in an embodiment of the present application, the processor may also perform split processing on the first data. Specifically, the processor may divide the first data into at least one batch of data according to the C-dimensional data information of the first data and the alignment mode of the processor; and sequentially input the at least one batch of data into the processor, so that at least one enabled core of the processor performs parallel calculations according to the at least one batch of data and the split data of the second data, respectively. Optionally, the above-mentioned processor may be a general-purpose processor or an artificial intelligence processor, etc., which is not specifically limited here.

[0043] For example, Figure 4 The implementation method of the RoiPooling operator for input data processing is shown. In this embodiment, the first data is N*512*23*40, the second data is N*304*1*5, 4 cores are enabled, namely core0, core1, core2, and core3, and the processor alignment is 256 alignment as an example to specifically illustrate the above data parallel processing method.

[0044] First, the processor obtains input data, which in this embodiment includes first data and second data. The processor can convert the four dimensional order of the input data into a dimensional order suitable for the processor. For example, the dimensional order of the input data is NCHW, and the dimensional order supported by the processor is NHWC. At this time, the processor can convert the dimensional order of the input data from NCHW to NHWC, and store and process the input data according to the converted dimensional order.

[0045] After the dimensional order conversion, the processor can segment the first data (the first data is stored according to the converted NHWC) according to the alignment of the first data and the second device. The C dimension of the first data is 512, and the data alignment is 256 alignment, so the first data can be divided into 512 / 256=2 segments. Each segment of the first data is N*256*23*40. When processing the input data, the second data is executed with each segment of the first data. After processing the first segment of data, the second segment of data is processed.

[0046] The first paragraph: the first data: N*256*23*40 the second data: N*304*1*5;

[0047] The first data of the second segment: N*256*23*40 The second data: N*304*1*5;

[0048] When processing each piece of data, it specifically includes:

[0049] The processor splits the second data according to the number of enabled cores to determine multiple groups of split data; and determines the size of each group of split data according to the number of enabled cores and the value of the C dimension of the second data. Specifically, the size of each group of split data is 304 / 4=76, the number of frames that each frame can process is 76, and the specific amount of data on each enabled core is:

[0050] core 0 first data: N*256*23*40 second data: N*76*1*5;

[0051] core 1 first data: N*256*23*40 second data: N*76*1*5;

[0052] core 2 first data: N*256*23*40 second data: N*76*1*5;

[0053] core 3 first data: N*256*23*40 second data: N*76*1*5;

[0054] The four cores process the first data and the second data of each input segment in parallel to obtain the final result.

[0055] As another embodiment, the data parallel processing method disclosed in the present invention can also be applied to a system including a first device and a second device, wherein the first device can be a general-purpose processor, such as a CPU, and the second device can be an artificial intelligence processor (IPU), a graphics processor (Graphics Processing Unit, referred to as GPU), an embedded neural network processor (Neural-network Processing Unit, referred to as NPU), etc. The first device and the second device can include multiple processor cores.

[0056] The input data is first input into the first device. The first device performs dimension conversion on the input data and copies the dimension-converted data to the second device so that the second device can process and calculate the input data. Specifically, in this implementation, the data arrangement method of the first device and the second device may refer to the arrangement order of different dimensions of data during the calculation process in the device. Due to the difference between the first device and the second device, the different data arrangement methods when calculating in the two devices make them have different calculation speeds. Therefore, the first device and the second device will predetermine their own data arrangement methods, and the data that needs to be calculated will first be converted into data consistent with its own data arrangement method, and then the corresponding calculation will be performed.

[0057] For example, assuming that the Roiling operator is to transpose the four-dimensional tensor, the data layout of the four-dimensional tensor in the first processing device is NCHW. The data layout of the four-dimensional tensor in the second processing device is NHWC. Therefore, after the first device obtains the input data, it transmits the input data to the second device. The second device first converts the dimension order of the input data and operates on the input data in the second device. Optionally, the dimension order conversion can be performed before the input data is copied to the second device, and the converted data is copied to the second processor device for operation. This article does not limit the specific method of data dimension conversion.

[0058] Figure 3 A schematic diagram of a data processing method according to an embodiment of the present disclosure is shown as follows: Figure 3 As shown, the method is applied to a system including a first device and a second device, and the method includes:

[0059] S310: The first device acquires input data, wherein the input data includes second data;

[0060] S320: The second device splits the second data according to the number of enabled cores to determine multiple groups of split data;

[0061] Optionally, the second device may also determine the size of each group of split data according to the number of enabled cores and the value of the C dimension of the second data.

[0062] S330: The second device transmits the split data to at least one enabled core of the second device respectively, so that at least one of the enabled cores can execute the split data in parallel; wherein the second device includes at least one enabled core. The number of enabled cores refers to the number of idle cores, and the processor can distribute the input data to the current idle core for processing. Multiple enabled cores can process multiple input data in parallel.

[0063] This embodiment takes the RoiPooling operator as an example to describe the above process in detail. When processing the RoiPooling operator, the second data in the above input data is the data of the frame of interest, that is, the roi frame data, which can generally be expressed as: N*304*1*5 according to NCHW, where the data information 304 of the second dimension represents the number of frames of interest, indicating that the RoiPooling operator contains a total of 304 frames of interest, and the data information represented by the lowest dimension data 5 is the coordinate of the roi frame, and the position of the roi frame can be located according to the coordinate of the roi frame.

[0064] After the first device obtains the input data, the second device can split the second data according to the number of enabled cores to determine multiple groups of split data. Specifically, the second device can process the second data according to the roi frame. Optionally, the second device can evenly distribute 304 roi frames to multiple idle cores for processing, so that each idle core can process at least one roi frame, avoiding the waste of idle core resources. For example, when the second input data is N*304*1*5, and there are currently 4 enabled cores, the size of each group of split data is 304 / 4=76. Therefore, the second data N*304*1*5 is finally split into 4 N*76*1*5 and assigned to 4 enabled cores for parallel operation.

[0065] Optionally, when the roi frames cannot be evenly distributed to the current idle cores, for example, the number of the current idle cores is 5, the second data is split into 4 N*61*1*5 and one N*60*1*5, which are distributed to the five idle cores for parallel processing.

[0066] Optionally, the second device may determine the size of each group of split data according to the number of enabled cores and the value of the C dimension of the second data.

[0067] In an alternative embodiment, when the value of the N dimension of the input data is less than or equal to a preset threshold, the second data is split according to the number of enabled cores to determine multiple sets of split data. Optionally, the preset threshold is the number of enabled cores. When the N dimension of the input data is less than or equal to the number of enabled cores, all the enabled cores cannot be fully utilized, resulting in a waste of the resources of the enabled cores. When the value of the N dimension of the input data satisfies being less than the number of enabled cores, the roi box can be split according to the number of enabled cores to achieve better operation efficiency and reflect the advantages of multiple cores. Optionally, the preset threshold data can also be other values, and the present disclosure does not impose any restrictions thereon.

[0068] In an alternative embodiment, when the N dimension of the input data is greater than the preset threshold, that is, when the N dimension of the input data is greater than the number of enabled cores, the input data is split according to the value of the N dimension of the input data. The input data can be split into N parts, and the N parts of data are distributed to multiple cores of the second device or to multiple cores of the same processor for parallel operation to achieve parallel operation of the N parts of data. Assuming that the splitting is performed according to the number M of enabled cores by the above method, at most M parts can be split to achieve parallel operation of M parts of data, and M < N. Therefore, when the N dimension of the input data is greater than the preset threshold (enabled cores), the operation efficiency of splitting according to the N dimension of the input data is higher than that according to the number of enabled cores.

[0069] Optionally, the input data further includes first data, where the first data is feature map data, representing featuremap data. There is a mapping relationship between the first data and the second data. According to the data information of the first information or the second information, the mapping relationship between the first data and the second data can be obtained. Then, according to the mapping relationship between the first data and the second data, and one of the input data, the other input data can be obtained. According to this method, when loading data, only part of the input data needs to be loaded, and the other input data can be obtained through the loaded part of the input data, so that the operation of the input data can be completed, reducing the data loading time and improving the operation efficiency. Based on this, the first device can obtain the input data in the following manner.

[0070] Optionally, the first device can directly obtain the first data and the second data for operation.

[0071] Optionally, the first device only obtains the first data; according to the data information of the first data, the second data is obtained. The data information of the first data includes the batch number information of the data. The first device can obtain the second data according to the batch number information of the first data. Specifically, the first device obtains the mapping relationship according to the batch number information of the first data, and obtains the second data according to the mapping relationship.

[0072] Optionally, when the first device only obtains the second data; the first data is obtained according to the data information of the second data. The data information of the second data includes W-dimensional information, and the first device can obtain the second data according to the W-dimensional information of the second data. Specifically, the first device can obtain the mapping relationship according to the W-dimensional information of the second data, and obtain the first data according to the mapping relationship.

[0073] Optionally, in an embodiment of the present application, the second device may also split and process the first data. Specifically, the second device may divide the first data into at least one batch of data according to the C-dimensional data information of the first data and the alignment mode of the processor; and sequentially input the at least one batch of data into the processor, so that at least one enabling core of the second device performs parallel calculations according to the at least one batch of data and the split data of the second data, respectively. Optionally, the first device may be a general-purpose processor, and the second device may be an artificial intelligence processor, etc., which are not specifically limited here.

[0074] Optionally, the input data may be split on the first device or on the second device. This embodiment is described by taking the data splitting on the second device as an example. The method steps of splitting the input data on the first device to obtain split data are similar to the steps of splitting the data on the second device to obtain split data, which will not be described in detail.

[0075] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0076] It should be further explained that although Figure 1 , Figure 2 , Figure 3 The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0077] Figure 5 FIG. 1 is a block diagram of a data processing device according to an embodiment of the present disclosure. Figure 5 As shown, the device may include a data acquisition module 41, a splitting module 42, and a transmission module 43.

[0078] An acquisition module 41, configured to acquire input data, wherein the input data includes second data;

[0079] A splitting module 42, configured to split the second data according to the number of enabled cores to determine a plurality of groups of split data;

[0080] The transmission module 43 is used to transmit the split data to at least one enabled core of the processor respectively, so that at least one enabled core can execute the split data in parallel; wherein, the processor includes at least one enabled core.

[0081] In a possible implementation, the splitting module is further used to determine the size of each group of split data according to the number of enabled cores and the value of the C dimension of the second data.

[0082] In a possible implementation, when the value of the N dimension of the input data is less than a preset threshold, the second data is split according to the number of enabled cores to determine a plurality of groups of split data.

[0083] In a possible implementation manner, the preset threshold is the number of enabled cores.

[0084] In a possible implementation, the input data also includes first data, and obtaining the input data also includes: an acquisition module is used to obtain the first data; the acquisition module is also used to obtain second data based on data information of the first data; or, the acquisition module is used to obtain the second data; the acquisition module is also used to obtain the first data based on data information of the second data.

[0085] In a possible implementation manner, the data information of the first data or the second data includes the mapping relationship, and the acquisition module obtains the mapping relationship according to the W-dimensional data information of the second data, and obtains the first data according to the mapping relationship.

[0086] In a possible implementation manner, the acquisition module obtains the mapping relationship according to the batch number information of the first data, and obtains the second data according to the mapping relationship.

[0087] In a possible implementation, the device further includes a dimension conversion module, which is used to perform dimension sequence conversion on the input data.

[0088] In a possible implementation manner, the device further includes a segmentation module, configured to divide the first data into at least one batch of data according to C-dimensional data information of the first data and an alignment manner of a processor.

[0089] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present disclosure can also be implemented in other ways. For example, the division of units / modules described in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0090] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present disclosure may be integrated into one unit / module, or each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0091] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. Unless otherwise specified, the artificial intelligence processor may be any appropriate hardware processor, such as a CPU, a GPU, an FPGA, a DSP, an ASIC, etc. Unless otherwise specified, the storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access memory DRAM (Dynamic Random Access Memory), a static random access memory SRAM (Static Random-Access Memory), an enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc.

[0092] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present disclosure is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0093] The embodiment of the present disclosure also provides a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the above method is implemented. The computer-readable storage medium may be a non-volatile computer-readable storage medium.

[0094] The embodiment of the present disclosure further proposes an electronic processing device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0095] Figure 6 1 is a structural diagram showing a combined processing device 1200 according to an embodiment of the present disclosure. Figure 6 As shown in FIG. 1 , the combined processing device 1200 includes a computing processing device 1202, an interface device 1204, other processing devices 1206, and a storage device 1208. According to different application scenarios, the computing processing device may include one or more computing devices 1210, which may be configured to execute the above-mentioned Figure 2 The operation described.

[0096] In different embodiments, the computing and processing device disclosed herein may be configured to perform user-specified operations. In an exemplary application, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, with respect to the computing and processing device disclosed herein, it may be regarded as having a single-core structure or a homogeneous multi-core structure.

[0097] In an exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0098] In one or more embodiments, the other processing device can serve as an interface between the computing device disclosed herein (which can be embodied as an artificial intelligence such as a computing device related to neural network computing) and external data and control, and perform basic controls including but not limited to data handling, starting and / or stopping the computing device, etc. In other embodiments, the other processing device can also cooperate with the computing device to jointly complete computing tasks.

[0099] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it into a storage device (or memory) on the computing and processing device chip. Further, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them into a control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0100] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0101] In some embodiments, the present disclosure also discloses a chip (e.g. Figure 7 In one implementation, the chip is a system on chip (SoC) and integrates one or more Figure 6 The chip can be connected to an external interface device (such as Figure 7 The external interface device 1306 shown in the figure is connected to other related components. The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as a video codec) and / or interface modules (such as a DRAM interface) may be integrated on the chip. In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 7 The board is described in detail.

[0102] Figure 7 FIG. 1 is a schematic diagram showing the structure of a board 1300 according to an embodiment of the present disclosure. Figure 7 As shown in , the board includes a storage device 1304 for storing data, which includes one or more storage units 1310. The storage device can be connected and data can be transmitted with the control device 1308 and the chip 1302 described above by means of, for example, a bus. Further, the board also includes an external interface device 1306, which is configured for data relay or switching between the chip (or the chip in the chip packaging structure) and an external device 1312 (such as a server or computer, etc.). For example, the data to be processed can be transmitted to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0103] In one or more embodiments, the control device in the disclosed board may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a microcontroller unit (MCU) to regulate the working state of the chip.

[0104] According to the above combination Figure 6 and Figure 7 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0105] According to different application scenarios, the electronic equipment or device disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, transportation, household appliances, and / or medical equipment. The transportation includes airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs. The electronic equipment or device disclosed herein may also be applied to the Internet, IoT, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and medical fields. Further, the electronic equipment or device disclosed herein may also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, electronic devices or devices with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or devices with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0106] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein may not necessarily be necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art may appreciate the parts that are not described in detail in a certain embodiment of the present disclosure, and may also refer to the relevant descriptions of other embodiments.

[0107] In terms of specific implementation, based on the disclosure and teaching of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented by other methods not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article divides them on the basis of considering logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0108] In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

[0109] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0110] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP and ASIC, etc. Further, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

[0111] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The foregoing content can be better understood in accordance with the following terms:

[0114] Clause 1. A method of data parallel processing, the method comprising:

[0115] Acquire input data, wherein the input data includes second data;

[0116] Splitting the second data according to the number of enabled cores to determine multiple groups of split data;

[0117] The split data are transmitted to at least one enabled core of a processor respectively, so that at least one enabled core can execute the split data in parallel; wherein the processor includes at least one enabled core.

[0118] Clause 2. The method according to clause 1, wherein determining the plurality of groups of split data comprises:

[0119] The size of each group of split data is determined according to the number of enabled cores and the value of the C dimension of the second data.

[0120] Clause 3. The method according to clause 2, further comprising:

[0121] The input data is transformed in dimensional order.

[0122] Clause 4. The method according to clause 3, further comprising:

[0123] When the value of the N dimension of the input data is less than or equal to a preset threshold, the second data is split according to the number of enabled cores to determine a plurality of groups of split data.

[0124] Clause 5. According to the method described in Clause 4, the method also includes: a preset threshold value is the number of enabled cores.

[0125] Clause 6. According to the method described in Clause 1, the input data also includes first data, and obtaining the input data further includes:

[0126] acquiring the first data;

[0127] Obtaining second data according to the data information of the first data; or,

[0128] acquiring the second data;

[0129] The first data is obtained according to the data information of the second data.

[0130] Clause 7. According to the method described in Clause 6, the data information of the first data or the second data includes the mapping relationship:

[0131] The mapping relationship is obtained according to the W-dimensional data information of the second data, and the first data is obtained according to the mapping relationship; or,

[0132] The mapping relationship is obtained according to the batch number information of the first data, and the second data is obtained according to the mapping relationship.

[0133] Clause 8. The method according to clause 2, further comprising:

[0134] Dividing the first data into at least one batch of data according to the C-dimensional data information of the first data and the alignment mode of the processor;

[0135] The at least one batch of data is sequentially input into the multi-core processor, so that at least one enabled core of the multi-core processor performs parallel calculations according to the at least one batch of data and the split data respectively.

[0136] Clause 9. An electronic device comprising a processor and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the method described in any one of clauses 1-8.

[0137] Clause 10. A computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method described in any one of Clauses 1-8.

[0138] The above contents are merely examples and explanations of the structure of the present invention. The technicians in this technical field may make various modifications or additions to the specific embodiments described or replace them in a similar manner. As long as they do not deviate from the structure of the invention or exceed the scope defined by the claims, they should all fall within the protection scope of the present invention.

Claims

1. A method for parallel data processing, characterized in that: The method comprises: Acquire input data, wherein the input data includes second data; Splitting the second data according to the number of enabled cores to determine multiple groups of split data; Respectively transmitting the split data to at least one enabled core of the processor so that at least one of the enabled cores can execute the split data in parallel; wherein the processor includes at least one enabled core; Determining multiple groups of split data includes: Determine the size of each group of split data according to the number of enabled cores and the value of the C dimension of the second data; The method further comprises: When the dimensional order of the input data does not conform to the data dimensional order required by the processor, converting the dimensional order of the input data; The method further comprises: When the value of the N dimension of the input data is less than or equal to a preset threshold, splitting the second data according to the number of enabled cores to determine multiple groups of split data; The preset threshold is the number of enabled cores.

2. The method according to claim 1, characterized in that: The input data further includes first data, and obtaining the input data further includes: acquiring the first data; Obtaining second data according to the data information of the first data; or, acquiring the second data; The first data is obtained according to the data information of the second data.

3. The method according to claim 2, characterized in that: The data information of the first data or the second data includes a mapping relationship: The mapping relationship is obtained according to the W-dimensional data information of the second data, and the first data is obtained according to the mapping relationship; or, The mapping relationship is obtained according to the batch number information of the first data, and the second data is obtained according to the mapping relationship.

4. The method according to claim 3, characterized in that: The method further comprises: Dividing the first data into at least one batch of data according to the C-dimensional data information of the first data and the alignment mode of the processor; The at least one batch of data is sequentially input into the processor, so that at least one enabled core of the processor performs parallel calculations according to the at least one batch of data and the split data respectively.

5. An electronic device, characterized in that: It comprises a processor and a memory for storing processor executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 4.

6. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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