Semiconductor device and method of operating a semiconductor device

Abstract

Embodiments of the present disclosure relate to a semiconductor device and a method for operating a semiconductor device. In a semiconductor device including a lockstep function, bus access conflicts of multiple processors are suppressed. The semiconductor device includes: a first processor; a second processor for monitoring the operation of the first processor in a first mode; a first bus and a second bus; a first non-shared resource and a second non-shared resource dedicated to the first processor or the second processor in a second mode; and a first selector for selecting a bus for transmitting an interface signal between the second processor and the selected bus. In the second mode, the first processor and the second processor execute different instructions, and the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus, and the second non-shared resource is accessed by the second processor via the second bus.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2019-111998 filed on June 17, 2019, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, for example, a semiconductor device including a plurality of processors, and a lockstep mode and a non-lockstep mode as operation modes in which the plurality of processors perform the same operation and in which the plurality of processors perform different operations. Background Art

[0004] In recent years, there is a semiconductor device including a built-in processor for executing a program, which achieves improvement in reliability or improvement in throughput by combining a plurality of processors. Such a semiconductor device can include a lockstep mode for operating a plurality of processors to obtain the same calculation result, and a non-lockstep mode for operating the plurality of processors differently.

[0005] There are the following disclosed technologies.

[0006] (Patent Document 1) Japanese Unexamined Patent Application Publication No. 2010-198131.

[0007] Patent document 1 discloses an example of a semiconductor device that can switch between a lock-step mode and a free-stepping mode as a non-lock-step mode. In the lock-step mode, the plurality of processors described in Patent document 1 detect errors by causing the plurality of processors to execute the same process and comparing the execution results of the process. On the other hand, in the free-stepping mode, the plurality of processors can execute different processes. Therefore, the semiconductor device described in Patent document 1 can improve the throughput of the entire semiconductor device in the free-stepping mode.

[0008] On the other hand, in a semiconductor device including a plurality of processors, circuits for realizing various functions may be provided as resources in addition to the plurality of processors. Here, the resources are, for example, memories, timers, I / O interface circuits, analog-to-digital converters, or peripheral circuits such as digital-to-analog converters. If the semiconductor device includes such resources, the processor writes to or reads from these resources via a bus. Summary of the invention

[0009] In the non-lock-step mode, multiple processors perform arithmetic processing in parallel and access resources via the bus as needed. At this time, when multiple processors share the bus, conflicts in bus access by multiple processors may occur. When a conflict in bus access occurs, one processor is allowed to access the bus, while another processor's access to the bus is shelved, resulting in a problem of performance degradation of the entire semiconductor device.

[0010] Patent document 1 discloses a processor system for providing an input signal from an external circuit shared with a main processor to a checker processor during a lockstep mode, and for providing an input signal from another external circuit to the checker processor during a free-stepping mode. However, Patent document 1 does not disclose any measures for suppressing bus access conflicts that may occur when multiple processors access peripheral devices in a non-lockstep mode.

[0011] One object of the present disclosure is to suppress conflicts between bus accesses of multiple processors in non-lockstep mode in a semiconductor device capable of switching between lockstep mode and non-lockstep mode, and to improve the performance of the semiconductor device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0012] Devices for problem solving

[0013] A semiconductor device includes: a first processor; a second processor for monitoring the operation of the first processor in a first mode; a first bus and a second bus; a first non-shared resource and a second non-shared resource, which are dedicated to the first processor or the second processor in a second mode; and a first selector for selecting a bus for transmitting interface signals between the second processor and the first processor. In the first mode, the first processor and the second processor execute the same instruction stream, and the first selector selects the first bus. In the second mode, the first processor and the second processor execute different instruction streams, and the first selector selects the second bus. In the second mode, the first processor accesses the first non-shared resource via the first bus, and the second processor accesses the second non-shared resource via the second bus.

[0014] According to another embodiment, a method for operating a semiconductor device includes: a first processor and a second processor, a first non-shared resource and a second non-shared resource, a first bus and a second bus, and first to third selectors, the first processor is coupled to the first bus, the method includes setting a first operation mode or a second operation mode, in the first operation mode, the first processor and the second processor execute the same instruction stream, and in the second operation mode, the first processor and the second processor execute different instruction streams. Executing different instruction streams includes: the first processor accesses the first non-shared resource via the first bus and the second selector, and the second processor accesses the second non-shared resource via the first selector, the second bus, and the third selector.

[0015] According to another embodiment, a semiconductor device includes: a first processor; a second processor for monitoring the operation of the first processor in a first mode; a first bus and a second bus; a shared resource coupled to the first bus and the second bus and used by the first processor and the second processor in common; in a second mode, a non-shared resource, dedicated to the second processor; and a first selector for selecting a bus for transmitting an interface signal between the second processor and the non-shared resource. In a first mode in which the first processor and the second processor execute the same instruction stream, the first selector selects the first bus, and the first selector transmits an interface signal between the first bus and the second processor. In a second mode, the first processor and the second processor execute different instruction streams, the first selector selects the second bus, and the second processor accesses the non-shared resource via the second bus.

[0016] According to one embodiment, a semiconductor device can suppress conflicts in bus access by multiple processors and improve the performance of the semiconductor device in a non-lockstep mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a first embodiment.

[0018] Figure 2 is a circuit diagram illustrating an exemplary configuration of a controller of the semiconductor device according to the first embodiment.

[0019] Figure 3 is a diagram illustrating an exemplary bus access path when the semiconductor device according to the first embodiment operates in the lockstep mode.

[0020] Figure 4 is a diagram illustrating an exemplary bus access path when the semiconductor device according to the first embodiment operates in a non-lockstep mode.

[0021] Figure 5is a flowchart illustrating an exemplary bus access operation of the semiconductor device according to the first embodiment.

[0022] Figure 6 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a second embodiment.

[0023] Figure 7 is a block diagram illustrating a configuration of a modified example of the semiconductor device according to the second embodiment.

[0024] Figure 8 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a third embodiment.

[0025] Fig. 9 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION

[0026] For the sake of clarity, the following description and drawings are appropriately omitted and simplified. In the drawings, the same elements are represented by the same reference numerals, and repeated description thereof is omitted when necessary.

[0027] (First embodiment)

[0028] Figure 1 1 is a block diagram illustrating an example of the configuration of the semiconductor device 1 according to the first embodiment. Figure 1 As shown in the figure, the semiconductor device 1 includes: a first processor 10, a second processor 11, a comparator 12, a selector (first selector) 13, a first bus 20, a second bus 21, a non-shared resource (first non-shared resource) 30, a non-shared resource (second non-shared resource) 32, a selector (second selector) 31, a selector (third selector) 33 and a controller 40.

[0029] The first processor 10 and the second processor 11 are processing circuits that execute a program (instruction stream) read from a memory (not shown) and perform processing. For example, the processor may be a CPU (central processing unit), a DSP (digital signal processor), etc. As operation modes of a plurality of built-in processors, the semiconductor device according to the first embodiment has a lockstep mode (i.e., a first mode, a first operation mode) in which a plurality of processors are operated so as to obtain the same calculation results from the corresponding processors; and a non-lockstep mode (i.e., a second mode, a second operation mode) in which a plurality of processors are independently operated.

[0030] In the lock-step mode, one processor is used for the main operation, and the other processor is used as a check processor to monitor the operation of one processor. In the lock-step mode, based on the difference between the operation results of the two processors, the failure of the operation core can be detected early, thereby improving the reliability of the operation result. On the other hand, in the non-lock-step mode, since a plurality of processors execute programs separately, high-speed arithmetic processing can be performed by increasing the number of programs to be executed in parallel.

[0031] In order to make the first processor 10 and the second processor 11 output the same operation result in the lockstep mode, it is preferred that the first processor 10 and the second processor 11 have the same circuit configuration, but the first processor 10 and the second processor 11 may have different configurations.

[0032] The first processor 10 is coupled to the first bus 20. The second processor may be coupled to the first bus 20 or the second bus 21 via a selector 13 described later.

[0033] although Figure 1 An exemplary configuration including two processors (i.e., the first processor 10 and the second processor 11) is shown, but the configuration of the semiconductor device 1 is not limited thereto. If the number of processors is 2 or more, the number of processors included in the semiconductor device 1 may be any number. For example, the semiconductor device 1 may include four processors.

[0034] The non-shared resources 30 and 32 are circuits including peripheral functions such as memories, timers, I / O interface circuits, analog-to-digital conversion circuits, or digital-to-analog conversion circuits. In the non-lockstep mode, each of the non-shared resources 30 and 32 is dedicated to the first processor 10 or the second processor 11. On the other hand, in the lockstep mode, the first processor 10 can utilize the two non-shared resources 30 and 32. In other words, the first processor 10 can access the two non-shared resources 30 and 32 and can utilize the arithmetic processing performed by the two non-shared resources 30 and 32. Although Figure 1 An exemplary configuration including two non-shared resources 30 and 32 as non-shared resources is shown, but the configuration of the semiconductor device 1 is not limited thereto. The semiconductor device 1 may include two or more non-shared resources of any number.

[0035] The first bus 20 is configured to enable data transfer between the first processor 10, the second processor 11, the non-shared resource 30, and the non-shared resource 32. The second bus 21 is configured to enable data transfer between the second processor 11, the non-shared resource 30, and the non-shared resource 32. As will be described later, the second processor 11 can send data to the first bus 20 or the second bus 21 via the selector 13, and receive data therefrom. More specifically, the selector 13 can send an interface signal group (i.e., the first interface signal group 15) sent from the first bus, or another interface signal group (i.e., the second interface signal group 17) sent from the second bus to the second processor 11. The selector 13 can send another interface signal group (i.e., the third interface signal group 16) output by the second processor 11 to the second bus 21. In addition, the non-shared resource 30 can send data to the first bus 20 or the second bus 21 via the selector 31, and receive data therefrom. Similarly, the non-shared resource 32 can send data to the first bus 20 or the second bus 21 via the selector 33, and receive data therefrom.

[0036] In the lockstep mode, the comparator 12 compares the operation result of the first processor 10 and the operation result of the second processor 11 monitoring the operation of the first processor. When the operation results of the first processor 10 and the second processor 11 are different from each other, the comparator 12 activates the error signal ERR.

[0037] More specifically, the comparator 12 compares an interface signal group (i.e., a fourth interface signal group 14) output by the first processor 10 to the non-shared resource 30, and another interface signal group 16 output by the second processor 11 to the non-shared resource 32. When the interface signal group 14 and the interface signal group 16 are different from each other, the comparator 12 activates the error signal ERR.

[0038] The signals monitored by the comparator 12 need not be all signals included in the interface signal group 14 and the interface signal group 16, and may be a portion of the signals included in the interface signal group 14 and the interface signal group 16. For example, the comparator 12 may compare only the data signal, or may compare both the address signal and the data signal. The error signal ERR may be activated in the lockstep mode or the non-lockstep mode, and may be referenced by the error processing circuit (not shown here) only in the lockstep mode.

[0039] The error signal ERR output from the comparator 12 may be used for various processes to ensure the reliability of the semiconductor device 1. For example, when the error signal ERR is activated, the semiconductor device 1 initializes the entire semiconductor device 1. When the error signal ERR is detected, the semiconductor device 1 may re-execute the procedure of activating the error signal ERR.

[0040] In response to the non-lockstep mode valid signal SEL_C, the selector 13 selects whether to send the interface signal group 15 transmitted from the first bus 20 to the second processor 11 or to send the interface signal group 17 transmitted from the second bus 21 to the second processor 11. In the lockstep mode, the selector 13 prevents the interface signal group 16 output by the second bus 11 from being transmitted to the first bus 20 and the second bus 21. On the other hand, in the non-lockstep mode, the selector 13 transmits the interface signal group 16 output by the second processor 11 to the second bus 21.

[0041] More specifically, in a state where the non-lock-step mode valid signal SEL_C indicates the lock-step mode, the selector 13 prevents the interface signal group 16 output by the second processor from being output to the first bus 20 and the second bus 21. In addition, in the lock-step mode, the selector 13 selects the interface signal group 15 transmitted from the first bus 20 and transmits it to the second processor 11 as an interface signal group (i.e., the fifth interface signal group 18).

[0042] In a state where the non-lock-step mode valid signal SEL_C indicates the non-lock-step mode, the selector 13 outputs the interface signal group 16 output by the second processor 11 to the second bus 21. In the non-lock-step mode, the selector 13 selects the interface signal group 17 from the interface signal group 15 sent from the first bus 20 and the interface signal group 17 sent from the second bus 21, and sends the interface signal group 17 as the interface signal group 18 to the second processor 11. That is, the second processor 11 accesses the non-shared resource 30 or the non-shared resource 32 via the second bus 21.

[0043] The selector 31 selects any one of the first bus 20 and the second bus 21, through which the first processor 10 or the second processor 11 accesses the first non-shared resource 30. In the lockstep mode, the bus selection signal SEL_P1 is a value of the selector 31 selecting the first bus 20. That is, in the lockstep mode, the first processor 10 accesses the non-shared resource 30 via the first bus 20 selected by the selector 31. On the other hand, in the non-lockstep mode, the selector 31 can select the first bus 20 or the second bus 21 based on the value of the bus selection signal SEL_P1. In the non-lockstep mode, the first processor 10 or the second processor 11 accesses the first non-shared resource 30 via the bus selected by the selector 31.

[0044] In addition to the above-mentioned normal bus access processing, the selector 31 can also detect illegal bus access in the non-lockstep mode. The selector 31 is coupled to the first bus 20 and the second bus 21, and also receives the bus selection signal SEL_P1. Therefore, the selector 31 can detect the transmission and reception access requests to the non-shared resource 30 that occur on the bus that is not selected by the bus selection signal SEL_P1. Therefore, the selector 31 can determine whether the bus access is normal.

[0045] The selector 33 selects any one of the first bus 20 and the second bus 21, through which the first processor 10 or the second processor 11 accesses the second non-shared resource 32. In the lockstep mode, the bus selection signal SEL_P2 is a value for the selector 33 to select the first bus 20. That is, in the lockstep mode, the first processor 10 accesses the non-shared resource 32 via the first bus 20 selected by the selector 33. On the other hand, in the non-lockstep mode, the selector 33 may select the first bus 20 or the second bus 21 based on the value of the bus selection signal SEL_P2. In the non-lockstep mode, the first processor 10 or the second processor 11 accesses the second non-shared resource 32 via the bus selected by the selector 33.

[0046] In addition to the above-mentioned normal bus access processing, the selector 33 can also detect illegal bus access in the non-lockstep mode. The selector 33 is coupled to the first bus 20 and the second bus 21, and also receives the bus selection signal SEL_P2. Therefore, the selector 33 can detect the transmission and reception access requests to the non-shared resource 32 that occur on the bus that is not selected by the bus selection signal SEL_P2. Therefore, the selector 33 can determine whether the bus access is normal.

[0047] As described above, the selectors 31 and 33 can determine whether the bus access is normal, but the configuration for determining whether the bus access is normal is not limited thereto. For example, the first processor 10 and the second processor 11 can each include an MPU (i.e., a memory protection unit not shown here), and the MPU can determine whether the bus access is normal. Alternatively, it can be determined whether the bus access is normal by a bus control circuit (not shown here) provided separately from the selectors 31 and 33.

[0048] The controller 40 is a control circuit that generates a non-lock-step mode valid signal SEL_C, a bus selection signal SEL_P1, and a bus selection signal SEL_P2. The non-lock-step mode valid signal SEL_C generated by the controller 40 is input to the selector 13. The bus selection signals SEL_P1 and SEL_P2 generated by the controller 40 are input to the selectors 31 and 33, respectively. Figure 1 In the drawings, these couplings are omitted to avoid complicating the drawings.

[0049] Figure 2 is a schematic diagram illustrating an exemplary configuration of the controller 40 according to the first embodiment. Figure 2 As shown in FIG. 1 , the controller 40 includes flip-flops 41, 42, and 43 and multiplexers 44 and 45. By setting expected values ​​in the setting registers 41, 42, and 43 configured with flip-flops, the values ​​of the non-lockstep mode valid signal SEL_C, the bus selection signal SEL_P1, and the bus selection signal SEL_P2 are determined. For example, before the semiconductor device 1 starts the main process, the first processor 10 may execute an initialization program to set the values ​​of the configuration registers 41, 42, and 43. Figure 2 In the embodiment, the values ​​of the non-lock-step mode valid signal SEL_C, the bus selection signal SEL_P1 and the bus selection signal SEL_P2 are determined by the values ​​of the setting registers 41, 42 and 43, but the method of determining the values ​​of the non-lock-step mode valid signal SEL_C, the bus selection signal SEL_P1 and the bus selection signal SEL_P2 is not limited to Figure 2 Configuration example. For example, the values ​​of the non-lock-step mode valid signal SEL_C, the bus selection signal SEL_P1, and the bus selection signal SEL_P2 can be set by reading the values ​​stored in a non-volatile memory such as a flash memory. The values ​​of the non-lock-step mode valid signal SEL_C, the bus selection signal SEL_P1, and the bus selection signal SEL_P2 can be set by reading the values ​​of external terminals (not shown here) provided in the semiconductor device 1.

[0050] For example, refer to Figure 2 , the non-lock-step mode valid signal SEL_C indicates the lock-step mode when it is 0, and indicates the non-lock-step mode when it is 1. The bus selection signals SEL_P1 and SEL_P2 indicate the selection of the first bus 20 when they are 0, and indicate the selection of the second bus 21 when they are 1. When the non-lock-step mode valid signal SEL_C is 0, the bus selection signals SEL_P1 and SEL_P2 are always 0, and both the selector 31 and the selector 33 select the first bus 20. On the other hand, when the non-lock-step mode valid signal SEL_C is 1, the bus selection signals SEL_P1 and SEL_P2 are determined according to the setting values ​​of the setting registers 42 and 43, respectively. Therefore, when SEL_C is 1, the selectors 31 and 33 respectively select which bus of the first bus 20 and the second bus 21 is variable.

[0051] Figure 3 is a diagram illustrating an exemplary bus access path when the semiconductor device 1 operates in the lockstep mode. Figure 3As indicated by the thick arrow in , in the lockstep mode, the selector 13 selects the first bus 20 and sends the interface signal group 15 included in the first bus 20 as the interface signal 18 to the second processor 11. Additionally, the selector 13 suppresses transmission so that the interface signal 16 group output by the second processor 11 is not sent to the first bus 20 and the second bus. Since the selector 31 selects the first bus 20, the first processor 10 accesses the non-shared resource 30 via the first bus. Similarly, since the selector 33 selects the first bus 20, the first processor 10 accesses the non-shared resource 32 via the first bus.

[0052] The first processor 10 sends an interface signal 14 to the non-shared resource 30 and the non-shared resource 32 via the first bus 20. The first processor 10 also receives an interface signal 15 from the non-shared resource 30 and the non-shared resource 32 via the first bus 20. The second processor 11 receives the interface signal 15 from the non-shared resource 30 and the non-shared resource 32 via the first bus 20 as an interface signal 18. The bus interface signal group 15 and the bus interface signal group 18 have the same value. Therefore, when both the first processor 10 and the second processor 11 operate normally, the interface signal group 14 reflecting the calculation result of the first processor 10 matches the interface signal group 16 reflecting the calculation result of the second processor 11. Therefore, the comparator 12 does not activate the error signal ERR. On the other hand, if the first processor 10 or the second processor 11 contains a fault, the comparator 12 activates the error signal ERR.

[0053] Figure 4 is a diagram illustrating an exemplary bus access path when the semiconductor device 1 operates in a non-lockstep mode. More specifically, Figure 4 4 shows the bus access path of the semiconductor device 1 when the setting registers 42 and 43 are set to 0 and 1, respectively (ie, SEL_P1=0 and SEL_P2=1). Figure 4 In, with Figure 3 More specifically, the bus access path formed by the first processor 10, the first bus 20 and the non-shared resource 30 is separated from the bus access path formed by the second processor 11, the second bus 21 and the non-shared resource 32, and the corresponding bus accesses do not conflict with each other.

[0054] In the non-lockstep mode (SEL_C=1), the selector 13 selects the second bus, the interface signal group 17 is sent to the second processor 11, and the interface signal group 16 is sent to the second bus 21. Since the selector 31 selects the first bus 20 by setting SEL_P1=0, the non-shared resource 30 is accessed by the first processor 10 via the first bus 20. Since the selector 33 selects the second bus 21 by setting SEL_P2=1, the non-shared resource 32 is accessed by the second processor 11 via the second bus.

[0055] The first processor 10 sends an interface signal 14 to the non-shared resource 30 via the first bus 20. The first processor 10 also receives an interface signal 15 from the non-shared resource 30 via the first bus 20. On the other hand, the second processor 11 sends an interface signal group 16 to the non-shared resource 32 via the second bus 21. The second processor 11 receives an interface signal group 17 as an interface signal group 18 from the non-shared resource 32 via the second bus 21.

[0056] Figure 5 is a flowchart illustrating an exemplary operation of the semiconductor device 1. Figure 5 The operation of the semiconductor device 1 is described. The method of operating the semiconductor device 1 includes a step S101 of setting the operation mode before starting the desired processing in the first processor 10 and the second processor 11. Here, the operation mode is a lockstep mode or a non-lockstep mode. For example, with the power-on reset of the semiconductor device 1, SEL_C is initialized to 0. That is, the operation mode is initialized to the lockstep mode by the power-on reset of the semiconductor device 1, but the method of setting the operation mode is not limited to this method. For example, SEL_C can be determined by referring to the value of the external terminal of the semiconductor device 1 when the semiconductor device 1 is powered on and reset. After the power-on reset of the semiconductor device 1 is released, the first processor can execute an initialization program to rewrite the value of the setting register 41 and set the value of SEL_C.

[0057] Then, in step S102, the semiconductor device 1 selects a bus through which the first processor 10 or the second processor 11 accesses the first non-shared resource 30. More specifically, for example, the first processor 10 executes a program to write a setting value in the setting register 42. Therefore, the bus selected by the selector 31 is set in the non-lockstep mode. Similarly, in step S103, the semiconductor device 1 selects a bus through which the first processor 10 or the second processor 11 accesses the first non-shared resource 32. More specifically, for example, the first processor 10 executes a program to write a setting value in the setting register 43. Therefore, the bus selected by the selector 33 is set in the non-lockstep mode.

[0058] In step S104 , the semiconductor device 1 causes the first processor 10 and the second processor 11 to start desired processing.

[0059] Each of the first processor 10 and the second processor 11 repeats the processing from step S105 to step S112 until the desired program processing is completed. That is, in step S105, the first processor 10 and the second processor 11 access the non-shared resources 30 and 32 respectively according to the program instructions executed by each. In step S107, in the lockstep mode (i.e., "yes" in step S106), the non-shared resources 30 and the non-shared resources 32 are accessed by the first processor 10 via the first bus 20. In the lockstep mode (i.e., "yes" in step S106), since the selector 13 selects the first bus, the second processor 11 receives the interface signal group 15. However, in the lockstep mode (i.e., "yes" in step S106), the access to the non-shared resources 30 or 32 by the second processor 11 via the second bus 21 does not occur.

[0060] On the other hand, in the non-lockstep mode (i.e., "No" in step S106), the first processor 10 accesses the non-shared resource 30 or 32 respectively according to the values ​​of SEL_P1 and SEL_P2. In the non-lockstep mode (i.e., "No" in step S106), since the selector 13 selects the second bus 21, the second processor 11 accesses the non-shared resource 30 or 32 respectively through the second bus 21 according to the values ​​of SEL_P1 and SEL_P2. Hereinafter, the operation of the semiconductor device 1 when the setting registers 42 and 43 are set to 0 and 1 respectively (i.e., when SEL_P1=0 and SEL_P2=1) will be described. In this case, the first processor 10 exclusively uses the non-shared resource 30, and the second processor 11 exclusively uses the non-shared resource 32.

[0061] In step S109, when the first processor 10 or the second processor 11 accesses the non-shared resource 30 or 32, the selector 31 or 33 determines whether the bus access is normal. For example, if the first processor 10 attempts to access the non-shared resource 30 dedicated to the first processor 10, the selector 31 determines that the access is normal (i.e., "yes" in step S109). On the other hand, when the first processor 10 attempts to access the non-shared resource 32 dedicated to the second processor 11, the selector 33 determines that the access is illegal (i.e., "no" in step S109). In step S112, when it is determined that the bus access is illegal, the semiconductor device 1 performs access error processing. For example, in step S112, as the access error processing, the semiconductor device 1 can cause the first processor 10 to perform exception processing.

[0062] In step S110, when it is determined that the bus access to the non-shared resource 30 or 32 is normal (i.e., "Yes" in step S109), it is determined whether the bus selected by the selector 31 or 33 is the first bus 20. If the selected bus is the first bus 20 (i.e., "Yes" in step S110), the non-shared resource 30 or 32 is accessed via the first bus 20 in step S107. On the other hand, in step S111, when the selected bus is not the first bus 20 (i.e., "No" in step S110), the non-shared resource 30 or 32 is accessed via the second bus 21. In the example described above, SEL_P1 is 0. Therefore, the first bus 20 is selected for the non-shared resource 30 (i.e., "Yes" in step S110). Therefore, in step S107, the non-shared resource 30 is accessed by the first processor 10 via the first bus. On the other hand, in the above example, SEL_P2 is 1. Therefore, the second bus 21 is selected for the non-shared resource 32 (ie, “No” in step S110 ). Therefore, in step S111 , the non-shared resource 32 is accessed by the second processor 11 via the second bus.

[0063] When the first processor 10 or the second processor 11 has not completed the execution of the corresponding program after the access to the non-shared resources 30 and 32 (steps S107, S111) or the access error processing (i.e., "No" in step S108), the processing from step S105 is repeated. On the other hand, in step S113, when the first processor 10 and the second processor 11 have completed the execution of the corresponding program (i.e., "Yes" in step S108), the processing of the semiconductor device 1 ends.

[0064] According to the first embodiment, the semiconductor device 1 includes a first bus 20, a second bus 21, non-shared resources 30 and 32, and selectors 13, 31, and 33. Therefore, in the non-lock-step mode, when the first processor 10 exclusively uses the non-shared resource 30, bus access to the non-shared resource 30 can be set to pass through the first bus 20 by the selection of the selector 31. In the non-lock-step mode, when the second processor 11 exclusively uses the non-shared resource 32, bus access to the non-shared resource 32 can be set to pass through the second bus 21 by the selection of the selector 33. Therefore, when the first processor 10 and the second processor 11 access the dedicated non-shared resources 30 and 32, respectively, the occurrence of bus access conflicts can be suppressed. In this way, the access paths of the corresponding non-shared resources exclusively used by the corresponding processors are completely separated in the non-lock-step mode, so that the performance of the semiconductor device 1 is not degraded due to access conflicts. In addition, since conflicts in bus access can be suppressed, the present invention is suitable for applications such as those requiring quality of service (i.e., QoS) security.

[0065] (Second embodiment)

[0066] Next, a second embodiment is described. Figure 6 1 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a second embodiment. The semiconductor device 1A according to the second embodiment is different from the semiconductor device 1 according to the first embodiment in that it further includes a shared resource 50 and an arbiter 51. Other configurations and operations are the same as those of the semiconductor device 1 described in the first embodiment, and therefore, the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0067] The shared resource 50 is a resource that can be accessed by any one of the first processor 10 and the second processor 11 in the non-lockstep mode. In other words, the first processor 10 and the second processor 11 jointly utilize the shared resource. The shared resource 50 is a circuit including peripheral functions such as a memory, a timer, an I / O interface circuit, an analog-to-digital conversion circuit, or a digital-to-analog conversion circuit. The shared resource 50 is coupled to the first bus 20 and the second bus 21 via the arbiter 51. Although Figure 6 An exemplary configuration including one shared resource 50 as a shared resource and two non-shared resources 30 and 32 as non-shared resources is shown, but the configuration of the semiconductor device 1A is not limited thereto. The semiconductor device 1A may include two or more shared resources coupled to the first bus 20 and the second bus 21. The semiconductor device 1A may include one non-shared resource and any number of shared resources.

[0068] The arbiter 51 arbitrates the processing order of the access request to the shared resource 50 received via the first bus 20 or the second bus 21. That is, in the non-lockstep mode, when the first access request of the first processor 10 to access the shared resource 50 via the first bus 20 conflicts with the second access request of the second processor 11 to access the shared resource 50 via the second bus 21, the arbiter 51 determines which access request is prioritized. The arbitration scheme of the arbiter 51 can adopt various schemes (such as a fixed priority scheme and a round robin scheme). In the case of adopting a system in which access is given priority to a specific bus as in a fixed priority system, it is preferred to implement a priority selection signal SEL_P3 for setting which bus access is prioritized. The priority selection signal SEL_P3 can be variable according to the register setting.

[0069] The operation of the semiconductor device 1A according to the second embodiment will be described. When the semiconductor device 1A operates in the lockstep mode, the first processor 10 accesses the non-shared resource 30, the non-shared resource 32, and the shared resource 50 via the first bus 20. When the semiconductor device 1A operates in the lockstep mode, the second processor 11 does not access any of the non-shared resource 30, the non-shared resource 32, or the shared resource 50 via the second bus 21, but only receives the interface signal group 15 via the first bus.

[0070] Next, when the semiconductor device 1A operates in the non-lockstep mode, the operation of the semiconductor device 1A under the setting of SEL_P1 = 0 and SEL_P2 = 1 will be described. In this case, the first processor 10 accesses the non-shared resource 30 and the shared resource 50 via the first bus 20. The second processor 11 accesses the non-shared resource 32 and the shared resource 50 via the second bus 21.

[0071] According to the second embodiment, the semiconductor device 1A includes a shared resource 50 and an arbiter 51. Therefore, when operating in a non-lockstep mode, the first processor 10 and the second processor 11 can access the shared resource 50 via the first bus 20 and the second bus 21, respectively. For access to the shared resource 50, access by the first processor 10 and access by the second processor 11 may conflict. However, the conflicting accesses are arbitrated by the arbiter 51.

[0072] Similar to the first embodiment, the bus used by the non-shared resources 30 and 32 can be specified by the selectors 31 and 33. Therefore, for example, the first processor 10 can access the non-shared resource 30 via the first bus 20. In addition, the second processor 11 can access the non-shared resource 32 via the second bus 21. Since the bus access to the non-shared resource 30 and the bus access to the non-shared resource 32 are separated from each other, the access to the non-shared resource 30 by the first processor 10 and the access to the non-shared resource 32 by the second processor 11 do not conflict with each other.

[0073] In the non-lockstep mode, the semiconductor device 1A according to the present embodiment can support resources shared among a plurality of processors. Therefore, for example, when the shared resource 50 is an SRAM (i.e., static random access memory), a plurality of processors can exchange data with each other via the shared resource 50. For example, when the shared resource 50 is a timer, processing can be performed based on the same information held by the timer.

[0074] (Modification Example of Second Embodiment)

[0075] Figure 71 is a configuration block diagram illustrating a modified example of the semiconductor device according to the second embodiment. Compared with the semiconductor device 1A according to the second embodiment, the semiconductor device 1B according to the present modified example is different therefrom in that a shared resource 50B includes a read interface 52 (hereinafter sometimes referred to as a "read I / F") and a write interface 53 (hereinafter sometimes referred to as a "write I / F"), and in that the semiconductor device 1B includes selectors 54 and 55 instead of the arbitrator 51. The shared resource 50B is a circuit including peripheral functions such as a memory, a timer, an I / O interface circuit, an analog-to-digital conversion circuit, or a digital-to-analog conversion circuit. The shared resource 50B is coupled to the first bus 20 and the second bus 21 via the selector 54 and the selector 55, and the shared resource 50B can be accessed by the first processor 10 and the second processor 11.

[0076] The read I / F 52 is an interface for reading data from the shared resource 50B. The selector 54 selects whether to access the read I / F 52 through the first bus 20 or through the second bus 21. The selector 54 receives the bus selection signal SEL_P3R output from the controller 40B, and selects one of the first bus 20 and the second bus 21. In the lockstep mode, SEL_P3R is set to a value that the selector 54 selects the first bus 20. In the lockstep mode, the read I / F 52 is accessed via the first bus 20. On the other hand, in the non-lockstep mode, SEL_P3R can be set to a value that the selector 54 selects the first bus 20 and a value that the selector 54 selects the second bus 21. In the non-lockstep mode, the read I / F 52 is accessed via the first bus 20 or the second bus according to the SEL_P3R value.

[0077] The write I / F 53 is used to write data to the shared resource 50B. The selector 55 selects whether to access the write I / F 55 via the first bus 20 or via the second bus 21. The selector 55 receives the bus selection signal SEL_P3W output from the controller 40B, and selects one of the first bus 20 and the second bus 21. In the lockstep mode, SEL_P3W is set to a value that the selector 55 selects the first bus 20. In the lockstep mode, the write I / F 53 is accessed via the first bus 20. On the other hand, in the non-lockstep mode, SEL_P3W may be set to a value that the selector 55 selects the first bus 20 and a value that the selector 55 selects the second bus 21. In the non-lockstep mode, the write I / F 53 is accessed via the first bus 20 or the second bus 21 according to the SEL_P3W value.

[0078] exist Figure 7In the embodiment, the selector 54 and the selector 55 are provided for both the read I / F 52 and the write I / F 53, but the configuration of the semiconductor device 1B is not limited thereto. For example, at least one of the selector 54 and the selector 55 may implement a similar Figure 6 The bus access arbitration function is similar to the arbiter 51 of FIG. Figure 6 When the selectors 54 and 55 implement a bus access arbitration function similar to that of an arbitrator, it is preferable to implement priority selection signals SEL_P3R and SEL_P3W for setting which bus access is preferentially processed.

[0079] Figure 6 and Figure 7 Selectors 31 and 33, Figure 7 Selectors 54 and 55 and Figure 6 The arbitrator 51 can realize both the selection function and the arbitration function described above.

[0080] The generation circuits of SEL_P3R and SEL_P3W included in the controller 40B are connected to the Figure 2 The generation circuits of SEL_P1 and SEL_P2 in are the same. Figure 2 , bus selection signals SEL_P1 and SEL_P2 indicate binary values ​​of 0 and 1. When the selection function and arbitration function are implemented as described above, the bus selection signals SEL_P1 and SEL_P2 can be implemented by increasing the number of setting registers to obtain three or more values ​​so that the implemented function can be selected.

[0081] The operation of the semiconductor device 1B according to the present modification example will be described. When the semiconductor device 1B operates in the lockstep mode, the first processor 10 accesses the non-shared resource 30, the non-shared resource 32, and the shared resource 50B via the first bus 20. When the semiconductor device 1B operates in the lockstep mode, the second processor 11 does not access any of the non-shared resource 30, the non-shared resource 32, or the shared resource 50B via the second bus 21, but receives the interface signal 15 only via the first bus. On the other hand, when the semiconductor device 1B operates in the non-lockstep mode, for example, under the setting of SEL_P1=0, SEL_P2=1, SEL_P3R=0, and SEL_P3W=1, the first processor accesses the non-shared resource 30 and the read I / F 52 of the shared resource 50B via the first bus 20. When the semiconductor device 1B operates in the non-lockstep mode, for example, under the setting of SEL_P1=0, SEL_P2=1, SEL_P3R=0, and SEL_P3W=1, the second processor 11 accesses the non-shared resource 32 and the write I / F 53 of the shared resource 50B via the second bus 21. As described above, under the setting of SEL_P3R=0 and SEL_P3W=1, the selectors 54 and 55 select different buses among the first bus 20 and the second bus 21.

[0082] In the semiconductor device 1B according to the present modification example, the shared resource 50B includes a read I / F 52 and a write I / F 53. The semiconductor device 1B further includes a selector 54 for selecting a bus used to access the read I / F 52, and a selector 55 for selecting a bus used to access the write I / F 53. According to the selection of the selector 54, the bus used to access the read I / F 52 is one of the first bus 20 and the second bus 21. Similarly, according to the selection of the selector 55, the bus used to access the write I / F 53 is one of the first bus 20 or the second bus 21. The selector 54 and the selector 55 can be configured to select different buses among the first bus 20 and the second bus 21. Therefore, it is possible to suppress the degradation of the processing performance of the semiconductor device 1B due to the conflict between the write access and the read access performed on the shared resource 50B.

[0083] Similar to the first embodiment, the bus used by the non-shared resources 30 and 32 can be selected by the selectors 31 and 33. Therefore, for example, the non-shared resource 30 can be accessed via the first bus 20. In addition, the non-shared resource 32 can be accessed via the second bus 21. Since the bus access to the non-shared resource 30 and the bus access to the non-shared resource 32 are separated from each other, the access to the non-shared resource 30 by the first processor 10 and the access to the non-shared resource 32 by the second processor 11 do not conflict with each other. Therefore, the performance degradation of the semiconductor device 1B due to the conflict of access to the non-shared resources 30 and 32 can be suppressed.

[0084] (Third Embodiment)

[0085] Figure 8 1 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a third embodiment. The semiconductor device 1C according to the third embodiment is different from the semiconductor device 1 according to the first embodiment in that it further includes a DMAC (i.e., direct memory access controllers 60 and 61). Other configurations and operations are the same as those of the semiconductor device 1 described in the first embodiment, and therefore, the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0086] The DMAC 60 is a first bus master and has a function of reading data specified by a transfer source address and writing the read data to a transfer destination address based on an operation instruction set by the first processor 10 via the first bus 20. The DMAC 60 communicates with the non-shared resource 30 or the non-shared resource 32 via the first bus 20.

[0087] The DMAC 61 is a second bus master and has a function of reading data specified by a transfer source address and writing the read data to a transfer destination address based on an operation instruction set by the second processor 11 via the second bus 21. The DMAC 61 communicates with the non-shared resource 30 or the non-shared resource 32 via the second bus 21.

[0088] In the lockstep mode, the DMAC 60 accesses the non-shared resources 30 and 32 via the first bus 20 based on the setting of the first processor 10. In the non-lockstep mode, the DMAC 60 accesses the non-shared resource 30 or the non-shared resource 32 via the first bus 20 based on the DMA transfer setting set by the first processor 10 via the first bus 20. The DMAC 61 accesses the non-shared resource 30 or the non-shared resource 32 via the second bus 21 based on the DMA transfer setting set by the second processor 11 via the second bus 21. The non-shared resources accessible to the DMAC 60 and the DMAC 61 are determined by the values ​​of the registers 42 and 43. For example, if the values ​​of the bus selection signals are SEL_P1=0 and SEL_P2=1, in the non-lockstep mode, the DMAC 60 accesses the non-shared resource 30 via the first bus 20. The DMAC 61 accesses the non-shared resource 32 via the second bus 21.

[0089] According to the third embodiment, the semiconductor device 1C includes the DMAC 60 and the DMAC 61. Therefore, in addition to the processor, the access paths of the DMAC 60 and the DMAC 61 can also be divided into the first bus and the second bus for DMA transfer handled by the DMAC including the bus master function. Therefore, in the non-lockstep mode, the DMA transfer of the DMAC 60 on the first bus 20 after the setup instruction of the DMA transfer from the first processor 10 to the DMAC 60 does not conflict with the DMA transfer of the DMAC 61 on the second bus 21 after the setup instruction of the DMA transfer from the second processor 11 to the DMAC 61. Therefore, even in the case where the semiconductor device includes other bus masters in addition to the processor, performance degradation caused by access conflicts on the bus can be suppressed.

[0090] exist Figure 8 In the embodiment of the present invention, the DMAC 60 and the bus master 61 are exemplary, but the configuration of the semiconductor device 1C is not limited thereto. The DMAC 60, 61 may be any peripheral functional circuit including other bus master functions.

[0091] exist Figure 8 In the configuration of FIG. 1 , the DMAC 60 and the first processor 10 share the first bus 20 as a bus master. Figure 8 Unlike the configuration shown in , a third bus (not shown) for DMAC 60 or DMAC 61 may be further added, and communication with non-shared resources or the like may be performed via the bus. In this case, it is preferred to extend selectors 31 and 33 so that the third bus can also be selected. However, selectors 31 and 33 are not necessarily configured to be able to couple to all buses.

[0092] In addition, the semiconductor device 1C may include a plurality of peripheral functions, including a bus master function coupled to the first bus as needed. Similarly, the semiconductor device 1C may include a plurality of peripheral functions, including a bus master function coupled to the second bus. The semiconductor device 1C may be configured not to include the DMAC 60 or 61.

[0093] (Fourth embodiment)

[0094] Fig. 9 1 is a block diagram illustrating an exemplary configuration of a semiconductor device according to a fourth embodiment. Compared with the semiconductor device 1 according to the first embodiment, the semiconductor device 1D according to the fourth embodiment is different therefrom in that the non-shared resource 32 is replaced by a non-shared resource 32D. Other configurations and operations are the same as those of the semiconductor device 1 described in the first embodiment, and therefore, the same reference numerals are assigned to the same configurations, and repeated descriptions are omitted.

[0095] In the semiconductor device 1D, the non-shared resource 32D includes a cryptographic coprocessor. The cryptographic coprocessor is a coprocessor that performs processing related to cryptographic processing. For example, if the semiconductor device 1D operates in a non-lockstep mode, the second processor is dedicated to the cryptographic coprocessor 32D.

[0096] According to the fourth embodiment, the semiconductor device 1D includes a first bus 20, a second bus 21, a selector 13, selectors 31 and 33, and a cryptographic coprocessor 32D as a non-shared resource. Therefore, the semiconductor device 1D can have the following configuration: for example, the first bus 20 coupling the first processor 10 and the second bus 21 coupling the second processor 11 and the cryptographic coprocessor 32D are separated from each other. In applications in the security field, it is generally necessary to separate QoS from other applications and ensure the security of QoS. Since in the non-lockstep mode, the access path to the cryptographic coprocessor 32D as a non-shared resource can be separated from the access path used by the first processor, the semiconductor device 1D according to this embodiment is suitable for implementing applications in the security field.

[0097] Although the invention made by the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the embodiments that have been described, and various modifications can be made without departing from the gist thereof. For example, the expansion of the bus slave in the second embodiment can be combined with the expansion of the bus master in the third embodiment. The DMACs 60 and 61 according to the third embodiment can be coupled to the first bus 20 and the second bus 21 respectively via a selector or an arbitrator.

Claims

1. A semiconductor device comprising: a first processor; a second processor that monitors operation of the first processor in the first mode; A first non-shared resource and a second non-shared resource are dedicated to the first processor or the second processor; a first bus, the first processor, the second processor, the first non-shared resource, and the second non-shared resource being coupled by the first bus; a second bus, the second processor, the first non-shared resource, and the second non-shared resource being coupled by the second bus; first selector; Second selector; as well as Third selector; wherein the first selector selects the first bus or the second bus, and transmits an interface signal group between the second processor and the selected bus through the first selector; wherein the second selector selects the first bus or the second bus, and the first non-shared resource is accessed by the first processor and the second processor via the bus selected by the second selector; wherein the third selector selects the first bus or the second bus, and the second non-shared resource is accessed by the first processor or the second processor via the bus selected by the third selector; wherein in the first mode, the first processor and the second processor execute the same instruction stream, the first selector selects the first bus, and transmits the first interface signal group included in the interface signal group to the second processor; Wherein, in the second mode, the first processor and the second processor execute different instruction streams, the first selector selects the second bus, the second selector selects the first bus, the third selector selects the second bus, and the second interface signal group included in the interface signal group is transmitted to the second processor. 2 . The semiconductor device according to claim 1 , wherein in the second mode, the first processor accesses the first non-shared resource via the first bus, and the second processor accesses the second non-shared resource via the second bus.

3. The semiconductor device according to claim 1, further comprising: Comparator; wherein the second processor outputs a third interface signal group included in the interface signal group to the first selector; wherein the first processor outputs a fourth interface signal group not included in the interface signal group to the first bus; and Wherein when the third interface signal group and the fourth interface signal group are different from each other, the comparator activates the error signal. 4 . The semiconductor device according to claim 3 , wherein the first selector prevents the third interface signal group from being sent to the first bus in the first mode, and transfers the third interface signal group to the second bus in the second mode.

5. The semiconductor device according to claim 1, wherein In the second mode, the second selector detects access to the first non-shared resource by the second processor as an illegal access, and the third selector detects access to the second non-shared resource by the first processor as an illegal access.

6. The semiconductor device according to claim 1, wherein In the second mode, selection of the first bus or the second bus by each of the second selector and the third selector is variable.

7. The semiconductor device according to claim 1, further comprising a shared resource commonly used by the first processor and the second processor, in, In the second mode, the first processor accesses the shared resource via the first bus, and the second processor accesses the shared resource via the second bus.

8. The semiconductor device according to claim 1, Further including: a shared resource utilized by the first processor and the second processor; fourth selector; as well as fifth selector; The shared resources include: Reading interface; and Write interface; wherein the fourth selector selects the first bus or the second bus, and the shared resource is accessed by the first processor or the second processor via the bus selected by the fourth selector; The fifth selector selects the first bus or the second bus, and the shared resource is accessed by the first processor or the second processor via the bus selected by the fifth selector.

9. The semiconductor device according to claim 8, wherein: In the second mode, the fourth selector and the fifth selector select different buses from the first bus and the second bus.

10. The semiconductor device according to claim 9, in, In the second mode, when the first processor includes read access to the shared resource via the first bus, the second processor includes write access to the shared resource via the second bus; and Wherein, in the second mode, when the first processor has write access to the shared resource via the first bus, the second processor includes read access to the shared resource via the second bus.

11. The semiconductor device according to claim 1, Further including: a first bus master; as well as a second bus master; The first bus master is coupled to the first bus, and the second bus master is coupled to the second bus. 12 . The semiconductor device according to claim 1 , wherein the second non-shared resource comprises a cryptographic coprocessor that performs cryptographic processing.

13. A method of operating a semiconductor device, the semiconductor device comprising a first processor and a second processor, a first non-shared resource and a second non-shared resource, a first bus and a second bus, and first to third selectors, wherein: The first processor is coupled to the first bus, and the method includes: Setting a first operation mode or a second operation mode; In the first operating mode, the same instruction stream is executed by the first processor and the second processor; and In the second operation mode, different instruction streams are executed by the first processor and the second processor; The execution of the same instruction stream includes: selecting the first bus by the first selector, and coupling the second processor to the first bus; selecting the first bus by the second selector, and coupling the first non-shared resource to the first bus; selecting the first bus by the third selector, and coupling the first bus with the second non-shared resource; accessing the first non-shared resource and the second non-shared resource by the first processor via the first bus and the second selector; transmitting the interface signal group to the second processor through the first bus via the second selector; and comparing outputs of the first processor and the second processor; and The execution of different instruction streams includes: selecting the second bus by the first selector and coupling the second processor to the second bus; selecting the first bus by the second selector and coupling the first non-shared resource to the first bus; The third selector selects the second bus and couples the second bus to the second non-shared resource; accessing the first non-shared resource by the first processor via the first bus and the second selector; and The second non-shared resource is accessed by the second processor via the second bus and the third selector.

14. The method of operating the semiconductor device according to claim 13, wherein the executing different instruction streams further comprises: Access to the second non-shared resource by the first processor and access to the first non-shared resource by the second processor are determined as illegal accesses.

15. The method of operating the semiconductor device according to claim 13, the semiconductor device further comprising a shared resource, The executing of different instruction streams further comprises: accessing the shared resource by the first processor via the first bus; as well as The shared resource is accessed by the second processor via the first selector and the second bus.

16. The method of operating the semiconductor device according to claim 13, the semiconductor device further comprising a first bus master and the second bus master, The executing of different instruction streams further comprises: coupling the first bus master to the first bus; as well as The second bus master is coupled to the second bus.

17. The method for operating the semiconductor device according to claim 13, wherein: The executing a different instruction stream further includes performing cryptographic processing using the second non-shared resource.

18. A semiconductor device comprising: a first processor; a second processor that monitors operation of the first processor in the first mode; A shared resource, used by the first processor and the second processor; a non-shared resource, dedicated to the second processor in the second mode; a first bus, using which the first processor, the second processor, the shared resource, and the non-shared resource are coupled; a second bus, by which the second processor, the shared resource, and the non-shared resource are coupled; first selector; as well as Second selector; wherein the first selector selects the first bus or the second bus, and transmits an interface signal group between the second processor and the bus selected by the first selector; wherein the second selector selects the first bus or the second bus, and the non-shared resource is accessed by the first processor and the second processor via the bus selected by the second selector; wherein in the first mode in which the first processor and the second processor execute the same instruction stream, the first selector selects the first bus and transmits a first interface signal group included in the interface signal group to the second processor; Wherein, in the second mode in which the first processor and the second processor execute different instruction streams, the first selector selects the second bus, and the second selector selects the first bus, and transmits the second interface signal group included in the interface signal group to the second processor.

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