DC-DC voltage converter with controller

Abstract

A system (100) includes a DC-DC voltage converter (102), the DC-DC voltage converter including: a high-side FET (104) including a gate, a source, and a drain; a node (124) coupled to the source of the high-side FET (104); a low-side FET (106) including a gate, a source, and a drain coupled to the node (124); and a controller (110) coupled to the gate of the high-side FET (104) to turn the high-side FET (104) on and off, and coupled to the gate of the low-side FET (106) to turn the low-side FET (106) on and off, the controller being configured to turn the low-side FET (106) on for a certain time interval before turning the high-side FET (104) on and to turn the low-side FET (106) off before turning the high-side FET (104) on.

Description

Background Art

[0001] A step-down DC-DC voltage converter regulates a load voltage, where the value of the load voltage is less than the input voltage provided by the power supply. The buck converter topology represents a class of DC-DC voltage converters having a switching device that controls the current through an inductor (and often also a capacitor) to regulate the load voltage. A buck converter includes: a high-side switching device that couples the inductor to the power supply; and a low-side switching device that provides a current path from ground to the inductor when the high-side switching device is turned off. In some buck converters, the high-side switching device is a field effect transistor (FET), referred to as a high-side FET, and the low-side device is a FET, referred to as a low-side FET, or a diode, sometimes referred to as a flyback diode. Summary of the invention

[0002] According to at least one example of the present invention, a system includes a DC-DC voltage converter, the DC-DC voltage converter including: a high-side FET, which includes a gate, a source and a drain; a node, which is coupled to the source of the high-side FET; a low-side FET, which includes a gate, a source and a drain coupled to the node; and a controller, which is coupled to the gate of the high-side FET to turn on and off the high-side FET, and is coupled to the gate of the low-side FET to turn on and off the low-side FET, the controller being configured to turn on the low-side FET for a certain time interval before turning on the high-side FET, and to turn off the low-side FET before turning on the high-side FET.

[0003] According to at least one example of the present invention, a system includes: an inductor; a first field effect transistor (FET) that conducts current to the inductor when turned on; a diode that is coupled to the inductor to conduct current to the inductor when the first FET is turned off; a second FET that is coupled in parallel with the diode; and a controller that turns on the second FET for a certain time interval before turning on the first FET, and turns off the second FET before turning on the first FET.

[0004] According to at least one example of the present invention, a method of operating a DC-DC voltage converter includes: turning on and off a high-side field effect transistor FET and a low-side FET in the DC-DC voltage converter to regulate the voltage at a node in the DC-DC voltage converter; during asynchronous operation of the DC-DC voltage converter, turning on the low-side FET for a certain time interval before turning on the high-side FET; and during asynchronous operation of the DC-DC voltage converter, turning off the low-side FET before turning on the high-side FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To describe various examples in detail, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 presenting a system including a DC-DC voltage converter according to various examples;

[0007] Figure 2 presenting timing diagrams according to various examples;

[0008] Figure 3 presenting a system including a DC-DC voltage converter according to various examples;

[0009] Figure 4 Methods according to various examples are presented.

[0010] Figure 5 Demonstrating controllers according to various examples;

[0011] Figure 6 presenting timing diagrams according to various examples;

[0012] Figure 7 presenting a system including a DC-DC voltage converter according to various examples; and

[0013] Figure 8 Systems including DC-DC voltage converters according to various examples are presented. DETAILED DESCRIPTION

[0014] In many conventional DC-DC voltage converters with a buck converter topology including a high-side device and a low-side device, when the low-side device is conducting forward diode conduction during asynchronous mode operation, the conduction current of the majority carriers in the low-side device causes the space region to be charged. When the high-side device is turned on to provide current to the load, some of the current in the high-side device is used to discharge the space region, which can cause undesirable power consumption. In addition, due to parasitic inductance, the current used to discharge the space region can cause undesirable noise spikes, which can interfere with other circuits coupled to the conventional DC-DC voltage converter.

[0015] Embodiments include a DC-DC voltage converter having a controller such that during asynchronous operation, the controller turns on the low side FET for a time interval to discharge the space region before turning on the high side FET.

[0016] Figure 1An illustrative system 100 is depicted that includes a DC-DC voltage converter 102. In some embodiments, the DC-DC voltage converter 102 is a buck converter. The DC-DC voltage converter 102 includes a high-side FET 104, a low-side FET 106, a gate driver 108, and a controller 110. (For some embodiments, the gate driver 108 may also include a charge pump). The controller 110 is coupled to the high-side FET 104 and the low-side FET 106 through the gate driver 108. In addition to the controller 110 and the gate driver 108, embodiments may also include other modules (not shown).

[0017] The high-side FET 104 includes a gate 112, a source 114, and a drain 116. A node 124 is coupled to the source 114 of the high-side FET 104. The node 124 is referred to as a switch node and can be a pin. The low-side FET 106 includes a gate 118, a source 120, and a drain 122 coupled to the node 124.

[0018] Through gate driver 108, controller 110 is coupled to gate 112 of high-side FET 104 to turn high-side FET 104 on and off, and to gate 118 of low-side FET 106 to turn low-side FET 106 on and off to provide a load voltage to load 126. Load 126 is coupled to node 124 through inductor 128 and capacitor 130.

[0019] The drain 116 of the high-side FET 104 is coupled to a power source 144, wherein Figure 1 The diagram illustrates providing a voltage V to the DC-DC voltage converter 102 IN 144 as an input voltage. Parasitic inductor 146 represents a parasitic inductance associated with coupling drain 116 to power supply 144. This coupling may include an input / output (I / O) pin (not shown). Source 120 of low-side FET 106 is coupled to ground 148. Parasitic inductor 150 represents a parasitic inductance associated with coupling source 120 to ground 148. This coupling may include an I / O pin (not shown).

[0020] exist Figure 1 In the specific embodiment illustrated in FIG. 1 , the controller 110 provides logic signals HS_ON, EN, and LS_ON to the gate driver 108 to turn on and off the high-side FET 104 and the low-side FET 106. The logical complement of these signals (in Figure 1 HS_ONZ, ENZ and LS_ONZ, respectively, are indicated as signals in the gate driver 108.

[0021] The gate driver 108 includes a NOR gate 133 coupled to series connected buffers 134 and 136, where the buffer 136 directly drives the gate 112 of the high-side FET 104. In practice, more than two buffers may be connected in series between the output of the NOR gate 133 and the gate 112 of the high-side FET 104, but for ease of illustration, only two such buffers are explicitly shown: buffers 134 and 136.

[0022] The gate driver 108 includes a NOR gate 138 coupled to series-connected buffers 140 and 142, with the buffer 142 directly driving the gate 118 of the low-side FET 106. In practice, more than two buffers may be connected in series between the output of the NOR gate 138 and the gate 118 of the low-side FET 106, but for ease of illustration, only two such buffers are explicitly shown: buffers 140 and 142.

[0023] Signals HS_ONZ and ENZ are provided as two inputs to NOR gate 133, and the output of buffer 142 is provided as a third input to NOR gate 133. Signals LS_ONZ and ENZ are provided as two inputs to NOR gate 138, and source 114 of high side FET 104 is connected to its third input.

[0024] To enable gate driver 108, controller 110 asserts signal EN high (deasserts signal ENZ low). With gate driver 108 enabled, controller 110 may operate DC-DC voltage converter 102 in synchronous mode or in asynchronous (or non-synchronous) mode according to signals HS_ON and LS_ON.

[0025] When the controller 110 operates the DC-DC voltage converter 102 in synchronous mode, the signals HS_ON and LS_ON alternately cycle between high and low states without overlap so that both the high-side FET 104 and the low-side FET 106 are not turned on at the same time. A feedback circuit (not shown) provides a feedback signal to the feedback node 132 so that the controller 110 can control the duty cycle of the signals HS_ON and LS_ON to provide a regulated load voltage to the load 126.

[0026] When the controller 110 operates the DC-DC voltage converter 102 in the asynchronous mode, the signal LS_ON is deasserted to a low state (LS_ONZ is asserted to a high state) so that the gate 118 of the low-side FET 106 remains in a low state. A feedback circuit (not shown) provides a feedback signal to a feedback node 132 so that the controller 110 can control the duty cycle of the signal HS_ON so that a regulated load voltage is provided to the load 126. The low-side FET 106 acts as a flyback diode to conduct current to the inductor 128 when the low-side FET 106 is conducting in the forward direction. When the controller 110 deasserts the signal HS_ON to a low state (asserts the signal HS_ONZ to a high state) to turn off the high-side FET 104, the low-side FET 106 conducts forward when the voltage at the node 124 decreases to a forward voltage drop below the ground voltage (approximately -0.7V). When controller 110 asserts signal HS_ON high (signal HS_ONZ is low), high-side FET 104 is turned on to provide current to inductor 128 through node 124 , and low-side FET 106 is reverse biased as the voltage at node 124 increases.

[0027] During asynchronous mode operation, when the low-side FET 106 is conducting in the forward direction, the conduction current of the majority carriers in the low-side FET 106 causes the space region to be charged. If the charge stored in the space region is not removed, then when the controller 110 turns on the high-side FET 104, some of the current provided by the high-side FET 104 will be used to discharge the space region. The current used to discharge the space region (referred to as the recovery space charge current) is across the voltage drop V IN Flow, which can cause undesirable power consumption. In addition, due to the parasitic inductance represented by parasitic inductors 146 and 150, the recovery space charge current causes noise spikes at nodes 152 and 154. These noise spikes can interfere with other circuits (not shown) coupled to DC-DC voltage converter 102.

[0028] During an asynchronous operation, Figure 1 In an embodiment of the present invention, the controller 110 is configured to turn on the low side FET 106 for a certain time interval before turning on the high side FET 104, and turn off the low side FET 106 before turning on the high side FET 104. The controller 110 is configured to turn on the low side FET 106 for the certain time interval to discharge the space region formed in the low side FET 106 during forward conduction of the low side FET 106 when the DC-DC voltage converter 102 is in asynchronous operation. The value of the time interval can be selected so that the space region is discharged, and this value can be a function of the size of the low side FET 106 (and / or if a flyback diode is used, the size of the flyback diode).

[0029] Figure 2 An illustrative timing diagram 200 is depicted when an embodiment (e.g., DC-DC voltage converter 102) is in asynchronous mode, showing the voltage variations over time of logic signals LS_ON and LS_ON and signal SW representing the voltage at node 124. Timing diagram 200 does not represent an actual depiction of signals LS_ON, LS_ON, and SW, but is used to represent illustrative characteristics of an embodiment (e.g., illustrative system 100).

[0030] Figure 2 2 shows two cycles starting at time t1, where both signals HS_ON and LS_ON are low, and low side FET 106 begins forward conduction when signal SW drops to approximately -0.7 V. A portion of signal SW labeled 202 indicates the spatial region that charges low side FET 106 when it conducts forward.

[0031] At time t1 when signal HS_ON is low and before controller 110 asserts signal HS_ON to high, controller 110 asserts signal LS_ON to high to turn on low-side FET 106, indicated by a portion of signal LS_ON labeled 204. When turned on, low-side FET 106 discharges the space region (indicated by an event labeled 206), causing signal SW to become 0V. Controller 110 turns off low-side FET 106 at time t2 by de-asserting signal LS_ON to low. At time t3, controller 110 asserts signal HS_ON to high, causing the voltage of signal SW to increase, indicated by an event labeled 208. Therefore, the controller 110 is configured to turn on the low side FET 106 for a time interval (represented by the time difference t2 − t1 ) before turning on the high side FET 104 and turn off the low side FET 106 before turning on the high side FET 104 during asynchronous operation of the DC-DC voltage converter 102 .

[0032] At time t4, the controller 110 deasserts the signal HS_ON to a low state to turn off the high-side FET 104, indicated by the event labeled 210, thereby causing the low-side FET 106 to conduct forward and charge the space region. The cycle repeats, with the event labeled 212 indicating that the signal LS_ON is asserted to a high state at time t5 to turn on the low-side FET 106 for a time interval that lasts until time t6. This event causes the space region to be discharged, and at time t7, the controller 110 asserts the signal HS_ON to a high state to turn on the high-side FET 104 again, indicated by the event labeled 214.

[0033] Figure 3An illustrative system 300 is depicted that includes a DC-DC voltage converter 302, wherein components of the DC-DC voltage converter 302 are similar to Figure 1 The components of the DC-DC converter 102 in Figure 1 The same markings as in . Figure 3 1 and 150. The details of the gate driver 108 and the parasitic inductors 146 and 150 are not shown in FIG. The DC-DC voltage converter 302 operates in a similar manner to the DC-DC voltage converter 102, but includes a diode 304 used as a flyback diode. The diode 304 is coupled in parallel with the low-side FET 106. The diode 304 includes an anode 306 coupled to the source 120 of the low-side FET 106, and includes a cathode 308 coupled to the node 124.

[0034] During asynchronous operation, when diode 304 is forward conducting, diode 304 provides a current path from ground 148 to inductor 128. The space region within diode 304 is charged during forward conduction, and controller 110 turns on low-side FET 106 to discharge the space region of diode 304.

[0035] right Figure 1 Illustrative system 100 and Figure 2 The description of the illustrative timing diagram 200 may be applicable to Figure 3 illustrative system 300 of , wherein it should be understood that during asynchronous operation when the low-side FET 106 is turned on for a certain time interval (e.g., Figure 2 Therefore, the controller 110 is configured to turn on the low-side FET 106 for the certain time interval to discharge the space region formed in the diode 304 during the forward conduction of the diode 304.

[0036] Figure 4 An illustrative method 400 of operating a DC-DC voltage converter 102 is depicted, wherein some or all of the steps in the illustrative method 400 may be performed by a circuit that is hardwired, controlled by firmware, controlled by software, or a combination thereof. The illustrative method 400 of operating a DC-DC voltage converter 102 includes: in step 402, turning on and off a high-side FET and a low-side FET in the DC-DC voltage converter to regulate a voltage at a node in the DC-DC voltage converter; in step 404, during asynchronous operation of the DC-DC voltage converter, turning on the low-side FET for a certain time interval before turning on the high-side FET; and in step 406, during asynchronous operation of the DC-DC voltage converter, turning off the low-side FET before turning on the high-side FET.

[0037] The illustrative method 400 further includes: in step 408, during asynchronous operation of the DC-DC voltage converter, turning on the low-side FET for a time interval to discharge a spatial region formed in the diode during forward conduction of the diode, wherein the diode is coupled in parallel with the low-side FET. The illustrative method 400 further includes: in step 410, during asynchronous operation of the DC-DC voltage converter, turning on the low-side FET for the certain time interval to discharge a spatial region formed in the low-side FET during forward conduction of the low-side FET when the DC-DC voltage converter is in asynchronous operation.

[0038] exist Figure 1 and Figure 3 In the embodiment of FIG. 1 , the high-side FET 104 and the low-side FET 106 are each illustrated as an n-type metal oxide semiconductor field effect transistor (nMOSFET). In some embodiments, a p-type metal oxide semiconductor field effect transistor (pMOSFET) may be used instead of a FET.

[0039] Figure 5 An illustrative controller 110 is depicted including logic and circuit elements that generate logic signals HS_ON and LS_ON when in asynchronous mode. Figure 5 Further illustrated are various logic signals used to generate logic signals HS_ON and LS_ON, labeled Low Qrr, HS, Block_LS, and LS. Not all circuit elements in the illustrative controller 110 are shown. Figure 6 Depiction Figure 5 6. An illustrative timing diagram 600 of the logic signals HS_ON, LS_ON, Low Qrr, HS, Block_LS, and LS of FIG.

[0040] The logic signal Low Qrr is periodically asserted high to indicate operation in the asynchronous mode, so that the logic signal LS_ON is asserted high for a certain time interval before HS_ON is asserted high to discharge the space region in the low-side FET 106. The logic signal Low Qrr is provided as a preset signal for the latch 502, and the logic signal LowQrr is provided as an input signal to the timer 504. When the logic signal Low Qrr is asserted high, the timer 504 de-asserts the logic signal HS to a low state, and asserts the logic signal HS to a high state again at a later time specified by the timer 504, such as Figure 6 6. The logic signal HS is provided to the latch 502 as a clock signal.

[0041] The output of latch 502 is logic signal Block_LS illustrated in illustrative timing diagram 600. After a delay indicated by delay element 510, logic signal Block_LS after logical inversion is provided as input to AND gate 506 and as input to AND gate 508. Logic signal HS is provided as input to AND gate 508.

[0042] The output of AND gate 508 is logic signal HS_ON. The logical inverse of logic signal HS_ON, labeled as logic signal LS, is provided as an input to AND gate 506. The output of AND gate 506 is logic signal LS_ON. Delay element 510 delays the output of latch 502 so that logic signal LS_ON is deasserted to a low state before logic signal HS_ON is asserted to a high state, as indicated in illustrative timing diagram 600. In this way, low side FET 106 is turned off before high side FET 104 is turned on.

[0043] Figure 5 A specific example of a circuit to generate logic signals HS_ON and LS_ON is provided, but many different circuit configurations may be employed to generate these logic signals.

[0044] In conventional switches, the power supply 144 provides reverse recovery charge via the high-side FET 104, resulting in lower efficiency and greater heat loss due to power loss in both the high-side FET 104 and the low-side FET 106 (and / or the diode 304). By discharging the space charge region in the low-side FET 106 when the node 124 is close to 0V, the power loss is relatively small due to the discharge of the space charge region. Power efficiency is improved. In addition, since the high-side FET 104 does not need to conduct additional current for reverse recovery charge, ringing is reduced. No specially designed diode or gate driver is required.

[0045] Embodiments may also be applicable to other types of DC-DC voltage converters in which space charge formed in a diode during asynchronous operation is discharged before energizing the inductor. Figure 7 and Figure 8 Two such examples are provided.

[0046] Figure 7An illustrative system 700 is depicted that includes a DC-DC voltage converter 702. The illustrative system 700 is configured as a step-up DC-DC voltage converter that includes a first FET 704 that conducts current to an inductor 128 when turned on, a diode 706 that is coupled to the inductor 128 to conduct current to the inductor 128 when the first FET 704 is turned off, a second FET 708 that is coupled in parallel with the diode 706, and a controller 110 that turns on the second FET 708 for a time interval before turning on the first FET 704 and turns off the second FET 708 before turning on the first FET 704. The load 126 is coupled to the diode 706 and the inductor 128 (through the diode 706 and the power source 144).

[0047] The first FET 704, when turned on, conducts current from the power source 144 to the inductor 128 to energize (increase the stored magnetic energy) the inductor 128. The diode 706 provides a current path for the inductor 128 when the inductor 128 provides energy (from its decreasing magnetic field) to the load 126 during asynchronous operation. When the second FET 708 conducts current to the inductor 128 during asynchronous operation, the second FET 708 discharges the space charge region formed in the diode 706.

[0048] Figure 2 The timing diagram can be applied to Figure 7 , where the first FET 704 may be identified as Figure 3 The high side FET 104 ( Figure 2 HS_ON in ) and the second FET 708 can be identified as Figure 3 The low side FET 106 ( Figure 2 Therefore, when describing Figure 1 or Figure 3 When comparing the previous embodiments of the present invention, the high side FET 104 may be referred to as the first FET and the low side FET 106 may be referred to as the second FET. In addition, in some embodiments, the diode 706 may be part of the second FET 708 so that the second FET 708 includes the diode 706.

[0049] Figure 8An illustrative system 800 is depicted that includes a DC-DC voltage converter 802. The illustrative system 800 configures a buck-boost DC-DC voltage converter that includes: a first FET 804 that conducts current to an inductor 128 when turned on; a diode 806 that is coupled to the inductor 128 to conduct current to the inductor 128 when the first FET 804 is turned off; a second FET 808 that is coupled in parallel with the diode 806; and a controller 110 that turns on the second FET 808 for a time interval before turning on the first FET 804, and turns off the second FET 808 before turning on the first FET 804. The load 126 is coupled to the diode 806 and the inductor 128 (through the diode 806 and the power source 144).

[0050] The first FET 804, when turned on, conducts current from the power source 144 to the inductor 128 to energize (increase the stored magnetic energy) the inductor 128. The diode 806 provides a current path for the inductor 128 during asynchronous operation when the inductor 128 provides energy (from its reduced magnetic field) to the load 126. The second FET 808 discharges the space charge region formed in the diode 806 when the second FET 808 conducts current to the inductor 128 during asynchronous operation.

[0051] Figure 2 The timing diagram can be applied to Figure 8 , where the first FET 804 may be identified as Figure 3 The high side FET 104 ( Figure 2 HS_ON in , and the second FET 808 can be identified as Figure 3 The low side FET 106 ( Figure 2 LS_ON).

[0052] In the foregoing discussion and in the claims, the terms "include" and "comprises" are used in an open manner and should be interpreted as meaning including but not limited to. In addition, the term "couple" or "couples" is intended to mean an indirect connection or a direct connection. Therefore, if a first device is coupled to a second device, the connection may be by a direct connection or by an indirect connection via other devices and connections. Similarly, a device coupled between a first component or location and a second component or location may be by a direct connection or by an indirect connection via other devices and connections. An element or feature "configured to" perform a task or function may be configured (e.g., programmed or structurally designed) to perform a function when manufactured by the manufacturer, and / or may be configured (or reconfigurable) by a user after manufacturing to perform a function and / or other additional or alternative functions. Configuration may be performed by firmware and / or software programming of the device, by construction and / or layout of hardware components and device interconnection, or a combination thereof. In addition, the phrase "grounding" or similar words used in the foregoing discussion are intended to include backplane grounding, ground grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of ground connection that may be applicable or suitable for the teachings of the present invention. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value.

[0053] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Numerous changes and modifications will become apparent to those skilled in the art after fully understanding the above disclosure. It is intended that the appended claims be interpreted as encompassing all such changes and modifications.

Claims

1. A DC-DC voltage converter, comprising: A first transistor having a gate, a source and a drain; a node coupled to the source of the first transistor; a second transistor having a gate, a source and a drain, the drain being coupled to the node, the second transistor having a spatial region capable of storing charge; and A controller is coupled to the gate of the first transistor and the gate of the second transistor. During an asynchronous mode, the controller is configured to turn on the second transistor for a time interval before turning on the first transistor to discharge the space region, and to turn off the second transistor before turning on the first transistor.

2. The DC-DC voltage converter of claim 1 comprising an inductor coupled to the node.

3. The DC-DC voltage converter of claim 2, comprising a power supply coupled to the drain of the first transistor.

4. The DC-DC voltage converter of claim 3, comprising a ground coupled to the source of the second transistor.

5. The DC-DC voltage converter of claim 1, comprising a power supply coupled to the drain of the first transistor.

6. The DC-DC voltage converter of claim 5, comprising a ground coupled to the source of the second transistor.

7. The DC-DC voltage converter of claim 1 , comprising a gate driver coupled to the gate of the first transistor and to the gate of the second transistor, the controller coupled to the gate driver to turn the first transistor on and off and turn the second transistor on and off.

8. The DC-DC voltage converter of claim 1, comprising a diode having an anode coupled to the source of the second transistor and having a cathode coupled to the node.

9. A DC-DC voltage converter system, comprising: Inductors; a first FET that conducts current to the inductor when turned on; a diode coupled to the inductor to conduct current to the inductor when the first FET is off, the diode having a spatial region capable of storing charge; a second FET coupled in parallel with the diode; and A controller turns on the second FET for a time interval to discharge the space region before turning on the first FET during an asynchronous mode, and turns off the second FET before turning on the first FET.

10. The system of claim 9, wherein the second FET comprises the diode.

11. The system of claim 10, comprising a power source coupled to the first FET, the first FET conducting current from the power source to the inductor when turned on.

12. The system of claim 9, comprising a load coupled to the diode and the inductor.

13. A method of operating a DC-DC voltage converter, the method comprising: Operating the DC-DC voltage converter in a synchronous mode includes alternately cycling on the high-side FET and the low-side FET without overlap; Operating the DC-DC voltage converter in an asynchronous mode includes cycling on only the high-side FET; as well as During asynchronous operation of the DC-DC voltage converter, a space region coupled to the low-side FET is discharged for a time interval before turning on the high-side FET.

14. The method of claim 13, comprising charging a spatial region of a diode coupled to the low-side FET during cycling the high-side FET on during asynchronous operation of the DC-DC voltage converter.

15. The method of claim 13, comprising charging a spatial region of the low side FET coupled to the high side FET during cycling the high side FET on during asynchronous operation of the DC-DC voltage converter.

16. The method of claim 13, comprising setting a value of the time interval based on a size of the spatial region.

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