Display device

Abstract

A display device is provided. The display device includes a plurality of pixels connected to a scan line and a data line crossing the scan line, wherein each of the plurality of pixels includes a light emitting element and a first transistor, the first transistor being configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, wherein the first transistor includes a first active layer, the first active layer includes an oxide semiconductor including indium (In), and wherein a content of indium in the oxide semiconductor of the first active layer is 70 at % or more.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0072739 filed on June 19, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device, and more particularly, to a display device including an oxide thin film transistor having an amount of indium (In) for increasing a driving voltage range of the oxide thin film transistor. Background Art

[0003] As multimedia technologies develop, the importance of display devices has steadily increased. Therefore, various types of display devices, such as organic light emitting displays (OLEDs), liquid crystal displays (LCDs), and the like, have been used.

[0004] The display device is a device for displaying an image, and includes a display panel, such as an organic light emitting display panel or a liquid crystal display panel. Among them, such a light emitting display panel may include a light emitting element. Examples of light emitting diodes (LEDs) may include organic light emitting diodes (OLEDs) using organic materials as fluorescent materials and inorganic light emitting diodes using inorganic materials as fluorescent materials.

[0005] The display device of the type described above includes a corresponding display panel, a gate drive circuit, a data drive circuit and a timing controller. The display panel includes a data line, a gate line and a pixel formed at the intersection of the data line and the gate line. When a gate signal is supplied to a thin film transistor as a switching element through the gate line, each of the pixels receives a data voltage from the data line. Each of the pixels emits light with a predetermined brightness according to the data voltage.

[0006] Display devices capable of displaying images with high resolution of ultra high definition (UHD) have been introduced, and display devices capable of displaying images with high resolution of 8K ultra high definition (8K UHD) are in the development stage. UHD refers to a resolution of 3,840×2,160 pixels, and 8K UHD refers to a resolution of 7,680×4,320 pixels.

[0007] In the case of a high-resolution display device, as the number of pixels increases, the driving current of each of the pixels may decrease. As a result, the driving voltage range of the driving transistor of each pixel may decrease. Summary of the invention

[0008] Aspects of the disclosure provide a display device including a thin film transistor having an oxide semiconductor active layer including a specific amount of indium (In).

[0009] However, aspects of the present disclosure may not be limited to the aspects set forth herein. The above and other aspects of the disclosure will become more apparent to those skilled in the art by referring to the following detailed description.

[0010] A display device according to an embodiment may include a driving transistor including an active layer that may be formed of an oxide semiconductor containing a relatively high amount of indium (In). In the case where the active layer of the transistor may be an oxide semiconductor containing a relatively high amount of indium (In), the driving transistor may have excellent performance in supplying a driving current as a driving voltage range may be expanded or increased.

[0011] Therefore, as the area per unit pixel decreases, the driving transistor can have excellent operation characteristics even if the driving transistor includes a channel region having a narrow length.

[0012] According to an embodiment, a display device may include a plurality of pixels connected to a scan line and a data line crossing the scan line, wherein each of the plurality of pixels includes a light emitting element and a first transistor, the first transistor being configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, wherein the first transistor includes a first active layer, the first active layer includes an oxide semiconductor including indium (In), and wherein a content of indium in the oxide semiconductor of the first active layer is 70 at % or greater.

[0013] The oxide semiconductor may include indium tin oxide (ITO) or indium tin gallium oxide (ITGO).

[0014] The sum of the amount of indium (In) and the amount of tin (Sn) in the oxide semiconductor may be greater than or equal to about 95 at %.

[0015] The amount of tin (Sn) in the oxide semiconductor may be in the range of about 5 at % to about 20 at %.

[0016] The first active layer may include a first region and a second region, the second region having an oxygen atomic concentration higher than that of the first region.

[0017] The second region may be located on an upper surface of the first active layer and at least one side surface of the first active layer.

[0018] The first active layer may include a first conductor region, a second conductor region, and a channel region disposed between the first conductor region and the second conductor region.

[0019] The first transistor may also include: a first light-shielding layer, arranged below the first active layer; a first gate electrode, arranged on the first active layer; a first source electrode, contacting the first conductor region through a first contact hole passing through the first insulating layer, the first insulating layer being arranged on the first gate electrode; and a first drain electrode, contacting the second conductor region through a second contact hole passing through the first insulating layer.

[0020] The first gate electrode may overlap the first active layer by an overlap amount of about 2 μm to about 10 μm.

[0021] The first source electrode may contact the first light shielding layer through a third contact hole passing through the first insulating layer and the buffer layer, and the buffer layer is disposed between the first active layer and the first light shielding layer.

[0022] The pixel may further include a second transistor configured to apply a data voltage of the data line to the first transistor according to a scan signal applied to the scan line, and the second transistor may include a second active layer including an oxide semiconductor including indium (In).

[0023] The second transistor may further include a second light shielding layer disposed under the second active layer and a second gate electrode disposed on the second active layer.

[0024] The second gate electrode may contact the second light shielding layer through a sixth contact hole passing through the first gate insulating layer and the buffer layer, the first gate insulating layer is disposed between the second active layer and the second gate electrode, and the buffer layer is disposed between the second active layer and the second light shielding layer.

[0025] The display device may further include a scan driver configured to output a scan signal to the scan line, wherein the scan driver may include a third transistor including a third active layer.

[0026] The first active layer of the first transistor may be disposed over the third active layer of the third transistor.

[0027] According to another embodiment, a display device may include a plurality of pixels connected to scan lines and data lines crossing the scan lines, wherein each of the plurality of pixels includes a light emitting element, a driving transistor, and a switching transistor, the driving transistor being configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, the switching transistor being configured to apply the data voltage of the data line to the driving transistor according to a scan signal applied to the scan line, wherein the driving transistor and the switching transistor each include an active layer, the active layer including an oxide semiconductor containing indium (In), and wherein a content of indium in the oxide semiconductor of the active layer is 70 at % or greater.

[0028] The oxide semiconductor may include indium tin oxide (ITO) or indium tin gallium oxide (ITGO).

[0029] A total amount of indium (In) and tin (Sn) in the oxide semiconductor may be greater than or equal to about 95 at %.

[0030] An oxygen atom concentration of an upper surface of the active layer of the driving transistor may be higher than an oxygen atom concentration of a lower surface of the active layer of the driving transistor.

[0031] The driving transistor may further include a gate electrode disposed on the active layer, and an overlapping region of the gate electrode and the active layer may have a length in a range of about 2 μm to about 10 μm. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the disclosure will become more apparent by describing the disclosed embodiments in detail with reference to the accompanying drawings, in which:

[0033] Figure 1 shows a plan view showing a display device according to an embodiment;

[0034] Figure 2 shows a block diagram schematically showing a display device according to an embodiment;

[0035] Figure 3 According to the embodiment Figure 2 A schematic diagram of an equivalent circuit of a pixel;

[0036] Figure 4 According to the embodiment Figure 2 A schematic diagram of an equivalent circuit of a pixel;

[0037] Figure 5 shows a plan view of a first transistor according to an embodiment;

[0038] Figure 6 Shown along Figure 5 A schematic cross-sectional view taken along line II' of FIG.

[0039] Figure 7 shows a plan view of a second transistor according to an embodiment;

[0040] Figure 8 Shown along Figure 7 A schematic cross-sectional view taken along line II-II';

[0041] Fig. 9 showing a graph showing a driving current according to a gate voltage of a first transistor according to an embodiment;

[0042] Fig.10A flowchart is shown, which illustrates a method of manufacturing a display device according to an embodiment;

[0043] Figures 11 to 15 A schematic cross-sectional view showing a method of manufacturing a display device according to an embodiment;

[0044] Fig.16 shows a schematic cross-sectional view of a first transistor according to another embodiment;

[0045] Fig.17 A schematic cross-sectional view is shown which partially illustrates the manufacturing process of Fig.16 The first transistor method;

[0046] Fig.18 Show according to Fig.16 a curve diagram of a gate voltage of a first transistor and a driving current;

[0047] Fig.19 shows a plan view of a second transistor according to another embodiment;

[0048] Fig. 20 Shown along Fig.19 A schematic cross-sectional view taken along line III-III'; and

[0049] Fig.21 A schematic cross-sectional view showing a portion of a display panel according to an embodiment. DETAILED DESCRIPTION

[0050] Although the disclosure can be modified in various ways and has additional embodiments, the embodiments are shown in the drawings and will be mainly described in the specification. However, the scope of the disclosure is not limited to the embodiments in the drawings and the specification, and should be understood to include all changes, equivalents and substitutes included in the spirit and scope of the disclosure.

[0051] The drawings and descriptions are to be regarded as merely illustrative in nature and thus are not limitations of the embodiments described and claimed herein. To describe the disclosed embodiments, some of the parts not related to the description may not be provided, and like reference numerals refer to like elements throughout the specification.

[0052] In the drawings, the size and thickness of each element are arbitrarily presented for better understanding and ease of description, but the disclosure is not limited thereto. In the drawings, the thickness of layers, panels, regions, and other elements may be exaggerated for clarity. In the drawings, the thickness of some layers and regions may be exaggerated for better understanding and ease of description.

[0053] In addition, in the specification, the phrase "in a plan view" means when observing the target part from above, and the phrase "in a cross-sectional view" means when observing the cross section taken by vertically cutting the target part from the side. In addition, the term "superimposed" or its variants means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "superimposed" can include stacking, stacking, facing (facing) or its variants, extending on ..., covering or partially covering or any other suitable terms, as will be recognized and understood by those of ordinary skill in the art. The term "facing (facing)" and its variants mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is inserted between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, but still facing each other. When a layer, region, substrate or zone is referred to as "on" another layer, region, substrate or zone, the layer, region, substrate or zone can be directly on the other layer, region, substrate or zone, or there can be an intermediate layer, region, substrate or zone between them. On the contrary, when a layer, region, substrate or zone is referred to as "directly on" another layer, region, substrate or zone, there may be no intermediate layer, region, substrate or zone between them. In addition, when a layer, region, substrate or zone is referred to as "below" another layer, region, substrate or zone, the layer, region, substrate or zone may be directly below the other layer, region, substrate or zone, or there may be an intermediate layer, region, substrate or zone between them. On the contrary, when a layer, region, substrate or zone is referred to as "directly below" another layer, region, substrate or zone, there may be no intermediate layer, region, substrate or zone between them. In addition, "on..." or "on..." may include positioning on or below an object, and does not necessarily represent a direction based on gravity.

[0054] For ease of description, spatially relative terms such as "below", "beneath", "below (lower)", "above", "above (upper)", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, in a case where the device shown in the accompanying drawings is flipped, a device positioned "below" or "below" another device may be placed "above" another device. Therefore, the illustrative term "below" may include both a position below and a position above. The device may also be positioned in other directions, and therefore, the spatially relative terms may be interpreted differently depending on the positioning.

[0055] Throughout the specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "indirectly connected" to the other element with one or more intermediate elements interposed therebetween. It will also be understood that when the terms "comprises," "includes," and / or variations thereof are used in this specification, they or it may indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0056] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate description and explanation thereof. For example, when a "first element" is discussed in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the teachings herein.

[0057] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless clearly defined in the specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an ideal or overly formal sense.

[0058] Figure 1 A plan view showing a display device according to an embodiment is shown. Figure 2 A block diagram schematically illustrating a display device according to an embodiment is shown.

[0059] Reference Figure 1 and Figure 2 , the display device 1 displays a moving image or a still image. The display device 1 may be any electronic device that provides a display screen. Examples of the display device 1 may include a television that provides a display screen, a laptop computer, a monitor, a billboard, an IoT device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera, and a camcorder.

[0060] The display device 1 may include a display panel that provides a display screen. Examples of the display panel may include an LED display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, and a field emission display panel. In the following description, the display device 1 may include an LED display panel. However, the disclosure is not limited thereto, and other types of display panels may be used.

[0061] The shape of the display device 1 may be variously modified. For example, the display device 1 may have shapes such as a rectangular shape elongated in the horizontal direction, a rectangular shape elongated in the vertical direction, a square shape, a rectangular shape with rounded corners (e.g., vertices), other polygonal shapes, and a circular shape. The shape of the display area DA of the display device 1 may also be similar to the overall shape of the display device 1. Figure 1 In the embodiment, the display device 1 may include a display area DA having a rectangular shape elongated in a horizontal direction.

[0062] The display device 1 may include a display area DA and a non-display area NDA. The display area DA may be an area where a screen may be displayed, and the non-display area NDA may be an area where a screen may not be displayed. The display area DA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area.

[0063] The display area DA may substantially occupy the center of the display device 1. The display area DA may include pixels PX. The pixels PX may be arranged in a matrix. The shape of each pixel PX may be a rectangular shape or a square shape in a plan view. However, the disclosure is not limited thereto, and the shape may be a rhombus shape in which each side is inclined relative to the first direction DR1.

[0064] The display device 1 according to the embodiment includes a display panel 10, integrated driving circuits 21 and 22, and a scan driver 30. The integrated driving circuits 21 and 22 may define a timing controller 21 and a data driver 22, respectively.

[0065] The display panel 10 may include a display area DA in which pixels PX are formed to display an image and a non-display area NDA as a peripheral area of ​​the display area DA. In the case where the display panel 10 may include a curved surface portion, the display area DA may be disposed on the curved surface portion. The image of the display panel 10 may also be seen on the curved surface portion.

[0066] Pixels PX, scan lines SL1 to SLk (k is an integer of 2 or more), data lines DL1 to DLj (j is an integer of 2 or more) connected to the pixels PX, and power lines may be provided in the display area DA. The scan lines SL1 to SLk may be formed in parallel in a first direction DR1, and the data lines DL1 to DLj may be formed in parallel in a second direction DR2 crossing the first direction DR1. Each of the pixels PX may be connected to at least one of the scan lines SL1 to SLk and one of the data lines DL1 to DLj.

[0067] Each of the pixels PX may include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor. Since the switching transistor may be turned on when a scan signal is applied through the scan lines SL1 to SLk, the data voltage of the data lines DL1 to DLj may be applied to the gate electrode of the driving transistor. The driving transistor may supply a driving current to the light emitting element according to the data voltage applied to the gate electrode, thereby achieving light emission. The driving transistor and at least one switching transistor may be thin film transistors. The light emitting element may emit light according to the driving current of the driving transistor. The light emitting element may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The capacitor may keep the data voltage applied to the gate electrode of the driving transistor constant.

[0068] The non-display area NDA may be defined as a region from outside the display area DA to an edge of the display panel 10. A scan driver 30 for applying scan signals to the scan lines SL1 to SLk and integrated driving circuits 21 and 22 may be disposed in the non-display area NDA.

[0069] The integrated driving circuits 21 and 22 may output signals and voltages for driving the display panel 10. To this end, the integrated driving circuits 21 and 22 may define a timing controller 21 and a data driver 22.

[0070] The timing controller 21 may receive input data RGB and a timing signal CS from a host system (not shown). The timing signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock. The host system may be an application processor of a smart phone or a tablet PC, a system on a chip of a monitor or a TV, etc.

[0071] The timing controller 21 may generate control signals for controlling operation timings of the data driver 22 and the scan driver 30. The control signals may include a source control signal CONT2 for controlling operation timings of the data driver 22 and a scan control signal CONT1 for controlling operation timings of the scan driver 30.

[0072] The data driver 22 may receive the digital video data DATA and the source control signal CONT2 from the timing controller 21. The data driver 22 may convert the digital video data DATA into analog data voltages according to the source control signal CONT2, and may supply the analog data voltages to the data lines DL1 to DLj of the display panel 10.

[0073] The integrated driving circuits 21 and 22 may be disposed in the non-display area NDA and may be disposed on one side of the display panel 10. The integrated driving circuits 21 and 22 may be formed as a single integrated circuit (IC) and may be mounted on the display panel 10 by using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. However, the disclosure may not be limited thereto. For example, the integrated driving circuits 21 and 22 may be mounted on a circuit board other than the display panel 10.

[0074] also, Figure 2 The integrated driving circuits 21 and 22 are shown to include a data driver 22 and a timing controller 21, but the disclosure may not be limited thereto. For example, as described above, the data driver 22 and the timing controller 21 may be formed as separate integrated circuits, rather than as one integrated circuit. Therefore, the timing controller 21 may be mounted on a circuit board, and the data driver 22 may be mounted on the display panel 10 by using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method.

[0075] The scan driver 30 may receive a scan control signal CONT1 from the timing controller 21. The scan driver 30 may generate scan signals S1 to Sk according to the scan control signal CONT1, and may supply the scan signals S1 to Sk to the scan lines SL1 to SLk of the display panel 10. The scan driver 30 may include a plurality of transistors and may be formed in the non-display area NDA of the display panel 10. The scan driver 30 may be formed as an integrated circuit and may be mounted on a gate flexible film attached to the other side of the display panel 10.

[0076] Although not shown, an anisotropic conductive film may be used to attach a circuit board to a pad (or "pad") provided on one edge of the display panel 10. Thus, the leads of the circuit board may be electrically connected to the pad. The circuit board may be a flexible film (such as a flexible printed circuit board), a printed circuit board, or a chip on a film. The circuit board may be bent to the lower side of the display panel 10. One side of the circuit board may be attached to one edge of the display panel 10, and the other side of the circuit board may be provided below the display panel 10 and connected to a system board on which a host system may be mounted.

[0077] The power supply circuit can generate a voltage required to drive the display panel 10 from the main power supply of the system board, and can supply the voltage to the display panel 10. For example, the power supply circuit can generate a first power supply voltage and a second power supply voltage for driving the light emitting element EL of the display panel 10 from the main power supply, and can supply them to a first voltage line VDD (see Figure 3 ) and the second voltage line VSS (see Figure 3 ). In addition, the power supply circuit may generate a driving voltage for driving the integrated driving circuits 21 and 22 and the scan driver 30 from a main power supply and supply them.

[0078] The power circuit may be formed as an integrated circuit and may be mounted on a circuit board, although the disclosure may not be limited thereto. For example, the power circuit may be formed integrally with the integrated driving circuits 21 and 22 .

[0079] Figure 3 According to the embodiment Figure 2 Schematic diagram of the equivalent circuit of a pixel.

[0080] Reference Figure 3 , the pixel PX may include a first transistor TR1, a second transistor TR2, a light emitting element EL, and a capacitor Cst. Figure 3 It is shown that each pixel PX may have a 2T1C (2 transistors-1 capacitor) configuration including one first transistor TR1, one second transistor TR2, and one capacitor Cst, but the disclosure may not be limited thereto. For example, each pixel PX may include a greater number of transistors and a plurality of capacitors.

[0081] Each of the first transistor TR1 and the second transistor TR2 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0082] Each of the first transistor TR1 and the second transistor TR2 may be formed as a thin film transistor. Figure 3 It can be seen that each of the first transistor TR1 and the second transistor TR2 can be formed by an N-type metal oxide semiconductor field effect transistor (MOSFET), but the disclosure may not be limited thereto. For example, each of the first transistor TR1 and the second transistor TR2 can be formed as a P-type MOSFET. Therefore, the position of the source electrode and the drain electrode of each of the first transistor TR1 and the second transistor TR2 can be changed. Here, with respect to the following discussion, the first transistor TR1 and the second transistor TR2 can be an N-type MOSFET.

[0083] The first transistor TR1 can supply a driving current to the light emitting element EL according to a data voltage applied to a gate electrode, thereby realizing light emission. For example, the first transistor TR1 can be a driving transistor. The gate electrode of the first transistor TR1 can be connected to the source electrode of the second transistor TR2, the source electrode of the first transistor TR1 can be connected to the first electrode of the light emitting element EL, and the drain electrode of the first transistor TR1 can be connected to a first voltage line VDD, wherein a first power supply voltage is applied to the first voltage line VDD.

[0084] Since the second transistor TR2 can be turned on when a scan signal can be applied from the kth scan line SLk (where k is a positive integer), the data voltage of the data line DLj can be applied to the gate electrode of the first transistor TR1. For example, the second transistor TR2 can be a switching transistor. The gate electrode of the second transistor TR2 can be connected to the kth scan line SLk, the source electrode of the second transistor TR2 can be connected to the gate electrode of the first transistor TR1, and the drain electrode of the second transistor TR2 can be connected to the jth data line DLj.

[0085] The capacitor Cst may be connected between the gate electrode and the source electrode of the first transistor TR1. Therefore, the capacitor Cst may maintain a data voltage applied to the gate electrode of the first transistor TR1 constant.

[0086] The light emitting element EL may emit light according to the driving current of the first transistor TR1. The light emitting element EL may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The first electrode of the light emitting element EL may be connected to the source electrode of the first transistor TR1, and the second electrode of the light emitting element EL may be connected to a second voltage line VSS, wherein a second power supply voltage that may be lower than the first power supply voltage is applied to the second voltage line VSS.

[0087] Figure 4 According to the embodiment Figure 2 Schematic diagram of the equivalent circuit of a pixel.

[0088] Reference Figure 4 , the pixel PX may include a first transistor TR1, a second transistor TR2, a sensing transistor SST, a light emitting element EL, and a capacitor Cst. Figure 4 It is shown that each pixel PX may have a 3T1C (3 transistors-1 capacitor) configuration including one first transistor TR1 , one second transistor TR2 , a sensing transistor SST, and one capacitor Cst.

[0089] Figure 4The circuit diagram of FIG. 1 may further include a compensation circuit including a sensing transistor SST and a reference line Vref. The compensation circuit may be a circuit that may be added in each pixel PX to compensate for a threshold voltage of the first transistor TR1.

[0090] The sensing transistor SST may be connected between the source electrode of the first transistor TR1 and the first electrode of the light emitting element EL. The gate electrode of the sensing transistor SST may be connected to the kth sensing signal line SSk, the drain electrode of the sensing transistor SST may be connected to the reference line Vref, and the source electrode of the sensing transistor SST may be connected to one end of the capacitor Cst. The sensing transistor SST may be turned on by the sensing signal of the kth sensing signal line SSk to supply a reference voltage that may be transmitted through the reference line Vref to the source electrode of the first transistor TR1. The sensing transistor SST may operate to sense the voltage or current of the source electrode of the first transistor TR1.

[0091] The reference line Vref may be connected to the scan driver 30. The scan driver 30 may sense the source electrode of the first transistor TR1 of each pixel PX in real time during a non-display period of an image or during a period of N frames (where N is an integer of 1 or more), and may generate a sensing result. The second transistor TR2, which may be a switching transistor, and the sensing transistor SST, which may be a sensing transistor, may be turned on at the same time. The sensing operation (via the reference line Vref) of the sensing transistor SST and the data output operation for outputting a data signal may be separated from each other according to the time division method of the scan driver 30.

[0092] The compensation target according to the sensing result may be a digital data signal, an analog data signal, gamma, etc. In addition, the compensation circuit for generating a compensation signal based on the sensing result may be implemented as a circuit in the scan driver 30, a circuit in the timing controller 21, or a separate circuit.

[0093] exist Figure 3 and Figure 4 In the embodiment, the pixel PX having the 2T1C configuration and the 3T1C configuration may be an example of a pixel. For example, the pixel may include a larger number of transistors or capacitors.

[0094] Figure 5 A plan view of a first transistor according to an embodiment is shown. Figure 6 Shown along Figure 5 A schematic cross-sectional view taken along line II'. Figure 7 A plan view of a second transistor according to an embodiment is shown. Figure 8 Shown along Figure 7 A schematic cross-sectional view taken along line II-II'.

[0095] Figures 5 to 8The first transistor TR1 as a driving transistor and the second transistor TR2 as a switching transistor are shown to be configured as coplanar. The coplanar configuration may include a top gate form in which a gate electrode may be formed above an active layer. However, the disclosure may not be limited thereto. For example, the first transistor TR1 and the second transistor TR2 of each pixel PX may have a bottom gate form in which a gate electrode may be formed below an active layer.

[0096] Reference Figures 5 to 8 Each pixel PX of the display panel 10 includes a first substrate 110, a buffer layer 120, a first gate insulating layer 130, a first transistor TR1, a second transistor TR2, a first interlayer insulating layer 160, a first passivation layer 170, a first planarization layer 180, a first electrode 191, an organic light emitting layer 192, a second electrode 193, a pixel defining layer 195 and an encapsulation layer 196.

[0097] The first transistor TR1 of each pixel PX may include a first gate electrode 310, a first active layer 350, a first source electrode 330, a first drain electrode 340, and a first light shielding layer 360. The second transistor TR2 of the pixel PX may include a second gate electrode 410, a second active layer 450, a second source electrode 430, and a second drain electrode 440.

[0098] The first substrate 110 may provide a region on which the first transistor TR1 and the second transistor TR2 may be formed. The first substrate 110 may be made of plastic or glass.

[0099] The first light shielding layer 360 may be disposed on the first substrate 110. The first light shielding layer 360 may block light from entering the first active layer 350 from the first substrate 110. The first light shielding layer 360 may prevent leakage current that may flow in the first active layer 350 when light from the first substrate 110 may be incident on the first active layer 350. The length of the first light shielding layer 360 in the third direction DR3 and the length of the first light shielding layer 360 in the fourth direction DR4 may be longer than the length of the first active layer 350 in the third direction DR3 and the length of the first active layer 350 in the fourth direction DR4. The first light shielding layer 360 may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0100] The buffer layer 120 may be disposed on the first light shielding layer 360. The buffer layer 120 may protect the first transistor TR1 and the second transistor TR2 of the pixel PX from moisture that may penetrate the first substrate 110. The buffer layer 120 may include inorganic layers stacked alternately. For example, the buffer layer 120 may be made of silicon oxide (SiO x) layer, silicon nitride (SiN x ) layer and a silicon oxynitride (SiON) layer are alternately stacked to form a multilayer.

[0101] The first active layer 350 and the second active layer 450 may be disposed on the buffer layer 120. The first active layer 350 may include a first conductor region 350a, a second conductor region 350b, and a channel region 350c, and the second active layer 450 may include a first conductor region 450a, a second conductor region 450b, and a channel region 450c. The channel regions 350c and 450c may be disposed between the first conductor regions 350a and 450a and the second conductor regions 350b and 450b.

[0102] The first active layer 350 and the second active layer 450 may be oxide semiconductors containing indium (In). In other words, the first active layer 350 and the second active layer 450 may both be defined by oxide semiconductors containing indium (In). The first active layer 350 and the second active layer 450 may include indium tin oxide (ITO) or indium tin gallium oxide (ITGO).

[0103] The active layers 350 and 450 of the first transistor TR1 and the second transistor TR2 may be made into oxide semiconductors containing a specific amount of indium (In), thereby improving the operating characteristics, electrical characteristics, etc. of the transistors. In some cases, such as in transistors, the oxide semiconductor may contain a relatively low amount of indium (In). The use of such transistors may result in a narrow range of driving voltages. Therefore, it is possible to prevent a transistor having such an oxide semiconductor active layer from being used as a driving transistor for transmitting a driving current to the light-emitting element EL of the pixel PX. In addition, as the number of pixels included in the display panel 10 of the display device 1 increases, the channel region of the active layer for the driving transistor may become narrower. As a result, a sufficient range of driving voltages may not be obtained.

[0104] In contrast, the display device 1 herein may include a first transistor TR1 as a driving transistor in which an oxide semiconductor active layer contains a specific amount of indium (In). Therefore, even if the active layer may have a channel region with a short length, the active layer may have a driving voltage that may be within a predetermined range. Therefore, a transistor having an oxide semiconductor active layer may be used as a driving transistor of the display device 1.

[0105] The first transistor TR1 may include a first active layer 350 having an oxide semiconductor including indium (In), and the first active layer 350 may have an indium content greater than or equal to about 70 at % (e.g., greater than or equal to about 71 at %, greater than or equal to about 72 at %, greater than or equal to about 73 at %, greater than or equal to about 74 at %, greater than or equal to about 75 at %, greater than or equal to about 76 at %, greater than or equal to about 77 at %, greater than or equal to about 78 at %, greater than or equal to about 79 at %) based on the amount of cations included in the oxide semiconductor. , about 80 at %, about 81 at %, about 82 at %, about 83 at %, about 84 at %, about 85 at %, about 86 at %, about 87 at %, about 88 at %, about 89 at %, about 90 at %, about 91 at %, about 92 at %, about 93 at %, about 94 at %, or about 95 at %. For example, the first active layer 350 may have a total amount of indium (In) of about 75 at %.

[0106] During the process of forming the gate insulating layer, defects may be formed in the active layer of the driving transistor. For example, an area that captures electrons may be formed in the band gap of the front channel region of the active layer. In the case where the active layer of the driving transistor may be an oxide semiconductor with a high amount of indium (In), the subthreshold swing (SS) of the driving transistor may be increased to a large value, and the slope of the driving current (drain-source current Ids) curve according to the driving voltage Vgs may be reduced. For example, within the same driving current range, the driving transistor may have a wider range of driving voltages.

[0107] Fig. 9 A graph showing a driving current according to a gate voltage of a first transistor according to an embodiment is shown, in comparison with a transistor having an amount of indium (In) included in an oxide semiconductor (as an active layer) different from that of the first transistor. Fig. 9 , a dotted line indicates a driving transistor including an oxide semiconductor having an indium (In) content of 52 at %. A solid line indicates a driving transistor including an oxide semiconductor having an indium (In) content of about 75 at % as an active layer according to one or more embodiments herein.

[0108] Reference Fig. 9 In the case where the active layer of the driving transistor may include a relatively high amount of indium (In), the slope of a curve in a graph of driving current (A) according to gate voltage (V) may be reduced. Fig. 9For the transistor shown by the dashed line, a swing value below the threshold voltage of about 0.25 can be observed, and a driving range of the gate voltage (V) of about 1.27V can be observed. In addition, due to the rising slope as shown by the dashed line, the incremental increase in the range of the driving voltage does not exceed the incremental increase in the range of the driving current. However, according to the transistor according to one or more embodiments herein, as shown by Fig. 9 As represented by the solid line, it can be observed that the swing value below the threshold voltage is about 0.56, and the driving range of the gate voltage (V) can be observed to be about 2.89V. A driving transistor having an oxide semiconductor containing a high amount of indium (In) (for example, greater than or equal to about 70at%) as an active layer can have a wider range of gate voltages (V) within the same range of driving currents (A). In other words, the range of driving voltages for controlling the driving current (A) of the light-emitting element EL for driving the pixel PX can be expanded (i.e., increased) compared to the range of driving voltages such as can be applied to transistors. As a result, the incremental increase in the range of the driving voltage can exceed the incremental increase in the range of the driving current. In addition, using a driving transistor as described herein, although in a high-resolution display device, as the number of pixels PX per unit area of ​​the display panel 10 can increase, the driving current of each of the pixels may decrease, but the reduction in the driving voltage range of the driving transistor can be prevented or reduced.

[0109] The first active layer 350 of the first transistor TR1 may further include tin (Sn). The total amount of indium (In) and tin (Sn) relative to the amount of cations included in the oxide semiconductor may be greater than or equal to about 95at%, for example, greater than or equal to about 96at%, greater than or equal to about 97at%, greater than or equal to about 98at%, or greater than or equal to about 99at%. The amount of tin (Sn) contained in the oxide semiconductor may be in the range of about 5at% to about 20at% based on the amount of cations included in the oxide semiconductor. Therefore, the first transistor TR1 may include a high amount of indium (In), and may include tin (Sn) in addition to indium (In), thereby ensuring excellent performance as a driving transistor.

[0110] Refer again Figures 5 to 8 The first gate insulating layer 130 may be disposed on the first active layer 350 and the second active layer 450. The first gate insulating layer 130 may include an inorganic material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) or their stacked structures.

[0111] The first gate electrode 310 and the second gate electrode 410 may be disposed on the first gate insulating layer 130. The first gate electrode 310 may overlap with or face the first active layer 350, and the first gate insulating layer 130 is interposed between the first gate electrode 310 and the first active layer 350. The second gate electrode 410 may overlap with or face the second active layer 450, and the first gate insulating layer 130 is interposed between the second gate electrode 410 and the second active layer 450. For example, the first gate electrode 310 may overlap with or face the channel region 350c of the first active layer 350, and the second gate electrode 410 may overlap with or face the channel region 450c of the second active layer 450. The first gate electrode 310 and the second gate electrode 410 may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0112] The overlapping or facing area between the first active layer 350 and the first gate electrode 310 may have a length in the range of about 2 μm to about 10 μm measured in a given direction. As described above, the first active layer 350 containing a high amount of indium (In) of the first transistor TR1 may have good operating characteristics. Therefore, even if the number of pixels PX per unit area of ​​the display panel 10 may be increased, resulting in a possible shortening of the length of the channel region of the active layer, a wide range of driving voltages may still be obtained. In this regard, the length W310 measured in a given direction (e.g., a third direction DR3 perpendicular to the fifth direction DR5) of the area where the first active layer 350 and the first gate electrode 310 overlap or face each other may be in the range of about 2 μm to about 10 μm, about 2.5 μm to about 4.5 μm, or about 3 μm to about 4 μm. However, other ranges within the range of about 2 μm to about 10 μm may also be applicable.

[0113] although Figure 6 and Figure 8 The first gate insulating layer 130 is shown to be disposed between the first gate electrode 310 and the first active layer 350 and between the second gate electrode 410 and the second active layer 450, but the embodiments herein may not be limited thereto. For example, the first gate insulating layer 130 may be formed on the upper surface and the side surface of each of the first active layer 350 and the second active layer 450.

[0114] The first interlayer insulating layer 160 may be disposed on the first gate electrode 310 and the second gate electrode 410. The first interlayer insulating layer 160 may include an inorganic material such as silicon oxide (SiO x ), Silicon Nitride (SiNx ) or their stacked structures.

[0115] The first interlayer insulating layer 160 may include a first contact hole CT1 passing through the first interlayer insulating layer 160 to expose a portion of the upper surface of the first active layer 350, and a second contact hole CT2 passing through the first interlayer insulating layer 160 to expose another portion of the upper surface of the first active layer 350. For example, the first contact hole CT1 may be formed to expose the first conductor region 350a of the first active layer 350, and the second contact hole CT2 may be formed to expose the second conductor region 350b of the first active layer 350. In addition, the third contact hole CT3 may be formed in the first interlayer insulating layer 160 and the buffer layer 120 to pass through the first interlayer insulating layer 160 and the buffer layer 120, thereby exposing the first light shielding layer 360.

[0116] The first interlayer insulating layer 160 may include a fourth contact hole CT4 passing through the first interlayer insulating layer 160 to expose a portion of the upper surface of the second active layer 450, and a fifth contact hole CT5 passing through the first interlayer insulating layer 160 to expose another portion of the upper surface of the second active layer 450. That is, the fourth contact hole CT4 may be formed to expose the first conductor region 450a of the second active layer 450, and the fifth contact hole CT5 may be formed to expose the second conductor region 450b of the second active layer 450.

[0117] The first source electrode 330 and the first drain electrode 340 of the first transistor TR1 and the second source electrode 430 and the second drain electrode 440 of the second transistor TR2 may be disposed on the first interlayer insulating layer 160 .

[0118] The first source electrode 330 may contact the first conductor region 350a formed on one side of the first active layer 350 through the first contact hole CT1. The first drain electrode 340 may contact the second conductor region 350b formed on the other side of the first active layer 350 through the second contact hole CT2.

[0119] The second source electrode 430 may contact the first conductor region 450a formed on one side of the second active layer 450 through the fourth contact hole CT4. The second drain electrode 440 may contact the second conductor region 450b formed on the other side of the second active layer 450 through the fifth contact hole CT5.

[0120] The first passivation layer 170 may be disposed on the source electrodes 330 and 430 and the drain electrodes 340 and 440 of the first transistor TR1 and the second transistor TR2. The first passivation layer 170 may include an inorganic material such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) or their stacked structures.

[0121] The first planarization layer 180 may be disposed on the first passivation layer 170. The first planarization layer 180 may planarize steps that may occur due to the formation of thin film transistors such as the first transistor TR1 and the second transistor TR2. The first planarization layer 180 may include an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0122] The light emitting element EL including the first electrode 191 , the organic light emitting layer 192 , and the second electrode 193 , and the pixel defining layer 195 may be formed on the first planarization layer 180 .

[0123] The first electrode 191 may be formed on the first planarization layer 180. The first electrode 191 may be connected to the first source electrode 330 of the first transistor TR1 through a contact hole CNT passing through the first passivation layer 170 and the first planarization layer 180.

[0124] The pixel defining layer 195 may be formed to cover the edge of the first electrode 191 on the first planarization layer 180 to divide the pixels. For example, the pixel defining layer 195 may define pixels. Each of the pixels may represent a region where the first electrode 191, the organic light emitting layer 192, and the second electrode 193 may be sequentially stacked, and holes from the first electrode 191 and electrons from the second electrode 193 may be combined with each other in the organic light emitting layer 192 to emit light.

[0125] The organic light emitting layer 192 may be disposed on the first electrode 191 and the pixel defining layer 195. The organic light emitting layer 192 may include a hole transport layer, a light emitting layer, and an electron transport layer. The organic light emitting layer 192 may be formed in a series configuration of two or more stacks, in which case a charge generation layer may be formed between the stacks.

[0126] The second electrode 193 may be formed on the organic light emitting layer 192. The second electrode 193 may be a common layer that may be commonly formed between pixels.

[0127] The light emitting element EL may be formed as a top emission type to emit light in an upward direction. The first electrode 191 may be formed of a metal material with high reflectivity (such as a stacked structure (Ti / Al / Ti) of aluminum (Al) and titanium (Ti), a stacked structure (ITO / Al / ITO) of Al and ITO, an APC alloy, a stacked structure (ITO / APC / ITO) of an APC alloy and ITO, etc.). The APC alloy is an alloy of silver (Ag), palladium (Pd) and copper (Cu). The second electrode 193 may include a transparent conductive material (TCO) (such as ITO or IZO) that can transmit light or a semi-transmissive conductive material (such as an alloy of magnesium (Mg), silver (Ag) or magnesium (Mg) and silver (Ag)). In the case where the second electrode 193 may include a semi-transmissive conductive material, the luminous efficiency may be improved due to the microcavity effect.

[0128] The encapsulation layer 196 may be formed on the second electrode 193 to prevent the penetration of oxygen or moisture. The encapsulation layer 196 may include at least one inorganic layer. The inorganic layer may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. In addition, the encapsulation layer 196 may include at least one organic layer to prevent particles from penetrating the encapsulation layer 196 and entering the organic light emitting layer 192 and the second electrode 193. The organic layer may be formed of epoxy resin, acrylate, or urethane acrylate.

[0129] A method of manufacturing the display device 1 including the first transistor TR1 and the second transistor TR2 will be described below.

[0130] Fig.10 A flowchart illustrating a method of manufacturing a display device according to an embodiment is shown. Figures 11 to 15 The method of manufacturing a display device according to an embodiment is shown along Figure 5 and Figure 7 Schematic cross-sectional views taken along lines II' and II-II'.

[0131] Reference Figures 10 to 15 ,like Fig.11 As shown in FIG. 1 , a first light shielding layer 360 ( Fig.10 Step S101), and a buffer layer 120 ( Fig.10 The first light shielding layer 360 may be formed by patterning a light shielding metal layer that may be formed on the first substrate 110 by a sputtering method through an etching process using a photoresist pattern. The buffer layer 120 may be formed by chemical vapor deposition. However, the disclosure may not be limited thereto.

[0132] Although the first light shielding layer 360 has been described above, it will be understood that another light shielding layer formed in the same manner as the first light shielding layer 360 may be disposed on the first substrate 110 .

[0133] like Fig.12 As shown in FIG. 1 , a first active layer 350 and a second active layer 450 may be formed on the buffer layer 120 ( Fig.10 Once a layer can be formed by a sputtering method, the first active layer 350 and the second active layer 450 can be formed by a patterning process using a photoresist. However, the disclosure may not be limited thereto, and in some cases, the first active layer 350 and the second active layer 450 may be formed by atomic layer deposition.

[0134] like Fig.13 As shown in FIG. 1 , a first gate insulating layer 130 ( Fig.10 Step S104), and a first gate electrode 310 and a second gate electrode 410 may be formed on the first gate insulating layer 130 ( Fig.10 Step S105).

[0135] The first gate insulating layer 130 may be formed by chemical vapor deposition. Once a gate metal layer is formed on the first gate insulating layer 130 by a sputtering method, the first gate electrode 310 and the second gate electrode 410 may be formed by performing a patterning process using a photoresist on the gate metal layer.

[0136] like Fig.14 As shown in FIG. 1 , a first interlayer insulating layer 160, first and second source electrodes 330 and 430, and first and second drain electrodes 340 and 440 may be formed to be included in the first and second transistors TR1 and TR2 ( Fig.10 The first and second source electrodes 330 and 430 and the first and second drain electrodes 340 and 440 may be formed by patterning a metal layer formed on the first interlayer insulating layer 160 by a sputtering method through an etching process using a photoresist pattern.

[0137] like Fig.15 As shown in FIG. 1 , a first passivation layer 170, a first planarization layer 180, a first electrode 191, an organic light emitting layer 192, a pixel defining layer 195, a second electrode 193 and an encapsulation layer 196 ( Fig.10 Step S107).

[0138] Hereinafter, a description of a first transistor TR1 and a second transistor TR2 according to another embodiment is as follows.

[0139] The first active layer 350 of the first transistor TR1 may further include a region in which the concentration of oxygen atoms O may be higher than that of other regions.

[0140] Fig.16 A schematic cross-sectional view is shown which illustrates a first transistor according to a further embodiment. Fig.17 is partially shown in the manufacturing Fig.16 A schematic cross-sectional view of a first transistor method. Fig.18 It shows that according to Fig.16 A graph of the driving current of the gate voltage of the first transistor.

[0141] Reference Figures 16 to 18 , the first transistor TR1_1 may further include a first region and a second region OL_1 having an oxygen atomic concentration higher than that of the first region. Fig.16 The first transistor TR1_1 is connected to Figure 6 The differences of the embodiments are: Fig.16 The first transistor TR1_1 also includes a second region OL_1 having a higher oxygen atom concentration.

[0142] Fig.16 The first transistor TR1_1 may include a second region OL_1 (as indicated by the shading provided) formed on at least an upper surface and at least one side surface of the first active layer 350_1. The second region OL_1 may also be partially formed in a region adjacent to the upper surface of the first active layer 350_1 (e.g., a corner between the upper surface and at least one side surface of the first active layer 350_1). The second region OL_1 may be formed above the bottom of the buffer layer 120 on which the first active layer 350_1 may be disposed, that is, at the top of the buffer layer 120.

[0143] The second region OL_1 may have a concentration of oxygen atoms O higher than that of the first region of the first active layer 350_1. The first region of the first active layer 350_1 may be a region of the first active layer 350_1 opposite to the upper surface (i.e., the lower surface of the first active layer 350_1). Therefore, the oxygen atom concentration of the upper surface of the first active layer 350_1 may be greater than that of the lower surface of the first active layer 350_1. Once the first active layer 350_1 may be formed, the second region OL_1 may be formed by irradiating plasma containing oxygen atoms on the first active layer 350_1.

[0144] like Fig.17 As shown in FIG. , in the case where a plasma containing oxygen atoms (e.g., N 2In the case where plasma (O plasma) is irradiated onto the first active layer 350_1 formed on the buffer layer 120, a second region OL_1 which may have an oxygen atom concentration higher than that of other regions of the first active layer 350_1 may be formed on the upper surface of the first active layer 350_1. Although plasma may be irradiated only on the first active layer 350_1 (as indicated by a downward arrow), plasma may also be irradiated on the second active layer 450 of the second transistor TR2. When plasma is irradiated, a second region OL_1 at which the oxygen atom concentration is higher than that of other regions may be formed in a region adjacent to the exposed upper surface and both side surfaces of the first active layer 350_1. Therefore, the oxygen atom concentration of the upper surface of the first active layer 350_1 may be greater than that of the lower surface of the first active layer 350_1.

[0145] In the case where the first active layer 350_1 may include the second region OL_1 having a higher oxygen atom concentration than other regions, the performance of the first transistor TR1_1 may be further maximized. Fig.18 As shown in , as described above, the first active layer 350_1 of the first transistor TR1_1 may contain a relatively high amount of indium (In) and include the second region OL_1 having a high oxygen atom concentration. Therefore, a swing value below the threshold voltage may increase.

[0146] exist Fig.18 In the figure, the dotted line indicates that the N 2 The solid line may indicate that the active layer of the driving transistor may be formed by irradiating N on an oxide semiconductor having an indium (In) content of about 75 at %. 2 O plasma to form an active layer of the driving transistor. Fig.18 In the curve represented by the dotted line, it can be observed that the swing value below the threshold voltage is about 0.26, and the driving range of the gate voltage (V) is about 1.28V. Fig.18 The solid line represents the curve (i.e., Fig.16 In the driving transistor including the oxide semiconductor active layer including the second region OL_1 shown in FIG, a swing value below the threshold voltage of about 0.58 can be observed, and a driving range of the gate voltage (V) of about 3.24 V can be observed. Fig. 9 By comparison, it can be seen that when N 2When N O plasma is irradiated to an oxide semiconductor containing about 75 at % of indium (In) to form a region having a high oxygen atomic concentration, the driving range of the gate voltage (V) can be further increased. Therefore, the first active layer 350_1 may include a second region OL_1 (which is formed by irradiating N 2 O plasma and a region with a high oxygen atom concentration), the first transistor TR1_1 according to the embodiment can have a wider driving range of the gate voltage (V) within the same range of the driving current (A). In other words, the first transistor TR1_1 according to the embodiment can have an incremental increase in the range of the driving voltage (V) that can exceed the incremental increase in the range of the driving current (A).

[0147] In addition, similar to the first transistor TR1 , the second transistor TR2 may include a light shielding layer.

[0148] Fig.19 A plan view of a second transistor according to another embodiment is shown. Fig. 20 Shown along Fig.19 A schematic cross-sectional view taken along line III-III'.

[0149] Reference Fig.19 and Fig. 20 , the second transistor TR2_2 according to the embodiment may further include a second light shielding layer 460_2. The second gate electrode 410_2 may be connected to the second light shielding layer 460_2. Fig.19 and Fig. 20 The second transistor TR2_2 is connected to Figure 7 and Figure 8 The second transistor TR2 may be different in that the second gate electrode 410_2 may be connected to the second light shielding layer 460_2.

[0150] Fig.19 and Fig. 20 The second transistor TR2_2 may include a second gate electrode 410_2, a second active layer 450_2, a second source electrode 430_2, a second drain electrode 440_2, and a second light shielding layer 460_2.

[0151] The second light shielding layer 460_2 may be disposed on the first substrate 110. The second light shielding layer 460_2 may prevent light from the outside from passing through the first substrate 110 and being incident on the second active layer 450_2. The length of the second light shielding layer 460_2 in the third direction DR3 and the length of the second light shielding layer 460_2 in the fourth direction DR4 may be longer than the length of the second active layer 450_2 in the third direction DR3 and the length of the second active layer 450_2 in the fourth direction DR4. The second light shielding layer 460_2 may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof. The buffer layer 120 may be formed on the second light shielding layer 460_2.

[0152] The second gate electrode 410_2 may contact the second light shielding layer 460_2 through the sixth contact hole CT6. The sixth contact hole CT6 may be formed to pass through the first gate insulating layer 130 and the buffer layer 120 to expose the second light shielding layer 460_2. The second gate electrode 410_2 and the second light shielding layer 460_2 disposed below the second active layer 450_2 may have the same voltage. For example, the second gate electrode 410_2 may be used as an upper gate electrode, and the second light shielding layer 460_2 may be used as a lower gate electrode. Therefore, since the second transistor TR2_2, which may be a switching transistor, may be driven in a dual-gate manner, when the second transistor TR2_2 may be turned off, leakage current may be prevented or reduced from flowing into the channel region 450c_2 of the second active layer 450_2 of the second transistor TR2_2.

[0153] Although not shown, the scan driver 30 may include a plurality of stages, and the plurality of stages may sequentially output the scan signal S to the scan lines SL1 to SLk of each pixel PX. The stages may include a pull-up transistor, a pull-down transistor, and a node controller. The pull-up transistor and the pull-down transistor may be formed in substantially the same manner as the second transistor TR2 or TR2_2. Although not shown, the display device 1 may further include a data voltage divider circuit, which may include a divider transistor. The divider transistor may also be formed in substantially the same manner as the second transistor TR2 or TR2_2. The pull-up transistor, the pull-down transistor, and the divider transistor may also include a gate electrode, an active layer, a source electrode, and a drain electrode, each of which may be formed substantially the same as the second transistor TR2 or TR2_2 described above.

[0154] Fig.21 A schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0155] Reference Fig.21, the display device 1 according to the embodiment may include transistor layers TFTL1 and TFTL2. The transistor layers TFTL1 and TFTL2 may include a first transistor layer TFTL1 and a second transistor layer TFTL2 having different transistors, respectively. The third transistor TR3_3 (for example, the third active layer 550_3 of the pull-up transistor of the scan driver 30 described above) may include polysilicon. The first transistor TR1_3 and the second transistor (for example, the aforementioned TR2 or TR2_2), which may be respectively used as the driving transistor and the switching transistor of each pixel PX, may be located above the third transistor TR3_3. Although only the first transistor TR1_3 is shown, the second transistor (for example, the aforementioned TR2 or TR2_2) may also be provided on the same layer as the first transistor TR1_3. The first transistor TR1_3 may include an active region 350_3 and a light shielding layer 360_3, and the active region 350_3 includes conductor regions 350a_3 and 350b_3 and a channel region 350c_3. Fig.21 The embodiment of may be different from other embodiments herein in that a plurality of transistors included in the display device 1 may be disposed in different transistor layers TFTL1 and TFTL2.

[0156] like Fig.21 As shown in FIG. 1 , the first transistor layer TFTL1 may include a third transistor TR3_3 , and the third transistor TR3_3 may include a third gate electrode 510_3 , a third active layer 550_3 , and third source and drain electrodes 530_3 and 540_3 .

[0157] The third active layer 550_3 may be disposed on the buffer layer 120. The third active layer 550_3 may include polycrystalline silicon, and may include a first doped region 550a_3, a second doped region 550b_3, and a channel region 550c_3. The channel region 550c_3 may be made of polycrystalline silicon that may not be doped with impurities, and the first doped region 550a_3 and the second doped region 550b_3 may be made of polycrystalline silicon doped with impurities. However, the disclosure may not be limited thereto, and the third active layer 550_3 may also be formed of an oxide semiconductor in the same manner as the active region 350_3.

[0158] The second gate insulating layer 230 may be disposed on the third active layer 550_3. The second gate insulating layer 230 may be made of, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ) or their stacked structures.

[0159] The third gate electrode 510_3 may be disposed on the second gate insulating layer 230. The third gate electrode 510_3 may overlap or face the third active layer 550_3, and the second gate insulating layer 230 is interposed between the third gate electrode 510_3 and the third active layer 550_3. The third gate electrode 510_3 may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0160] Although the second gate insulating layer 230 may be disposed between the third active layer 550_3 and the third gate electrode 510_3 , the second gate insulating layer 230 may also be formed on the upper surface and the side surface of the third active layer 550_3 .

[0161] The second interlayer insulating layer 260 may be disposed on the third gate electrode 510_3. The second interlayer insulating layer 260 may be made of an inorganic material (such as silicon oxide (SiO x ), Silicon Nitride (SiN x ) or their stacked structures).

[0162] The second interlayer insulating layer 260 may include a seventh contact hole CT7 passing through the second interlayer insulating layer 260 to expose a portion of the upper surface of the third active layer 550_3, and an eighth contact hole CT8 passing through the second interlayer insulating layer 260 to expose another portion of the upper surface of the third active layer 550_3. For example, the seventh contact hole CT7 may be formed to expose the first doped region 550a_3 of the third active layer 550_3, and the eighth contact hole CT8 may be formed to expose the second doped region 550b_3 of the third active layer 550_3.

[0163] A third source electrode 530_3 and a third drain electrode 540_3 of the third transistor TR3_3 may be disposed on the second interlayer insulating layer 260 .

[0164] The third source electrode 530_3 may contact the first doping region 550a_3 formed on one side of the third active layer 550_3 through the seventh contact hole CT7. The third drain electrode 540_3 may contact the second doping region 550b_3 formed on the other side of the third active layer 550_3 through the eighth contact hole CT8.

[0165] The second passivation layer 270 may be formed on the third source electrode 530_3 and the third drain electrode 540_3. The second passivation layer 270 may be formed of an inorganic layer (eg, silicon oxide (SiO x ) layer, silicon nitride (SiN x ) layer or a multilayer structure thereof).

[0166] The second planarization layer 280 may be disposed on the second passivation layer 270. The second planarization layer 280 may planarize a step caused by the formation of a thin film transistor such as the third transistor TR3_3. The second planarization layer 280 may be formed of an organic layer such as an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0167] The insulating layer 121 may be disposed on the second planarization layer 280. Figures 5 to 8 The first interlayer insulating layer 160, the first passivation layer 170, and the first planarizing layer 180 described above may be formed on the insulating layer 121. Fig.21 In the embodiment shown in FIG. 1 , a first transistor layer TFTL1 including a third transistor TR3_3 may be disposed on the first substrate 110, and the third transistor TR3_3 may be a voltage divider transistor and a pull-up transistor and a pull-down transistor included in the scan driver 30. A second transistor layer TFTL2 including a first transistor TR1_3 and a second transistor (e.g., the aforementioned TR2 or TR2_2) (respectively serving as a driving transistor and a switching transistor of each pixel PX) may be disposed on the first transistor layer TFTL1. A light emitting element EL including a first electrode 191, an organic light emitting layer 192, and a second electrode 193 may be formed on the second transistor layer TFTL2.

[0168] However, the disclosure may not be limited thereto. Fig.21 In the embodiment of the present invention, the third transistor TR3_3 may have a different configuration. For example, the third transistor TR3_3 may further include a light shielding layer. In addition, the first transistor TR1_3 and the second transistor (eg, the aforementioned TR2 or TR2_2) may be respectively disposed in different transistor layers TFTL1 and TFTL2.

[0169] Although disclosed embodiments have been described, it is to be understood that the disclosure may not be limited to these embodiments, and that various changes and modifications may be made by those skilled in the art within the spirit and scope of the disclosure as claimed. Therefore, the disclosed subject matter may not be limited to any single embodiment described herein, and the scope of the disclosure may be determined according to the claims.

Claims

1. A display device, comprising: A plurality of pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the plurality of pixels includes a light emitting element and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, wherein the first transistor includes a first active layer, the first active layer includes an oxide semiconductor including indium, and wherein a content of the indium in the oxide semiconductor of the first active layer is 70 at % or more, and The first active layer includes a first region and a second region, and the second region has an oxygen atomic concentration higher than that of the first region.

2. The display device according to claim 1, wherein: The oxide semiconductor includes indium tin oxide or indium tin gallium oxide.

3. The display device according to claim 2, wherein: The sum of the amount of the indium and the amount of tin in the oxide semiconductor is greater than or equal to 95 at %.

4. The display device according to claim 3, wherein: The amount of the tin in the oxide semiconductor is in a range of 5 at % to 20 at %.

5. The display device according to claim 1, wherein: The second region is located on an upper surface of the first active layer and at least one side surface of the first active layer.

6. The display device according to claim 1, wherein: The first active layer includes a first conductor region, a second conductor region, and a channel region disposed between the first conductor region and the second conductor region.

7. A display device, comprising: A plurality of pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the plurality of pixels includes a light emitting element and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, wherein the first transistor includes a first active layer, the first active layer includes an oxide semiconductor including indium, and wherein a content of the indium in the oxide semiconductor of the first active layer is 70 at % or greater, The first active layer includes a first conductor region, a second conductor region, and a channel region disposed between the first conductor region and the second conductor region, and Wherein, the first transistor further comprises: A first light shielding layer, disposed below the first active layer; a first gate electrode, disposed on the first active layer; a first source electrode in contact with the first conductor region through a first contact hole penetrating through a first insulating layer, the first insulating layer being disposed on the first gate electrode; and The first drain electrode contacts the second conductor region through a second contact hole penetrating through the first insulating layer.

8. The display device according to claim 7, wherein: The first gate electrode overlaps the first active layer with an overlap amount of 2 μm to 10 μm.

9. The display device according to claim 7, wherein: The first source electrode contacts the first light shielding layer through a third contact hole penetrating the first insulating layer and a buffer layer, and the buffer layer is disposed between the first active layer and the first light shielding layer.

10. The display device according to claim 7, wherein: The pixel further includes a second transistor configured to apply the data voltage of the data line to the first transistor according to a scan signal applied to the scan line, and the second transistor includes a second active layer including an oxide semiconductor including indium.

11. A display device, comprising: A plurality of pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the plurality of pixels includes a light emitting element and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, wherein the first transistor includes a first active layer, the first active layer includes an oxide semiconductor including indium, and wherein a content of the indium in the oxide semiconductor of the first active layer is 70 at % or greater, wherein the pixel further includes a second transistor configured to apply the data voltage of the data line to the first transistor according to a scan signal applied to the scan line, and the second transistor includes a second active layer including an oxide semiconductor including indium, and Wherein, the second transistor further comprises: a second light shielding layer, disposed below the second active layer; and The second gate electrode is disposed on the second active layer.

12. The display device according to claim 11, wherein: The second gate electrode contacts the second light shielding layer through a sixth contact hole passing through a first gate insulating layer and a buffer layer, the first gate insulating layer is arranged between the second active layer and the second gate electrode, and the buffer layer is arranged between the second active layer and the second light shielding layer.

13. The display device according to claim 11, further comprising: a scan driver configured to output a scan signal to the scan line, The scan driver includes a third transistor, and the third transistor includes a third active layer.

14. A display device, comprising: A plurality of pixels connected to scan lines and data lines intersecting the scan lines, wherein each of the plurality of pixels includes a light emitting element and a first transistor configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, wherein the first transistor includes a first active layer, the first active layer includes an oxide semiconductor including indium, and wherein a content of the indium in the oxide semiconductor of the first active layer is 70 at % or greater, Wherein, the display device further includes: a scan driver configured to output a scan signal to the scan line, wherein the scan driver comprises a third transistor, the third transistor comprises a third active layer, and The first active layer of the first transistor is arranged above the third active layer of the third transistor.

15. A display device, comprising: A plurality of pixels connected to scan lines and data lines intersecting the scan lines, Each of the plurality of pixels includes a light emitting element, a driving transistor and a switching transistor, wherein the driving transistor is configured to control a driving current supplied to the light emitting element according to a data voltage applied from the data line, and the switching transistor is configured to apply the data voltage of the data line to the driving transistor according to a scanning signal applied to the scanning line. The driving transistor and the switching transistor each include an active layer, and the active layer includes an oxide semiconductor including indium. wherein the content of indium in the oxide semiconductor of the active layer is 70 at % or more, and The oxygen atom concentration of the upper surface of the active layer of the driving transistor is higher than the oxygen atom concentration of the lower surface of the active layer of the driving transistor.

16. The display device according to claim 15, wherein: The oxide semiconductor includes indium tin oxide or indium tin gallium oxide.

17. The display device according to claim 16, wherein: The sum of the amount of the indium and the amount of tin in the oxide semiconductor is greater than or equal to 95 at %.

18. The display device according to claim 16, wherein: The driving transistor further includes a gate electrode disposed on the active layer, and an overlapping region of the gate electrode and the active layer has a length in a range of 2 μm to 10 μm.

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