Aggregated and virtualized solid-state drives accessed via multiple logical address spaces

Abstract

The present application relates to aggregated and virtualized solid-state drives accessed via multiple logical address spaces. A solid-state drive includes a drive aggregator and multiple component solid-state drives. The drive aggregator associates host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the multiple component solid-state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have overlapping regions hosted on the same group of memory cells, such that the memory cells can be addressed in any of the logical address spaces having the overlapping regions.

Description

Technical Field

[0001] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, the aggregation and virtualization of solid-state drives that are accessible using separate logical address spaces. Background Art

[0002] The memory subsystem may be a storage system, such as a solid-state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, nonvolatile memory components and volatile memory components. Examples of memory components include memory integrated circuits. Some memory integrated circuits are volatile and require power to maintain stored data. Some memory integrated circuits are nonvolatile and can retain stored data even when not powered. Examples of nonvolatile memory include flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), and electronically erasable programmable read-only memory (EEPROM) memory, among others. Examples of volatile memory include dynamic random access memory (DRAM) and static random access memory (SRAM).In general, a host system may utilize a memory subsystem to store data at and retrieve data from memory components.

[0003] For example, a computer may include a host system and one or more memory subsystems attached to the host system. The host system may have a central processing unit (CPU) that communicates with the one or more memory subsystems to store and / or retrieve data and instructions. Instructions for the computer may include an operating system, device drivers, and application programs. The operating system manages resources in the computer and provides common services for application programs, such as memory allocation and resource time-sharing. Device drivers operate or control specific types of devices in the computer; and the operating system uses the device drivers to provide resources and / or services provided by those types of devices. The computer system's central processing unit (CPU) may run the operating system and device drivers to provide services and / or resources to application programs. The central processing unit (CPU) may run application programs that use those services and / or resources. For example, an application program that implements a type of application of the computer system may instruct the central processing unit (CPU) to store data in and retrieve data from the memory components of the memory subsystem. Summary of the Invention

[0004] One aspect of the present disclosure provides a solid-state drive, wherein the solid-state drive includes: a drive aggregator having multiple host interfaces; and multiple component solid-state drives connected to the drive aggregator, each of the component solid-state drives having a controller capable of processing commands from a host system; wherein the drive aggregator is configured to associate the host interfaces with different logical address spaces, interpret commands received from the host interfaces in the different logical address spaces, and implement the commands using the multiple component solid-state drives.

[0005] Another aspect of the present disclosure provides a method, wherein the method includes: a drive aggregator having multiple host interfaces associating the host interfaces with different logical address spaces; mapping the different logical address spaces to the aggregated capacity of multiple component solid-state drives connected to the drive aggregator by the drive aggregator; simultaneously receiving a first command from parallel connections to one or more host systems via the multiple host interfaces in the drive aggregator; interpreting the first command received from the host interface in the different logical address spaces by the drive aggregator; and transmitting a second command from the drive aggregator to the multiple component solid-state drives based on interpreting the first command in the different logical address spaces.

[0006] Another aspect of the present disclosure provides a drive aggregator, wherein the drive aggregator includes: a plurality of host interfaces, each of which is configured to communicate with a host system; a plurality of drive interfaces, each of which communicates with a plurality of component solid-state drives; and translation logic coupled between the host interface and the plurality of drive interfaces, wherein the translation logic is configured to interpret addresses in commands received in the plurality of host interfaces in different logical address spaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0008] Figure 1 An example computing system with a memory subsystem according to some embodiments of the present disclosure is shown.

[0009] Figure 2 Shows a host system connected to a virtualized single solid-state drive with multiple component solid-state drives.

[0010] Figure 3 A drive aggregator according to one embodiment is shown.

[0011] Figure 4 A method implemented in a drive aggregator according to one embodiment is shown.

[0012] Figure 5 A method of distributing commands received in a virtualized solid-state drive to solid-state drives is presented.

[0013] Figure 6 Shows multiple host systems connected to a virtualized single solid-state drive with multiple component solid-state drives.

[0014] Figure 7 A drive aggregator with multiple host interfaces is shown according to one embodiment.

[0015] Figure 8 A host system is shown connected to a virtualized single solid-state drive via multiple parallel and / or redundant connections.

[0016] Figure 9 A method of processing commands received in a virtualized solid-state drive via multiple host interfaces is presented.

[0017] Figure 10 A virtualized single solid-state drive is shown configured to be accessed via a separate logical address space according to one embodiment.

[0018] Figure 11 A drive aggregator configured to facilitate access to memory / storage resources in a virtualized single solid-state drive using separate logical address spaces is shown.

[0019] Figure 12-14 An example of address mapping is shown.

[0020] Figure 15 A method of virtualizing memory / storage resources in a single solid-state drive using separate logical address spaces for access is presented. DETAILED DESCRIPTION

[0021] At least some aspects of the present disclosure are directed to techniques for aggregating multiple memory subsystems into a combined memory subsystem that acts as a single memory subsystem for a host system. In some embodiments, the single memory subsystem is configured with multiple host interfaces to serve multiple host systems, or to serve a single host system via multiple parallel and / or redundant connections.

[0022] Currently, solid-state drives (SSDs) can be provided in a single integrated circuit package. For example, a solid-state drive (SSD) may be packaged in a ball grid array (BGA) form factor. A BGA SSD has a controller embedded in the integrated circuit package to process commands from a host system, control operations to access data in a media unit or memory component embedded in the BGA SSD, and generate responses to commands from the host system. However, the single integrated circuit package and / or BGA form factor may limit the storage capacity of a BGA SSD.

[0023] At least some aspects of the present disclosure address the above and other deficiencies through a drive aggregator configured to aggregate and virtualize multiple SSDs into a single SSD for a host system. Thus, multiple BGA SSDs can be used to construct a single high-capacity SSD for a host system. The combined SSD can have a storage capacity not limited by a single integrated circuit package and / or BGA form factor.

[0024] Typically, a drive aggregator can be used to aggregate and virtualize multiple memory subsystems for a host system. One example of a memory subsystem is a storage device connected to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module connected to a central processing unit (CPU) via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), and the like. In some embodiments, the memory subsystem is a hybrid memory / storage device subsystem that provides both memory and storage functions. Generally speaking, a host system may utilize a memory subsystem that includes one or more memory components. The host system can provide data for storage at the memory subsystem and can request retrieval of data from the memory subsystem.

[0025] Figure 1 An example computing system 100 is shown having a memory subsystem according to some embodiments of the present disclosure. Figure 1 In FIG, solid-state drive 101 is shown as an example of this memory subsystem. The aggregate solid-state drive 101 is constructed using multiple component solid-state drives 107 to 109. The drive aggregator 103 of the solid-state drive 101 virtualizes the entire combined capacity of the multiple component solid-state drives 107 to 109 into the capacity of the aggregate solid-state drive 101. The drive aggregator 103 shields the component solid-state drives 107 to 109 from the host system 111 so that the host system 111 can access the memory capacity of the multiple component solid-state drives 107 to 109 by addressing a single solid-state drive 101. In general, Figure 1 Each of the components in the solid-state drives 107 to 109 is another example of a memory subsystem.

[0026] Generally speaking, a memory subsystem may include media, such as a media unit / memory component. The media unit / memory component may be a volatile memory component, a non-volatile memory component, or a combination thereof. Each of the media units / memory components can perform operations to store, record, program, write, or submit new data independently of the operations of the other media units / memory components. Therefore, the media units / memory components can be used to execute write commands in parallel. In some embodiments, the memory subsystem is a storage system. An example of a storage system is a solid-state drive (SSD). In other embodiments, the memory subsystem is a memory module. Examples of memory modules include DIMMs, NVDIMMs, and NVDIMM-Ps. In yet another embodiment, the memory subsystem is a hybrid memory / storage device subsystem. Typically, the computing system 100 may include a host system 111, which uses a memory subsystem (e.g., solid-state drive 101) via a computer bus 117. For example, the host system 111 can write data to the memory subsystem and read data from the memory subsystem.

[0027] Host system 111 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or any other computing device that includes memory and processing devices. Host system 111 may include or be coupled to a memory subsystem (e.g., solid-state drive 101) via a computer bus 117, such that host system 111 can read data from or write data to the memory subsystem. Host system 111 may be coupled to the memory subsystem via a physical host interface. As used herein, "coupled" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intervening component), whether wired or wireless, including, for example, electrical, optical, magnetic, or other connections. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, and the like. The physical host interface may be used to transmit data between host system 111 and a memory subsystem (e.g., solid-state drive 101). When the memory subsystem is coupled to the host system 111 via a PCIe interface, the host system 111 can further utilize an NVM Express (NVMe) interface to access the storage capacity of the memory subsystem. The physical host interface can provide an interface for passing control, address, data, and other signals between the host system 111 and the memory subsystem (e.g., solid-state drive 101). Figure 1 Solid-state drive 101 is shown as an example memory subsystem.In general, host system 111 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Host system 111 includes a processing device 113 and a controller 115. The processing device 113 of host system 111 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, controller 115 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, controller 115 controls communications on a computer bus 117 coupled between host system 111 and a memory subsystem (e.g., solid-state drive 101).

[0029] Typically, the controller 115 may send commands or requests to the memory subsystem for desired access to memory storage capacity. The controller 115 may further include interface circuitry to communicate with the memory subsystem via the computer bus 117. The interface circuitry may convert responses received from the memory subsystem into information for the host system 111.

[0030] The controller 115 of the host system 111 can communicate with the controller 115 of the memory subsystem to perform operations such as reading data, writing data, or erasing data, and other such operations, at the memory components of the memory subsystem. In some examples, the controller 115 is integrated into the same integrated circuit package as the processing device 113. In other examples, the controller 115 is separate from the integrated circuit package of the processing device 113. The controller 115 and / or the processing device 113 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 115 and / or the processing device 113 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0031] In general, the media units / memory components of a memory subsystem (e.g., solid-state drive 107 or 109) may include any combination of different types of non-volatile memory components and / or volatile memory components. An example of a non-volatile memory component includes non-AND (NAND)-type flash memory. Each of the memory components may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., a data block) used by the host system 111. Although non-volatile memory components such as NAND-type flash memory are described, the memory components may be based on any other type of memory, such as volatile memory. In some embodiments, the memory component may be, but is not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, ferroelectric random access memory (FeTRAM), ferroelectric RAM (FeRAM), conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), nanowire-based nonvolatile memory, memory incorporating memristor technology, and cross-point arrays of nonvolatile memory cells. The cross-point array of the nonvolatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. Furthermore, the memory cells of a memory component can be grouped into memory pages or data blocks, which can refer to cells of a memory component used to store data.

[0032] Generally speaking, a memory subsystem (e.g., solid-state drive 107 or 109) may have a controller that communicates with the memory components of the memory subsystem to perform operations such as reading, writing, or erasing data, and other such operations (e.g., in response to commands dispatched on a command bus). The memory subsystem controller may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller may include a processing device (e.g., a processor) configured to execute instructions stored in the controller's local memory. For example, the local memory of the memory subsystem controller may include embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem, including handling communications between the memory subsystem and a host system (e.g., 111). In some embodiments, the local memory may include memory registers that store memory pointers, retrieved data, etc. The local memory may also include read-only memory (ROM) for storing microcode. While typical memory subsystems have a controller, in another embodiment of the present disclosure, the memory subsystem may not include a controller, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Typically, the controller of a memory subsystem (e.g., solid-state drive 107 or 109) may receive commands or operations from a host system 111 and may convert the commands or operations into instructions or appropriate commands to enable desired access to the memory components of the memory subsystem. The controller of a memory subsystem (e.g., solid-state drive 107 or 109) may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses. The controller of a memory subsystem (e.g., solid-state drive 107 or 109) may further include a host interface circuit system to communicate with a host system (e.g., 111) via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions for accessing the memory components, and convert responses associated with the memory components into information for the host system (e.g., 111).

[0034] The memory subsystem (e.g., solid-state drive 107 or 109) may also include additional circuitry or components. In some embodiments, the memory subsystem (e.g., solid-state drive 107 or 109) may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem's controller and decode the addresses to access memory components in the memory subsystem.

[0035] Computing system 100 includes a drive aggregator 103 that aggregates the capacity of component solid-state drives 107-109 and virtualizes the entire combined capacity into the capacity of a single solid-state drive 101. In some embodiments, drive aggregator 103 includes logic circuitry to translate commands / requests from host system 111 into commands / requests to solid-state drives 107-109, and / or to translate responses from solid-state drives 107-109 into responses to host system 111. Drive aggregator 103 accesses commands from host system 111 according to a communication protocol for solid-state drives to accept commands from host systems. Drive aggregator 103 constructs commands according to a communication protocol for host systems to issue commands to solid-state drives and transmits the commands to each of component solid-state drives (e.g., 107 or 109). Drive aggregator 103 accepts responses from each of component solid-state drives (e.g., 107 or 109) according to a communication protocol between the host system and solid-state drives. The drive aggregator 103 constructs a response according to the communication protocol between the host system and the solid-state drives and transmits the response to the host system 111. In one embodiment, the communication protocol used between the host system 111 and the drive aggregator 103 can be the same as the communication protocol used between the drive aggregator 103 and the component solid-state drives 107 to 109. In one embodiment, the communication protocol used between the host system 111 and the drive aggregator 103 can be different from the communication protocol used between the drive aggregator 103 and the component solid-state drives 107 to 109. The drive aggregator 103 behaves like a controller of a standard solid-state drive to the host system 111 according to one communication protocol, and behaves like a standard host system to the component solid-state drives 107 to 109 according to the same or different communication protocol.

[0036] In the solid-state drive 101, the drive aggregator 103 is connected to the component solid-state drives 107 to 109 via a bus 105. For example, the bus 105 may include a point-to-point serial connection from the drive aggregator 103 to the component solid-state drives 107 to 109. The point-to-point serial connection between the drive aggregator 103 and the component solid-state drives 107 to 109 may be based on the Serial Advanced Technology Attachment (SATA) communication protocol, the Peripheral Component Interconnect Express (PCIe) communication protocol, or another protocol. The computer bus 117 between the host system 111 and the drive aggregator 103 may be based on the Serial Advanced Technology Attachment (SATA) communication protocol, the Peripheral Component Interconnect Express (PCIe) communication protocol, the Universal Serial Bus (USB) communication protocol, the Fibre Channel communication protocol, the Serial Attached SCSI (SAS) communication protocol, the Double Data Rate (DDR) memory bus communication protocol, etc.

[0037] The drive aggregator 103 can be implemented using an integrated circuit chip having a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). Alternatively, the drive aggregator 103 can be implemented at least in part via software or firmware. For example, the drive aggregator 103 or a processing device embedded within the drive aggregator 103 can be configured to execute instructions stored in a memory for performing the operations of the drive aggregator 103 described herein. In some embodiments, the drive aggregator 103 is implemented in a single integrated circuit chip configured on an overall solid-state drive 101 having multiple component solid-state drives 107.

[0038] Figure 2 A host system 111 is shown connected to a virtualized single solid-state drive having multiple component solid-state drives 107-109. For example, the virtualized single solid-state drive may be used to implement Figure 1 Solid state drive 101 is shown.

[0039] exist Figure 2 In the embodiment, printed circuit board 131 is configured with pins 133 for connecting a single solid-state drive 101 to a host system 111. For example, connection 135 may be a point-to-point serial connection based on SATA, PCIe, USB, or another standard. Based on the communication standard, host system 111 is configured to recognize the device configured on printed circuit board 131 as a single solid-state drive 101. Host system 111 addresses the memory in the device based on the recognition of the device as a single solid-state drive 101.

[0040] Commands from the host system 111 are received in the drive aggregator 103 via connection 135 and pin 133. The received commands are processed in the drive aggregator 103 for adjustment, mapping, and / or distribution to the component solid-state drives 107 to 109. For example, each of the component solid-state drives 107 to 109 may be implemented as a ball grid array (BGA) solid-state drive (SSD) capable of directly processing commands from the host system 111. For example, when the connection 137 from the component solid-state drive 109 to the drive aggregator 103 is directly connected to the host system 111, the host system 111 can recognize the solid-state drive 109 and communicate directly with the solid-state drive 109 to store data in the solid-state drive 109 and / or retrieve data from the solid-state drive 109.

[0041] For example, BGA SSD 107 may have a controller 141 capable of directly communicating with a host system (eg, 111 ) to receive commands and provide responses; and may have a plurality of media units (memory components) 143 - 147 having memory cells for storing data.

[0042] The drive aggregator 103 is configured to shield the details of the component solid-state drives 107-109 from the host system 111. Thus, the host system 111 does not have to individually address the component solid-state drives 107-109. For example, according to a set of predetermined rules, the drive aggregator 103 may forward some commands from the host system 111 to one component solid-state drive (e.g., 107) and forward other commands from the host system 111 to another component solid-state drive (e.g., 109).

[0043] For example, the drive aggregator 103 may divide the logical address space of the entire capacity of the device configured on the printed circuit board 131 into a plurality of zones. Each of the zones is associated with a corresponding one of the component solid-state drives 107 to 109. When the drive aggregator 103 receives a command received from the host system 111, the drive aggregator 103 determines the zone in which the logical address of the command is located, identifies the target solid-state drive (e.g., 107) associated with the determined zone, adjusts the command to at least map the logical address in the command received in the host to the logical address in the target solid-state drive (e.g., 107), and transmits the adjusted command to the target solid-state drive (e.g., 107).

[0044] In some embodiments, the host system 111 is configured to organize the memory capacity of the virtualized single solid-state drive 101 on the printed circuit board into named portions. The named portions of the memory capacity are namespaces. Logical addresses can be defined within separate namespaces for the memory capacity of the virtualized single solid-state drive 101. For example, a first namespace allocated for a first portion of n blocks of memory capacity can have logical block addressing (LBA) addresses in the range of 0 to n-1; and a second namespace allocated for a second portion of m blocks of memory capacity can have LBA addresses in the range of 0 to m-1. To access a memory block, the host system 111 identifies the namespace and the LBA address defined within the namespace.

[0045] The drive aggregator 103 may be configured to distribute operations requested by the host system 111 to the component solid-state drives 107 to 109 based on namespaces. For example, the drive aggregator 103 may assign different namespaces created on the memory capacity of the virtualized single solid-state drive 101 to different component solid-state drives 107 to 109. The drive aggregator 103 may then simply forward commands from the host system 111 to the component solid-state drives based on the namespace specified in the command.

[0046] Figure 3 The drive aggregator 103 is shown according to one embodiment. For example, Figure 3 The drive aggregator 103 can be used to Figure 2 printed circuit board 131 and / or Figure 1 A virtualized single solid-state drive 101.

[0047] Figure 3 The drive aggregator 103 can be integrated into a single integrated circuit chip. Figure 3 The drive aggregator 103 includes a host interface 151 for connection 135 to a host system (e.g., 111), translation logic 153, and a plurality of drive interfaces 155 to 157. Each of the drive interfaces 155 to 157 can be used for connection (e.g., 137) to a component solid-state drive (e.g., 109).

[0048] Host interface 151 is configured to implement the solid-state drive side of a communication protocol between a host system and a solid-state drive. Each of drive interfaces 155 and 157 is configured to implement the host system side of a communication protocol between a host system and a solid-state drive. In some examples, drive interfaces 155-157 may support different communication protocols (e.g., SATA and PCIe) so that different types of component solid-state drives 107-109 can be used.

[0049] The translation logic 153 is configured to receive commands from the host interface 151 and generate one or more commands for the drive interfaces 155 to 157. The translation logic 153 generates responses to the commands from the host interface 151 upon receiving one or more corresponding responses from the drive interfaces 155 to 157.

[0050] The drive aggregator 103 has an address map 159 that controls the operation of the translation logic 153. For example, the address map 159 can be used to translate logical addresses in the capacity of the virtualized single solid-state drive 101 into corresponding logical addresses in the capacity of a corresponding component solid-state drive (e.g., 107 or 109) connected to one of the drive interfaces 155 to 157. Based on the address translation, the translation logic 153 can generate a corresponding command for the corresponding drive interface (e.g., 155 or 157).

[0051] In some embodiments, the communication protocols used in connection 135 and connection 137 are different. Therefore, translation logic 153 performs command translation based on the difference in communication protocols.

[0052] In some embodiments, the communication protocols used in connection 135 and connection 137 are different, and translation logic 153 may simply forward commands received in connection 135 to drive interface 157. For example, when a namespace is created on a component solid-state drive (e.g., 109) connected to drive interface 157, commands from host interface 151 for read or write operations in the namespace may be forwarded to drive interface 157.

[0053] The translation logic 153 may be implemented as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or one or more microprocessors that execute an instruction set. The instructions and / or address map 159 may be stored in a local memory unit of the drive aggregator 103. Alternatively, or in combination, the instructions and / or address map 159 may be stored in one or more of the component solid-state drives (e.g., 107 to 109) connected to the drive interfaces 155 to 157.

[0054] Figure 4 A method implemented in the drive aggregator 103 according to one embodiment is shown. For example, Figure 4 The method can be implemented in Figure 1 、 2 and / or the drive aggregator 103 shown in 3 .

[0055] At block 201, the drive aggregator 103 receives a command from the host system 111. The command specifies an operation to be performed by the solid-state drive 101. The drive aggregator 103 acts as a controller for a single solid-state drive 101 to the host system 111. Therefore, commands from the host system 111 to the drive aggregator are configured to address the same solid-state drive 101. The drive aggregator 103 is connected to a plurality of solid-state drives 107 to 109.

[0056] At block 203, the drive aggregator 103 maps the address in the command from the host system 111 to an address in a solid-state drive (e.g., 107 or 109) among the plurality of solid-state drives 107 to 109 connected to the drive aggregator 103. The mapping may be based on a namespace specified in the command from the host system 111, a predetermined address mapping scheme, and / or the address map 159.

[0057] At block 205, the drive aggregator 103 generates a command and transmits the command to the solid-state drive (e.g., 107 or 109). The command to the solid-state drive (e.g., 107 or 109) is configured for the operation specified in the command received from the host system 111 and for the address mapped in the solid-state drive (e.g., 107 or 109).

[0058] For example, a logical address defined in a namespace created in the memory capacity of a single solid-state drive 101 may be mapped to the same logical address defined in a namespace created in the memory capacity of a solid-state drive (e.g., 107 or 109) assigned to implement the namespace.

[0059] For example, the space of logical addresses defined in the entire memory capacity of a single solid-state drive 101 represented by the drive aggregator 103 can be divided into zones (e.g., according to a predefined scheme). Different zones can be mapped to the space of logical addresses defined in the memory capacity of the component solid-state drives 107 to 109.

[0060] When the communication protocol between the host system 111 and the drive aggregator 103 is different from the communication protocol between the drive aggregator 103 and the component solid-state drives 107 to 109 , the drive aggregator 103 may perform command translation according to the communication protocol.

[0061] When the communication protocol between the host system 111 and the drive aggregator 103 is the same as the communication protocol between the drive aggregator 103 and the component solid-state drives 107 to 109, in some embodiments (e.g., when the address mapping is namespace-based), the drive aggregator 103 can be configured to forward the command to the target solid-state drive 101 unchanged.

[0062] For example, the communication protocol between the host system 111 and the drive aggregator 103, and the communication protocol between the drive aggregator 103 and the component solid-state drives 107 to 109, and the drive aggregator 103 can each be any one of the standard protocols, such as the protocol for the Serial Advanced Technology Attachment (SATA) interface, the protocol for the Peripheral Component Interconnect Express (PCIe) interface, the protocol for the Universal Serial Bus (USB) interface, the protocol for the Fibre Channel, etc.

[0063] At block 207 , the drive aggregator 103 receives a response from the solid-state drive (eg, 107 or 109 ) in response to the command to the solid-state drive (eg, 107 or 109 ).

[0064] At box 209, the drive aggregator 103 generates a response based on the response from the solid state drive (e.g., 107 or 109) and transmits the response to the host system 111, where the response to the host system is in response to a command from the host system for the operation and address specified in the command from the host system.

[0065] In some embodiments, the drive aggregator 103 performs protocol translation to account for protocol differences between the connection 135 to the host system 111 and the connection (e.g., 137) to the component solid-state drive (e.g., 109). In other embodiments, the drive aggregator 103 performs further adjustments to responses to the host system 111 to account for logical address differences between commands from the host system 111 and commands to the component solid-state drive (e.g., 109).

[0066] Figure 5 A method for distributing commands received in a virtualized solid-state drive to solid-state drives is presented. For example, Figure 5 The method can be implemented on Figure 2 The components of the configuration shown in the solid state drives 107 to 109 are Figure 1 In the virtualized solid-state drive 101. For example, Figure 5 The method can be implemented in Figure 1 、 2 and / or the drive aggregator 103 shown in 3 .

[0067] At block 241 , the drive aggregator 103 virtualizes the plurality of solid-state drives 107 to 109 into a single solid-state drive 101 connected to the host system 111 .

[0068] At block 243 , the drive aggregator 103 receives a first command from the host system 111 to create a namespace on the capacity of the virtualized solid-state drive 101 .

[0069] At block 245 , the drive aggregator 103 selects a solid-state drive (eg, 107 or 109 ) from the plurality of solid-state drives 107 to 109 for the namespace.

[0070] At block 247 , the drive aggregator 103 stores data associating the namespace with the selected solid-state drive (eg, 107 or 109 ).

[0071] At block 249 , the drive aggregator 103 transmits a first command to the selected solid-state drive (eg, 107 or 109 ) to create a namespace in the selected solid-state drive (eg, 107 or 109 ).

[0072] At block 251 , the drive aggregator 103 receives a second command from the host system 111 identifying a namespace.

[0073] At block 253 , the drive aggregator 103 transmits a second command to the selected solid-state drive (eg, 107 or 109 ) based on the association of the namespace with the selected solid-state drive.

[0074] like Figure 5 The techniques for distributing commands to the component solid-state drives 107 to 109 may simplify the translation logic 153 of the drive aggregator 103 and thus reduce the complexity, energy consumption, and cost of the translation logic 153 .

[0075] In some embodiments disclosed herein, a single solid-state drive is configured with multiple physical host interfaces that allow multiple host systems to access the memory / storage capacity of the solid-state drive. In some embodiments, the host system can use multiple parallel and / or redundant connections to the multiple physical host interfaces of the solid-state drive to improve performance and / or reliability.

[0076] Figure 6 Multiple host systems 111 - 112 are shown connected to a virtualized single solid-state drive 101 configured on a printed circuit board 131 having multiple component solid-state drives 107 - 109 .

[0077] Similar to Figure 2 The solid state drive 101 shown in FIG. Figure 6 The solid-state drive 101 shown in FIG. 1 can be constructed using a plurality of BGA SSDs (e.g., 107) as component solid-state drives 107 to 109. Each component solid-state drive (e.g., 107) has a controller (e.g., 141) that can directly serve the host system (e.g., 111) without the drive aggregator 103 when the component solid-state drive (e.g., 107) is directly connected to the host system (e.g., 111).

[0078] The drive aggregator 103 is configured to virtualize the memory / storage capacity of the set of component solid-state drives 107 - 109 into the memory / storage capacity of a single virtualized solid-state drive 101 and into a uniform memory / storage resource for the host systems 111 - 112 .

[0079] The printed circuit board 131 is configured with multiple sets of pins 133 and 134. Each set of pins (e.g., 133 or 134) is sufficient to establish a connection between the host system (e.g., 111 or 112) and the solid-state drive 101 so as to fully access the solid-state drive 101. For example, the host system (e.g., 111 or 112) can use any set of pins (e.g., 133 or 134) to transmit a command or request to the solid-state drive 101 and receive a response to the corresponding command or request.

[0080] Multiple sets of pins 133 to 134 allow Figure 6 The host systems 111-112 in FIG. 1 communicate with the solid-state drive 101 using parallel connections 135-136, respectively. For example, the host system 111 can send a command / request to the solid-state drive 101 via connection 135 and pin 133, while the host system 112 can send a similar command / request (or a different type of command / request) to the solid-state drive 101 via another connection 136 and an alternative pin 134. For example, the host system 111 can send a write command at the same time as the host system 112 sends a write command or a read command to the solid-state drive 101. Thus, the host systems 111-112 can share the memory / storage resources provided by the solid-state drive 101 as a whole.

[0081] Figure 6 The drive aggregator 103 can service commands / requests from each host system (e.g., 111 or 112) in a manner similar to Figure 2-5 Shown in and about Figure 2-5 The drive aggregator 103 is described.

[0082] In some examples, when two simultaneous commands are mapped to the same component solid-state drive (e.g., 107 or 109) for execution, Figure 6 The drive aggregator 103 may further resolve conflicts by scheduling commands for non-simultaneous execution, as discussed further below.

[0083] Figure 7 A drive aggregator 103 is shown having multiple host interfaces 151-152 according to one embodiment. For example, Figure 7 The drive aggregator 103 can be Figure 8 The solid-state drive 101 is used.

[0084] Figure 7The translation logic 153 can be based on the address mapping 159 in a similar manner to Figure 3 The translation logic 153 distributes commands received in the host interface (eg, 151 or 152 ) to the drive interfaces 155 to 157 .

[0085] Furthermore, when multiple commands are received simultaneously in multiple host interfaces 151-152, the operations of the commands may be mapped to different drive interfaces in some cases and to the same drive interface in other cases. For example, when multiple commands are configured to operate on logical addresses associated with the same drive interface 155, conflicts may occur. Such conflicts prevent the translation logic 153 from executing commands simultaneously using the drive interfaces in parallel. In this case, the translation logic 153 may use the command queue 161 to schedule the sequential execution of the commands to avoid conflicts.

[0086] When there are no conflicts, multiple commands received simultaneously in multiple host interfaces 151-152 can be executed in parallel by separate component solid-state drives (e.g., 107-109) respectively connected to drive interfaces 155-157. Such execution can, in some embodiments, be performed by generating corresponding commands for the component solid-state drives (e.g., 107-109) or by forwarding the received commands to the corresponding drive interfaces 155-157.

[0087] When a conflict exists, the translation logic 153 may use the command queue 161 to schedule sequential execution of conflicting commands received from different host interfaces 151 to 152. For example, when two commands received in the host interfaces 151 and 152 identify the same name space (or logical address region) associated with the driver interface 155 according to the address map 159, the translation logic 153 may queue one of the commands in the command queue 161 and forward the other command to the driver interface 155 (or generate and transmit a corresponding command for the operation of the other command after appropriate protocol and / or address translation). Subsequently, the translation logic 153 may retrieve the remaining command from the command queue 161 and forward it to the driver interface (or generate and transmit a corresponding command for the operation of the command retrieved from the command queue after appropriate protocol and / or address translation).

[0088] In some implementations, the translation logic 153 does not support the execution of commands received from the host interface (e.g., 151 or 152) in the order in which the commands were received from the host interface (e.g., 151 or 152). The translation logic 153 can arrange the execution order of the commands via the command queue to increase the parallel transmission of commands to the drive interfaces 155 to 157 and thus improve the overall performance of the solid-state drive 101 with the drive aggregator 103.

[0089] In some examples, two or more of host interfaces 151 - 152 may be used by the same host system to increase communication bandwidth to the drive aggregator and / or improve reliability in the connection to the drive aggregator.

[0090] Figure 8 A host system 111 is shown connected to a virtualized single solid-state drive 101 via multiple parallel and / or redundant connections 135-136. For example, Figure 8 Virtualizing a single solid-state drive 101 can be done using Figure 7 The drive aggregator 103 is similar to Figure 6 The virtualization of a single solid-state drive 101 is implemented in this manner.

[0091] exist Figure 8 In the example, a single solid-state drive 101 is virtualized with the ability to Figure 7 133 to 134 are connected to separate host system pins. Figure 8 In the example of FIG, multiple sets of pins 133-134 of the solid-state drive 101 are connected to the same host system 111 via parallel redundant connections. Thus, the host system 111 can use any one of the connections to send a specific command to the solid-state drive 101 (e.g., to write / store data in a memory cell or to read / retrieve data from a memory cell).

[0092] For example, when one of the connections (eg, 135 or 136) fails, the host system 111 can use the remaining connection (eg, 136 or 135) to access the memory / storage capacity of the solid state drive 101. Thus, the reliability of the system is improved.

[0093] Furthermore, the host system 111 can send multiple commands in parallel to the solid-state drive 101 for execution via connections 135 and 136. For example, the host system 111 can simultaneously send a read command via connection 135 while sending a write command via connection 136. For example, the host system 111 can use connection 135 for a read data stream stored in a namespace configured on component solid-state drive 107 while using connection 136 for a write data stream retrieved from another namespace configured on another component solid-state drive 109.

[0094] Figure 9 A method of processing commands received in a virtualized solid-state drive 101 via multiple host interfaces 151 to 152 is shown. For example, Figure 9 The method can be implemented in Figure 6 or 8 having components solid state drives 107 to 109 Figure 1 In the virtualized solid-state drive 101. For example, Figure 9The method can be implemented in Figure 6 、 7 and / or the drive aggregator 103 shown in 8. In addition, Figure 9 The method can be used with Figure 4 and / or a combination of the 5 methods.

[0095] At block 271 , a drive aggregator 103 having at least two host interfaces (eg, 151 and 152 ) simultaneously receives a first command in a first host interface (eg, 151 ) and a second command in a second host interface (eg, 152 ).

[0096] At box 273, the translation logic 153 of the drive aggregator 103 determines whether the first and second commands are to be executed in the same solid-state drive (e.g., 107 or 109) among the multiple solid-state drives 107 to 109 connected to the drive aggregator 103 via the drive interfaces 155 to 157 of the drive aggregator 103.

[0097] At box 275 , the determination that the first and second commands will be executed in the same solid-state drive (e.g., 107 or 109 ) leads to box 279 ; and the determination that the first and second commands will be executed in different solid-state drives (e.g., 107 and 109 ) leads to box 279 .

[0098] For example, for each corresponding command in the first and second commands received in the host interface (e.g., 151 and 152), the translation logic 153 may determine the memory unit to be operated. For example, the memory unit may be operated for reading data or for writing data according to the logical address specified in the corresponding command. When the memory unit is determined to be in a component solid-state drive (e.g., 107 or 109) connected to the drive interface (e.g., 155 or 157), the corresponding command will be executed in the component solid-state drive (e.g., 107 or 109). For example, the address map 159 may be used to identify the component solid-state drive (e.g., 107 or 109) based on the logical address of the memory unit specified in the corresponding command and / or the name space of the logical address (e.g., as described above in conjunction with Figure 4 and 5 When each command is mapped to a component solid-state drive (e.g., 107 or 109), multiple simultaneous commands may be mapped to the same component solid-state drive (e.g., 107 or 109) in some instances and not to any of the same component solid-state drives (e.g., 107 or 109) in other instances.

[0099] At block 277 , the translation logic 153 transmits commands to two of the plurality of solid-state drives 107 - 109 in parallel to perform operations of the first and second commands since the first and second commands do not operate on the same component solid-state drive (eg, 107 or 109 ).

[0100] At block 279, the translation logic 153 schedules the commands for sequential transmission to the same solid-state drive (e.g., 107 or 109) to perform the operations of the first and second commands because the first and second commands operate on the same component solid-state drive (e.g., 107 or 109). Sequential transmission resolves conflicts.

[0101] Similar to Figure 4 and 5 In the operations, commands transmitted in parallel or sequentially to the solid-state drive to perform the operations of the first and second commands may involve protocol translation and address translation.

[0102] For example, when the communication protocol on host connections 135-136 is different than the communication protocol on the drive connection (eg, 137), translation logic 153 translates from the protocol for the first and second commands to commands to drive interfaces 155-157.

[0103] For example, when the communication protocol on host connection 135 to 136 is the same as the communication protocol on the driver connection (e.g., 137) and the address mapping 159 is based on the association between the namespace and the component driver hosting the namespace above, the translation logic 153 can simply forward the first and second commands as corresponding commands to the driver interface 155 to 157.

[0104] For example, when the address mapping 159 is used to map the LBA address region in the command received in the host interface 151 to 152 to a different LBA address in the component solid-state drive 157 to 159, the translation logic 153 may replace the LBA address in the command received in the host interface 151 to 152 with the mapped LBA address calculated according to the address mapping 159 for the corresponding component solid-state drive 157 to 159.

[0105] In some embodiments disclosed herein, a virtualized single solid-state drive having multiple component solid-state drives is configured to be addressable via multiple logical address spaces. For example, the multiple logical address spaces may be used in a manner similar to multiple solid-state drives, each solid-state drive having a separate logical address space associated with the host interface of the corresponding solid-state drive. However, when multiple solid-state drives are used separately to provide separate logical address spaces, the memory / storage device resources identified using the logical address space are limited to being physically hosted within a particular solid-state drive. In contrast, when multiple solid-state drives are configured as component solid-state drives of a virtualized single solid-state drive having multiple logical address spaces, the memory / storage device resources of each logical address space may be hosted among the component solid-state drives to improve performance and / or capacity management. For example, the virtualized single solid-state drive may have a plurality of logical address spaces. Figure 6-8 . Each of the host interfaces can be configured to accept memory / storage access requests in a separate logical address space, as if the host interface were connected to a separate solid-state drive. A drive aggregator that virtualizes a single solid-state drive can use memory / storage resources in different component solid-state drives for different portions of the logical address space associated with the host interface.

[0106] Figure 10 A virtualized single solid-state drive 101 is shown configured to be accessed via separate logical address spaces 163-164 according to one embodiment.

[0107] Similar to Figure 6 or 8 virtualizing a single solid state drive 101, Figure 10 The virtualized single solid-state drive 101 has multiple sets of pins 133 to 134. Each set of pins (eg, 133 or 134) can be used to establish a connection (eg, 135 or 136) to a host system (eg, 111 or 112).

[0108] exist Figure 10 , separate logical address spaces 163 to 164 are associated with multiple groups of pins 133 to 134, respectively. For example, the same command with the same logical address can be received in a virtualized single solid-state drive 101 using separate pin groups (e.g., 133 and 134), respectively. The identification of the logical address can optionally include the use of a namespace. Because the separate pin groups (e.g., 133 and 134) are associated with different logical address spaces (e.g., 163 and 164), the same logical address in the same command can be considered as addressing the same logical address. Figure 10The drive aggregator 103 can optionally map these different memory units to the same component solid-state drive (e.g., 107 or 109), or to separate component solid-state drives (e.g., 107 and 109). Each of the logical address spaces 163-164 is not limited to being physically hosted in a specific component solid-state drive among the component solid-state drives 107-109. Each of the logical address spaces 163-164 can be physically hosted in more than one component solid-state drive among the component solid-state drives 107-109. Because the logical address spaces 163-164 are separated from each other, memory / resources accessed via one set of pins (e.g., 133) cannot be accessed via another set of pins (e.g., 134). The drive aggregator 103 can dynamically distribute the memory / storage device resources of the logical address spaces 163-164 based on the workload and / or usage pattern of the logical address spaces 163-164.

[0109] In some implementations, some or all of the different groups of pins 133-134 may be configured to be associated with the same logical address space. For example, when the array pins 133-134 are connected via parallel connections 135-136 in parallel, the array pins 133-134 may be configured to be associated with the same logical address space. Figure 8 109 , the array pins 133-134 can be configured to share the same logical address space when connected to the same host system 111 in the manner shown in FIG. Thus, the host system 111 can use any of the connections 135-136 to the pins 133-134 to access data stored in a memory cell in one of the component solid-state drives 107-109. Alternatively, the host system 111 can configure some of the array pins 133-134 to share the same logical address space while other sets of pins do not share the same logical address space.

[0110] Similarly, when array pins 133 to 134 are connected Figure 6 When connected to separate hosts 111-112 in the manner shown in FIG. 1 , some or all of the different sets of pins 133-134 may be configured to be associated with the same logical address space. Thus, some or all of the host systems 111-112 may share the same logical address space and a set of memory units associated with the logical address space.

[0111] For example, during an initialization process, the host system (e.g., 111-112) may send a command to the array pins 133-134 to indicate a sharing state of the logical address space associated with the array pins 133-134. The drive aggregator 103 is configured to implement sharing by mapping addresses of the shared logical address space to the same set of memory resources in the component solid-state drives 107-109 and mapping addresses of the non-shared logical address space to separate sets of memory resources in the component solid-state drives 107-109.

[0112] Furthermore, in some embodiments, a host system (e.g., 111-112) may issue a command requesting partial sharing of logical address spaces 163-164. For example, a logical address region (e.g., represented by a namespace) in logical address space 163 may be configured to be shared with a corresponding logical address region (e.g., represented by a corresponding namespace) in logical address space 164. Thus, either of separate connections 135 and 136 may be used to access the same data stored in the same set of memory cells assigned to the shared logical address region between logical address spaces 163 and 164. For example, data stored in the shared logical address region via connection 135 may be accessed via alternate connection 136.

[0113] However, some logical address regions may not be shared between logical address spaces 163 and 164. Thus, data stored in non-shared logical address regions may be restricted from being accessed via respective connections 135 and 136 for respective logical address spaces 163 and 164. For example, data stored in non-shared logical address regions via connection 135 is prohibited from being accessed via connection 136.

[0114] Figure 11 A drive aggregator 103 is shown configured to facilitate access to memory / storage resources in a virtualized single solid-state drive using separate logical address spaces. For example, Figure 11 The drive aggregator 103 can be Figure 10 The solid-state drive 101 is used.

[0115] Similar to Figure 7 The drive aggregator 103, Figure 11 The drive aggregator 103 has multiple host interfaces 151 - 152 for separate connections 135 - 136 to one or more host systems (eg, 111 - 112 ).

[0116] generally, Figure 11 The host interfaces 151 to 152 of the drive aggregator 103 are respectively associated with separate logical address spaces 163 to 164. Address mappings 158 to 159 are configured for the logical address spaces 163 to 164, respectively.

[0117] When logical address spaces 163-164 do not have a shared area, address maps 158-159 do not have overlapping portions. For example, address map 158 maps logical addresses in space 163 to a group of memory cells connected to drive interfaces 155-157; address map 158 maps logical addresses in space 164 to another group of memory cells connected to drive interfaces 155-157; and the different groups of memory cells identified in address maps 158 and 159 do not have common memory cells.

[0118] When some logical address spaces 163-164 are partially shared (e.g., in response to a configuration command received from a host system), address maps 158-159 have overlapping portions. For example, address map 158 maps a portion of the logical addresses in space 163 to a group of memory cells connected to drive interfaces 155-157; address map 158 maps a portion of the logical addresses in space 164 to another group of memory cells connected to drive interfaces 155-157. When the portion of the logical addresses in space 163 and the portion of the logical addresses in space 164 are configured to be shared across logical address spaces 163 and 164, address map 158 maps the portion of the logical addresses in space 163 to the same group of memory cells to which address map 159 mapped the portion of the logical addresses in space 164. However, when the portion of the logical address in space 163 and the portion of the logical address in space 164 are configured not to be shared across logical address spaces 163 and 164, the group of memory cells to which the portion of the logical address in space 163 is mapped by address mapping 158 does not share any memory cells in the group of memory cells to which the portion of the logical address in space 164 is mapped by address mapping 159.

[0119] Similarly, the drive aggregator 103 can configure address mappings 158-159 to allow some or all of the host interfaces 151-152 to share the same logical address space. The sharing can be implemented by the address mappings 158-159 of the respective host interfaces being mapped to the same set of memory cells connected to the drive interfaces 155-157. In some examples, sharing can be implemented by sharing the address mappings of some or all of the host interfaces 151-152.

[0120] Figure 12-14 An example of address mapping is shown. For example, Figure 12-14 The address map 154 ​​shown in FIG can be Figure 11 is used in the drive aggregator 103.

[0121] exist Figure 12In the present invention, namespaces 181 and 182 created by commands received via separate host interfaces 151 and 152 are considered to be different namespaces. When namespaces 181 and 182 have the same identification in commands received via separate host interfaces 151 and 152, the namespaces 181 and 182 of host interfaces 151 and 152 are mapped to different drive interfaces 155 and 157. Therefore, commands using the same namespace identification but different host interfaces are addressed to different component solid-state drives (e.g., 107 and 109); and data stored in a command issued via one host interface (e.g., 151) using the namespace identification cannot be accessed by a command issued via another host interface (e.g., 152).

[0122] Alternatively, the same identifications of namespaces 181 and 183 of host interfaces 151 and 152 may be mapped to different namespace identifications using address mapping 154. Different namespace identifications may be used to create corresponding namespaces in the same component solid-state drive (e.g., 107) connected to the same drive interface (e.g., 155) or in different component solid-state drives (e.g., 107 and 109) connected to different drive interfaces (e.g., 155 and 157).

[0123] Figure 13 FIG2 shows a configuration in which a namespace 181 is shared between two host interfaces 151 and 152. Namespace 181 is mapped to driver interface 155. Figure 13 The address map 154 ​​identifies the namespace and commands received in the host interface 151 or in the host interface 152 can be forwarded to the drive interface 155 to access the same group of memory cells. For example, the host connection 135 can be used to store data in the namespace 181 hosted in the component solid-state drive (e.g., 107) connected to the drive interface 155; and another host connection 136 can be used to retrieve data from the namespace 181 hosted in the same component solid-state drive (e.g., 107) connected to the same drive interface 155.

[0124] In general, multiple namespaces may be mapped to driver interface 155. Some namespaces mapped to driver interface 155 may be shared across multiple host interfaces (e.g., 151 and 152), while other namespaces mapped to driver interface 155 may not be shared between host interfaces.

[0125] Figure 14 A configuration is shown in which namespaces 181 and 183 created via host interface 151 are hosted on different component solid-state drives (eg, 107 and 109 ) connected to different drive interfaces 155 and 157 .

[0126] Generally speaking, some namespaces 181 and 183 created via host interface 151 can be shared across multiple host interfaces; and some namespaces 181 and 183 created via host interface 151 cannot be shared with any other host interface. Figure 12-14 various combinations and alternatives.

[0127] Figure 15 A method of accessing memory / storage resources in a virtualized single solid-state drive using separate logical address spaces is presented. For example, Figure 15 The method can be implemented on Figure 2 、 6 , 8 or 10 of the components of the solid state drive 107 to 109 in the configuration shown Figure 1 In the virtualized solid-state drive 101. For example, Figure 15 The method can be implemented on Figure 11 、 12 , 13 and / or 14 shown in the address mapping Figure 6-8 , 10 and / or 11 shown in the drive aggregator 103. In addition, Figure 15 The method can be used with Figure 4 、 5 , and / or methods in 9 are used in combination.

[0128] At block 281 , the drive aggregator 103 is configured to associate its multiple host interfaces 151 - 152 with different logical address spaces 163 - 164 .

[0129] At block 283 , the drive aggregator 103 maps the different logical address spaces 163 - 164 to the aggregate capacity of the plurality of component solid state drives 107 - 109 connected to the drive aggregator 103 in the virtualized signal solid state drive 101 .

[0130] At block 285 , the drive aggregator 103 simultaneously receives a first command from the parallel connections 135 - 136 to one or more host systems (eg, 111 and / or 112 ) via the plurality of host interfaces 151 - 152 .

[0131] At block 287 , the drive aggregator 103 interprets the first command received from the host interfaces 151 - 152 in the different logical address spaces 163 - 164 .

[0132] For example, the drive aggregator 103 may be configured with separate address mappings 158 to 159 that are respectively associated with the multiple host interfaces 151 to 152 to translate logical addresses identified in commands received from the host interfaces 151 to 152 into logical addresses in commands transmitted from the drive aggregator 103 to the multiple component solid-state drives 107 to 109.

[0133] At block 289 , the drive aggregator 103 transmits a second command to the plurality of component solid-state drives 107 - 109 based on interpreting the first command in the different logical address spaces 163 - 164 .

[0134] For example, the plurality of host interfaces 151-152 may include a first host interface 151 and a second host interface 152, wherein the first host interface 151 and the second host interface 152 are associated with the same logical address space that is separate and distinct from at least one other logical address space associated with a third interface of the plurality of host interfaces 151-152. Thus, data stored by a command transmitted via the first interface is not addressable by a command transmitted via the third interface, but is addressable by a command transmitted via the second interface.

[0135] For example, the plurality of host interfaces 151-152 may include a first host interface 151 associated with a first logical address space and a second host interface 152 associated with a second logical address space; the address map 158 maps the first logical address space to a first portion of the aggregate capacity of the plurality of component solid-state drives 107-109; and the address map 159 maps the second logical address space to a second portion of the aggregate capacity of the plurality of component solid-state drives 107-109. The first portion of the aggregate capacity and the second portion of the aggregate capacity may be partially completely separate from each other or configured to partially overlap with each other.

[0136] When the first portion of the aggregate capacity and the second portion of the aggregate capacity are partially configured to partially overlap with each other, the first portion of the data stored by the command transmitted via the first host interface 151 is not addressable by the command transmitted via the second host interface 152; and the second portion of the data stored by the command transmitted via the first host interface 151 is addressable by the command transmitted via the second host interface 152.

[0137] For example, namespace 181 associated with first host interface 151 and namespace 183 associated with second host interface 152 may be mapped to separate non-overlapping portions of the aggregate capacity of component solid-state drives 107-109, or to overlapping portions of a first portion of the aggregate capacity and a second portion of the aggregate capacity.

[0138] Above (for example, in conjunction with Figure 4 、 5 , 9 and / or 15) can be performed by processing logic, which can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, Figure 4 、5 , 9 and / or 15 are at least partially Figure 1 、 2 , 3, 6, 7, 8, 10, or 11 is executed by the drive aggregator 103. Although shown in a particular sequence or order, the order of operations may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated operations may be performed in a different order, and some operations may be performed in parallel. In addition, one or more operations may be omitted in various embodiments. Therefore, not all operations are required in every embodiment. Other operational flows are possible.

[0139] In some embodiments, the communication channel between the host system 111 and the memory subsystem (e.g., solid-state drive 101) includes a computer network, such as a local area network, a wireless local area network, a wireless personal area network, a cellular communication network, a broadband high-speed always-on wireless communication connection (e.g., a current or future generation mobile network link); and the host system 111 and the memory subsystem can be configured to communicate with each other using data storage management and usage commands similar to those in the NVMe protocol.

[0140] Some embodiments involving the operation of the drive aggregator 103 may be implemented using computer instructions executed by one or more microprocessors. The computer instructions may be configured as firmware for the solid-state drive 101. In some examples, hardware circuitry may be used to implement at least some of the functionality. The firmware may be initially stored in a non-volatile storage medium or another non-volatile device and loaded into volatile DRAM and / or in-processor cache for execution by the drive aggregator's microprocessor.

[0141] Non-transitory computer storage media may be used to store instructions for firmware of a memory subsystem (eg, solid-state drive 101, or any of component solid-state drives 107 to 109). When executed by a microprocessor, the instructions cause the memory subsystem to perform the methods discussed above.

[0142] Generally speaking, an example machine of a computer system may have an instruction set for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, this computer system may correspond to a host system (e.g., Figure 1 1 ), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 solid-state drive 101), or may be used to perform operations of the drive aggregator 103 (e.g., execute instructions to perform operations corresponding to the reference Figure 1-15In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in a client-server network environment, or in the capacity of a server or a client user machine in a peer-to-peer (or distributed) network environment.

[0143] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is shown, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0144] An example machine may include a processing device, a main memory (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static random access memory (SRAM), etc.), and a data storage system, which communicate with each other via a bus (which may include multiple buses).

[0145] The processing devices discussed herein may include one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, the processing devices may be complex instruction set computing (CISC) microprocessors, reduced instruction set computing (RISC) microprocessors, very long instruction word (VLIW) microprocessors, or processors that implement other instruction sets, or processors that implement a combination of instruction sets. The processing devices discussed herein may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, and the like. The processing devices are typically configured to execute instructions for performing the operations and steps discussed herein. The example machine may further include a network interface device for communicating via a computer network.

[0146] The data storage system disclosed herein may include a machine-readable storage medium (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions or software embodying any one or more of the methods or functions described herein. The instructions may also reside, completely or at least partially, in a main memory and / or a processing device during execution by the computer system, with the main memory and processing device also constituting the machine-readable storage medium. The machine-readable storage medium, the data storage system, and / or the main memory may correspond to a memory subsystem.

[0147] In one embodiment, the instructions stored in the example machine include instructions to implement functionality corresponding to the driver aggregator 103 (e.g., as described in reference to Figure 1-15 (described herein). Although a machine-readable storage medium may be discussed as a single medium in one embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include (but not be limited to) solid-state memories, optical media, and magnetic media.

[0148] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally considered to be a self-consistent sequence of operations leading to a desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. At times, primarily for common usage reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0149] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0150] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0151] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the description below. Furthermore, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0152] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0153] In this specification, various functions and operations are described as being performed by or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that the intention of such expressions is that the functions are derived from the execution of computer instructions by one or more controllers or processors (e.g., microprocessors). Alternatively or in combination, the functions and operations may be implemented using dedicated circuitry with or without software instructions, such as using an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Embodiments may be implemented using hardwired circuitry without software instructions or in combination with software instructions. Therefore, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source of instructions executed by the data processing system.

[0154] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A solid-state drive comprising: a drive aggregator having multiple host interfaces; as well as a plurality of component solid-state drives connected to the drive aggregator, each of the component solid-state drives having a controller capable of processing commands from a host system; wherein the drive aggregator is configured to associate the host interface with a different logical address space, interpret commands received from the host interface in the different logical address space, and implement the commands using the plurality of component solid-state drives, and wherein the drive aggregator is configured with separate address mappings respectively associated with the plurality of host interfaces to translate from logical addresses identified in the commands received from the host interfaces to logical addresses in commands transmitted from the drive aggregator to the plurality of component solid-state drives. 2 . The solid-state drive of claim 1 , wherein data stored by a command transmitted via a first interface among the plurality of host interfaces is not addressable by a command transmitted via a second interface among the plurality of host interfaces.

3. The solid-state drive of claim 1 , wherein data stored by a command transmitted via a first interface among the plurality of host interfaces is not addressable by a command transmitted via a second interface among the plurality of host interfaces, but is addressable by a command transmitted via a third interface among the plurality of host interfaces.

4. The solid-state drive of claim 1 , wherein a first portion of data stored by a command transmitted via a first interface among the plurality of host interfaces is not addressable by a command transmitted via a second interface among the plurality of host interfaces; and a second portion of data stored by a command transmitted via the first interface is addressable by a command transmitted via the second interface.

5. The solid-state drive according to claim 1 , further comprising: a printed circuit board having a plurality of sets of pins, each set of pins configured for connection to a host system via a computer bus; The drive aggregator and the plurality of component solid-state drives are mounted on the printed circuit board. 6 . The solid-state drive of claim 5 , wherein each of the component solid-state drives is integrated within an integrated circuit package having a ball grid array (BGA) form factor.

7. The solid-state drive of claim 6, wherein the drive aggregator further comprises: a plurality of drive interfaces configured to communicate with the plurality of component solid-state drives, respectively; as well as Translation logic is coupled between the host interface and the plurality of drive interfaces to generate commands to the component solid-state drives based on the address mapping.

8. The solid-state drive of claim 7 , wherein the host interface is configured according to a first communication protocol between a host system and the solid-state drive; the plurality of drive interfaces are configured according to a second communication protocol between the host system and the solid-state drive; and each of the first communication protocol and the second communication protocol is one of: Protocol for the Serial Advanced Technology Attachment (SATA) interface; A protocol for the Peripheral Component Interconnect Express (PCIe) interface. Protocol for Universal Serial Bus USB interface; as well as The protocol used for Fibre Channel.

9. A method implemented in a drive aggregator, comprising: Associating, by the drive aggregator having a plurality of host interfaces, the host interfaces with different logical address spaces; mapping, by the drive aggregator, the different logical address spaces to an aggregate capacity of a plurality of component solid-state drives connected to the drive aggregator; concurrently receiving, in the drive aggregator, via the plurality of host interfaces, a first command from parallel connections to one or more host systems; interpreting, by the drive aggregator, the first command received from the host interface in the different logical address space; as well as transmitting a second command from the drive aggregator to the plurality of component solid-state drives based on interpreting the first command in the different logical address space, wherein the plurality of host interfaces include a first host interface associated with a first logical address space and a second host interface associated with a second logical address space; the first logical address space is mapped to a first portion of the aggregate capacity of the plurality of component solid-state drives; and the second logical address space is mapped to a second portion of the aggregate capacity of the plurality of component solid-state drives.

10. The method of claim 9, wherein the first portion of the aggregate capacity and the second portion of the aggregate capacity partially overlap each other.

11. The method of claim 10, wherein a namespace associated with the first host interface and a namespace associated with the second host interface are mapped to an overlapping portion of the first portion of the aggregate capacity and the second portion of the aggregate capacity.

12. A drive aggregator comprising: a plurality of host interfaces, each configured to communicate with a host system; a plurality of drive interfaces that respectively communicate with the plurality of component solid-state drives; as well as translation logic coupled between the host interface and the plurality of drive interfaces, wherein the translation logic is configured to interpret addresses in commands received in the plurality of host interfaces in different logical address spaces, wherein subsets of the different logical address spaces have overlapping regions that map to the same group of memory cells in the plurality of component solid-state drives; and the memory cells are addressable using commands transmitted to a host interface associated with the subsets of the different logical address spaces.

13. The drive aggregator of claim 12, further comprising: an integrated circuit package, wherein the plurality of host interfaces, the translation logic, and the plurality of driver interfaces are packaged in the integrated circuit package; The translation logic includes a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

14. The drive aggregator of claim 13 , wherein each of the host interfaces is configured to implement a point-to-point serial connection between a host system and a solid-state drive; and each of the plurality of drive interfaces is configured to implement a point-to-point serial connection between a host system and a solid-state drive.

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