A multi-input pulse modulator circuit

Abstract

The present invention proposes a multi-input pulse modulator circuit, which includes: an internal power supply circuit, which constitutes a linear voltage regulator circuit as a whole and provides voltage for chip operation; a signal selection circuit, which is electrically connected to the internal power supply circuit; a monostable circuit, which is electrically connected to the signal selection circuit and can adjust the output pulse width of the monostable trigger chip and the delayed output time when the signal is turned off; a pulse amplification circuit, which is electrically connected to the internal power supply circuit and the pulse amplification circuit is electrically connected to the signal selection circuit. In order to improve the amplitude and driving capability of the pulse output signal, the output signal with a fixed pulse width can be amplified, and functions such as the pulse voltage width following the input signal and the pulse voltage width being fixed can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply circuits, and in particular to a multi-channel input pulse modulator circuit. Background Art

[0002] Traditional pulse modulators typically operate with a single input signal, producing a single pulse output whose output pulse width follows the input signal. These modulators typically amplify the power of a single input control signal. However, multi-input pulse control is often used in T / R components of airborne and missile-borne systems. This allows for real-time switching of input pulses based on actual application conditions and selection of pulse widths as required. Traditional single-input pulse modulators are unable to display this function. Summary of the Invention

[0003] In order to solve the above problems, the present invention proposes a multi-input pulse modulator circuit.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention provides a multi-channel input pulse modulator circuit, the multi-channel input pulse modulator circuit comprising:

[0006] The internal power supply circuit constitutes a linear voltage regulator circuit as a whole, providing the voltage for the chip to work;

[0007] a signal gating circuit, the signal gating circuit being electrically connected to the internal power supply circuit;

[0008] a monostable circuit, the monostable circuit being electrically connected to the signal gating circuit, the monostable circuit being capable of adjusting both the output pulse width of the monostable trigger chip and the delayed output time when the signal is turned off;

[0009] A pulse amplification circuit is electrically connected to the internal power supply circuit and the signal selection circuit. In order to improve the amplitude and driving capability of the pulse output signal, the output signal of the fixed pulse width can be amplified.

[0010] Furthermore, the internal power supply circuit includes a capacitor C4, a capacitor C12, a resistor R3 and a MOS transistor Q1, wherein the C pin of the MOS transistor Q1 is electrically connected to the resistor R3, the B pin of the MOS transistor Q1 is electrically connected to the capacitor C12, and the E pin of the MOS transistor Q1 is electrically connected to the capacitor C4.

[0011] Furthermore, the internal power supply circuit includes a capacitor C11, a resistor R4, a diode D2 and a diode D5, one end of the capacitor C11 is electrically connected to the resistor R4, the other end of the capacitor C11 is electrically connected to the diode D5, one end of the resistor R4 is electrically connected to the resistor R3, and the other end of the resistor R4 is electrically connected to the diode D2.

[0012] Furthermore, the signal selection circuit includes a chip U3-B, a gate U1-A, a gate U1-B and a gate U1-C, pin 12 of the chip U3-B is electrically connected to pin 10 of the gate U1-A, pin 5 of the chip U3-B is electrically connected to pin 1 of the gate U1-B, pin 9 of the chip U3-B is grounded, and pin 10 of the chip U3-B is electrically connected to pins 2 and 13 of the gate U1-B.

[0013] Furthermore, pin 11 of the gate U1-A is electrically connected to pin 13 of the gate U1-B, pin 8 of the gate U1-A is electrically connected to pin 5 of the gate U1-C, and pin 12 of the gate U1-B is electrically connected to pins 3 and 4 of the gate U1-C.

[0014] Furthermore, the signal selection circuit includes capacitor C7, capacitor C9, resistor R20 and resistor R21, one end of the capacitor C7 is electrically connected to pin 6 of the chip U3-B, and the other end of the capacitor C7 is electrically connected to pin 7 of the chip U3-B, one end of the resistor R20 is electrically connected to the capacitor C7, and the other end of the resistor R20 is electrically connected to pin 9 of the chip U3-B, one end of the resistor R21 is electrically connected to the capacitor C7, and the other end of the resistor R21 is electrically connected to pin 14 of the selector U1-A.

[0015] Furthermore, the signal selection circuit includes a gate U2-A, a gate U2-B, a gate U2-C and a gate U2-D, pin 1 of the gate U2-A is electrically connected to pin 6 of the gate U2-B, pin 3 of the gate U2-A is electrically connected to the TTL pin, pins 4 and 5 of the gate U2-B are electrically connected, pins 12 and 13 of the gate U2-D are electrically connected, and pin 11 of the gate U2-D is electrically connected to pin 11 of the gate U1-A.

[0016] Furthermore, the signal selection circuit includes a chip U3-A, a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a capacitor C5, pin 1 of the chip U3-A is electrically connected to the resistor R14, pin 2 of the chip U3-A is electrically connected to pin 6 of the selector U1-C, pin 3 of the chip U3-A is electrically connected to the resistor R13, pin 4 of the chip U3-A is electrically connected to pin 2 of the selector U2-A, pin 8 of the chip U3-A is grounded, one end of the capacitor C5 is electrically connected to pin 14 of the chip U3-A, the other end of the capacitor C5 is electrically connected to pin 15 of the chip U3-A, and pin 16 of the chip U3-A is electrically connected to the resistor R12.

[0017] Furthermore, the pulse amplification circuit includes a chip U11, a capacitor C18 and a capacitor C19, pin 3 of the chip U11 is grounded, pin 5 of the chip U11 is electrically connected to the capacitor C19, one end of the capacitor C18 is electrically connected to pin 2 of the chip U11, and the other end of the capacitor C18 is electrically connected to pin 4 of the chip U11.

[0018] Furthermore, the pulse amplification circuit includes a chip U10, a MOS tube Q2, a capacitor C15 and a diode D7. Pin 4 of the chip U10 is electrically connected to pin 8 of the chip U11, pin 5 of the chip U10 is electrically connected to pin 3 of the selector U2-A, pin 6 of the chip U10 is electrically connected to pin 5 of the chip U11, one end of the diode D7 is electrically connected to pin 10 of the chip U10, and the other end of the diode is electrically connected to the MOS tube Q2. One end of the capacitor C15 is electrically connected to pin 9 of the chip U10, and the other end of the capacitor C15 is electrically connected to pin 11 of the chip U10.

[0019] Beneficial effects of the present invention:

[0020] The multi-input pulse modulator circuit proposed in this invention consists of four main components: an internal power supply circuit, a signal selection circuit, a monostable circuit, and a pulse amplifier circuit. This modulator circuit provides a single pulse voltage output. By prioritizing the three input signals, it can achieve functions such as pulse voltage width tracking the input signal and fixed pulse voltage width. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1. It is an internal power supply circuit diagram of the multi-input pulse modulator circuit of the present invention;

[0022] Figure 2 A monostable and signal gating circuit diagram of a multi-input pulse modulator circuit of the present invention;

[0023] Figure 3A pulse amplification circuit diagram of a multi-input pulse modulator circuit of the present invention;

[0024] Figure 4 It is a module diagram of the multi-input pulse modulator circuit of the present invention. DETAILED DESCRIPTION

[0025] In order to more clearly and completely illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings.

[0026] Please refer to Figures 1 to 4 , the present invention is achieved through the following technical solutions:

[0027] The present invention provides a multi-channel input pulse modulator circuit, the multi-channel input pulse modulator circuit comprising:

[0028] The internal power supply circuit constitutes a linear voltage regulator circuit as a whole, providing the voltage for the chip to work;

[0029] a signal gating circuit, the signal gating circuit being electrically connected to the internal power supply circuit;

[0030] a monostable circuit, the monostable circuit being electrically connected to the signal gating circuit, the monostable circuit being capable of adjusting both the output pulse width of the monostable trigger chip and the delayed output time when the signal is turned off;

[0031] A pulse amplification circuit is electrically connected to the internal power supply circuit and the signal selection circuit. In order to improve the amplitude and driving capability of the pulse output signal, the output signal of the fixed pulse width can be amplified.

[0032] In this embodiment, 1. when there is a signal at the first input terminal, the output is a synchronous signal with a pulse voltage width of 500ns (the output frequency is the same as the input signal frequency and the pulse width is fixed);

[0033] 2. When there is a signal at the second input terminal, the output is a synchronous signal with a pulse voltage width of 500ns (the output frequency is the same as the input signal frequency and the pulse width is fixed);

[0034] 3. When there are signals at both the first and second input terminals, the output is a synchronous signal with a pulse width of 500ns (the output frequency follows the frequency of the second input signal and the pulse width is fixed); if the second input terminal signal is removed at this time, the pulse signal will continue to be output after a delay of approximately 200μs;

[0035] 4. When there is a signal at the third input terminal, the width of the output pulse voltage follows the third input signal and has the same frequency.

[0036] Furthermore, the internal power supply circuit includes a capacitor C4, a capacitor C12, a resistor R3, and a MOS transistor Q1, wherein the C pin of the MOS transistor Q1 is electrically connected to the resistor R3, the B pin of the MOS transistor Q1 is electrically connected to the capacitor C12, and the E pin of the MOS transistor Q1 is electrically connected to the capacitor C4; the internal power supply circuit includes a capacitor C11, a resistor R4, a diode D2, and a diode D5, wherein one end of the capacitor C11 is electrically connected to the resistor R4, and the other end of the capacitor C11 is electrically connected to the diode D5, one end of the resistor R4 is electrically connected to the resistor R3, and the other end of the resistor R4 is electrically connected to the diode D2.

[0037] In this embodiment, the internal power supply circuit is composed of capacitor C4, capacitor C11, capacitor C12, resistor R3, resistor R4, diode D2, diode D5 and MOS transistor Q1. Resistor R3 is a current limiting resistor, diode D2 is a Schottky diode, diode D5 is a voltage regulator diode, and MOS transistor Q1 is an NPN transistor. The whole constitutes a linear voltage regulator circuit. By selecting a suitable value of D5, a voltage that can be used for chip operation is obtained.

[0038] Furthermore, the signal gating circuit includes a chip U3-B, a gate U1-A, a gate U1-B and a gate U1-C, wherein the 12th pin of the chip U3-B is electrically connected to the 10th pin of the gate U1-A, the 5th pin of the chip U3-B is electrically connected to the 1st pin of the gate U1-B, the 9th pin of the chip U3-B is grounded, the 10th pin of the chip U3-B is electrically connected to the 2nd and 13th pins of the gate U1-B; the 11th pin of the gate U1-A is electrically connected to the 13th pin of the gate U1-B, the 8th pin of the gate U1-A is electrically connected to the gate U1-C The 5th pin of the gate U1-B is electrically connected to the 3rd and 4th pins of the gate U1-C; the signal gating circuit includes a capacitor C7, a capacitor C9, a resistor R20 and a resistor R21, one end of the capacitor C7 is electrically connected to the 6th pin of the chip U3-B, the other end of the capacitor C7 is electrically connected to the 7th pin of the chip U3-B, one end of the resistor R20 is electrically connected to the capacitor C7, the other end of the resistor R20 is electrically connected to the 9th pin of the chip U3-B, one end of the resistor R21 is electrically connected to the capacitor C7, and the other end of the resistor R21 is electrically connected to the gate U1 -A's 14th pin is electrically connected; the signal gating circuit includes a gate U2-A, a gate U2-B, a gate U2-C and a gate U2-D, the 1st pin of the gate U2-A is electrically connected to the 6th pin of the gate U2-B, the 3rd pin of the gate U2-A is electrically connected to the TTL pin, the 4th pin and the 5th pin of the gate U2-B are electrically connected, the 12th pin and the 13th pin of the gate U2-D are electrically connected, and the 11th pin of the gate U2-D is electrically connected to the 11th pin of the gate U1-A; the signal gating circuit includes a chip U3-A, a resistor R11, a resistor R12, a resistor R13, resistor R14 and capacitor C5, pin 1 of the chip U3-A is electrically connected to the resistor R14, pin 2 of the chip U3-A is electrically connected to pin 6 of the selector U1-C, pin 3 of the chip U3-A is electrically connected to the resistor R13, pin 4 of the chip U3-A is electrically connected to pin 2 of the selector U2-A, pin 8 of the chip U3-A is grounded, one end of the capacitor C5 is electrically connected to pin 14 of the chip U3-A, the other end of the capacitor C5 is electrically connected to pin 15 of the chip U3-A, and pin 16 of the chip U3-A is electrically connected to the resistor R12.

[0039] In this embodiment, the signal gating circuit consists of two parts: gate 1 and gate 2. Gate U1 is a 54HC10 chip, divided into gate U1-A, gate U1-B, and gate U1-C. This chip is a three-input NAND gate (gate 1). Gate U2 is a 54HC00 chip, divided into gate U2-A, gate U2-B, gate U2-C, and gate U2-D. This chip is a two-input NAND gate (gate 2).

[0040] When only Vin1 signal is input, the other two input signals of the three-input NAND gate connected to the Vin1 input terminal are both high level. The output signal of the NAND gate is processed by the monostable circuit and output as a signal with fixed pulse width. After passing through the gate 2, the output signal with fixed pulse width (TTL) can be obtained, and its frequency changes with Vin1.

[0041] When only Vin2 signal is input, the other two input terminals of the corresponding three-input NAND gate are both high level. The output signal of the NAND gate is processed by the monostable circuit to obtain an output signal with a fixed pulse width. After passing through gate 2, the output signal with a fixed pulse width (TTL) can be obtained, and its frequency changes with Vin2.

[0042] When only the Vin3 signal is input, the three-input NAND gates (selector 2) corresponding to Vin1 and Vin2 both output high-level signals. The two high-level signals are then selected by the NAND gate to obtain low-level signals, that is, the 2-pin input of the monostable U3-A is a low-level signal. Combined with the truth table function of the monostable circuit, it can be seen that the 4-pin of the monostable U3-A is a high-level signal, and the pulse output TTL signal follows the Vin3 signal.

[0043] Furthermore, the pulse amplification circuit includes a chip U11, a capacitor C18 and a capacitor C19, the 3rd pin of the chip U11 is grounded, the 5th pin of the chip U11 is electrically connected to the capacitor C19, one end of the capacitor C18 is electrically connected to the 2nd pin of the chip U11, and the other end of the capacitor C18 is electrically connected to the 4th pin of the chip U11; the pulse amplification circuit includes a chip U10, a MOS tube Q2, a capacitor C15 and a diode D7, the 4th pin of the chip U10 is electrically connected to the 5th pin of the chip U11. It is electrically connected to pin 8 of the chip U11, pin 5 of the chip U10 is electrically connected to pin 3 of the selector U2-A, pin 6 of the chip U10 is electrically connected to pin 5 of the chip U11, one end of the diode D7 is electrically connected to pin 10 of the chip U10, and the other end of the diode is electrically connected to the MOS tube Q2, one end of the capacitor C15 is electrically connected to pin 9 of the chip U10, and the other end of the capacitor C15 is electrically connected to pin 11 of the chip U10.

[0044] In this embodiment, after the input signal is processed by the logic gate and the monostable circuit, the resulting TTL pulse signal has a small driving capability and a low amplitude. In order to increase the amplitude and driving capability of the pulse output signal, the TTL signal can be amplified.

[0045] The circuit primarily consists of chip U10, chip U11, diodes D6 and D7, MOS transistor Q2, capacitors C13 to C17, and resistors R5 to R8. Chip U10 is ZHM6901BN, and chip U11 is ER7660. The circuit formed by chip U11, capacitors C18, and capacitor C19 converts the polarity of the AVCC voltage level to generate the enable signal EN for control chip U10. Chip U10 is a high-end MOS driver that processes the TTL signal and then drives MOS transistor Q2 on and off, generating the circuit's final output pulse signal.

[0046] Of course, the present invention may have many other implementations. Based on this implementation, other implementations obtained by ordinary technicians in this field without any creative work are all within the scope of protection of the present invention.

Claims

1. A multi-input pulse modulator circuit, characterized in that: The multi-channel input pulse modulator circuit comprises: The internal power supply circuit constitutes a linear voltage regulator circuit as a whole, providing the voltage for the chip to work; a signal gating circuit, the signal gating circuit being electrically connected to the internal power supply circuit; a monostable circuit, the monostable circuit being electrically connected to the signal gating circuit, the monostable circuit being capable of adjusting both the output pulse width of the monostable trigger chip and the delayed output time when the signal is turned off; a pulse amplifying circuit, the pulse amplifying circuit being electrically connected to the internal power supply circuit and the signal gating circuit, and being designed to amplify an output signal of a fixed pulse width in order to increase the amplitude and driving capability of the pulse output signal; The signal gating circuit includes a chip U3-B, a gate U1-A, a gate U1-B and a gate U1-C, wherein pin 12 of the chip U3-B is electrically connected to pin 10 of the gate U1-A, pin 5 of the chip U3-B is electrically connected to pin 1 of the gate U1-B, pin 9 of the chip U3-B is grounded, and pin 10 of the chip U3-B is electrically connected to pins 2 and 13 of the gate U1-B; The signal gating circuit includes a capacitor C7, a capacitor C9, a resistor R20, and a resistor R21. One end of the capacitor C7 is electrically connected to pin 6 of the chip U3-B, and the other end of the capacitor C7 is electrically connected to pin 7 of the chip U3-B. One end of the resistor R20 is electrically connected to the capacitor C7, and the other end of the resistor R20 is electrically connected to pin 9 of the chip U3-B. One end of the resistor R21 is electrically connected to the capacitor C7, and the other end of the resistor R21 is electrically connected to pin 14 of the gate U1-A. The signal selection circuit includes a chip U3-A, a resistor R11, a resistor R12, a resistor R13, a resistor R14 and a capacitor C5, pin 1 of the chip U3-A is electrically connected to the resistor R14, pin 2 of the chip U3-A is electrically connected to pin 6 of the selector U1-C, pin 3 of the chip U3-A is electrically connected to the resistor R13, pin 4 of the chip U3-A is electrically connected to pin 2 of the selector U2-A, pin 8 of the chip U3-A is grounded, one end of the capacitor C5 is electrically connected to pin 14 of the chip U3-A, the other end of the capacitor C5 is electrically connected to pin 15 of the chip U3-A, and pin 16 of the chip U3-A is electrically connected to the resistor R12; The signal selection circuit includes a gate U2-A, a gate U2-B, a gate U2-C and a gate U2-D. Pin 1 of the gate U2-A is electrically connected to pin 6 of the gate U2-B, pin 3 of the gate U2-A is electrically connected to the TTL pin of the pulse amplifier circuit, pins 4 and 5 of the gate U2-B are electrically connected, pins 12 and 13 of the gate U2-D are electrically connected, and pin 11 of the gate U2-D is electrically connected to pin 11 of the gate U1-A.

2. The multi-input pulse modulator circuit according to claim 1, characterized in that: The internal power supply circuit includes a capacitor C4, a capacitor C12, a resistor R3 and a MOS transistor Q1. The C pin of the MOS transistor Q1 is electrically connected to the resistor R3, the B pin of the MOS transistor Q1 is electrically connected to the capacitor C12, and the E pin of the MOS transistor Q1 is electrically connected to the capacitor C4.

3. The multi-input pulse modulator circuit according to claim 2, characterized in that: The internal power supply circuit includes a capacitor C11, a resistor R4, a diode D2 and a diode D5. One end of the capacitor C11 is electrically connected to the resistor R4, and the other end of the capacitor C11 is electrically connected to the diode D5. One end of the resistor R4 is electrically connected to the resistor R3, and the other end of the resistor R4 is electrically connected to the diode D2.

4. The multi-input pulse modulator circuit according to claim 1, wherein: Pin 11 of the gate U1-A is electrically connected to pin 13 of the gate U1-B, pin 8 of the gate U1-A is electrically connected to pin 5 of the gate U1-C, and pin 12 of the gate U1-B is electrically connected to pins 3 and 4 of the gate U1-C.

5. The multi-input pulse modulator circuit according to claim 1, wherein: The pulse amplification circuit includes a chip U11, a capacitor C18 and a capacitor C19. Pin 3 of the chip U11 is grounded, pin 5 of the chip U11 is electrically connected to the capacitor C19, one end of the capacitor C18 is electrically connected to pin 2 of the chip U11, and the other end of the capacitor C18 is electrically connected to pin 4 of the chip U11.

6. The multi-input pulse modulator circuit according to claim 5, characterized in that: The pulse amplification circuit includes a chip U10, a MOS tube Q2, a capacitor C15 and a diode D7. Pin 4 of the chip U10 is electrically connected to pin 8 of the chip U11, pin 5 of the chip U10 is electrically connected to pin 3 of the selector U2-A, pin 6 of the chip U10 is electrically connected to pin 5 of the chip U11, one end of the diode D7 is electrically connected to pin 10 of the chip U10, and the other end of the diode is electrically connected to the MOS tube Q2. One end of the capacitor C15 is electrically connected to pin 9 of the chip U10, and the other end of the capacitor C15 is electrically connected to pin 11 of the chip U10.

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