Sensor panel and display device including the same

Abstract

A sensor panel comprises: a substrate; a sensing portion located on the substrate, the sensing portion comprising a plurality of sensors; and a partition wall located between adjacent sensors, wherein each sensor comprises a first sensor electrode, a piezoelectric layer and a second sensor electrode, and the partition wall has a lower dielectric constant than the piezoelectric layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0076761, filed on Jun. 27, 2019, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a sensor panel having excellent security and a high recognition rate and a display device including the sensor panel. Background Art

[0003] As the information age matures, there is growing interest in information displays that process and display massive amounts of information. In response to this, various display devices having advantages of thin thickness, light weight, and low power consumption have been developed and have received attention.

[0004] Display devices are widely used in electronic devices such as monitors of computers or televisions and portable electronic devices such as smart phones or tablet computers to provide various types of information in various ways.

[0005] Incidentally, since information provided through a display device of an electronic device may be personal information related to personal privacy or commercial information such as sales secrets, it is necessary to strengthen security.

[0006] Password authentication has been widely used as an authentication method for security. However, since passwords are easily leaked and vulnerable to security attacks, biometrics for personal authentication and convenience have recently emerged as an alternative.

[0007] Capacitive or optical fingerprint sensors have been proposed as one of the biometric technologies. Capacitive or optical fingerprint sensors allow electronic devices to be used through fingerprints (ie, user's biometric information), thereby enhancing security compared to password authentication.

[0008] However, since the capacitive or optical fingerprint sensor recognizes the fingerprint in a two-dimensional method of storing an image, it is easily affected by external environmental conditions. Therefore, due to the low resolution, it is difficult to recognize an accurate fingerprint and it is easy to forge. There is still a problem of low security. Summary of the invention

[0009] Accordingly, embodiments of the present disclosure are directed to a sensor panel and a display device including the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0010] An aspect of the present disclosure is to provide a sensor panel having excellent security and a high recognition rate and a display device including the sensor panel.

[0011] Additional features and aspects will be described in the following description, and some features will become apparent from the description, or can be learned by practicing the inventive concepts provided herein. Other features and aspects of the inventive concepts can be realized and obtained by the structures specifically pointed out in the written description or derived therefrom, as well as its claims and drawings.

[0012] To achieve these and other aspects of the present inventive concept, as embodied and broadly described herein, a sensor panel comprises: a substrate; a sensing portion located on the substrate, the sensing portion comprising a plurality of sensors; and a partition wall located between adjacent sensors, wherein each sensor comprises a first sensor electrode, a piezoelectric layer, and a second sensor electrode, and the partition wall has a lower dielectric constant than the piezoelectric layer.

[0013] As another aspect, a display device includes: a sensor panel, the sensor panel including: a substrate; a sensing portion located on the substrate, the sensing portion including a plurality of sensors; and a partition wall located between adjacent sensors, wherein each sensor includes a first sensor electrode, a piezoelectric layer, and a second sensor electrode, and the partition wall has a lower dielectric constant than the piezoelectric layer; and a display panel located on the sensor panel, wherein the sensing portion is disposed between the substrate and the display panel.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and, together with the description, serve to explain various principles of the present disclosure. In the drawings:

[0016] Figure 1 is a cross-sectional view schematically showing a display device according to a first embodiment of the present disclosure;

[0017] Figure 2 is a schematic partial cross-sectional view of a display panel of a display device according to a first embodiment of the present disclosure;

[0018] Figure 3 is a schematic partial cross-sectional view of a sensor panel according to a first embodiment of the present disclosure;

[0019] Figure 4 is a schematic cross-sectional view for explaining an information detection process using the display device according to the first embodiment of the present disclosure;

[0020] Figure 5 is a schematic partial plan view of a sensor panel according to a first embodiment of the present disclosure;

[0021] Figure 6 is a schematic partial cross-sectional view of a sensor panel according to a second embodiment of the present disclosure;

[0022] Figure 7 and Figure 8 is a schematic partial plan view of a sensor panel according to other embodiments of the present disclosure, and shows transistors, sensors, and partition walls; and

[0023] Fig. 9 and Fig.10 is a view schematically illustrating a display device including a sensor panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to the exemplary embodiments of the present disclosure, which are illustrated in the accompanying drawings.

[0025] Figure 1 is a cross-sectional view schematically showing a display device according to a first embodiment of the present disclosure.

[0026] exist Figure 1 , the display device according to the first embodiment of the present disclosure includes a display panel 100, a cover window 200, a sensor panel 300, a flexible printed circuit 410, and a sensor driving part 420. Although not shown in the figure, the display device of the present disclosure may further include a driving part for driving the display panel 100.

[0027] Here, the display panel 100 includes a plurality of pixels and displays an image by selectively driving the plurality of pixels. The display panel 100 may be an electroluminescent display panel, and a structure of the display panel 100 will be described in detail later.

[0028] The cover window 200 is disposed on an upper surface of the display panel 100, ie, a first surface through which an image is output. The cover window 200 protects the display panel 100 from external impact. The cover window 200 may be attached to the display panel 100 through an adhesive layer (not shown).

[0029] The cover window 200 is formed of a transparent material. For example, the cover window 200 may be formed of glass or plastic, but is not limited thereto.

[0030] The sensor panel 300 is disposed on the lower surface of the display panel 100, that is, the second surface on the opposite side of the first surface. The sensor panel 300 may have a smaller size than the display panel 100 and may be attached to one side of the lower surface of the display panel 100. However, the present disclosure is not limited thereto.

[0031] Although not shown in the figure, the sensor panel 300 includes a sensing portion including a plurality of sensors. Each sensor is an ultrasonic sensor that generates ultrasonic waves by being supplied with a voltage and generates a voltage change, that is, a capacitance change, by sensing the reflected and / or diffracted ultrasonic waves. The structure of the sensor panel 300 including the ultrasonic sensors will be described in detail later.

[0032] The sensor panel 300 is connected to the sensor driving unit 420 through the flexible printed circuit 410. The sensor driving unit 420 may be configured as an integrated circuit (IC). The sensor driving unit 420 may supply voltage to each sensor of the sensor panel 300 and receive a voltage change generated from each sensor, thereby detecting desired information.

[0033] Figure 2 1 is a schematic partial cross-sectional view of a display panel of a display device according to a first embodiment of the present disclosure. As described above, the display panel 100 of the display device according to the first embodiment of the present disclosure may be an electroluminescent display panel. The display panel 100 includes a plurality of pixels, each pixel including red, green and blue sub-pixels. Each sub-pixel has substantially the same structure, and Figure 2 A sub-pixel area corresponding to each sub-pixel is shown.

[0034] exist Figure 2 In the present invention, a patterned semiconductor layer 122 is formed on an insulating substrate 110. The insulating substrate 110 may be a glass substrate or a plastic substrate. For example, polyimide may be used for the plastic substrate, but is not limited thereto.

[0035] The semiconductor layer 122 may be formed of polysilicon, and in this case, both ends of the semiconductor layer 122 may be doped with impurities. Alternatively, the semiconductor layer 122 may be formed of an oxide semiconductor material.

[0036] Meanwhile, a buffer layer (not shown) may be further formed between the insulating substrate 110 and the semiconductor layer 122. The buffer layer may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), and may be a single layer or a multilayer.

[0037] A gate insulating layer 130 formed of an insulating material is formed on the semiconductor layer 122 substantially over the entire insulating substrate 110. The gate insulating layer 130 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx).

[0038] A gate electrode 132 formed of a conductive material such as metal is formed on the gate insulating layer 130 corresponding to the center of the semiconductor layer 122. In addition, a gate line (not shown) and a first capacitor electrode (not shown) may be formed on the gate insulating layer 130. The gate line extends in a first direction, and the first capacitor electrode is connected to the gate electrode 132.

[0039] For example, the gate electrode 132, the gate line, and the first capacitor electrode may be formed of one or more of aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr), copper (Cu), and alloys thereof, and may have a single-layer structure or a multi-layer structure, but is not limited thereto.

[0040] Meanwhile, in the first embodiment of the present disclosure, although the gate insulating layer 130 is formed substantially on the entire insulating substrate 110 , the gate insulating layer 130 may be patterned to have the same shape as the gate electrode 132 .

[0041] An interlayer insulating layer 140 formed of an insulating material is formed on the gate electrode 132 substantially over the entire insulating substrate 110. The interlayer insulating layer 140 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), or an organic insulating material such as photoacryl or benzocyclobutene.

[0042] The interlayer insulating layer 140 has a first contact hole 140a and a second contact hole 140b exposing the top surface of both ends of the semiconductor layer 122. The first contact hole 140a and the second contact hole 140b are provided at both sides of the gate electrode 132 and are spaced apart from the gate electrode 132. Here, the first contact hole 140a and the second contact hole 140b are formed in the gate insulating layer 130 and the interlayer insulating layer 140. Alternatively, when the gate insulating layer 130 is patterned to have the same shape as the gate electrode 132, the first contact hole 140a and the second contact hole 140b are formed only in the interlayer insulating layer 140.

[0043] A source electrode 142 and a drain electrode 144 formed of a conductive material such as metal are formed on the interlayer insulating layer 140. In addition, a data line (not shown), a power line (not shown), and a second capacitor electrode (not shown) may be formed on the interlayer insulating layer 140.

[0044] For example, the source electrode 142 and the drain electrode 144, the data line, the power line, and the second capacitor electrode can be formed of one or more of aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr), copper (Cu), and alloys thereof, and can have a single-layer structure or a multi-layer structure, but is not limited thereto.

[0045] The source electrode 142 and the drain electrode 144 are spaced apart from each other, and the gate electrode 132 is arranged between them. The source electrode 142 and the drain electrode 144 contact both ends of the semiconductor layer 122 through the first contact hole 140a and the second contact hole 140b, respectively. Although not shown in the figure, the data line extends in the second direction and crosses the gate line to define each sub-pixel area. The power line for providing a high potential voltage is spaced apart from the data line. The second capacitor electrode is connected to the drain electrode 144 and overlaps with the first capacitor electrode to form a storage capacitor, wherein the interlayer insulating layer 140 located therebetween serves as a dielectric. Alternatively, the first capacitor electrode can be connected to the drain electrode 144, and the second capacitor electrode can be connected to the gate electrode 132.

[0046] The semiconductor layer 122 , the gate electrode 132 , and the source and drain electrodes 142 and 144 constitute a thin film transistor T. Here, the thin film transistor T may have a coplanar structure in which the gate electrode 132 and the source and drain electrodes 142 and 144 are disposed on one side of the semiconductor layer 122 , that is, above the semiconductor layer 122 , but is not limited thereto.

[0047] The thin film transistor T corresponds to the driving thin film transistor. A switching thin film transistor (not shown) having the same structure as the driving thin film transistor T may be further formed in each sub-pixel region on the insulating substrate 110. At this time, the gate electrode 132 of the driving thin film transistor T may be connected to the drain electrode (not shown) of the switching thin film transistor T, and the source electrode 142 of the driving thin film transistor T may be connected to the power line (not shown). In addition, the gate electrode (not shown) and the source electrode (not shown) of the switching thin film transistor may be connected to the gate line and the data line, respectively.

[0048] Meanwhile, one or more sensing thin film transistors having the same structure as the driving thin film transistor T may be further formed in each sub-pixel region on the insulating substrate 110 , but is not limited thereto.

[0049] A capping layer 150 formed of an insulating material is formed on the source electrode 142 and the drain electrode 144 substantially on the entire insulating substrate 110. The capping layer 150 may be formed of an organic insulating material such as photo acrylic or benzocyclobutene. The capping layer 150 may have a flat top surface.

[0050] In addition, although not shown in the figure, an inorganic insulating layer may be further formed under the capping layer 150, that is, between the capping layer 150 and the thin film transistor T. The inorganic insulating layer may be formed of silicon oxide (SiO2) or silicon nitride (SiNx).

[0051] The capping layer 150 has a drain contact hole 150a exposing the drain electrode 144. Here, the drain contact hole 150a may be laterally spaced apart from the second contact hole 140b. Alternatively, the drain contact hole 150a may be formed right above the second contact hole 140b.

[0052] The first electrode 160 formed of a conductive material having a high work function is formed on the capping layer 150. The first electrode 160 is formed in each sub-pixel region and contacts the drain electrode 144 through the drain contact hole 150a. For example, the first electrode 160 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0053] Meanwhile, the display panel 100 of the display device according to the first embodiment of the present disclosure may be a top emission type, in which the light of the light emitting diode is output in a direction opposite to the insulating substrate 110. Therefore, the first electrode 160 may also include a reflective electrode or a reflective layer below the transparent conductive material layer, the reflective electrode or the reflective layer being formed of a metal material with a relatively high reflectivity. For example, the reflective electrode or the reflective layer may be formed of an aluminum-palladium-copper (APC) alloy or silver (Ag). At this time, the first electrode 160 may have a three-layer structure formed of ITO / APC / ITO or ITO / Ag / ITO, but is not limited thereto.

[0054] A bank 162 formed of an insulating material is formed on the first electrode 160. The bank 162 overlaps the edge of the first electrode 160, covers the edge of the first electrode 160, and exposes the central portion of the first electrode 160. The bank 162 may be formed of an organic insulating material having hydrophobicity. Alternatively, the bank 162 may be formed of an organic insulating material having hydrophilicity and may be treated to have hydrophobicity. However, the present disclosure is not limited thereto. At the same time, a bank having hydrophilicity may be further formed below the bank 162.

[0055] Next, the light emitting layer 170 is formed on the first electrode 160 exposed by the bank 162 .

[0056] Although not shown in the figure, the light emitting layer 170 may include a first charge auxiliary layer, a light emitting material layer, and a second charge auxiliary layer sequentially disposed on the first electrode 160. The light emitting material layer may be formed of any one of red, green, and blue light emitting materials, but is not limited thereto. The light emitting material may be an organic light emitting material such as a phosphorescent compound or a fluorescent compound, or may be an inorganic light emitting material such as a quantum dot.

[0057] The first charge auxiliary layer may be a hole auxiliary layer, and the hole auxiliary layer may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL). In addition, the second charge auxiliary layer may be an electron auxiliary layer, and the electron auxiliary layer may include at least one of an electron injection layer (EIL) and an electron transport layer (ETL). However, the present disclosure is not limited thereto, and other modifications are possible.

[0058] Here, the light emitting layer 170 can be formed by a solution process. Therefore, the process can be simplified, and a display device with a large size and high resolution can be provided. A spin coating method, an inkjet printing method, or a screen printing method can be used as a solution process, but the present disclosure is not limited thereto, and other variations are possible. When the solution dries, the drying speed of the solvent in the region adjacent to the bank 162 is different from that in other regions. Therefore, the height of the light emitting layer 170 in the region adjacent to the bank 162 can be increased as it approaches the bank 162.

[0059] Alternatively, the light emitting layer 170 may be formed by a vacuum evaporation process, or may be formed by a mixture of a solution process and a vacuum evaporation process.

[0060] The second electrode 180 formed of a conductive material having a lower work function is formed on the light emitting layer 170 substantially over the entire insulating substrate 110. The second electrode 180 may be formed of aluminum (Al), magnesium (Mg), silver (Ag), or an alloy thereof. The second electrode 180 may have a relatively thin thickness so that light from the light emitting layer 170 may be transmitted through the second electrode. Alternatively, the second electrode 180 may be formed of a transparent conductive material such as indium gallium oxide (IGO), but is not limited thereto.

[0061] The first electrode 160, the light emitting layer 170, and the second electrode 180 constitute a light emitting diode De. The first electrode 160 may be used as an anode, and the second electrode 180 may be used as a cathode, but are not limited thereto.

[0062] As described above, the display panel 100 according to the first embodiment of the present disclosure may be a top emission type, in which light from the light emitting layer 170 of the light emitting diode De is output in a direction opposite to the insulating substrate 110, that is, output to the outside through the second electrode 180. The top emission type display panel may have a wider emission area than a bottom emission type display panel of the same size, thereby improving brightness and reducing power consumption.

[0063] At this time, the light emitting diode De of each sub-pixel region may have an element thickness for a microcavity effect, which corresponds to the wavelength of the emitted light, thereby improving light efficiency.

[0064] Next, an encapsulation layer 190 may be formed on the second electrode 180 substantially on the entire insulating substrate 110 to block moisture or oxygen introduced from the outside, thereby protecting the light emitting diode De. The encapsulation layer 190 may be formed of a UV curable sealant or a frit sealant. Alternatively, the encapsulation layer 190 may include an inorganic layer and an organic layer alternately stacked.

[0065] Meanwhile, the display panel 100 according to the first embodiment of the present disclosure may further include a polarizing plate 192 on the encapsulation layer 190. The polarizing plate 192 may be a circular polarizing plate that includes a linear polarizer and a quarter wave plate and converts linear polarized light into circular polarized light or converts circular polarized light into linear polarized light. The polarizing plate 192 blocks external light from being reflected by the display panel 100 and then output, thereby improving contrast.

[0066] Figure 3 3 is a schematic partial cross-sectional view of a sensor panel according to a first embodiment of the present disclosure. As described above, the sensor panel 300 includes a sensing portion including a plurality of sensors SE located on a substrate 310. Each sensor SE is an ultrasonic sensor including a first sensor electrode 360, a piezoelectric layer 370, and a second sensor electrode 380.

[0067] More specifically, if Figure 3 As shown, a blocking layer 312 is formed on the substrate 310. The blocking layer 312 is formed on substantially the entire substrate 310, and blocks ultrasonic waves generated by the sensor SE and advancing toward the substrate 310 from being reflected by the substrate 310 and returning to the sensor SE. The blocking layer 312 may absorb ultrasonic waves generated from the sensor SE and advancing toward the substrate 310. For example, the blocking layer 312 may be formed of copper, but is not limited thereto.

[0068] Meanwhile, the substrate 310 is formed of an insulating material. The substrate 310 may be a glass substrate or a plastic substrate, but is not limited thereto.

[0069] The insulating layer 314 is formed on the barrier layer 312 substantially on the entire substrate 310. The insulating layer 314 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), but is not limited thereto.

[0070] A patterned semiconductor layer 322 is formed corresponding to each sensor SE on the insulating layer 314. The semiconductor layer 322 may be formed of polysilicon, and in this case, both ends of the semiconductor layer 322 may be doped with impurities. Alternatively, the semiconductor layer 322 may be formed of an oxide semiconductor material.

[0071] The gate insulating layer 330 formed of an insulating material is formed on the semiconductor layer 322 substantially on the entire substrate 310. The gate insulating layer 330 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx).

[0072] A gate electrode 332 formed of a conductive material such as metal is formed on the gate insulating layer 330 corresponding to the center of each semiconductor layer 322. In addition, a gate line (not shown) may be formed on the gate insulating layer 330. The gate line extends in one direction, and the gate electrode 332 is connected to the gate line.

[0073] For example, the gate electrode 332 and the gate line may be formed of one or more of aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr), copper (Cu) and alloys thereof, and may have a single-layer structure or a multi-layer structure, but is not limited thereto.

[0074] Meanwhile, in the first embodiment of the present disclosure, although the gate insulating layer 330 is formed substantially on the entire substrate 310 , the gate insulating layer 330 may be patterned to have the same shape as the gate electrode 332 .

[0075] An interlayer insulating layer 340 formed of an insulating material is formed on the gate electrode 332 substantially over the entire substrate 310. The interlayer insulating layer 340 may be formed of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) or an organic insulating material such as photoacryl or benzocyclobutene.

[0076] The interlayer insulating layer 340 has a first contact hole 340a and a second contact hole 340b exposing the top surface of both ends of each semiconductor layer 322. The first contact hole 340a and the second contact hole 340b are provided on both sides of the gate electrode 332 and are spaced apart from the gate electrode 332. Here, the first contact hole 340a and the second contact hole 340b are formed in the gate insulating layer 330 and the interlayer insulating layer 340. Alternatively, when the gate insulating layer 330 is patterned to have the same shape as the gate electrode 332, the first contact hole 340a and the second contact hole 340b are formed only in the interlayer insulating layer 340.

[0077] A source electrode 342 and a drain electrode 344 formed of a conductive material such as metal are formed on the interlayer insulating layer 340. In addition, a data line (not shown) may be formed on the interlayer insulating layer 340.

[0078] For example, the source electrode 342, the drain electrode 344 and the data line may be formed of one or more of aluminum (Al), molybdenum (Mo), titanium (Ti), nickel (Ni), chromium (Cr), copper (Cu) and alloys thereof, and may have a single-layer structure or a multi-layer structure, but is not limited thereto.

[0079] The source electrode 342 and the drain electrode 344 are spaced apart from each other, and the gate electrode 332 is disposed therebetween. The source electrode 342 and the drain electrode 344 contact both ends of the semiconductor layer 322 through the first contact hole 340a and the second contact hole 340b, respectively. Although not shown in the figure, the data line extends in one direction and crosses the gate line.

[0080] The semiconductor layer 322, the gate electrode 332, and the source and drain electrodes 342 and 344 constitute a thin film transistor SW as a switching element. Here, the thin film transistor SW may have a coplanar structure in which the gate electrode 332 and the source and drain electrodes 342 and 344 are disposed on one side of the semiconductor layer 322, i.e., above the semiconductor layer 322, but is not limited thereto.

[0081] Meanwhile, one or more thin film transistors having the same structure as the thin film transistor SW may be further formed to correspond to each sensor SE. In addition, a CMOS (Complementary Metal Oxide Semiconductor) element having the same or similar structure as the thin film transistor SW may be further formed on the substrate 310 .

[0082] A capping layer 350 formed of an insulating material is formed on the source electrode 342 and the drain electrode 344 substantially on the entire insulating substrate 310. The capping layer 350 may be formed of an organic insulating material such as photo acrylic or benzocyclobutene. The capping layer 350 may have a flat top surface.

[0083] In addition, although not shown in the figure, an inorganic insulating layer may be further formed under the capping layer 350, that is, between the capping layer 350 and the thin film transistor SW. The inorganic insulating layer may be formed of silicon oxide (SiO2) or silicon nitride (SiNx).

[0084] The capping layer 350 has a drain contact hole 350a exposing the drain electrode 344. Here, the drain contact hole 350a may be laterally spaced apart from the second contact hole 340b. Alternatively, the drain contact hole 350a may be formed right above the second contact hole 340b.

[0085] The first sensor electrode 360 ​​formed of a conductive material is patterned and formed on the cover layer 350 corresponding to each sensor SE. The first sensor electrode 360 ​​contacts the drain electrode 344 through the drain contact hole 350a. For example, the first sensor electrode 360 ​​may be formed of indium tin oxide (ITO), copper (Cu), or molybdenum titanium (Mo—Ti) alloy, but is not limited thereto.

[0086] The piezoelectric layer 370 is formed on the first sensor electrode 360 ​​substantially on the entire substrate 310 .

[0087] The piezoelectric layer 370 may be formed of a piezoelectric material that generates electrical energy by material deformation due to external mechanical energy and generates material deformation by electrical energy. The piezoelectric layer 370 may be formed by coating or printing ink including a piezoelectric material. The piezoelectric material may be a piezoelectric polymer, a piezoelectric ceramic, or an organic-inorganic composite.

[0088] For example, the piezoelectric polymer may be PVDF (polyvinylidene fluoride), P(VDF-TrFE) (poly(vinylidene fluoride-trifluoroethylene copolymer)), P(VDF-TrFE-CFE) (poly(vinylidene fluoride-trifluoroethylene copolymer-chlorofluoroethylene)), P(VDF-TrFE-CTFE) (poly(vinylidene fluoride-trifluoroethylene copolymer-chlorotrifluoroethylene)), PVDF doped with carbon nanotubes, or a phosphazene-based polymer, but is not limited thereto. Polybis(trifluoroethoxy)phosphazene may be used as the phosphazene-based polymer.

[0089] In addition, the piezoelectric ceramic may be PbZrTiO3 (PZT, lead zirconate titanate), Pb(MgNb)-PbZrTiO3, PNN-PT (Pb(NiNb)-PbTiO3) or PLZT (PbLaZrTiO3). Alternatively, the piezoelectric ceramic may be a lead-free piezoelectric material such as BaTiO3 (BTO, barium titanate) or KNaNbO3 (KNN, potassium sodium niobate).

[0090] Meanwhile, the organic-inorganic composite may include the above-mentioned piezoelectric ceramic and a polymer. Here, the polymer may be one of the above-mentioned piezoelectric polymers, or may be a non-piezoelectric polymer such as epoxy resin, polyimide or polyurethane.

[0091] The piezoelectric layer 370 may have a thickness of 0.5 μm to 80 μm, advantageously 1 μm to 50 μm, and more advantageously 5 μm to 10 μm. If the thickness of the piezoelectric layer 370 is less than 0.5 μm, it is difficult to generate ultrasonic waves. If the thickness of the piezoelectric layer 370 is greater than 80 μm, a high voltage is required to generate ultrasonic waves, and the receiving sensitivity is reduced.

[0092] A partition wall 372 formed of an insulating material is formed on the piezoelectric layer 370. The partition wall 372 is formed between adjacent sensors SE, that is, between adjacent first sensor electrodes 360.

[0093] The partition wall 372 has a lower dielectric constant than the piezoelectric layer 370, thereby blocking the electric field between adjacent sensors SE. For example, the dielectric constant of the partition wall 372 may be greater than 1.0 and less than 2.0, and advantageously, greater than 1.0 and less than 1.5.

[0094] Here, the partition wall 372 is spaced apart from the first sensor electrode 360. In addition, the partition wall 372 may be provided between adjacent thin film transistors SW and spaced apart from the thin film transistor SW. Alternatively, the partition wall 372 may partially overlap with the thin film transistor SW.

[0095] The partition wall 372 may be formed by coating a polymer material and then patterning it or by printing a polymer material. For example, the partition wall 372 may be formed of a polyimide-based compound, a polydimethylsiloxane-based compound, a polyacrylate-based polymer, or a polyurethane-based polymer, but is not limited thereto.

[0096] The second sensor electrode 380 is formed on the partition wall 372 substantially over the entire substrate 310. The second sensor electrode 380 covers the partition wall 372 and contacts the top and side surfaces of the partition wall 372. In addition, the second sensor electrode 380 contacts the piezoelectric layer 370 between the partition walls 370.

[0097] Here, the first sensor electrode 360 ​​and the second sensor electrode 380 overlapped with each other and the piezoelectric layer 370 therebetween constitute each sensor SE. As described above, each sensor SE is an ultrasonic sensor.

[0098] The second sensor electrode 380 may be formed by depositing indium tin oxide (ITO) or molybdenum titanium (MoTi) alloy by a sputtering method or applying silver ink by a coating method, but is not limited thereto. Here, the thickness of the second sensor electrode 380 formed by the sputtering method may be less than the thickness of the second sensor electrode 380 formed by the coating method. For the reception sensitivity of the sensor, it is advantageous for the second sensor electrode 380 to have a smaller thickness because the sensor SE is relatively close to the sensor SE. Figure 1 The distance between the display panels 100 is reduced.

[0099] A passivation layer 382 is formed on the second sensor electrode 380. Since the thickness of the second sensor electrode 380 is smaller than the thickness of the partition wall 372, the top surface of the second sensor electrode 380 has a step difference 372 caused by the partition wall, and the passivation layer 382 covers the step difference.

[0100] Here, the passivation layer 382 may be formed only on the second sensor electrode 380 between adjacent patterns of the partition wall 372. At this time, a top surface of the passivation layer 382 is flush with a top surface of the second sensor electrode 380.

[0101] Alternatively, the passivation layer 382 may be formed on the top surface of the partition walls 372 and on the second sensor electrodes 380 between the partition walls 372. In this case, the passivation layer 382 has a flat top surface, and the thickness of the passivation layer 382 on the sensor SE is thicker than that on the partition walls 372.

[0102] The passivation layer 382 may be formed of an organic insulating material, for example, a polyimide-based compound or an acryl-based compound, but is not limited thereto.

[0103] The adhesive layer 390 is formed on the passivation layer 382 substantially on the entire substrate 310. When the passivation layer 382 is formed only on the second sensor electrode 380 between the partition walls 372, the adhesive layer 390 contacts the passivation layer 382 and the second sensor electrode 380.

[0104] Alternatively, when the passivation layer 382 is formed on the partition walls 372 and on the second sensor electrodes 380 between the partition walls 372 , the adhesive layer 390 contacts only the passivation layer 382 .

[0105] The adhesive layer 390 may be formed of an organic material, an inorganic material, or a mixture of an organic material and an inorganic material. For example, epoxy resin or an optically clear adhesive (OCA) may be used for the adhesive layer 390, but is not limited thereto.

[0106] The sensor panel 300 is attached to the Figure 1Here, the adhesive layer 390 is included in the sensor panel 300. However, the adhesive layer 390 may be included in Figure 1 In the display panel 100.

[0107] An information detection process using a display device including the sensor panel 300 will be described with reference to the accompanying drawings.

[0108] Figure 4 is a schematic cross-sectional view for explaining an information detection process using a display device according to a first embodiment of the present disclosure, and will also refer to Figure 3 sensor panel.

[0109] like Figure 3 and Figure 4 As shown, in the display device according to the first embodiment of the present disclosure, the cover window 200 is attached to the upper surface of the display panel 100, and the sensor panel 300 is attached to the lower surface of the display panel 100. At this time, the sensor SE of the sensor panel 300 is disposed between the display panel 100 and the substrate 310 of the sensor panel 300, and the thin film transistor SW is disposed between the sensor SE and the substrate 310.

[0110] Meanwhile, the target object 500 is arranged on the cover window 200. That is, the target object 500 is arranged on the upper surface of the cover window 200. For example, the target object 500 may be a finger print having peaks and valleys, but is not limited thereto. Here, the peaks of the target object 500 contact the cover window 200 of the display device, and the valleys of the target object 500 are spaced apart from the cover window 200, so that another material layer such as an air layer or a moisture layer is disposed between the valleys and the cover window 200. In the present disclosure, an example of providing an air layer will be described.

[0111] A voltage is applied from the sensor driving section 420 to the sensor SE of the sensor panel 300, and the sensor SE of the sensor panel 300 generates ultrasonic waves U11 and U21. At this time, the voltage applied to the sensor SE is an AC (alternating current) voltage. The piezoelectric layer 370 of the sensor SE vibrates by the applied AC voltage, thereby generating ultrasonic waves U11 and U21.

[0112] The generated ultrasonic waves U11 and U21 pass through the display panel 100 and the cover window 200 and are transmitted to the target object 500. Then, the ultrasonic waves U11 and U21 transmitted to the target object 500 are reflected by the target object 500, and the reflected ultrasonic waves U12 and U22 pass through the cover window 200 and the display panel 100 and are transmitted to the sensor panel 300. The sensor SE of the sensor panel 300 receives the reflected ultrasonic waves U12 and U22 to thereby generate a voltage. Figure 1The sensor driving part 420 receives the voltage generated from the sensor SE and detects information about the target object 500 by calculating the distance between the target object 500 and the sensor SE.

[0113] At this time, the intensity of the ultrasonic wave U12 reflected by the peak of the target object 500 is different from the intensity of the ultrasonic wave U22 reflected by the valley of the target object 500. That is, the ultrasonic waves U11, U12, U21, and U22 are reflected, absorbed, or refracted when passing through the medium, so that their intensities are reduced. Since the ultrasonic waves U21 and U22 corresponding to the valley of the target object 500 also pass through the air layer compared to the ultrasonic waves U11 and U12 corresponding to the peak of the target object 500, the intensity of the ultrasonic wave U12 reflected by the peak of the target object 500 is greater than the intensity of the ultrasonic wave U22 reflected by the valley of the target object 500.

[0114] Therefore, the sensors SE of the sensor panel 300 generate different voltages to correspond to the reflected ultrasonic waves U12 and U22 having different intensities, and Figure 1 The sensor driving section 420 detects information such as the shape of the target object 500 from these voltages.

[0115] As described above, in the display device according to the first embodiment of the present disclosure, since the sensor SE of the sensor panel 300 recognizes the target object in a three-dimensional method by using ultrasonic waves, safety is superior to a capacitive or optical sensor that recognizes the target object in a two-dimensional method.

[0116] In the display device according to the first embodiment of the present disclosure, the sensor SE is arranged Figure 1 between the display panel 100 and the substrate 310, thus, by reducing Figure 1 By reducing the distance between the display panel 100 and the sensor SE, the attenuation and refraction of the ultrasonic wave can be minimized. Therefore, the receiving sensitivity of the sensor SE is improved and the recognition rate is improved, thereby improving the sensing accuracy.

[0117] In addition, in the display device according to the first embodiment of the present disclosure, the partition wall 372 between the adjacent sensors SE supports the sensor panel 300. When the sensor panel 300 is attached to Figure 1 When the display panel 100 is formed, the sensor electrode and the piezoelectric material of the sensor SE are prevented from being damaged, and deformation of the piezoelectric material due to external pressure such as a touch can be minimized.

[0118] At this time, as the thickness of the partition wall 372 increases, the sensor SE and Figure 1 The distance between the display panels 100 increases, and the receiving sensitivity of the sensor SE decreases. Therefore, it is favorable that the thickness of the partition wall 372 is 0.5 μm to 10 μm.

[0119] At the same time, the partition wall 372 blocks the ultrasonic wave generated and received by the specific sensor SE from advancing to another sensor SE adjacent to the specific sensor SE through reflection and refraction, thereby optimizing the advancing path of the ultrasonic wave and further improving the sensing accuracy.

[0120] At this time, as the modulus increases, the ultrasonic wave advances well. In order to effectively block the ultrasonic wave, it is desirable that the partition wall 372 has a relatively low modulus. On the other hand, it is preferred that the passivation layer 382 provided on the sensor SE has a relatively high modulus so that the ultrasonic wave advances well. Therefore, the modulus of the partition wall 372 is smaller than the modulus of the passivation layer 382. For example, the modulus of the partition wall may be 10 5 Up to 10 6 Pa, and the modulus of the passivation layer 382 may be 10 7 Up to 10 9 Pa, but not limited to this.

[0121] In addition, as described above, the partition wall 372 has a lower dielectric constant than the piezoelectric layer 370, and the partition wall 372 blocks the electric field between the first sensor electrode 360 ​​and the second sensor electrode 380 in the region between the adjacent sensors SE. Therefore, the partition wall 372 can prevent the generation of unnecessary ultrasonic waves in the region other than the sensor SE.

[0122] Will refer to Figure 5 The planar arrangement structure of the partition walls in the first embodiment of the present disclosure is described.

[0123] Figure 5 is a schematic partial plan view of a sensor panel according to the first embodiment of the present disclosure, and shows transistors, sensors, and partition walls.

[0124] exist Figure 5 In the embodiment, a plurality of thin film transistors SW are arranged in a matrix shape along a first direction and a second direction perpendicular to the first direction. A plurality of sensors SE respectively connected to the plurality of thin film transistors SW are arranged in a matrix shape along the first direction and the second direction. A partition wall 372 is provided between adjacent sensors SE. Here, the first direction may correspond to the vertical direction in the figure, and the second direction may correspond to the horizontal direction in the figure.

[0125] More specifically, the partition wall 372 includes a first pattern 372a and a second pattern 372b. The first pattern 372a of the partition wall 372 is disposed between adjacent sensors SE along the first direction, and the second pattern 372b of the partition wall 372 is disposed between adjacent sensors SE along the second direction. The first pattern 372a extends in the second direction, the second pattern 372b extends in the first direction, and the first pattern 372a and the second pattern 372b cross each other. Therefore, the partition wall 372 may have a mesh structure, and each sensor SE may be surrounded by the partition wall 372.

[0126] Alternatively, the partition wall is not formed in a region where the sensors SE are relatively far from each other, so that the partition wall may be formed in a line shape.

[0127] Here, the partition wall 372 is spaced apart from the sensor SE and the thin film transistor SW. Alternatively, the partition wall 372 may be spaced apart from the sensor SE and partially overlap the thin film transistor SW.

[0128] Figure 6 : is a schematic partial cross-sectional view of a sensor panel according to a second embodiment of the present disclosure. In addition to the configuration on the sensor SE, Figure 6 The sensor panel of the embodiment has the same structure as the sensor panel of the first embodiment. The same parts will be denoted by the same reference numerals, and the explanation of the same parts will be shortened or omitted.

[0129] exist Figure 6 In the embodiment, a barrier layer 312 and an insulating layer 314 are sequentially formed on a substrate 310, a thin film transistor SW as a switching element is formed on the insulating layer 314, and a capping layer 350 is formed on the thin film transistor SW.

[0130] The first sensor electrode 360 ​​formed of a conductive material is patterned and formed on the cover layer 350 corresponding to each sensor SE. The first sensor electrode 360 ​​is connected to the drain electrode 344 of the corresponding thin film transistor SW.

[0131] The piezoelectric layer 370 formed of a piezoelectric material is formed on the first sensor electrode 360 ​​substantially all over the substrate 310. Here, the piezoelectric layer 370 may have a thickness of 0.5 to 80 μm, advantageously 1 to 50 μm, and more advantageously 5 to 10 μm.

[0132] A partition wall 372 formed of an insulating material is formed on the piezoelectric layer 370. The partition wall 372 is formed between adjacent sensors SE, that is, between adjacent first sensor electrodes 360.

[0133] The partition wall 372 has a lower dielectric constant than the piezoelectric layer 370, thereby blocking the electric field between adjacent sensors SE. For example, the dielectric constant of the partition wall 372 may be greater than 1.0 and less than 2.0, and advantageously, greater than 1.0 and less than 1.5. In addition, in order to prevent the receiving sensitivity of the sensor SE from being reduced, it is advantageous for the thickness of the partition wall 372 to be 0.5 μm to 10 μm.

[0134] The second sensor electrode 380 is formed on the partition wall 372 substantially on the entire substrate 310. The second sensor electrode 380 covers the partition wall 372 and contacts the top and side surfaces of the partition wall 372. In addition, the second sensor electrode 380 contacts the piezoelectric layer 370 between the partition walls 370.

[0135] Here, the first sensor electrode 360 ​​and the second sensor electrode 380 overlapped with each other and the piezoelectric layer 370 therebetween constitute each sensor SE. As described above, each sensor SE is an ultrasonic sensor.

[0136] Adhesive layer 392 is formed on second sensor electrode 380 substantially over substrate 310. Since the thickness of second sensor electrode 380 is smaller than that of partition wall 372, the top surface of second sensor electrode 380 has a step difference due to partition wall 372, and adhesive layer 392 covers the step difference.

[0137] At this time, adhesive layer 392 is also formed on the top surface of partition wall 372 and has a flat top surface. The thickness of adhesive layer 392 located between adjacent patterns of partition wall 372, that is, located on sensor SE, is thicker than that of adhesive layer 392 located on partition wall 372.

[0138] The adhesive layer 392 may be formed of an organic material, an inorganic material, or a mixture of an organic material and an inorganic material. For example, epoxy resin or an optically clear adhesive (OCA) may be used for the adhesive layer 390, but is not limited thereto.

[0139] Meanwhile, since the adhesive layer 392 is formed relatively thick on the sensor SE, the adhesive layer 392 may have a relatively high modulus so that ultrasonic waves advance well. At this time, it is desirable that the modulus of the adhesive layer 392 is greater than that of the partition wall 372 .

[0140] The sensor panel 300 is attached to the Figure 1 The display panel 100 is provided.

[0141] As described above, in the second embodiment of the present disclosure, since the adhesive layer 372 covers the step difference caused by the partition wall 372 , the passivation layer may be omitted, thereby reducing the manufacturing process and cost compared to the first embodiment.

[0142] Meanwhile, in the present disclosure, the arrangement of the partition wall varies according to the arrangement of the thin film transistor and the sensor. Figure 7 and Figure 8 A planar arrangement structure of partition walls according to other embodiments of the present disclosure is described.

[0143] Figure 7 and Figure 8 is a schematic partial plan view of a sensor panel according to other embodiments of the present disclosure, and shows transistors, sensors, and partition walls.

[0144] exist Figure 7 and Figure 8 In the embodiment, a plurality of first thin film transistors SW1 and second thin film transistors SW2 are arranged in a matrix shape along a first direction and a second direction perpendicular to the first direction. At this time, the first thin film transistors SW1 and the second thin film transistors SW2 are connected to each other along the first direction. Here, the first direction may correspond to the vertical direction in the figure, and the second direction may correspond to the horizontal direction in the figure.

[0145] A plurality of first sensors SE1 and second sensors SE2 are arranged in a matrix shape along the first direction and the second direction. Here, the first sensor SE1 is connected to the first thin film transistor SW1, and the second sensor SE2 is connected to the second thin film transistor SW2. The first sensor SE1 and the second sensor SE2 respectively connected to the first thin film transistor SW1 and the second thin film transistor SW2 connected to each other along the first direction are spaced apart from each other along the first direction.

[0146] Meanwhile, a partition wall 372 is provided between the adjacent sensors SE1 and SE2.

[0147] More specifically, refer to Figure 7 , the partition wall 372 includes a first pattern 372c, a second pattern 372d, and a third pattern 372e. The first pattern 372c and the second pattern 372d are disposed between the first sensor SE1 and the second sensor SE2 adjacent to each other in the first direction, and the third pattern 372e is disposed between the first sensor SE1 and the second sensor SE2 adjacent to each other in the second direction. The first pattern 372c and the second pattern 372d extend in the second direction and are parallel to each other. The third pattern 372e extends in the first direction and intersects the first pattern 372c and the second pattern 372d.

[0148] At this time, the first pattern 372c is disposed between the first thin film transistor SW1 and the second thin film transistor SW2 connected to each other in the first direction, and partially overlaps with the first thin film transistor SW1 and the second thin film transistor SW2. The second pattern 372d is disposed between the first thin film transistor SW1 and the second thin film transistor SW2 spaced apart from each other in the first direction, and is spaced apart from the first thin film transistor SW1 and the second thin film transistor SW2. Therefore, the partition wall 372 may have a mesh structure, and each of the sensors SE1 and SE2 may be surrounded by the partition wall 372.

[0149] On the other hand, reference Figure 8 , the partition wall 372 includes a first pattern 372c, a second pattern 372d, a third pattern 372f, and a fourth pattern 372g. The first pattern 372c and the second pattern 372d are disposed between the first sensor SE1 and the second sensor SE2 adjacent to each other in the first direction, and the third pattern 372f and the fourth pattern 372g are disposed between the first sensor SE1 and the second sensor SE2 adjacent to each other in the second direction. The first pattern 372c and the second pattern 372d extend in the second direction and are parallel to each other. The third pattern 372f and the fourth pattern 372g extend in the first direction and are parallel to each other. The third pattern 372f and the fourth pattern 372g intersect the first pattern 372c and the second pattern 372d.

[0150] At this time, the first pattern 372c is disposed between the first thin film transistor SW1 and the second thin film transistor SW2 connected to each other in the first direction, and partially overlaps with the first thin film transistor SW1 and the second thin film transistor SW2. The second pattern 372d is disposed between the first thin film transistor SW1 and the second thin film transistor SW2 spaced apart from each other in the first direction, and is spaced apart from the first thin film transistor SW1 and the second thin film transistor SW2. In addition, the third pattern 372f is disposed between the first sensor SE1 and the second sensor SE2 adjacent in the second direction, and is spaced apart from the first thin film transistor SW1 and the second thin film transistor SW2. The fourth pattern 372g is disposed between the first sensor SE1 and the second sensor SE2 adjacent in the second direction, and partially overlaps with the first thin film transistor SW1 and the second thin film transistor SW2. Here, the fourth pattern 372g is disposed between the third pattern 372f and the first sensor SE1 and the second sensor SE2. Therefore, the partition wall 372 may have a mesh structure, and each of the sensors SE1 and SE2 may be surrounded by the partition wall 372.

[0151] As described above, when the distance between the adjacent sensors SE1 and SE2 is relatively far, the number of partition walls 372 provided between the adjacent sensors SE1 and SE2 may be increased, and the arrangement of the partition walls 372 is not limited to the illustrated configuration.

[0152] The sensor panel of the present disclosure can be applied to display devices of various sizes, which will be referred to as Fig. 9 and Fig.10 Give a description.

[0153] Fig. 9 and Fig.10 is a view schematically illustrating a display device including a sensor panel according to an embodiment of the present disclosure.

[0154] exist Fig. 9 and Fig.10 In the embodiment of the present disclosure, the display device includes Figure 1 The display panel 100 and Figure 1 The sensor panel 300 includes the display panel 100 having a display area DA and a non-display area NDA, and the sensor panel 300 has a sensing area SA. Figure 1 The display panel 100 displays an image through the display area DA, and the non-display area NDA surrounds the display area DA. The non-display area NDA may surround at least one side of the display area DA.

[0155] Here, the sensing area SA is disposed within the display area DA. Fig. 9 As shown in FIG. 1 , the sensing area SA may have a length smaller than that of the display area DA in the horizontal direction and the vertical direction. Fig.10 As shown, the sensing area SA may have a horizontal length substantially the same as that of the display area DA and a vertical length smaller than that of the display area DA. However, the length of the sensing area SA is not limited thereto and may be configured in various ways as desired.

[0156] The display device of the present disclosure has excellent safety by applying a sensor panel including an ultrasonic sensor to the display device.

[0157] At this time, by attaching the sensor panel to the display panel so that the ultrasonic sensor is adjacent to the display panel, the distance between the display panel and the ultrasonic sensor can be reduced to minimize the attenuation and refraction of ultrasonic waves, and the recognition rate of the ultrasonic sensor can be improved, thereby improving the sensing accuracy.

[0158] In addition, by providing a partition wall between adjacent ultrasonic sensors, when the sensor panel is attached to the display panel, the sensor electrodes and the piezoelectric material of the ultrasonic sensor can be prevented from being damaged, and deformation of the piezoelectric material due to external pressure can be minimized.

[0159] At the same time, the partition wall can prevent the ultrasonic wave from advancing in an undesired direction, thereby optimizing the advancing path of the ultrasonic wave and further improving the sensing accuracy.

[0160] Furthermore, the partition wall has a lower dielectric constant than the piezoelectric layer, and blocks the electric field in a region other than the ultrasonic sensor, thereby preventing generation of undesired ultrasonic waves.

[0161] It will be apparent to those skilled in the art that various modifications and variations may be made to the display device of the present disclosure without departing from the technical concept or scope of the present disclosure. Therefore, the present disclosure is intended to cover various modifications and variations of the present disclosure as long as they fall within the scope of the attached claims and their equivalents.

Claims

1. A sensor panel, comprising: substrate; a sensing portion located on the substrate, the sensing portion comprising a plurality of sensors; and The partition wall between adjacent sensors, wherein each sensor comprises a first sensor electrode, a piezoelectric layer, and a second sensor electrode sequentially formed on the substrate, and wherein the partition wall has a lower dielectric constant than the piezoelectric layer, The partition wall is disposed on the piezoelectric layer, located between adjacent first sensor electrodes and spaced apart from the first sensor electrodes.

2. The sensor panel according to claim 1, wherein: The sensor generates and senses ultrasonic waves.

3. The sensor panel according to claim 1, wherein: The partition wall is disposed between the piezoelectric layer and the second sensor electrode.

4. The sensor panel according to claim 3, wherein: The sensor panel also includes a passivation layer on the second sensor electrode, the passivation layer having a larger modulus than the partition wall.

5. The sensor panel according to claim 4, wherein: The passivation layer is disposed on the second sensor electrode between adjacent patterns of the partition wall, and a top surface of the passivation layer is flush with a top surface of the second sensor electrode over the partition wall.

6. The sensor panel according to claim 5, wherein: The sensor panel also includes an adhesive layer on the passivation layer, the adhesive layer contacting the passivation layer and the second sensor electrode.

7. The sensor panel according to claim 4, wherein: The passivation layer is disposed on the second sensor electrode located between adjacent patterns of the partition wall and on the second sensor electrode located on a top surface of the partition wall, and the passivation layer has a flat top surface.

8. The sensor panel according to claim 3, wherein: The sensor panel further includes an adhesive layer on the second sensor electrode, the adhesive layer having a modulus greater than that of the partition wall.

9. The sensor panel according to claim 8, wherein: The adhesive layer is disposed on the second sensor electrode located between adjacent patterns of the partition wall and on the second sensor electrode located on the top surface of the partition wall, and the thickness of the adhesive layer located between adjacent patterns of the partition wall is thicker than the thickness of the adhesive layer located on the top surface of the partition wall.

10. The sensor panel according to claim 1, wherein: The partition wall includes a plurality of patterns parallel to and spaced apart from each other between the adjacent sensors.

11. The sensor panel according to claim 1, wherein: The partition wall has a thickness of 0.5 μm to 10 μm.

12. The sensor panel according to claim 1, wherein: The partition wall is formed of a polyimide-based compound, a polydimethylsiloxane-based compound, a polypropylene-based polymer, or a polyurethane-based polymer.

13. The sensor panel according to claim 1, wherein: The sensor panel further includes a plurality of thin film transistors between the substrate and the plurality of sensors, and the first sensor electrodes of the plurality of sensors are respectively connected to the plurality of thin film transistors.

14. The sensor panel according to claim 2, wherein: The sensor panel further includes a blocking layer formed on the substrate and blocking the ultrasonic wave.

15. The sensor panel according to claim 1, wherein: The second sensor electrode has a smaller thickness than the partition wall so that a top surface of the second sensor electrode has a step difference.

16. A display device, comprising: A sensor panel, the sensor panel comprising: substrate; a sensing portion located on the substrate, the sensing portion comprising a plurality of sensors; and The partition wall between adjacent sensors, wherein each sensor comprises a first sensor electrode, a piezoelectric layer, and a second sensor electrode sequentially formed on the substrate, and the partition wall has a lower dielectric constant than the piezoelectric layer; and a display panel located on the sensor panel, The sensing unit is disposed between the substrate and the display panel. The partition wall is disposed on the piezoelectric layer, located between adjacent first sensor electrodes and spaced apart from the first sensor electrodes.

17. The display device according to claim 16, wherein: The display panel is an electroluminescent display panel, which includes an insulating substrate and light emitting diodes located on the insulating substrate.

18. The display device according to claim 16, wherein: The partition wall is disposed between the piezoelectric layer and the second sensor electrode.

19. The display device according to claim 18, wherein: The sensor panel also includes a passivation layer on the second sensor electrode, the passivation layer having a larger modulus than the partition wall.

20. The display device according to claim 19, wherein: The passivation layer is disposed on the second sensor electrode between adjacent patterns of the partition wall, and a top surface of the passivation layer is flush with a top surface of the second sensor electrode over the partition wall.

21. The display device according to claim 20, wherein: The sensor panel also includes an adhesive layer on the passivation layer, the adhesive layer contacting the passivation layer and the second sensor electrode.

22. The display device according to claim 18, wherein: The sensor panel further includes an adhesive layer on the second sensor electrode, the adhesive layer having a modulus greater than that of the partition wall.

23. The display device according to claim 16, wherein: The sensor panel is attached to the display panel such that the plurality of sensors are arranged between the display panel and a substrate of the sensor panel.

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