Method for programming a phase change memory device, memory device, and electronic system

Abstract

Embodiments of the present disclosure relate to a method for programming a phase change memory device, a memory device, and an electronic system. A method for programming a differential type of phase change memory device includes: in a first programming mode, during a first time interval, supplying the same first programming current to all direct and complementary memory cells to be programmed with the first programming current, the first programming current being a type selected between a SET current and a RESET current; and in a second programming mode, during a second time interval, supplying the same second programming current to all direct and complementary memory cells to be programmed with the second programming current, the second programming current being another type selected between the SET current and the RESET current, thereby completing the writing of a logical word in the memory device in only two time steps.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of Italian Patent Application No. 102019000010419, filed on Jun. 28, 2019, which is incorporated herein by reference. Field of the Invention

[0003] The present invention relates to a method for programming a phase change memory device of the differential type, a phase change memory device, and an electronic system including the phase change memory device. Background Art

[0004] Non-volatile phase change memories (PCMs) are known in the art, in which, to store information, the properties of materials having the following property are exploited: the property of switching between phases with different electrical characteristics. For example, these materials can switch between a disordered amorphous phase and an ordered crystalline or polycrystalline phase, and the two phases are associated with significantly different values of resistivity and thus with different values of the stored data. For example, elements of Group VI of the periodic table (such as tellurium (Te), selenium (Se), or antimony (Sb), referred to as chalcogenide or chalcogen materials) can be advantageously used to provide phase change memory cells. The phase change is obtained as follows: by a resistive electrode (commonly referred to as a heater) arranged in contact with a corresponding region of the chalcogen material, locally raising the temperature of the cell of the chalcogen material. A selection device (e.g., a MOSFET) is connected to the heater and enables an electrical programming current to pass through the corresponding heater (referred to as "SET" and "RESET" current pulses, which have corresponding values depending on the phase change to be generated). The above current generates the temperature required for the phase change by the Joule effect. During reading, the state of the chalcogen material is detected as follows: applying a voltage low enough so as not to cause appreciable heating, and then reading the value of the current flowing in the cell. Given that the current is proportional to the conductivity of the chalcogen material, it is possible to determine which state the material is in and thus trace back to the data stored in the memory cell. Summary of the Invention

[0005] In a known manner, non-volatile memories include an array of memory cells arranged in rows (word lines) and columns (bit lines). In the case of PCM, each memory cell is formed by a phase change memory element and a selector transistor connected in series. Based on address logic signals received at the input and using more or less complex decoding schemes, column decoders and row decoders enable the selection of memory cells and, in particular, enable the selection of the corresponding word lines and bit lines addressed each time.

[0006] The column decoder includes a plurality of analog selection switches (represented by transistors), and the plurality of analog selection switches receive address signals on their respective control terminals. The selection switches are organized according to a hierarchical tree structure, and the number of selection switches at each hierarchical level is linked to the organization and the size of the memory array. When enabled, the selection switches enable the selected bit lines to be brought to a determined voltage and / or current value according to the operation to be implemented. In particular, a current path is created between the programming or read level and the selected bit lines. The above-mentioned current path is defined by a series of a certain number of selection switches.

[0007] In a known manner, the sense amplifier performs: reading the data stored in the memory cell, comparing the current (or an electrical quantity related thereto) flowing in the selected memory cell (also referred to as the "direct cell") with a reference current flowing in the complementary cell (implementing the so-called "differential read"). Obviously, the programming step must also envisage the writing of logical data in both the direct memory cell and the complementary cell. For example, writing a bit (e.g., logical "0") in the complementary cell is associated with a RESET state or a RESET pulse, while the same bit (e.g., logical "0") is written in the direct cell by a SET pulse. Therefore, each operation of writing a bit includes both the writing of the direct cell and the writing of the corresponding complementary cell to support subsequent read steps. This type of memory is called a differential memory.

[0008] To accelerate the programming (writing) operation, it is known that, according to the type of pulse to be sent (RESET or SET) and according to the type of cell (direct or complementary), several bits are written in parallel by programming the memory cells in parallel. For example, the direct cells are accessed, and those cells to be programmed with the data "0" are programmed simultaneously with the above data; then, maintaining the access to the direct cells valid, those cells to be programmed with the data "1" are programmed simultaneously with the above data. The same procedure is executed for the complementary cells.

[0009] Obviously, this type of solution has some drawbacks.

[0010] In particular, the pulses for programming the cells into the SET state and the RESET state respectively have different shapes from each other (therefore, at each pulse, the current generator must be configured to generate the correct pulse), and at least four groups of pulses, as well as the corresponding channels of the current generator configuration, must be envisaged (two for SET / RESET of the direct cells, two for SET / RESET of the complementary cells). This causes a considerable time cost in the programming step and does not allow the full utilization of the parallelism between the direct cells and the complementary cells.

[0011] The object of the present invention is to provide a method for programming a phase change memory device, as well as a phase change memory device, which will make it possible to solve, in whole or in part, the problems identified above and associated with known types of PCM devices, and will optimize the programming operations with respect to direct and complementary memory cells. The object of the present invention is also to provide an electronic system comprising such a phase change memory device.

[0012] Thus, according to the present invention, there is provided a method for programming a phase change memory device, a phase change memory device, and an electronic system comprising such a phase change memory device, as respectively defined in the appended claims.

[0013] To better understand the present invention, its preferred embodiments will now be described by way of non-limiting example only and with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To more fully understand the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1A and Figure 1B shows a corresponding circuit for programming a non-volatile memory device (in particular of the PCM type) according to an embodiment of the present invention, and for the purposes of understanding the present invention, is limited to the part of the non-volatile memory device of interest;

[0016] Figure 2 illustrates a timing diagram according to one aspect of the present invention, which timing diagram corresponds to the writing of a logical word in the Figure 1A and Figure 1B non-volatile memory device;

[0017] Figure 3 illustrates a logic circuit that generates programming pulses for direct cells and corresponding complementary cells according to the bits of the logical word to be written;

[0018] Figure 4 illustrates a simplified circuit implementation of a programming driver for direct and complementary memory cells;

[0019] Figure 5 illustrates a logic circuit according to a further embodiment of an embodiment with respect to Figure 3 that generates programming pulses for direct cells and corresponding complementary cells according to the bits of the logical word to be written; and

[0020] Figure 6 is a simplified block diagram of an electronic system incorporating a non-volatile memory device in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] According to the present invention, two programming drivers are proposed for programming memory cells, namely, a programming driver dedicated to writing to direct cells and a programming driver dedicated to writing to complementary cells. The activation of one programming driver or the other depends on the data to be written (logical data "0" or RESET; logical data "1" or SET).

[0022] In Figure 1A is schematically illustrated and generally designated by reference numeral 1 as a part of a non-volatile memory device, in particular a part of a non-volatile memory device of the PCM type, which is limited to the part required for understanding the present invention.

[0023] In particular, the memory device 1 includes: a programming driver 7 having an output 7a, and the output 7a is connected to the main bit line MBL via a corresponding selector 4a (here, as an example, a MOSFET of p-MOS type) D '; and a programming driver 9 having an output 9a, and the output 9a is connected to the main bit line MBL via a corresponding selector 5a (here, as an example, a MOSFET of p-MOS type) C '. The programming drivers 7 and 9 form a programming stage of the memory device 1.

[0024] The memory device 1 further includes a memory array 2, and the memory array 2 includes a plurality of first memory cells 3a and a plurality of second memory cells 3b, which can be selected by corresponding local word lines WL<0>, WL<1>... and local bit lines BL<0>... BL<7>. In FIG. 1, the word lines corresponding to the part of the direct cells are identified by the subscript "D" (WL D <>), while the word lines corresponding to the part of the complementary cells are identified by the subscript "C" (WL C <>); the same applies to the bit lines. In a manner known per se, the second memory cells 3b correspond to the first memory cells 3a in terms of their number and manufacturing characteristics. In use, the second memory cells 3b store logical data complementary to that stored in the first memory cells 3a. During the differential read of the first memory cells 3a, the second memory cells 3b are interrogated in order to read the logical data stored in the first memory cells 3a via a comparison as follows: comparison with the logical data stored in the corresponding second memory cells 3b.

[0025] The first memory cells 3a form a first memory portion 2a'; the second memory cells 3b form a second memory portion 2b'.

[0026] The local bit lines BL<0>-BL<7> of the first memory section 2a’ are connected to the main bit line MBL D ’. The local bit lines BL<0>-BL<7> of the second memory section 2b’ are connected to the main bit line MBL C ’.

[0027] The memory cells 3a, 3b are identical to each other and include a phase change element and a selector element (not shown in detail) operatively coupled to the phase change element. The phase change element includes a phase change material (e.g., chalcogenide) and can thus store data in the form of a resistance level that correlates to the different phases presented by the phase change material (thus, the phase change element operates like a resistor with variable resistance). The selector element is, for example, a MOS transistor that has a gate terminal connected to the respective word lines WL<0>, WL<1>…, a first conductive terminal connected to the phase change element, and a second conductive terminal connected to a reference potential (e.g., ground). The selector element is controlled such that when selected (i.e., turned on via a signal on the respective local word lines WL<0>, WL<1>… coupled thereto), a write / read current can pass through the above-mentioned phase change element during the respective operations of writing / reading logical data in the phase change element.

[0028] The non-volatile memory device 1 also includes a row decoder (not shown here), which is adapted to select the local word lines WL<0>, WL<1>… corresponding to the memory cells 3a, 3b each time it is addressed, and the non-volatile memory device 1 includes a column decoder (not shown here), which is adapted to select the bit lines of the memory cells 3a, 3b to be addressed. Given the matrix structure, the activation of the local word lines WL<0>, WL<1>, …, and the local bit lines BL<0>-BL<7> enables the unique selection of only one memory cell 3a, 3b.

[0029] A type of read stage, which is known per se and includes a sense amplifier (not shown), has inputs coupled to the main bit lines MBL D ’ and MBL C ’ respectively via switches 4a and 5a.

[0030] During writing, according to the need to access the respective main bit lines MBL D ’, MBL C ’, the switches 4a, 5a are driven to conduction and inhibition for programming the memory cells 3a, 3b connected thereto.

[0031] According to one aspect of the present invention, the programming drivers 7 and 9 are implemented by a current mirror and receive respective current signals PG at the inputIN_D [i] and PG IN_C [i], which current signal represents both the logic data (“1” or “0”) to be written and the signal to turn on or activate the corresponding programming drivers 7 and 9 so that the current signals PG IN_D [i] and PG IN_C [i] can pass through. In this way, the data to be written itself enables the corresponding programming driver 7 or 9.

[0032] The selectors 4a and 5a receive on their respective control terminals the on / off signals YNP D and YNP C . Additional selection switches 8a, 8b (p-MOS type) are provided in a manner known per se for selecting / deselecting the bit lines BL<0>-BL<7> of the first and second memory sections 2a’, 2b’. Generally, the selection switches are organized according to a tree structure by hierarchical level, and the number of selection switches in each hierarchical level is linked to the organization and the size of the memory array. Like the selection switches 8a, 8b, once enabled, the selectors 4a, 5a can bring the selected bit lines to a determined voltage and / or current value according to the operation to be performed; in particular, a current path is created between the programming level and the selected bit lines.

[0033] Figure 1B Illustrated are two programming drivers 7, 9, each programming driver being coupled to a respective plurality of main bit lines MBL D ’, MBL D ” and MBL C ’, MBL C ”. As already described and illustrated with reference to Figure 1A , connected to each main bit line are local bit lines and memory cells. In addition to what has already been described with reference to Figure 1A , in Figure 1B , the memory device 1’ further includes: a third main bit line MBL D ”, which is coupled to the programming driver 7 via a respective MOSFET selector 4b (p-MOS type); and a fourth main bit line MBL C ”, which is coupled to the programming driver 9 via a respective MOSFET selector 5b.

[0034] Coupled to the third main bit line MBL D ” are the local bit lines BL<0>-BL<7>, and coupled to each local bit line BL<0>-BL<7> are the memory cells 6a to form a memory section 2a”, which memory section 2a” repeats what has already been referred to Figure 1AThe circuit diagram described for the memory section 2a'. Similarly, coupled to the fourth main bit line MBL C ” are the local bit lines BL<0>-BL<7>, and coupled to each local bit line BL<0>-BL<7> are the memory cells 6b to form the memory section 2b”, the memory section 2b” repeating the circuit diagram described with reference to Figure 1A the memory section 2b'.

[0035] Furthermore, it can be noted that the present invention is equally applicable to a memory in which Figure 1A or Figure 1B the circuit diagram is repeated N times (where N is included, for example, between 40 and 128), and thus includes a number of programming drivers equal to 2N. FIG. 1 actually illustrates the i-th circuit diagram among the N circuit diagrams, which may exist and generally exist in large-sized memories.

[0036] In the following part of the description, reference will be made to Figure 1A without this implying any loss of generality.

[0037] The present invention contemplates that the programming of the memory cells 3a, 3b is carried out according to Figure 2 the timing diagram illustrated in.

[0038] According to one embodiment, the programming of the memory cells is carried out by words of bits, i.e., by selecting and writing the entire word line WL<0> or WL<1> etc. of the memory array 2. Thus, the content described below applies to the writing of words in the corresponding word lines, for example, the writing of a word in the word line WL<0>.

[0039] Referring to Figure 2 , in the time interval T1, a RESET pulse is generated, i.e., an electrical pulse suitable for programming the memory cells 3a, 3b addressed by the word line WL<0> to the logic state “0”. In this interval T1, all the direct cells and complementary cells in the word line WL<0> to be programmed with the RESET pulse are programmed simultaneously. For this purpose, in the time interval T1, all the programming drivers in the memory 1 coupled to the memory cells 3a, 3b to be programmed with the RESET pulse are activated, and only these programming drivers are activated. For example, if the programming driver 7 (via the corresponding main bit line MBL D ’ and the local bit line BL) is operatively coupled to the memory cell 3a to be programmed, the programming driver 7 is activated (i.e., a programming current flows through the corresponding programming driver and the main bit line to reach the memory cell 3a to be programmed).

[0040] In this way, the RESET pulse is transmitted only through the active programming drivers. At the same time, all programming drivers not operatively coupled to the memory cells to be programmed with the RESET pulse are deactivated.

[0041] In a manner known per se and corresponding to the prior art, the memory cells 3a, 3b to be programmed are addressed by appropriately selecting the corresponding word lines WL and the corresponding bit lines BL. Thus, the desired programming for all memory cells 3a, 3b to be programmed with the RESET pulse and only for these memory cells 3a, 3b is obtained, regardless of whether they are direct type cells or complementary type cells. Given that the data is differential (if the direct cell is in the SET state, the complementary cell is in the RESET state and vice versa), since there are always as many cells as the number of bits in the word, and similarly, there are as many cells to be set as the number of bits in the word, the maximum parallelism is always exploited.

[0042] During the interval T1, no SET pulses are generated.

[0043] Referring again to Figure 2 , during the time interval T2, SET pulses are generated for programming the remaining memory cells belonging to the same word line WL<0> previously selected. During this interval T2, all direct cells and complementary cells to be programmed with the SET pulse are programmed simultaneously. For this purpose, during the time interval T2, all programming drivers coupled to the main bit line are activated and only these programming drivers are activated, the main bit line in turn being coupled to the memory cells to be programmed with the SET pulse. For example, if programming driver 7 (via the corresponding main bit line MBL D ’) is operatively coupled to the cell 3a to be programmed with the SET pulse, this programming driver 7 is activated (i.e., the programming current flows through the corresponding programming driver and the main bit line to reach the memory cell).

[0044] In this way, the SET pulse is transmitted only through the active programming drivers. At the same time, all programming drivers not operatively coupled to the memory cells to be programmed with the SET pulse are deactivated.

[0045] As already said, in a manner known per se and consistent with the prior art, the memory cells 3a, 3b to be programmed are addressed by appropriately selecting the corresponding word lines WL and the corresponding bit lines BL. Thus, the desired programming for all memory cells 3a, 3b to be programmed with the SET pulse and only for these memory cells 3a, 3b is obtained, regardless of whether they are direct type cells or complementary type cells.

[0046] During time interval T2, no RESET pulse is generated.

[0047] Therefore, all cells corresponding to the word being written in the corresponding word line WL<0> in memory 2 (i.e., both direct cells and complementary cells) are programmed only in two time intervals, thereby considerably accelerating the programming step.

[0048] Obviously, interval T1 can be used to generate SET pulses, and interval T2 can be used to generate RESET pulses.

[0049] Reference Figure 3 , there is now illustrated a logic circuit 30 for generating current signals PG IN_D [i] and PG IN_C [i].

[0050] Starting from the left in Figure 3 , the logic circuit 30 includes a multiplexer 32 having two signal inputs 32a, 32b, a control input 32c, and an output 32d.

[0051] The signal inputs 32a, 32b are configured to receive logic data DATA_IN[i], which is the digital data "0" or "1" belonging to the digital word to be written in the memory. For example, in the four-bit digital word 1100, we will have DATA_IN[0] = "1", DATA_IN[1] = "1", DATA_IN[2] = "0", and DATA_IN[3] = "0".

[0052] The control input 32c receives a digital control signal SET_P presenting a digital value "0" or "1", where "0" controls the multiplexer 32 to transfer the logic data DATA_IN[i] at the input 32a (corresponding to the negated value of DATA_IN[i]) to the output 32d, and "1" controls the multiplexer 32 to transfer the logic data DATA_IN[i] at the input 32b to the output 32d.

[0053] The logic circuit 30 further includes a first NAND logic gate 34 having an input 34a connected to the output 32d of the multiplexer 32 (and receiving the logic signal DATA_DIR[i]), and an input 34b configured to receive an enable signal EN_PL_PULSE presenting a digital value "0" or "1".

[0054] The logic circuit 30 further includes a second NAND logic gate 36 having an input 36a connected to the output 32d of the multiplexer 32 (and receiving the logic signal DATA_COMP[i]) and an input 36b configured to receive the enable signal EN_PL_PULSE. The input 36a is inverted by the NOT gate 35; that is, the logic data obtained by the "NAND" gate 36 on the said input is the inverted output of the multiplexer 32, i.e., DATA_COMP[i]=NOT(DATA_DIR[i]).

[0055] The output from the NAND gate 34 is the signal ENAB_D[i], and the signal ENAB_D[i] represents the (low voltage) enable signal for the programming driver corresponding to the direct cell of the i-th bit. The output from the NAND gate 36 is the signal ENAB_C[i], and similarly represents the (low voltage) enable signal for the programming driver corresponding to the complementary cell of the i-th bit.

[0056] The logic circuit 30 further includes a first level shifter 37 and a second level shifter 41 which are respectively coupled to the output of the NAND gate 34 and the output of the NAND gate 36 for receiving the signal ENAB_D[i] and the signal ENAB_C[i]. The first and second level shifters 37, 41 have the function of shifting the signal from the value managed by the logic gate (usually, a value V within 1.2V±10%) DD12 ) to a higher value (usually, a value V within the range between 4.5V and 6V HIGH ).

[0057] The logic circuit 30 further includes a buffer 38 and a buffer 39. In view of the fact that the programming driver is of P type (i.e., if the programming driver is driven by "0", it is closed), the buffer 38 and the buffer 39 have the function of inverting the signal, thereby generating the current signals PG IN_D [i] and PG IN_C [i].

[0058] During use, the control signal SET_P at the input of the multiplexer 32 indicates whether the current time interval is Figure 2 the time interval T1 (SET_P = "0", i.e., RESET) or the time interval T2 (SET_P = "1", i.e., SET).

[0059] In the case where the current time interval is T1, the inverted logic bit of DATA_IN[i] will be passed to the output 32d of the multiplexer 32; in the case where the current time interval is T2, the logic bit of DATA_IN[i] will be transmitted to the output 32d of the multiplexer 32.

[0060] Figure 3 The number of logic circuits 30 of the type illustrated in the figure is equal to the maximum length of the digital words that can be stored in the memory 2. In fact, each logic circuit 30 receives the corresponding (ith) bit of DATA_IN[i] and generates two outputs that are adapted to form the inputs of the corresponding programming drivers 7, 9 and are adapted to control the activation and deactivation of the corresponding programming drivers 7, 9 in order to write the logic data and its complement in the corresponding addressed memory cells.

[0061] Figure 4 The circuit embodiments of the drivers 7, 9 are illustrated, and the drivers 7, 9 are activated according to the logic data to be written.

[0062] Figure 4 The circuit of includes a main or control branch 42 that includes: a current generator 44 that is configured to cooperate in generating a RESET pulse or a SET pulse according to operating conditions, the current generator 44 being connected between a reference terminal 44a (ground) and a bias terminal 44b; and a first current mirror device 48 (here, a diode-connected, P-type MOSFET) that forms the first element of a current mirror 50.

[0063] The current generator 44 and the first current mirror device 48 are connected in series between the reference ground terminal 44a and a line at a potential V HIGH (e.g., equal to 5V) to form the control branch 42. In use, a current i CTR flows between the line at a potential V HIGH and the reference ground terminal 44a.

[0064] Through the current mirror 50, the current i CTR flowing through the control branch 42 is mirrored into the corresponding programming currents I D 's, MBL C 's, etc. (i.e., all the main bit lines that form part of the memory device 1). PROG in.

[0065] From Figure 4 It can be noted that according to the activation of additional corresponding current mirror devices 56, 57 (here, P-type MOSFETs), the current I PROG (as previously mentioned, a RESET pulse or a SET pulse according to operating conditions) flows through the corresponding main bit lines MBL D ', MBL C’... , the current mirror devices 56, 57 are connected to the first current mirror device 48 in a current mirror configuration. In particular, the activation of the additional current mirror devices 56, 57 is controlled by two corresponding switches, which in turn are turned on / off by signals that are generated at the output of the logic circuit 30 from Figure 3 (i.e., the signals PG IN_D [i] and PG IN_C [i]).

[0066] Regarding the main bit line MBL D ’, there are: a switch 61 (e.g., a P-channel transistor), coupled between the gate of the current mirror device 56 and the gate of the current mirror device 48; and a switch 62 (e.g., a P-channel transistor), coupled between the gate of the current mirror device 56 and the line at the potential V HIGH . In this way, as is apparent from the illustrated circuit configuration, when the switch 61 is turned on and the switch 62 is turned off, i.e., only when the control signals ( / PG IN_D [i] and PG IN_D [i]) applied to the respective gate terminals have values such that the switch 61 enters the conducting operating state and the switch 62 enters the inhibited operating state (here, the signal PG IN_D [i] applied to the switch 62 is complementary to the signal / PG IN_D [i] applied to the switch 61), the current i CTR on the control branch 42 is mirrored in the main bit line MBL D ’. Conversely, when programming is not in progress, under the control of the signals / PG IN_D [i] and PG IN_D [i], the switch 61 is turned off and the switch 62 is turned on.

[0067] Regarding the main bit line MBL C ’, there are also: a switch 63, coupled between the gate of the current mirror device 57 and the gate of the current mirror device 48; and a switch 64, coupled between the gate of the current mirror device 57 and the line at the potential V HIGH . In this way, as is apparent from the illustrated circuit configuration, only when the switch 63 is turned on and the switch 64 is turned off, i.e., only when the respective control signals / PG IN_C [i] and PG IN_C [i] applied to the respective gate terminals of the switch 63 and the switch 64 have values such that the current i CTR on the control branch 42 is effectively mirrored in the main bit line MBL C’ in which the value is such that it causes switch 63 to enter an operating state of current conduction and causes switch 64 to enter a prohibited operating state (here, the signal PG applied to switch 64 IN_C [i] is complementary to the signal / PG applied to switch 63 IN_C [i]). Conversely, when programming is not in progress, under the control of signals / PG IN_C [i] and PG IN_C [i], switch 63 is turned off and switch 64 is turned on.

[0068] The same configuration is thus repeated for all the main bit lines (not shown here for simplicity of description) forming the memory device 1.

[0069] Figure 6 FIG. illustrates a part of an electronic system 100 according to another embodiment of the present invention. The electronic system 100 can be used in an electronic device such as a PDA (Personal Digital Assistant), a portable or fixed computer that may have wireless data transfer capabilities, a mobile phone, a digital audio player, a camera or video camera, or other devices capable of processing, storing, transmitting, and receiving information.

[0070] Specifically, the electronic system 100 includes: a controller 101 (e.g., provided with a microprocessor, DSP, or microcontroller); an input / output device 102 (e.g., provided with a keypad and a display) for inputting and displaying data; a non-volatile memory device 1 or 1’, provided with an array of the previously described phase change type memory cells; a wireless interface 104 (e.g., an antenna) for transmitting and receiving data through a radio frequency wireless communication network; and a RAM 105, all of which are coupled through a bus 106. A battery 107 can be used as a power supply source in the electronic system 100, and the electronic system can also be provided with a camera or video camera 108.

[0071] According to what is described and illustrated herein, the advantages provided by the present invention become clearly apparent.

[0072] In particular, the programming (writing) time of the memory is considerably reduced because the entire digital word (both in direct form and complementary form) is written only in two time intervals.

[0073] This also makes it possible to reduce the stress experienced by the memory and the peripheral circuits.

[0074] Furthermore, the programming control section is simplified because it is not necessary to pre-select the type of bit to be written and thus not necessary to pre-select the corresponding current pulses (SET / RESET) to be generated.

[0075] Finally, it is clear that modifications and variations can be made to what has been described and illustrated herein without departing from the scope of the invention as defined by the appended claims.

[0076] Figure 5 A logic circuit 30' is shown, which in addition to the elements already described with reference to Figure 3 also includes additional AND logic gates 72, 74 (optional), which are arranged between the output of the multiplexer 32 and the inputs 34a of the logic gate 34 and the input 36a of the logic gate 36, respectively.

[0077] The AND logic gate 72 has three inputs 72a - 72c and one output 72d. The input 72a is coupled to the output 32d of the multiplexer 32, while the other inputs 72b and 72c receive the respective signals MODIFY_DIR[i] and MASK_PAR[i]. The signal MODIFY_DIR[i] is a logic data "1" or "0", and indicates whether a modification (MODIFY_DIR[i] = "1") in the write is required for the corresponding logic data DATA_IN[i] at the input, for example, due to a previous write error detected at the test level. The signal MASK_PAR[i] is a logic data "1" or "0", and indicates write parallelism (in fact, due to the limitation of the maximum current that can be delivered, it is not always possible to program the number of bits equal to the number of words in a manner known per se).

[0078] The output 72d of the AND logic gate 72 generates a signal DATA_DIR[i], which is supplied to the input 34a of the logic gate 34.

[0079] The AND logic gate 74 has three inputs 74a - 74c and one output 74d. The input 74a is coupled to the output 32d of the multiplexer 32 via an inverter (to receive inverted logic data), while the other inputs 74b and 74c receive the respective signals MODIFY_COMP[i] and MASK_PAR[i]. The signal MODIFY_COMP[i] has a function similar to that of the signal MODIFY_DIR[i]. The same applies to the signal MASK_PAR[i]. The output 74d of the AND logic gate 74 generates a signal DATA_COMP[i], which is supplied to the input 36a of the logic gate 36.

Claims

1. A method for programming a phase change memory device, the phase change memory device including a memory array, the memory array including a plurality of first portions, each first portion being provided with a first local bit line, the first local bit line being connected to a first memory cell, the first memory cell being adapted to store corresponding first logic data, the first logic data including a first logic bit associated with a first resistance state of the first memory cell and a second logic bit associated with a second resistance state of the first memory cell, the memory array further including corresponding plurality of second portions, each second portion being provided with a second local bit line, the second local bit line being connected to a second memory cell, the second memory cell being adapted to store corresponding second logic data complementary to the first logic data ； The phase change memory device further includes: a write level for writing the logic data in the first memory cell and the second memory cell, the write level having a plurality of first programming drivers and corresponding plurality of second programming drivers; a plurality of first main bit lines extending between the corresponding first programming drivers and the first local bit lines of the corresponding first portions; and a plurality of second main bit lines extending between the corresponding second programming drivers and the second local bit lines of the corresponding second portions, the method including: In a first programming mode, during a first time interval, supply, through the plurality of first programming drivers and the plurality of second programming drivers, the same first programming current to all the first memory cells and the second memory cells to be programmed with the first programming current, the first programming current being a type selected between a set current and a reset current; and In a second programming mode, during a second time interval, supply, through the plurality of first programming drivers and the plurality of second programming drivers, the same second programming current to all the first memory cells and the second memory cells to be programmed with the second programming current, the second programming current being another type selected between the set current and the reset current, thereby completing the writing of a logic word in the memory array.

2. The method according to claim 1, wherein: During the first programming mode: All the first programming drivers coupled to the first memory cells to be programmed with the first programming current are activated by corresponding first activation signals, the first activation signals being generated starting from the first logic bit; and All the second programming drivers are activated by corresponding second activation signals, the second activation signals being generated starting from the second logic bit; and During the second programming mode: All the first programming drivers coupled to the first memory cells to be programmed with the second programming current are activated by corresponding third activation signals, the third activation signals being generated starting from the second logic bit; and All of the second programming drivers coupled to the second memory cells are activated by respective fourth activation signals that are generated starting from the first logic bit.

3. The method according to claim 2, wherein each of the plurality of first programming drivers includes a respective first current mirror circuit configured to receive the first programming current and the second programming current during respective ones of the first programming mode and the second programming mode, the method further comprises: During respective ones of the first programming mode and the second programming mode, supplying the first programming current and the second programming current to the first main bit line through respective ones of the first current mirror circuits; and Connecting or disconnecting the first main bit line from the respective first current mirror circuit according to a first value that is activated by the first activation signal and the third activation signal.

4. The method according to claim 3, wherein each of the plurality of second programming drivers includes a respective second current mirror circuit configured to receive the first programming current and the second programming current during respective ones of the first programming mode and the second programming mode, the method further comprises: During respective ones of the first programming mode and the second programming mode, supplying the first programming current and the second programming current to the second main bit line through respective ones of the second current mirror circuits; and Connecting or disconnecting the second main bit line from the respective second current mirror circuit according to a second value that is activated by the second activation signal and the fourth activation signal.

5. The method according to claim 1, wherein: During the first programming mode and during the first time interval, supplying the first programming current and the second programming current comprises: Supplying the first programming current to all of the first memory cells to be programmed with the first logic bit through the plurality of first programming drivers; and Supplying the second programming current to all of the second memory cells complementary to the first memory cells to be programmed with the first logic bit through the plurality of second programming drivers; and During the second programming mode and during the second time interval, supplying the first programming current and the second programming current comprises: Supplying the second programming current to all of the first memory cells to be programmed with the second logic bit through the plurality of second programming drivers; and Supplying the first programming current to all of the second memory cells complementary to the first memory cells to be programmed with the second logic bit through the plurality of second programming drivers.

6. The method according to claim 5, wherein: During the first programming mode: All of the first programming drivers coupled to the first memory cells to be programmed by the first programming current are activated by respective first activation signals that are generated starting from the first logic bit; and all of the second programming drivers are activated by respective second activation signals that are generated starting from the second logic bit; and During the second programming mode: All of the first programming drivers coupled to the first memory cells to be programmed by the second programming current are activated by respective third activation signals that are generated starting from the second logic bit; and All of the second programming drivers coupled to the second memory cells are activated by respective fourth activation signals that are generated starting from the first logic bit.

7. The method according to claim 6, wherein each of the plurality of first programming drivers includes a respective first current mirror circuit configured to receive the first programming current and the second programming current during respective ones of the first programming mode and the second programming mode, the method further comprises: During respective ones of the first programming mode and the second programming mode, supplying the first programming current and the second programming current to the first main bit line through the respective first current mirror circuit; and Electrically connecting or disconnecting the first main bit line from the respective first current mirror circuit according to a first value that is activated by the first activation signal and the third activation signal.

8. The method according to claim 7, wherein each of the plurality of second programming drivers includes a respective second current mirror circuit configured to receive the first programming current and the second programming current during respective ones of the first programming mode and the second programming mode, the method further comprises: During respective ones of the first programming mode and the second programming mode, supplying the first programming current and the second programming current to the second main bit line through the respective second current mirror circuit; and Electrically connecting or disconnecting the second main bit line from the respective second current mirror circuit according to a second value that is activated by the second activation signal and the fourth activation signal.

9. A phase change memory device, comprising: A memory array, comprising: A plurality of first portions, each first portion being provided with a first local bit line connected to a first memory cell adapted to store respective first logic data, the first logic data including a first logic bit associated with a first resistance state of the first memory cell and a second logic bit associated with a second resistance state of the first memory cell; and A corresponding plurality of second portions, each second portion being provided with a second local bit line, the second local bit line being connected to a second memory cell, the second memory cell being adapted to store corresponding second logic data complementary to the first logic data; A write stage for writing the logic data in the first memory cell and the second memory cell, including a plurality of first programming drivers and corresponding plurality of second programming drivers; A plurality of first main bit lines extending between the corresponding first programming drivers and the first local bit lines of the corresponding first portions; and A plurality of second main bit lines extending between the corresponding second programming drivers and the second local bit lines of the corresponding second portions, wherein the phase change memory device is configured to: In a first programming mode, supply, by the plurality of first programming drivers and the plurality of second programming drivers and during a first time interval, the same first programming current to all the first memory cells and the second memory cells to be programmed with the first programming current, the first programming current being a type selected between a set current and a reset current; and In a second programming mode, supply, by the plurality of first programming drivers and the plurality of second programming drivers and during a second time interval, the same second programming current to all the first memory cells and the second memory cells to be programmed with the second programming current, the second programming current being another type selected between the set current and the reset current, thereby completing the writing of a logic word in the memory array.

10. The phase change memory device according to claim 9, wherein: During the first programming mode: All the first programming drivers coupled to the first memory cells to be programmed via the first programming current are activated by corresponding first activation signals, the first activation signals being generated starting from the first logic bit; And All the second programming drivers are activated by corresponding second activation signals, the second activation signals being generated starting from the second logic bit; and During the second programming mode: All the first programming drivers coupled to the first memory cells to be programmed via the second programming current are activated by corresponding third activation signals, the third activation signals being generated starting from the second logic bit; And All the second programming drivers coupled to the second memory cells are activated by corresponding fourth activation signals, the fourth activation signals being generated starting from the first logic bit.

11. The phase change memory device according to claim 10, wherein each first programming driver of the plurality of first programming drivers includes a corresponding first current mirror circuit, the first current mirror circuit being configured to receive the first programming current and the second programming current during the corresponding first programming mode and the second programming mode, Each first current mirror circuit is coupled to a common reference branch configured to generate the first programming current and the second programming current, and each first current mirror circuit includes a plurality of respective first programming branches coupled to the reference branch and the first main bit line to mirror the first programming current and the second programming current on the first programming branches. Each first programming branch is coupled to the reference branch through a respective first enable switch configured to be selectively driven to conduction and inhibition by the first activation signal and the third activation signal.

12. The phase change memory device according to claim 11, wherein each of the plurality of second programming drivers includes a respective second current mirror circuit configured to receive the first programming current and the second programming current during respective ones of the first programming mode and the second programming mode. The second current mirror circuit includes a plurality of second programming branches coupled to the reference branch and the second main bit line for mirroring the first programming current and the second programming current. Each second programming branch is coupled to the reference branch through a respective second enable switch configured to be selectively driven to conduction and inhibition by the second activation signal and the fourth activation signal.

13. The phase change memory device according to claim 9. Wherein: During the first programming mode and during the first time interval, supplying the first programming current and the second programming current includes: Supplying the first programming current to all of the first memory cells to be programmed with the first logic bit through the plurality of first programming drivers; and Supplying the second programming current to all of the second memory cells complementary to the first memory cells to be programmed with the first logic bit through the plurality of second programming drivers; and During the second programming mode and during the second time interval, supplying the first programming current and the second programming current includes: Supplying the second programming current to all of the first memory cells to be programmed with the second logic bit through the plurality of second programming drivers; and Supplying the first programming current to all of the second memory cells complementary to the first memory cells to be programmed with the second logic bit through the plurality of second programming drivers.

14. The phase change memory device according to claim 13. Wherein: During the first programming mode: All of the first programming drivers coupled to the first memory cells to be programmed via the first programming current are activated by respective first activation signals generated starting from the first logic bit; And All of the second programming drivers are activated by respective second activation signals that are generated starting from the second logic bit; and During the second programming mode: All of the first programming drivers coupled to a first memory cell to be programmed via the second programming current are activated by respective third activation signals that are generated starting from the second logic bit; And All of the second programming drivers coupled to a second memory cell are activated by respective fourth activation signals that are generated starting from the first logic bit.

15. The phase change memory device according to claim 14, wherein each of the plurality of first programming drivers includes a respective first current mirror circuit configured to receive the first programming current and the second programming current during the respective first programming mode and the second programming mode, Each first current mirror circuit is coupled to a common reference branch configured to generate the first programming current and the second programming current, and each first current mirror circuit includes a plurality of respective first programming branches coupled to the reference branch and the first main bit line to mirror the first programming current and the second programming current on the first programming branches, Each first programming branch is coupled to the reference branch through a respective first enable switch configured to be selectively driven to be conductive and inhibited by the first activation signal and the third activation signal.

16. The phase change memory device according to claim 15, wherein each of the plurality of second programming drivers includes a respective second current mirror circuit configured to receive the first programming current and the second programming current during the respective first programming mode and the second programming mode, The second current mirror circuit includes a plurality of second programming branches coupled to the reference branch and the second main bit line for mirroring the first programming current and the second programming current, Each second programming branch is coupled to the reference branch through a respective second enable switch configured to be selectively driven to be conductive and inhibited by the second activation signal and the fourth activation signal.

17. An electronic system, Comprising: A controller; A random access memory coupled to the controller; A wireless interface coupled to the controller; And A phase change memory device coupled to the controller, the phase change memory device comprising: A memory array, the memory array comprising: A plurality of first portions, each first portion being provided with a first local bit line, the first local bit line being connected to a first memory cell, the first memory cell being adapted to store corresponding first logic data, the first logic data including a first logic bit associated with a first resistance state of the first memory cell and a second logic bit associated with a second resistance state of the first memory cell; and Corresponding plurality of second portions, each second portion being provided with a second local bit line, the second local bit line being connected to a second memory cell, the second memory cell being adapted to store corresponding second logic data complementary to the first logic data; A write stage for writing the logic data in the first memory cell and the second memory cell, including a plurality of first programming drivers and corresponding plurality of second programming drivers; A plurality of first main bit lines, the plurality of first main bit lines extending between the corresponding first programming drivers and the first local bit lines of the corresponding first portions; and A plurality of second main bit lines, the plurality of second main bit lines extending between the corresponding second programming drivers and the second local bit lines of the corresponding second portions, wherein the phase change memory device is configured to: In a first programming mode, through the plurality of first programming drivers and the plurality of second programming drivers and during a first time interval, supply the same first programming current to all the first memory cells and the second memory cells to be programmed with the first programming current, the first programming current being a type selected between a set current and a reset current; and In a second programming mode, through the plurality of first programming drivers and the plurality of second programming drivers and during a second time interval, supply the same second programming current to all the first memory cells and the second memory cells to be programmed with the second programming current, the second programming current being another type selected between the set current and the reset current, thereby completing the writing of a logic word in the memory array.

18. The electronic system according to claim 17, wherein the electronic system is selected from the following group, the group including: Personal digital assistant (PDA), portable computer, mobile phone, smart phone, tablet computer, digital audio player, camera or video camera.

19. The electronic system according to claim 17, wherein: During the first programming mode: All the first programming drivers coupled to the first memory cells to be programmed via the first programming current are activated by corresponding first activation signals, the first activation signals being generated starting from the first logic bit; and All the second programming drivers are activated by corresponding second activation signals, the second activation signals being generated starting from the second logic bit; and During the second programming mode: All of the first programming drivers coupled to the first memory cells to be programmed via the second programming current are activated by respective third activation signals generated starting from the second logic bit; and All of the second programming drivers coupled to the second memory cells are activated by respective fourth activation signals generated starting from the first logic bit.

20. The electronic system according to claim 17, wherein: In the first programming mode and during the first time interval, supplying the first programming current and the second programming current includes: supplying the first programming current to all of the first memory cells to be programmed with the first logic bit via the plurality of first programming drivers; and supplying the second programming current to all of the second memory cells complementary to the first memory cells to be programmed with the first logic bit via the plurality of second programming drivers; and In the second programming mode and during the second time interval, supplying the first programming current and the second programming current includes: supplying the second programming current to all of the first memory cells to be programmed with the second logic bit via the plurality of second programming drivers; and supplying the first programming current to all of the second memory cells complementary to the first memory cells to be programmed with the second logic bit via the plurality of second programming drivers.

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