Display device

Abstract

A display device is provided, the display device includes a panel, the panel includes a substrate and an insulating layer, the substrate includes a display area in which pixels are arranged and a pad area in which a terminal portion connected to the display area is arranged, the insulating layer is arranged on the same layer in the display area and the pad area. The thickness of the insulating layer in the display area and the thickness of the insulating layer in the pad area are different thicknesses.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0078339, filed on June 28, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device, and to an organic light emitting display device in which a pad region including a terminal portion to which a driving chip is connected has an improved structure. Background Art

[0004] A display device such as an organic light emitting display device includes, for example, a panel including a display region and a pad region on a substrate, and a driving chip connected to a terminal portion of the pad region.

[0005] Therefore, a display area in which an image is realized and a driving chip serving as a controller are connected to each other through the terminal portion, and when the connection is stably established, the display device can operate smoothly.

[0006] It should be understood that the background of the present technology section is intended to provide, in part, a useful background for understanding the technology. However, the background of the present technology section may also include ideas, concepts or understandings that are not part of the ideas, concepts or understandings that a person skilled in the relevant art would have known or understood before the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] One or more embodiments include an improved display device in which a stable connection between a terminal portion in a pad region and a driving chip may be achieved.

[0008] According to one or more embodiments, a display device may include a panel and a driving chip, the panel including a substrate and an insulating layer, the substrate including a display area in which a plurality of pixels are arranged and a pad area in which a terminal portion connected to the display area is arranged, the insulating layer being arranged on the same layer in the display area and the pad area, wherein a thickness of the insulating layer in the display area and a thickness of the insulating layer in the pad area are different thicknesses, and the driving chip is connected to the terminal portion of the pad area.

[0009] The thickness of the insulating layer in the pad region may be smaller than the thickness of the insulating layer in the display region.

[0010] The thickness of the insulating layer in the entire pad region may be smaller than the thickness of the insulating layer in the display region.

[0011] The terminal portion may be a closed loop, and a thickness of the insulating layer in an inner part of the closed loop within the pad region may be smaller than a thickness of the insulating layer in an outer part of the closed loop.

[0012] The thickness of the insulating layer in the pad region may be about 50% or less of the thickness of the insulating layer in the display region.

[0013] A difference between a thickness of the insulating layer in the pad region and a thickness of the terminal portion in the pad region may be about 50% or less of the thickness of the terminal portion.

[0014] In each of the multiple pixels in the display area, the active layer, the gate electrode, the first source-drain electrode, the second source-drain electrode and the pixel electrode may be stacked, and the insulating layer may include a first through-hole layer between the first source-drain electrode and the second source-drain electrode and a second through-hole layer between the second source-drain electrode and the pixel electrode.

[0015] In an embodiment, a display device may include: a substrate including a display area in which a plurality of pixels are arranged and a pad area in which a terminal portion connected to the display area is arranged; a driving chip connected to the terminal portion of the pad area; and an insulating layer arranged on the same layer in the display area and the pad area. The insulating layer may include a first through-hole layer and a second through-hole layer in the pad area and in the display area, and the thickness of the first through-hole layer and the second through-hole layer in the pad area may be different from the thickness of the first through-hole layer and the second through-hole layer in the display area. The terminal portion may include an input terminal and an output terminal. The thickness of the first through-hole layer and the second through-hole layer between the input terminal and the output terminal may be less than the thickness of the first through-hole layer and the second through-hole layer in the display area. The thickness of the insulating layer in the pad area may be about 50% or less of the thickness of the insulating layer in the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a plan view of a display device according to an embodiment of the present disclosure;

[0018] Figure 2 is along Figure 1 A schematic cross-sectional view taken along line II-II of ;

[0019] Figure 3A and Figure 3B This is a diagram of connecting the driver chip to Figure 2 A schematic cross-sectional view of a process for manufacturing a terminal portion of the device;

[0020] Figure 4is a schematic cross-sectional view illustrating a process of connecting a driver chip to a terminal portion having a structure as a comparative example;

[0021] FIG. 5A to FIG. 5E It is used to describe manufacturing Figure 2 A schematic cross-sectional view of a method for displaying a device as shown in FIG. 1 ; and

[0022] Figure 6 is a schematic cross-sectional view of a pad region of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to an embodiment, an example of which is illustrated in the accompanying drawings, wherein the same reference numerals refer to the same elements throughout. In this regard, the embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments described below with reference to the accompanying drawings are only used to explain the aspects of the description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. A statement such as "at least one of...", when located after a list of elements, modifies the list of the entire element and does not modify the individual elements in the list.

[0024] Since the present disclosure allows various changes and numerous embodiments, aspects of the embodiments will be illustrated in the drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and methods for implementing them will be more fully described with reference to the drawings in which embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0025] One or more embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The same or corresponding components are given the same reference numerals regardless of the figure number, and redundant descriptions are omitted.

[0026] Furthermore, in this specification, the phrase “in a plan view” means when the subject portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross-section taken by vertically cutting the subject portion is viewed from the side.

[0027] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0028] It will be further understood that when used in this specification, the terms "include" and / or "comprises" may indicate the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of other features, integers, steps, operations, elements, parts and / or combinations thereof.

[0029] When a layer, film, zone, substrate or region is referred to as being "on" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly on another layer, film, zone, substrate or region, or an intermediate layer, film, zone, substrate or region may exist between the layer, film, zone, substrate or region and another layer, film, zone, substrate or region. On the contrary, when a layer, film, zone, substrate or region is referred to as being "directly on" another layer, film, zone, substrate or region, there may not be an intermediate layer, film, zone, substrate or region between the layer, film, zone, substrate or region and another layer, film, zone, substrate or region. In addition, when a layer, film, zone, substrate or region is referred to as being "below" another layer, film, zone, substrate or region, the layer, film, zone, substrate or region may be directly below another layer, film, zone, substrate or region, or an intermediate layer, film, zone, substrate or region may exist between the layer, film, zone, substrate or region and another layer, film, zone, substrate or region. Conversely, when a layer, film, region, substrate, or area is referred to as being "directly below" another layer, film, region, substrate, or area, there may be no intervening layers, films, regions, substrates, or areas between the layer, film, region, substrate, or area and the other layer, film, region, substrate, or area. In addition, "above" or "on" may include placement on or below an object and does not necessarily imply a direction based on gravity.

[0030] For ease of description, spatially relative terms such as "below," "below," "down," "above," or "on" may be used herein to describe the relationship between one element or component and another element or component as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, in the case where the device illustrated in the accompanying drawings is flipped, a device placed "below" or "below" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both a lower position and an upper position. The device may also be positioned in other directions, and thus the spatially relative terms may be interpreted differently depending on the orientation.

[0031] Throughout the specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element or “indirectly connected” to the other element with one or more intervening elements interposed therebetween.

[0032] It will be understood that although the terms "first", "second", or "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate the description and explanation of the elements. For example, when discussed in the description, a "first element" may be named a "second element" or a "third element", and the "second element" and the "third element" may be named in a similar manner without departing from the teachings herein.

[0033] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 5% of the stated value.

[0034] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0035] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described successively can be performed substantially at the same time, or in the reverse order of the described order.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined in the specification.

[0037] Figure 1 The plan view and plan structure of a display device according to an embodiment of the present disclosure are illustrated. An organic light emitting display device is illustrated as an example of a display device. Although the organic light emitting display device is illustrated as an example, other displays can be expected according to the spirit and scope of the present disclosure.

[0038] like Figure 1 As shown in FIG. 1 , in the panel of the organic light emitting display device, the display area DA and the pad area PA ( FIG. 5A to FIG. 5E ) may be provided over the substrate 100, pixels P are arranged in the display area DA and an image is realized, and the pad area PA has a terminal portion 130 provided on the pad area PA and electrically connected to the display area DA.

[0039] The terminal portion 130 may include an input terminal 131 and an output terminal 132, and the driver chip 10 (eg, see Figure 3A ) can be coupled and connected to the terminal portion 130. In other words, Figure 3A The driving chip 10 and the display area DA may be connected to each other through the terminal portion 130 .

[0040] Reference numeral 110 indicates a scan driver that applies a scan signal to a scan line SL arranged in the display area DA according to a signal of the driving chip 10. Reference numeral 120 indicates a data driver that applies a data signal to a data line DL arranged in the display area DA according to a signal of the driving chip 10. The driving chip 10 may be connected to the display area DA via the terminal portion 130, the scan driver 110, and the data driver 120, and when the connection between the driving chip 10 and the terminal portion 130 is unstable, image realization on the display area DA may not be properly completed.

[0041] Therefore, according to the embodiment, in order to stably connect the driving chip 10 and the terminal part 130, the insulating layer 133 formed on the same layer in the display area DA and the pad area PA, respectively, has the following structure: Figure 2 The improved structure shown in .

[0042] Figure 2 is along Figure 1 1 is a schematic cross-sectional view taken along line II-II of , and illustrates the structure of the pixel P in the display area DA on the right and the vicinity of the terminal portion 130 in the pad area PA on the left.

[0043] Since the pixel P and the terminal portion 130 can be formed at the same time by stacking several conductive layers and several insulating layers on the substrate 100, the materials used to form the corresponding elements can be the same. For example, while layers such as the first gate electrode G1 of the pixel P (which can also serve as the lower electrode of the capacitor to be described later), the first source-drain electrode SD1, and the second source-drain electrode SD2 are formed, the input terminal 131 and the output terminal 132 of the terminal portion 130 can be formed. While layers such as the first through-hole layer VIA1 and the second through-hole layer VIA2 among several insulating layers arranged in the pixel P are stacked, the insulating layer 133 surrounding the terminal portion 130 can be formed.

[0044] The thickness d1 and d2 of the first through hole layer VIA1 and the second through hole layer VIA2 of the insulating layer 133 arranged in the pad area PA may be made smaller than the thickness D1 and D2 of the first through hole layer VIA1 and the second through hole layer VIA2 arranged in the pixel P of the display area DA. When the first through hole layer VIA1 and the second through hole layer VIA2 are formed using a photolithography process, the difference between the thickness of the display area DA and the pad area PA may be generated by using a half-tone mask through the difference in exposure and etching to achieve the difference in thickness of the through hole layers VIA1 and VIA2 in their respective areas. The thickness d1 and d2 of the first through hole layer VIA1 and the second through hole layer VIA2 of the insulating layer 133 arranged in the pad area PA are made thinner to prevent the increase of the step difference between the insulating layer 133 and the input terminal 131 and the output terminal 132. When the step difference is greatly increased due to the increase in the difference between the thickness h1 of each of the input terminal 131 and the output terminal 132 and the thickness h2 of the insulating layer 133, when Figure 3A Problems such as electrical connection problems may occur when the driving chip 10 may be later connected to the display area DA through the terminal portion 130. Therefore, in order to prevent the electrical connection problem, the thicknesses d1 and d2 of the first and second via layers VIA1 and VIA2 of the insulating layer 133 arranged in the pad area PA are made about 50% or less of the thicknesses D1 and D2 of the first and second via layers VIA1 and VIA2 arranged in the display area DA.

[0045] To understand how step differences can occur, we will now refer to FIG. 3A to FIG. 4 The process of connecting the driving chip 10 is described below. Figure 3A and Figure 3B A schematic cross-sectional view illustrating a process of connecting the driving chip 10 to the terminal portion 130 and a structure of the embodiment is illustrated, and Figure 4 A structure having a severe step difference according to a comparative example different from the embodiments herein is illustrated.

[0046] like Figure 3A As shown in , when the driver chip 10 is connected to the terminal portion 130 , the driver chip 10 is pressed downward and attached to the terminal portion 130 using the anisotropic conductive film 20 placed between the bumps 11 of the driver chip 10 and the input terminals 131 and output terminals 132 of the terminal portion 130 .

[0047] The anisotropic conductive film 20 includes conductive balls 21 distributed therein, and when Figure 3B When the anisotropic conductive film 20 is pressed, a large number of conductive balls 21 need to be distributed between the bumps 11 and the input terminals 131 and the output terminals 132 so that the driving chip 10 can be stably electrically connected to the terminal portion 130 .

[0048] However, if the thickness h2' of the insulating layer 133 is significantly greater than the thickness h1 of each of the input terminal 131 and the output terminal 132, then Figure 4 There is a large step difference as shown in . When the driver chip 10 is pressed down and attached to the terminal portion 130, a large mass flow occurs in the anisotropic conductive film 20 in the direction from the center to the outside of the anisotropic conductive film 20, and therefore a large number of conductive balls 21 slide out and flow to the outside. In other words, since the gap between the driver chip 10 and the insulating layer 133 is relatively smaller than the gap between the protrusion 11 and the input terminal 131 and the output terminal 132, a large pressure is applied to the center of the anisotropic conductive film 20, and therefore when the driver chip 10 is pressed and attached, the conductive balls 21 are unevenly distributed and slide out and flow to the outside. The conductive balls 21 are hardly distributed between the protrusion 11 and the input terminal 131 and the output terminal 132, resulting in an electrically unstable connection. In other words, the number of conductive balls that facilitate proper electrical connection is compromised due to the aforementioned large step difference.

[0049] In order to prevent this unstable connection problem, the thicknesses d1 and d2 of the insulating layer 133 in the pad area PA are made approximately half or less of the thicknesses D1 and D2 of the insulating layer 133 in the display area DA, and thus the difference between the thickness h2 of the insulating layer 133 and the thickness h1 of each of the input terminal 131 and the output terminal 132 is made approximately 50% or less of the thickness h1 of each of the input terminal 131 and the output terminal 132.

[0050] When the insulating layer 133 does not initially exist in the pad area PA, connection failure due to the step difference may not occur. However, since the embedded circuit 134 (or inspection circuit) for checking whether the electrical signal is correctly connected in the product assembly stage is arranged in the pad area PA, the insulating layer 133 needs to cover and protect the embedded circuit 134.

[0051] A process of manufacturing a display device having such a structure will be described in detail later, and the internal structure of the pixel P of the display area DA will now be described in more detail.

[0052] refer to Figure 2 In order to structure the pixels P in the display area DA, the substrate 100 may include a glass material or a polymer resin or any other suitable material.

[0053] A buffer layer 101 for preventing impurities from penetrating into an active layer ACT of a thin film transistor may be formed on a substrate 100. The buffer layer 101 may include an inorganic insulating material such as silicon nitride, silicon oxynitride, or silicon oxide, and may be a single layer or multiple layers including the inorganic insulating material.

[0054] The thin film transistor and the capacitor may be arranged on the buffer layer 101. The thin film transistor may include an active layer ACT, a first gate electrode G1, and a first source-drain electrode SD1. According to an embodiment, the thin film transistor may be a top gate type in which the first gate electrode G1 is arranged on the active layer ACT and the first gate insulating layer 102 is between the first gate electrode G1 and the active layer ACT. However, according to an embodiment, the thin film transistor may be a bottom gate type.

[0055] The active layer ACT may include polysilicon. As an example, the active layer ACT may include amorphous silicon, an oxide semiconductor, an organic semiconductor, etc. The first gate electrode G1 may include a low-resistance metal material. The first gate electrode G1 may include a conductive material including, for example, molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and the first gate electrode G1 may be formed as a multilayer or a single layer including the foregoing materials.

[0056] The first gate insulating layer 102 between the active layer ACT and the first gate electrode G1 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. The first gate insulating layer 102 may be a single layer or multiple layers including the foregoing materials.

[0057] The first source-drain electrode SD1 may be on the same layer as the scan line SL and may include the same material as included in the scan line SL. For example, the first source-drain electrode SD1 and the scan line SL may include aluminum (Al) having low resistance and high conductivity.

[0058] The capacitor may include a lower electrode and an upper electrode G2 overlapping each other, and the second gate insulating layer 103 is between the lower electrode and the upper electrode G2. The capacitor may overlap with the thin film transistor. In other words, the first gate electrode G1 of the thin film transistor may also serve as the lower electrode of the capacitor. The top of the upper electrode G2 may be covered by the interlayer insulating layer 104. The upper electrode G2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu) and titanium (Ti), and the upper electrode G2 may be formed as a multilayer or a single layer including the aforementioned materials.

[0059] The term "overlapping" may include layer, stacked, facing, extending over, covering or partially covering or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The term "non-overlapping" may include "spaced apart" or "disposed beside" or "offset" and any other suitable equivalents as would be appreciated and understood by one of ordinary skill in the art.

[0060] The second gate insulating layer 103 and the interlayer insulating layer 104 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, or hafnium oxide. Each of the second gate insulating layer 103 and the interlayer insulating layer 104 may be a single layer or multiple layers including the foregoing materials.

[0061] The thin film transistor and the capacitor may be covered by the first via layer VIA1. An upper surface of the first via layer VIA1 may include an approximately flat surface.

[0062] The second source-drain electrode SD2 used as a contact metal layer may be between the thin film transistor and the pixel electrode 221. The second source-drain electrode SD2 may contact the thin film transistor through a contact hole formed in the first through-hole layer VIA1, and the pixel electrode 221 may contact the second source-drain electrode SD2 through a contact hole formed in the second through-hole layer VIA2. The second source-drain electrode SD2 may be on the same layer as the layer on which the data line DL is located, and may include the same material as that included in the data line DL. For example, the second source-drain electrode SD2 and the data line DL may include aluminum (Al) having low resistance and high conductivity. Therefore, the first source-drain electrode SD1 and the second source-drain electrode SD2, the scan line SL, and the data line DL may all include the same low-resistance metal material.

[0063] The first through-hole layer VIA1 and the second through-hole layer VIA2 of the insulating layer 133 may include an organic insulating material such as a commercial polymer (such as polymethyl methacrylate ("PMMA") or polystyrene ("PS")), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend of the foregoing materials. According to an embodiment, the first through-hole layer VIA1 and the second through-hole layer VIA2 may include polyimide. The list of materials for the first through-hole layer VIA1 and the second through-hole layer VIA2 of the insulating layer 133 is non-exhaustive and may include other suitable materials as will be appreciated and understood by those of ordinary skill in the art.

[0064] The pixel electrode 221 may be on the second through hole layer VIA2. The pixel electrode 221 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to an embodiment, the pixel electrode 221 may include a reflective layer containing, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound of these materials. According to an embodiment, the pixel electrode 221 may include a conductive oxide of ITO, IZO, ZnO, or In above / below the reflective layer. 2 O 3 The film formed.

[0065] The pixel defining layer 215 may be on the pixel electrode 221. The pixel defining layer 215 may include an opening through which the upper surface of the pixel electrode 221 is exposed, and may cover the edge of the pixel electrode 221. The pixel defining layer 215 may include an organic insulating material. As an example, the pixel defining layer 215 may include an organic insulating material such as silicon nitride (SiN x ), silicon oxynitride (SiON) or silicon oxide (SiO x As another example, the pixel defining layer 215 may include an organic insulating material and an inorganic insulating material.

[0066] The emission layer 222 on the pixel electrode 221 may include a low molecular or high molecular organic material that emits light of a certain color. For example, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) may be stacked on the pixel electrode 221 to be adjacent to the emission layer 222.

[0067] The emission layer 222 can be formed independently in each pixel so that pixels emitting red light, green light, and blue light constitute a single pixel unit, or the emission layer 222 can be formed together over the entire pixel area, regardless of the position of the pixel. For example, the emission layer 222 can be formed, for example, by vertically stacking a layer of a light-emitting substance that emits red light, a layer of a light-emitting substance that emits green light, and a layer of a light-emitting substance that emits blue light, or by mixing a layer of a light-emitting substance that emits red light, a layer of a light-emitting substance that emits green light, and a layer of a light-emitting substance that emits blue light. Any combination of various other colors of emitted white light can be used. The display device may include a color conversion layer or a color filter that converts the emitted white light into light of a given color.

[0068] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include a transparent or semi-transparent layer containing, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy of these materials.

[0069] When the first gate electrode G1 and the first and second source-drain electrodes SD1 and SD2 of the display area DA are formed, the input terminal 131 and the output terminal 132 of the pad area PA may also be formed. When the first and second via layers VIA1 and VIA2 are formed, the insulating layer 133 of the pad area PA may also be formed. The embedded circuit 134 may be on the same layer as the first gate electrode G1 and one of the first and second source-drain electrodes SD1 and SD2 are on, and may include the same material as the material included in the first gate electrode G1 and one of the first and second source-drain electrodes SD1 and SD2.

[0070] The display device having such a structure can be FIG. 5A to FIG. 5E The method shown in the figure is used to manufacture.

[0071] like Figure 5A As shown in FIG. 1 , a buffer layer 101 and a first gate insulating layer 102 may be formed in the display area DA and the pad area PA over the substrate 100, and a first gate electrode G1 of the display area DA may be formed over the first gate insulating layer 102. Respective lower portions of the input terminal 131 and the output terminal 132 may be formed over the same layer in the pad area PA as the layer over which the first gate electrode G1 may be formed, and may be formed of the same material as that used to form the first gate electrode G1.

[0072] like Figure 5B As shown in , the upper electrode G2 and the first source-drain electrode SD1 may be formed in the display area DA. The respective middle portions of the input terminal 131 and the output terminal 132 may be formed on the same layer as the layer on which the first source-drain electrode SD1 may be formed in the pad area PA, and may be formed of the same material as the material used to form the first source-drain electrode SD1. The embedded circuit 134 may also be formed.

[0073] like Figure 5C As shown in , the first via layer VIA1 may be formed in both the display area DA and the pad area PA. As described above, the thickness d1 of the first via layer VIA1 in the pad area PA is made about half or less of the thickness D1 of the first via layer VIA1 in the display area DA by using a half-tone mask so as to reduce the step difference caused by the difference between the thickness of each of the input terminal 131 and the output terminal 132 and the thickness of the insulating layer 133 as described above.

[0074] like Figure 5DAs shown in , the second source-drain electrode SD2 may be formed in the display area DA. The respective upper portions of the input terminal 131 and the output terminal 132 may be formed on the same layer as the layer on which the second source-drain electrode SD2 may be formed in the pad area PA, and may be formed of the same material as the material used to form the second source-drain electrode SD2.

[0075] like Figure 5E As shown in , the second via layer VIA2 can be formed in both the display area DA and the pad area PA. Similarly, by using a half-tone mask, the thickness d2 of the second via layer VIA2 in the pad area PA can be made approximately half or less of the thickness D2 of the second via layer VIA2 in the display area DA. In the pad area PA, the thickness h2 of the insulating layer 133 and the thickness h1 of each of the input terminal 131 and the output terminal 132 can become similar to each other, and thus a step difference can be rarely generated. Even when the step difference may not be completely prevented, when the step difference is approximately 50% or less of the thickness h1 of each of the input terminal 131 and the output terminal 132, a large mass flow of the conductive ball 21 can be sufficiently prevented from occurring in the anisotropic conductive film 20 (see FIG. 2 ) when the driving chip 10 is attached. Figure 3B )middle.

[0076] When the pixel electrode 221, the emission layer 222 and the counter electrode 223 are formed, as shown in FIG. Figure 2 The display device shown in can be implemented.

[0077] When the driver chip 10 is connected to the terminal portion 130 of the pad area PA of the display device according to the above, the driver chip 10 is pressed down and attached to the terminal portion 130, and the anisotropic conductive film 20 is placed between the bump 11 of the driver chip 10 and the input terminal 131 and the output terminal 132 of the terminal portion 130, as shown in FIG. Figure 3A and Figure 3B as shown in .

[0078] Therefore, almost no step difference can be generated between the insulating layer 133 and the input terminal 131 and the output terminal 132, and thus a large mass flow may not occur in the anisotropic conductive film 20, and thus, appropriate conductive balls 21 can be distributed between the protrusion 11 and the input terminal 131 and the output terminal 132, resulting in an electrically stable connection.

[0079] Therefore, a stable connection between the terminal portion 130 and the driving chip 10 can be ensured, and thus, a connection failure of the driving chip 10 can be prevented, thereby improving the reliability of the product.

[0080] According to the above-described embodiment, the formation of the thickness h2 of the thin insulating layer 133 with respect to the pad area PA is illustrated. Figure 6 As shown in , the insulating layer 133 existing between the input terminal 131 and the output terminal 132 may be formed to be thin, or the insulating layer 133 existing only between the input terminal 131 and the output terminal 132 may be formed to be thin.

[0081] In other words, Figure 1 As shown in , the pad area PA may be located at the lower end portion of the panel, and the terminal portion 130 may have the shape of a closed loop whose center may be hollow. According to the embodiment described above, the insulating layer 133 may be formed to be thin in the entire lower end portion of the panel (ie, the pad area PA). However, since the insulating layer 133 does not have to be an obstacle when the driver chip 10 can be attached, the entire pad area PA may not be formed to be thin, but the space between the input terminal 131 and the output terminal 132 facing the driver chip 10 (ie, only the inside of the closed loop) may be formed to be thin, or only the space between the input terminal 131 and the output terminal 132 facing the driver chip 10 (ie, only the inside of the closed loop) may be formed to be thin. In other words, the thickness of the insulating layer 133 inside the closed loop in the pad area PA may be less than the thickness of the insulating layer outside the closed loop.

[0082] Still, a stable connection between the terminal portion 130 and the driving chip 10 can be ensured.

[0083] Therefore, according to the display device of the embodiment described above, a stable connection between the terminal portion 130 and the driving chip 10 of the pad area PA can be ensured, and a connection failure of the driving chip 10 can be prevented, resulting in an improvement in the reliability of the product.

[0084] It should be understood that the embodiments described herein should be considered to be merely descriptive and not for limiting purposes. The description of the features or aspects in each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various modifications in form and detail may be made in one or more embodiments without departing from the spirit and scope as defined by the appended claims.

Claims

1. A display device, comprising: A panel, comprising: a substrate, comprising a display area and a pad area, wherein a plurality of pixels are arranged in the display area, wherein a terminal portion connected to the display area is arranged in the pad area, wherein the terminal portion comprises an input terminal and an output terminal, wherein the input terminal and the output terminal are defined in a hollow area between the input terminal and the output terminal; and an insulating layer arranged on the same layer in the display region and the pad region, and arranged in the hollow region and spaced apart from the input terminal and the input terminal, wherein a thickness of the insulating layer in the display region and a thickness of the insulating layer in the pad region are different thicknesses; and A driving chip is connected to the terminal portion of the pad area.

2. The display device according to claim 1, wherein: The thickness of the insulating layer in the pad region is smaller than the thickness of the insulating layer in the display region.

3. The display device according to claim 2, wherein: The thickness of the insulating layer in the entire pad region is smaller than the thickness of the insulating layer in the display region.

4. The display device according to claim 2, wherein: The terminal portion is a closed loop, and The thickness of the insulating layer inside the closed loop in the pad region is smaller than the thickness of the insulating layer outside the closed loop.

5. The display device according to claim 2, wherein: The thickness of the insulating layer in the pad region is 50% or less of the thickness of the insulating layer in the display region.

6. The display device according to claim 2, wherein: A difference between the thickness of the insulating layer in the pad region and the thickness of the terminal portion in the pad region is 50% or less of the thickness of the terminal portion.

7. The display device according to claim 1, wherein: In each of the plurality of pixels in the display area, an active layer, a gate electrode, a first source-drain electrode, a second source-drain electrode, and a pixel electrode are stacked, and The insulating layer includes a first via layer between the first source-drain electrode and the second source-drain electrode and a second via layer between the second source-drain electrode and the pixel electrode.

8. A display device, comprising: A substrate, the substrate comprising a display area and a pad area, wherein a plurality of pixels are arranged in the display area, wherein a terminal portion connected to the display area is arranged in the pad area, wherein the terminal portion comprises an input terminal and an output terminal, wherein the input terminal and the output terminal are defined in a hollow area between the input terminal and the output terminal; A driving chip connected to the terminal portion of the pad area; as well as an insulating layer arranged on the same layer in the display region and the pad region, and arranged in the hollow region and spaced apart from the input terminal and the input terminal, wherein the insulating layer includes a first through-hole layer and a second through-hole layer in the pad region and in the display region, The thickness of the first through-hole layer and the second through-hole layer in the pad area is different from the thickness of the first through-hole layer and the second through-hole layer in the display area.

9. The display device according to claim 8, wherein: The thickness of the first and second via layers between the input and output terminals is smaller than the thickness of the first and second via layers in the display region.

10. The display device according to claim 8, wherein: The thickness of the insulating layer in the pad region is 50% or less of the thickness of the insulating layer in the display region.

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