Power factor correction at a switch mode power supply

Abstract

Embodiments of a method and an apparatus are disclosed. In one embodiment, a method for power factor correction (PFC) at a switch mode power supply (SMPS) is disclosed. The method involves receiving an input voltage, generating a reference waveform in phase with the input voltage, determining a time value for phase shifting a PFC current signal, scaling the time value with a phase factor to generate a scaled time value, phase shifting the reference waveform according to the scaled time value to generate a phase shifted reference waveform, and generating the PFC current signal based on the phase shifted reference waveform.

Description

Technical Field

[0001] This invention relates to power factor correction at switch-mode power supplies. Background Technology

[0002] A power supply is an electrical device that supplies electricity to electrical loads. The primary function of a power supply is to convert the voltage and current from a source into the correct voltage and current to power the load. Therefore, power supplies are sometimes called power converters.

[0003] The power factor (PF) of an alternating current (AC) power system is defined as the ratio of the actual power absorbed by the load to the apparent power flowing in the circuit, and is a dimensionless number in a closed interval from -1 to 1. A power factor less than one indicates that the voltage and current are out of phase, thus reducing their instantaneous product. Actual power is the instantaneous product of voltage and current and represents the ability of electricity to do work. Apparent power is the average product of current and voltage. Apparent power can be greater than actual power, attributable to energy stored in the load and returned to the source, or to nonlinear loads that distort the waveform of the current drawn from the source. A negative power factor occurs when a device (usually a load) generates electricity and that electricity then flows back towards the source.

[0004] In power systems, for the same amount of useful power delivered, a load with a low power factor draws more current than a load with a high power factor. Power factor correction (PFC) increases the power factor of a load, thereby improving the efficiency of the distribution system to which it is attached. Passive networks of capacitors or inductors can be used to correct linear loads (e.g., induction motors) with low power factors. Nonlinear loads, such as rectifiers, distort the current drawn from the system. In these cases, active or passive power factor correction can be used to counteract the distortion and increase the power factor.

[0005] The capacitors used to filter input current noise in a PFC circuit (electromagnetic interference (EMI) filter capacitors) can result in a lower power factor (PF) in a switch-mode power supply (SMPS). However, depending on the location of the EMI filter capacitor in the PFC circuit (e.g., after the bridge rectifier), the total harmonic distortion (THD) can increase, especially at low output loads in the SMPS. Therefore, a PFC technique is needed that can improve PF while reducing THD in the SMPS. Summary of the Invention

[0006] Embodiments of a method and an apparatus are disclosed. In one embodiment, a method for power factor correction (PFC) at a switch-mode power supply (SMPS) is disclosed. The method involves: receiving an input voltage; generating a reference waveform in phase with the input voltage; determining a time value for phase-shifting a PFC current signal; scaling the time value with a phase factor to generate a scaled time value; phase-shifting the reference waveform according to the scaled time value to generate a phase-shifted reference waveform; and generating a PFC current signal based on the phase-shifted reference waveform.

[0007] In one embodiment of the method, the time value is determined according to the following equation: time value = arctan(C*ω*Vac / Iac) / ω, where C is the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS, ω is the frequency of the input voltage, Vac is the input voltage, and Iac is the regulating current signal.

[0008] In one embodiment of the method, the current signal is adjusted to regulate the output voltage of the SMPS to the target reference voltage.

[0009] In one embodiment of the method, the phase factor is a value greater than 0 and less than 1.

[0010] In one embodiment of the method, generating a PFC current signal based on a phase-shifted reference waveform involves multiplying the phase-shifted reference waveform by an adjusted current signal to generate a phase-shifted current signal, and rectifying the phase-shifted current signal to generate a PFC current signal.

[0011] In one embodiment of the method, the method further relates to outputting a PFC current signal when both the input voltage and the voltage of the phase-shifted reference waveform have a value greater than zero or when both the input voltage and the voltage of the phase-shifted reference waveform have a value less than zero.

[0012] In one embodiment of the method, the SMPS includes a power stage, and the method further relates to receiving a PFC current signal at a pulse width modulator (PWM) in the power stage; and outputting a PWM signal from the PWM to a switch such that the average current in the inductor in the power stage is equal to the PFC current signal.

[0013] In one embodiment of the method, determining the time value for phase shifting the PFC current signal involves: generating an input current waveform based on the frequency of the input voltage and the regulating current signal; generating a capacitor current waveform based on the input voltage, the frequency of the input voltage, and the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS; comparing the capacitor current waveform with the input current waveform; and determining the time value based on the time when the input current waveform equals the capacitor current waveform.

[0014] In one embodiment of the method, the input current waveform is generated according to the following equation: Input current waveform = Iac*sin(ωt), where Iac is the adjustment current signal, ω is the frequency of the input voltage, and t is a value greater than 0.

[0015] In one embodiment of the method, the capacitor current waveform is generated according to the following equation: capacitor current waveform = C*ω*Vac*cos(ωt), where C is the total capacitance of the one or more EMI filter capacitors, ω is the frequency of the input voltage, Vac is the input voltage, and t is a value greater than 0.

[0016] In one embodiment, a switch-mode power supply (SMPS) configured for power factor correction (PFC) is disclosed. The SMPS includes: a reference signal generation circuit configured to receive an input voltage and generate a reference waveform in phase with the input voltage; a processing circuit configured to determine a time value for phase-shifting a PFC current signal; a scaling circuit configured to scale the time value with a phase factor to generate a scaled time value; a phase-shifted signal generation circuit configured to phase-shift the reference waveform according to the scaled time value to generate a phase-shifted reference waveform; and a PFC signal generation circuit configured to generate a PFC current signal based on the phase-shifted reference waveform.

[0017] In one embodiment of SMPS, the processing circuit is configured to determine the time value according to the following equation: Time value = arctan(C*ω*Vac / Iac) / ω, where C is the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in SMPS, ω is the frequency of the input voltage, Vac is the input voltage, and Iac is the regulating current signal.

[0018] In one embodiment of the SMPS, the current signal is adjusted to regulate the output voltage of the SMPS to a target reference voltage.

[0019] In one embodiment of SMPS, the phase factor is a value greater than 0 and less than 1.

[0020] In one embodiment of SMPS, the PFC signal generation circuit configured to generate a PFC current signal is further configured to multiply the phase-shifted reference waveform by an adjustment current signal to generate a phase-shifted current signal, and to rectify the phase-shifted current signal to generate a PFC current signal.

[0021] In one embodiment of the SMPS, the SMPS further includes a switching circuit configured to output a PFC current signal when both the input voltage and the voltage across the phase-shifted reference waveform are greater than zero, or when both the input voltage and the voltage across the phase-shifted reference waveform are less than zero.

[0022] In one embodiment of the SMPS, the SMPS further includes a power stage, the power stage including a pulse width modulator (PWM), a switch connected to the PWM, and an inductor connected to the switch, wherein the PWM is configured to receive a PFC current signal and output the PWM signal to the switch such that the average current in the inductor is equal to the PFC current signal.

[0023] In one embodiment of the SMPS, the processing circuit configured to determine the time value is further configured to: generate an input current waveform based on the frequency of the input voltage and the regulating current signal; generate a capacitor current waveform based on the input voltage, the frequency of the input voltage, and the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS; compare the capacitor current waveform with the input current waveform; and determine the time value based on the time when the input current waveform equals the capacitor current waveform.

[0024] In one embodiment of SMPS, the processing circuit is configured to generate the input current according to the following equation: Input current waveform = Iac*sin(ωt), where Iac is the regulating current signal, ω is the frequency of the input voltage, and t is a value greater than 0.

[0025] In one embodiment of SMPS, the processing circuit is configured to generate a capacitor current waveform according to the following equation: capacitor current waveform = C * ω * Vac * cos(ωt), where C is the total capacitance of the one or more EMI filter capacitors, ω is the frequency of the input voltage, Vac is the input voltage, and t is a value greater than 0. Attached Figure Description

[0026] Figure 1 An example of a switch-mode power supply (SMPS) with boost power factor correction (PFC) circuitry is depicted.

[0027] Figure 2 A simplified example of an SMPS with a boost-type PFC circuit is depicted.

[0028] Figure 3 Describe the waveforms of a conventional SMPS with a PFC circuit.

[0029] Figure 4 Describe the waveforms of a conventional SMPS with a PFC circuit that includes the current waveforms of the EMI filter capacitor.

[0030] Figure 5 The waveforms of an SMPS with a PFC circuit including a PFC current waveform phase-shifted according to conventional methods are depicted.

[0031] Figure 6 Waveforms of an SMPS having a PFC circuit including a PFC current waveform phase-shifted according to the method of this disclosure are depicted.

[0032] Figure 7 Describe the waveform of an SMPS with a PFC circuit, which is Figure 6 The subgroup of waveforms depicted in the text.

[0033] Figure 8 This is a graph of total harmonic distortion (THD) versus power factor (PF) for an example application.

[0034] Figure 9 Describe the components of an analog implementation of an SMPS with PFC circuitry.

[0035] Figure 10 Describe the components of a digital implementation of an SMPS with PFC circuitry.

[0036] Figure 11A Describe an example of an analog reference signal generation circuit, and Figure 11B Describe an example of a digital reference signal generation circuit.

[0037] Figure 12 This is a flowchart of an example method for power factor correction (PFC) at a switch-mode power supply (SMPS). Detailed Implementation

[0038] It is readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following more detailed descriptions of the various embodiments illustrated in the figures are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. While various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0039] The invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments should be considered in all respects as illustrative rather than restrictive. Therefore, the scope of the invention is indicated by the appended claims rather than by a detailed description thereof. All variations within the meaning and scope of the equivalents of the claims are covered within its scope.

[0040] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable with this invention should be included in or in any single embodiment of the invention. In fact, language relating to features and advantages should be understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, discussions of features and advantages throughout this specification, as well as similar language, may (but are not necessarily) refer to the same embodiment.

[0041] Furthermore, the features, advantages, and characteristics described in this invention can be combined in any suitable manner in one or more embodiments. Those skilled in the art will recognize that, in view of the description herein, this invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be identified in certain embodiments.

[0042] References to "one embodiment," "an embodiment," or similar language throughout this specification mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but not necessarily all, refer to the same embodiment.

[0043] Figure 1 An example of a switch-mode power supply (SMPS) 100 with boost power factor correction (PFC) circuitry is depicted. SMPS 100 includes an AC trunk input voltage (Vin) 102, a bridge rectifier (BR) 104, a first capacitor (C1) 106, a second capacitor (C2) 108, a switching element (S1) 110, an inductor (Lpfc) 112, a rectifier diode (DI) 114, and an output capacitor (C3) 116.

[0044] The AC trunk input voltage (Vin) 102 supplies voltage to the SMPS 100. The first capacitor (C1) 106 and the second capacitor (C2) 108 are filter capacitors for electromagnetic interference (EMI). In some applications, common-mode and differential-mode inductors may also be present. A bridge rectifier (BR) 104 converts the AC trunk input voltage (Vin) 102 into a rectified input voltage (Vrect). The rectified input voltage (Vrect) is used to generate a PFC current (Ipfc), which is, for example, a switching current with a switching frequency of 100 kHz.

[0045] The power stage of the SMPS 100 may include a switching element (S1) 110, an inductor (Lpfc) 112, a rectifier diode (D1) 114, and an output capacitor (C3) 116. The output voltage (Vout) 118 of the power stage is typically higher than the peak value of the AC trunk input voltage (Vin) 102. In some applications, the output of the power stage may be connected to another SMPS, such as a flyback circuit or an LLC circuit.

[0046] Figure 2 A simplified example of a switch-mode power supply (SMPS) 200 with boost-type power factor correction (PFC) circuitry is depicted. SMPS 200 is... Figure 1The simplified model of SMPS 100 is shown in the figure. SMPS 200 includes an AC trunk input voltage (Vin) 202, a bridge rectifier (BR) 204, a first capacitor (C1) 206, a second capacitor (C2) 208, and a current source 110.

[0047] The AC trunk input voltage (Vin) 202 supplies voltage to the SMPS 200. The first capacitor (C1) 206 and the second capacitor (C2) 208 are filter capacitors for electromagnetic interference (EMI). In some applications, common-mode and differential-mode inductors may also be present. A bridge rectifier (BR) 204 converts the AC trunk input voltage (Vin) 202 to a rectified input voltage (Vrect). The rectified input voltage (Vrect) is used to generate the average PFC current (Ipfc_average). It is worth noting that, unlike... Figure 1 In this context, Ipfc represents the switching current. Figure 2 In this context, Ipfc_average represents the average value of the switching current. Therefore, Figure 2 The image depicts a current source 210 corresponding to the average value of the switching current, as shown in the image. Figure 1 The switching element (S1), inductor (Lpfc), rectifier diode (D1) and / or output capacitor (C3) depicted in the figure are in contrast.

[0048] Figure 3 The waveform 300 depicts a typical SMPS with PFC circuitry. The waveforms shown include the voltage waveform for the rectified input voltage (Vrect), and the current waveforms for the switching PFC current (Ipfc_switching), the average PFC current (Ipfc_average), and the input current (Iin). It is worth noting that the switching PFC current (Ipfc_switching) is not based on... Figure 3 The horizontal scale is extracted. The switching PFC current (Ipfc_switching) can have a switching frequency of, for example, 100 kHz. The average PFC current (Ipfc_average) is the average value of the switching PFC current (Ipfc_switching) and is in phase with the mains input voltage (Vin). The mains input voltage can typically have a frequency of, for example, 50 Hz or 60 Hz.

[0049] Figure 4A waveform 400 is depicted for a conventional SMPS with a PFC circuit including the current waveform of the EMI filter capacitor. The waveforms shown include voltage waveforms for the mains input voltage (Vin) and the rectified input voltage (Vrect), and current waveforms for the first capacitor current (Ic1), the second capacitor current (Ic2), the average PFC current (Ipfc_average), and the input current (Iin). The input current (Iin) is equal to the sum of the first capacitor current (Ic1), the second capacitor current (Ic2), and the average PFC current (Ipfc_average).

[0050] The power factor (PF) of an AC power system can be defined as the ratio of the actual power absorbed by the load to the apparent power flowing in the circuit (PF = actual power / apparent power). Actual power is the instantaneous product of voltage and current, representing the electrical system's ability to do work. Apparent power is the average product of current and voltage.

[0051] Ideally, PF should be a value of 1 (PF = 1). A power factor less than one indicates that the voltage and current are out of phase, thus reducing their instantaneous product. Here, when PF = 1, the SMPS acts as a resistor against the mains input voltage (Vin), and the input current (Iin) is in phase with the mains input voltage (Vin).

[0052] However, as Figure 4 As shown, the first capacitor current (Ic1) is phase-shifted by 90 degrees relative to the mains input voltage (Vin). The input current (Iin) is phase-shifted by approximately 30 degrees relative to the mains input voltage (Vin). Therefore, corresponding to Figure 4 The power factor of the waveform is not equal to 1. Although the average PFC current (Ipfc_average) is in phase with the mains input voltage (Vin), the input current (Iin), which is the sum of the first capacitor current (Ic1), the second capacitor current (Ic2), and the average PFC current (Ipfc_average), is not in phase with the mains input voltage (Vin) due to the presence of capacitor currents Ic2 and Ic3. In addition to the power factor not being equal to 1, the input current (Iin) is also not an ideal sine wave. Distortion on the input current (Iin) produces higher harmonics, which means that the total harmonic distortion (THD) is greater than zero.

[0053] Figure 5A waveform 500 depicts an SMPS with a PFC circuit including a PFC current waveform phase-shifted according to conventional methods. The waveforms shown include voltage waveforms for the mains input voltage (Vin) and the rectified input voltage (Vrect), and current waveforms for the first capacitor current (Ic1), the second capacitor current (Ic2), the average PFC current (Ipfc_average), and the input current (Iin). The input current (Iin) is equal to the sum of the first capacitor current (Ic1), the second capacitor current (Ic2), and the average PFC current (Ipfc_average).

[0054] like Figure 5 As shown, the average PFC current (Ipfc_average) is calculated based on the phase shift time t1 of the conventional method used to improve the power factor. Correspondingly, the input current (Iin) is now in phase with the mains input voltage (Vin) (and not in phase with the mains input voltage). Figure 4 (This contrasts with the input current). Thus, the average PFC current (Ipfc_average) is phase-shifted by time t1, resulting in an improvement in the power factor (e.g., relative to the input current). Figure 4 (electricity factor). However, although the electricity factor has been improved, such as Figure 5 As shown, the input current (Iin) is still significantly distorted. The large distortion in the input current (Iin) indicates that the total harmonic distortion (THD) is not at its lowest possible value.

[0055] Figure 6 A waveform 600 of an SMPS having a PFC circuit including a PFC current waveform with phase shift according to the method of this disclosure is depicted. The waveform shown includes voltage waveforms for the mains input voltage (Vin) and the rectified input voltage (Vrect), and current waveforms for the first capacitor current (Ic1), the second capacitor current (Ic2), the average PFC current (Ipfc_average), and the input current (Iin). The input current (Iin) is equal to the sum of the first capacitor current (Ic1), the second capacitor current (Ic2), and the average PFC current (Ipfc_average).

[0056] like Figure 6 As shown, the average PFC current (Ipfc_average) is partially phase-shifted by time t2 according to the method for improving the power factor disclosed herein. Correspondingly, a small phase shift exists between the input current (Iin) and the mains input voltage (Vin). Thus, the partial phase shift time t2 of the average PFC current (Ipfc_average) causes the power factor to be relatively... Figure 4 The power factor achieved in this process is improved. However, the phase shift time t2 of the average PFC current cannot be relative to... Figure 5The power factor implemented in [the system] improves the power factor. However, in [the context of this], Figure 6 In the middle, the distortion on the input current (Iin) is compared to Figure 5 The distortion on the input current shown is significantly reduced. The reduced distortion on the input current (Iin) indicates... Figure 6 The total harmonic distortion (THD) shown is relative to Figure 5 The THD shown is significantly improved. Therefore, although partially shifting the average PFC current (Ipfc_average) by the phase shift time t2 may result in a smaller improvement in the power factor, a larger improvement in THD is achieved.

[0057] Figure 7 The waveform 700 of the SMPS with PFC circuitry is depicted. Figure 6 The waveforms depicted are subgroups. The waveforms shown include current waveforms for the first capacitor current (Ic1), the second capacitor current (Ic2), the average PFC current (Ipfc_average), and the input current (Iin). Figure 7 In the diagram, the current waveform is depicted on a vertical scale to show how the sum of the first capacitor current (Ic1), the second capacitor current (Ic2), and the average PFC current (Ipfc_average) equals the input current (Iin).

[0058] In one embodiment, the input voltage Vin(t) can be determined by equation (1):

[0059] (1) Vin(t)=Vac*sin(ωt), where Vac is the peak trunk input voltage and ω is the trunk input voltage frequency in radians / second.

[0060] In one embodiment, in order for the SMPS to behave like a resistive load on the mains input voltage, the input current Iin(t) can be determined by equation (2):

[0061] (2) Iin(t)=Iac*sin(ωt), where Iac is the current used to adjust the output voltage to the target reference voltage.

[0062] In one embodiment, the total capacitor current Ic(t) can be determined by equation (3):

[0063] (3) Ic(t)=C*dVin(t) / dt=C*ω*Vac*cos(ωt), where C is the sum of all EMI filter capacitors (e.g., C=C1+C2).

[0064] In one embodiment, the PFC current Ipfc(t) is determined by equation (4):

[0065] (4)Ipfc(t)=Iin(t)-Ic(t)=Iac*sin(ωt)-C*ω*Vac*cos(ωt).

[0066] In one embodiment, the phase-shifted PFC current can begin at t = t1, where t1 is the point in time at which the waveforms for the input current Iin(t) and the capacitor current Ic(t) intersect (e.g., Iin(t1) = Ic(t1)). Accordingly, the value of t1 can be determined according to equations (5) to (8):

[0067] (5) Iin(t1)=Ic(t1)→Iac*sin(ωt1)=C*ω*Vac*cos(ωt1), which is equivalent to equation (6).

[0068] (6) sin(ωt1) / cos(ωt1)=C*ω*Vac / Iac, which is equivalent to equation (7).

[0069] (7) tan(ωt1)=C*ω*Vac / Iac, and therefore, t1 can be determined by equation (8).

[0070] (8)t1=arctan(C*ω*Vac / Iac) / ω.

[0071] In one embodiment, the partially phase-shifted PFC current may begin at t = t2. The value of t2 can be determined by equation (9):

[0072] (9) t2 = α * t1, where α is the phase factor.

[0073] It is worth noting that a phase factor α with a value equal to 0 (α = 0) can produce a result similar to that relative to... Figure 4 The power factor (PF) and total harmonic distortion (THD) are described. Furthermore, a phase factor α with a value equal to 1 (α = 1) can produce a result similar to that relative to... Figure 5 The PF and THD are described. Accordingly, embodiments of this disclosure implement a phase factor α having a value between 0 and 1. By selecting a phase factor α greater than 0 but less than 1, the PF and THD can be optimized depending on application requirements.

[0074] Figure 8This is graph 800 showing the total harmonic distortion (THD) versus power factor (PF) for an example application. As shown, for the example application, the lowest THD is achieved by implementing a phase factor α equal to 0.3 (α = 0.3). Compared to conventional phase-shifting methods used to improve the power factor (where α = 0), the PF is improved from nearly 0.90 to nearly 0.94, while the THD is improved from nearly 8% to nearly 2%. If a better PF is needed, the phase factor α can be set to a larger value, at the cost of higher THD.

[0075] In one embodiment, THD can be optimized by minimizing distortion on the input current Iin. (See also...) Figure 6 The minimum distortion on the input current Iin is achieved when Δt1 = Δt2. The phase factor α used for minimum THD depends on the total capacitance before and after the bridge rectifier (e.g., BR 104). For low capacitance after the bridge rectifier, a low phase factor α can be set, for example, α = 0.2. For high capacitance after the bridge rectifier, a higher phase factor α can be set, for example, α = 0.5.

[0076] Figure 9 The components of an analog implementation of the SMPS 900 with PFC circuitry are depicted. A proportional-integral (PI) regulator 916 generates a regulated current signal (Iac) that is intended to regulate the output voltage (Vout) to a target voltage (Vref). A reference signal generation circuit 902 generates a sinusoidal reference signal (ref) in phase with the mains input voltage (Vac). The following description is related to... Figure 11A and 11B Discuss an example of the reference signal generation circuit 902.

[0077] Processing circuit 940, configured to determine the time value for phase shifting the PFC current (Ipfc), includes a multiplier 904, a capacitor current circuit 906, a comparator 908, a crossover point determiner 910, and a phase sampler 912. A sinusoidal reference signal (ref) is multiplied by an adjustment current signal (Iac) via multiplier 904. The output of multiplier 904 is a sinusoidal signal (Iin(t)) with an amplitude proportional to Iac (Iin(t) = Iac * sin(ωt)). The capacitor current circuit 906 outputs a sinusoidal signal (Ic(t)) with an amplitude proportional to the sum of the currents in the EMI filter capacitors present in the SMPS 900, for example, Ic1 + Ic2 = Ic(t) = C * ω * Vac * cos(ωt), where C = C1 + C2.

[0078] In one embodiment, the PFC current (Ipfc) can be phase-shifted by a time value t = t1, where t1 is the point in time when the input current waveform intersects (or equals) the capacitor current waveform. Accordingly, the output of multiplier 904 is compared with the output of capacitor current circuit 906 by comparator 908. The output of comparator 908 switches at the time value (t = t1) where the output of multiplier 904 equals the output of capacitor current circuit 906 (e.g., at t = t1: Iac*sin(ωt1) = C*ω*Vac*cos(ωt1)). Crossover point determiner 910 determines the point where the sinusoidal signal output by multiplier 904 intersects with the sinusoidal signal output by capacitor current circuit 906.

[0079] Phase sampler 912 samples the phase of the sinusoidal reference signal (ref) based on the intersection point determined by intersection point determiner 910. The sampled phase corresponds to the time value t = t1. The time value t1 is scaled by a phase factor α via a scaling circuit (e.g., multiplier) 914 to generate a scaled time value t2. The scaled time value t2 can be used to partially phase shift the PFC current (Ipfc).

[0080] A phase-shifted signal generation circuit (e.g., a sine wave generator) 918 generates a phase-shifted sine wave signal by scaling a sine wave reference signal (ref) by a time value t2. A PFC signal generation circuit 942, configured to generate a PFC current (Ipfc), includes a multiplier 920 and a rectifier 922. The multiplier 920 multiplies the output signal (Iac) of the PI regulator 916 by the phase-shifted sine wave signal. The output of the multiplier 920 is rectified by the rectifier 922 to generate a rectified signal (PFC current signal (Ipfc)). The rectified signal is switched by a switch 924 to output a predetermined PFC current signal (Ipfc).

[0081] In one embodiment, switch 924 closes to output a predetermined PFC current signal (Ipfc) when both the phase-shifted voltage and the mainline input voltage (Vac) are positive or both are negative (e.g., sign_shifted*sign_mains > 0). The determination of whether the mainline input voltage (Vac) is positive or negative can be performed by the mainline input voltage sign comparator 926. The determination of whether the phase-shifted voltage is positive or negative can be performed by the phase-shifted voltage comparator 928.

[0082] The power stage 944 of the SMPS 900 includes at least a pulse width modulator (PWM) 930, a switch (S1) 932, and an inductor (Lpfc) 934. The PWM 930 receives a predetermined PFC current signal (Ipfc) and outputs the PWM signal to the switch (S1) 932 such that the average current in the inductor (Lpfc) 934 is equal to the predetermined PFC current signal (Ipfc). In one embodiment, the PWM 930 may be, for example, a hysteresis control module, where (Ipk_high + Ipk_low) / 2 = Ipfc, where Ipk_high is the maximum current in the inductor (Lpfc) 934 and Ipk_low is the minimum current in the inductor (Lpfc) 934.

[0083] Figure 10 Components of a digital implementation of an SMPS 1000 with PFC circuitry are depicted. In one embodiment, relative to... Figure 10 All signals described (e.g., t1, t2, Iac, Ipfc, etc.) are digital signals. Furthermore, relative to... Figure 10 All circuit elements described are digital state machines or digital processors.

[0084] The proportional-integral (PI) regulator 1016 generates a predetermined regulating current signal (Iac) to adjust the output voltage (Vout) to a target voltage (Vref). The reference signal generation circuit 1002 generates a sinusoidal reference signal (ref) in phase with the mains input voltage (Vac). The following is related to... Figure 11A and 11B Discuss an example of the reference signal generation circuit 1002.

[0085] In one embodiment, the PFC current (Ipfc) can be phase-shifted by a time value t = t1, where t1 is the point in time where the input current waveform intersects with the capacitor current waveform. Accordingly, the digital processor 1040 can determine the time value t1 based on the mains input voltage (Vac), the regulating current signal (Iac), the mains input voltage frequency (ω) in radians per second, and the total capacitance of the EMI filter capacitors present in the SMPS 1000 (e.g., C = C1 + C2). For example, the digital processor 1040 can determine the time t1 value based on the following equation:

[0086] t1=arctan(C*ω*Vac / Iac) / ω.

[0087] Digital processor 1040 outputs time value t1 to scaling circuit (e.g., multiplier) 1014. Scaling circuit 1014 scales time value t1 by a phase factor α to generate scaled time value t2. Scaled time value t2 can be used to partially phase shift the PFC current (Ipfc).

[0088] A phase-shifted signal generation circuit (e.g., a sine wave generator) 1018 generates a phase-shifted sine wave signal by scaling a sine wave reference signal (ref) by a time t2 value. A PFC signal generation circuit 1042, configured to generate a PFC current (Ipfc), includes a multiplier 1020 and a rectifier 1022. The multiplier 1020 multiplies the output signal (Iac) of the PI regulator 1016 by the phase-shifted sine wave signal. The output of the multiplier 1020 is rectified by the rectifier 1022 to generate a rectified signal (PFC current (Ipfc)). The rectified signal is switched by a switch 1024 to output a predetermined PFC current signal (Ipfc).

[0089] In one embodiment, switch 1024 closes to output a predetermined PFC current signal (Ipfc) when both the phase-shifted voltage and the mainline input voltage (Vac) are positive or both are negative (e.g., sign_shifted*sign_mains > 0). The determination of whether the mainline input voltage (Vac) is positive or negative can be performed by the mainline input voltage sign comparator 1026. The determination of whether the phase-shifted voltage is positive or negative can be performed by the phase-shifted voltage comparator 1028.

[0090] The power stage 1044 of the SMPS 1000 includes at least a pulse width modulator (PWM) 1030, a switch (S1) 1032, and an inductor (Lpfc) 1034. The PWM 1030 receives a predetermined PFC current signal (Ipfc) and outputs the PWM signal to the switch (S1) 1032, such that the average current in the inductor (Lpfc) 1034 is equal to the predetermined PFC current signal (Ipfc). In one embodiment, the PWM 1030 may be, for example, a hysteresis control module, where (Ipk_high + Ipk_low) / 2 = Ipfc, where Ipk_high is the maximum current in the inductor (Lpfc) 1034 and Ipk_low is the minimum current in the inductor (Lpfc) 1034.

[0091] In the above embodiments, the power supply implementing the PFC circuit is a boost-mode switch-mode power supply (SMPS). However, in other embodiments, other types of power supplies may be used, such as flyback SMPS, LCC SMPS, or any other suitable SMPS for power factor correction.

[0092] The embodiments of this disclosure offer advantages over conventional techniques for power factor correction. For example, an advantage over conventional techniques is that total harmonic distortion (THD) and power factor (PF) can be optimized for different applications by setting the value of the phase factor α. See also Figure 8For applications requiring low THD, the phase factor α can be set to a lower value (e.g., α = 0.3). For applications requiring higher PF but not necessarily the lowest possible THD, the phase factor α can be set to a higher value (e.g., α = 0.6). In one embodiment, the phase factor α can be an analog or digital parameter for the SMPS controller. This provides SMPS manufacturers with the flexibility to optimize the power supply according to their requirements.

[0093] Figure 11A An example of an analog reference signal generation circuit 1100 is depicted, and Figure 11B An example of a digital reference signal generation circuit 1150 is depicted. In one embodiment, Figure 9 The reference signal generation circuit 902 and / or Figure 10 The reference signal generation circuit 1002 can be implemented as either an analog reference signal generation circuit 1100 or a digital reference signal generation circuit 1150.

[0094] like Figure 11A As shown, the analog reference signal generation circuit 1100 comprises several components, including a first capacitor 1102, a second capacitor 1104, a first resistor 1106, a second resistor 1108, a third resistor 1110, a fourth resistor 1112, and a comparator 1114. Upon receiving an input (e.g., a line input voltage (Vac)), the arrangement of the components enables the analog reference signal generation circuit 1100 to generate a reference signal 1116 (e.g., a sinusoidal reference signal (ref)). In one embodiment, the frequency of the reference signal 1116 can be determined by the following equation: frequency = 1 / (2*π*R*C), where R is the value of the first resistor 1106 and the second resistor 1108, and C is the value of the first capacitor 1102 and the second capacitor 1104.

[0095] like Figure 11B As shown, the digital reference signal generation circuit 1150 includes a digital counter 1154 and a lookup table 1156. A clock signal (clk) 1152 is fed into the digital counter 1154. The digital counter 1154 feeds its input into the lookup table 1156. The lookup table 1156 is based on the input-output reference signal 1158 (e.g., a sine wave reference signal (ref)) from the digital counter 1154.

[0096] Figure 12This is a process flowchart 1200 of an example method for power factor correction (PFC) at a switch-mode power supply (SMPS). In one embodiment, at block 1202, the method involves receiving an input voltage (e.g., a mains input voltage Vac). For example, the reception of the input voltage is performed by a reference signal generation circuit (e.g., reference signal generation circuit 902 or reference signal generation circuit 1002).

[0097] At block 1204, the method involves generating a reference waveform that is in phase with the input voltage. For example, the generation of the reference waveform is performed by a reference signal generation circuit (e.g., reference signal generation circuit 902 or reference signal generation circuit 1002).

[0098] At block 1206, the method involves determining a time value for phase shifting the PFC current signal. For example, the determination of the time value is performed by processing circuitry (e.g., processing circuitry 940 or digital processor 1040).

[0099] In one embodiment, the method involves determining a time value for phase shifting the PFC current signal according to the following equation: time value = arctan(C*ω*Vac / Iac) / ω, where C is the total capacitance of one or more EMI filter capacitors in the SMPS, ω is the frequency of the input voltage, Vac is the input voltage, and Iac is the regulating current signal. In one embodiment, the regulating current signal regulates the output voltage of the SMPS to a target reference voltage.

[0100] In one embodiment, the method involves: generating an input current waveform based on the frequency of the input voltage and a regulated current signal, and generating a capacitor current waveform based on the input voltage, the frequency of the input voltage, and the total capacitance of the one or more EMI filter capacitors to determine a time value for phase shifting the PFC current signal. The method then compares the capacitor current waveform with the input current waveform and determines the time value based on the time at which the input current waveform equals the capacitor current waveform.

[0101] In one embodiment, the method involves generating an input current waveform according to the following equation: Input current waveform = Iac * sin(ωt), where Iac is the regulating current signal, ω is the frequency of the input voltage, and t is a value greater than 0. In another embodiment, the method involves generating a capacitor current waveform according to the following equation: Capacitor current waveform = C * ω * Vac * cos(ωt), where C is the total capacitance of the one or more EMI filter capacitors, ω is the frequency of the input voltage, Vac is the input voltage, and t is a value greater than 0.

[0102] At block 1208, the method involves scaling time values ​​with a phase factor to generate scaled time values. For example, the scaling of the time values ​​is performed by scaling circuitry (e.g., scaling circuitry 914 or scaling circuitry 1014). In one embodiment, the phase factor is a value greater than 0 and less than 1.

[0103] At block 1210, the method involves phase-shifting a reference waveform according to a scaled time value to generate a phase-shifted reference waveform. For example, the phase shift of the reference waveform is performed by a phase-shifted signal generation circuit (e.g., phase-shifted signal generation circuit 918 or phase-shifted signal generation circuit 1018).

[0104] At block 1212, the method relates to generating a PFC current signal based on a phase-shifted reference waveform. For example, the generation of the PFC current signal is performed by a PFC signal generation circuit (e.g., PFC signal generation circuit 942 or PFC signal generation circuit 1042). In one embodiment, the PFC current signal is generated by multiplying the phase-shifted reference waveform by an adjusted current signal to generate a phase-shifted current signal and rectifying the phase-shifted current signal to generate the PFC current signal.

[0105] At block 1214, the method relates to outputting a PFC current signal. For example, the output of the PFC current signal is performed by a switching circuit (e.g., switch 924 or switch 1024). In one embodiment, the method relates to outputting a PFC current signal when both the input voltage and the voltage across the phase-shifted reference waveform are greater than zero, or when both the input voltage and the voltage across the phase-shifted reference waveform are less than zero.

[0106] In one embodiment, the SMPS includes a power stage (e.g., power stage 944 or power stage 1044). Accordingly, at block 1216, the method involves receiving a PFC current signal at a pulse width modulator (PWM) (e.g., PWM 930 or PWM 1030) in the power stage.

[0107] At block 1218, the method involves outputting a PWM signal from the PWM to a switch (e.g., switch 932 or switch 1032) such that the average current in the inductors (e.g., inductor 934 or inductor 1034) in the power stage is equal to the PFC current signal.

[0108] The operations described above for a switch-mode power supply configured for power factor correction can be implemented in hardware, firmware, or a combination thereof, or in a combination of hardware and software, or in a combination of firmware and software, or in a combination of hardware, firmware, and software.

[0109] Although the operations of the methods herein are shown and described in a specific order, the order of operations for each method may be changed so that specific operations can be performed in reverse order, or so that specific operations can be performed at least partially concurrently with other operations. In another embodiment, instructions or sub-operations of different operations may be implemented intermittently and / or alternately.

[0110] It should also be noted that at least some operations of the methods described herein can be implemented using software instructions stored on a computer-usable storage medium for execution by a computer. As an example, embodiments of a computer program product include a computer-usable storage medium for storing a computer-readable program.

[0111] Computer-usable or computer-readable storage media can be electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems (or devices or apparatuses). Examples of non-transitory computer-usable and computer-readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and optical discs. Current examples of optical discs include compact optical discs with read-only memory (CD-ROM), compact optical discs with read / write capability (CD-R / W), and digital video optical discs (DVDs).

[0112] Alternatively, embodiments of the present invention can be implemented entirely in hardware or in implementations containing both hardware and software elements. In software-based embodiments, the software may include, but is not limited to, firmware, resident software, microcode, etc.

[0113] Although specific embodiments of the invention have been described and illustrated, the invention is not limited to the specific form or arrangement of the portions thus described and illustrated. The scope of the invention will be defined by the appended claims and their equivalents.

Claims

1. A method for power factor correction (PFC) at a switch-mode power supply (SMPS), characterized in that, The method includes: Receive input voltage; Generate a reference waveform that is in phase with the input voltage; Determining a time value for phase shifting the PFC current signal includes: generating an input current waveform based on the frequency of the input voltage and a regulating current signal; generating a capacitor current waveform based on the input voltage, the frequency of the input voltage, and the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS; comparing the capacitor current waveform with the input current waveform; and determining the time value based on the time when the input current waveform equals the capacitor current waveform. The time value is scaled using a phase factor to generate a scaled time value; The reference waveform is phase-shifted according to the scaled time value to generate a phase-shifted reference waveform; and Generating the PFC current signal based on the phase-shifted reference waveform includes: multiplying the phase-shifted reference waveform by an adjustment current signal to generate a phase-shifted current signal, and rectifying the phase-shifted current signal to generate the PFC current signal.

2. The method according to claim 1, characterized in that, The time value is determined according to the following equation: Time value = arctan(C*ω*Vac / Iac) / ω, Where C is the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS, ω is the frequency of the input voltage, Vac is the input voltage, and Iac is the regulating current signal.

3. The method according to claim 2, characterized in that, The regulating current signal adjusts the output voltage of the SMPS to the target reference voltage.

4. The method according to claim 1, characterized in that, The phase factor is a value greater than 0 and less than 1.

5. The method according to claim 1, characterized in that, Additionally, the PFC current signal is output in the following situations: Both the input voltage and the voltage of the phase-shifted reference waveform are either greater than zero or both are less than zero.

6. The method according to claim 1, characterized in that, The SMPS includes a power stage, and the method further includes: The PFC current signal is received at the pulse width modulator in the power stage; and The PWM signal from the pulse width modulator is output to the switch, such that the average current in the inductor of the power stage is equal to the PFC current signal.

7. The method according to claim 1, characterized in that, The input current waveform is generated according to the following equation: Input current waveform = Iac*sin(ωt), Where Iac is the regulating current signal, ω is the frequency of the input voltage, and t is a value greater than 0.

8. A switch-mode power supply (SMPS) configured for power factor correction (PFC), characterized in that, include: A reference signal generation circuit is configured to receive an input voltage and generate a reference waveform in phase with the input voltage; A processing circuit configured to determine a time value for phase shifting a PFC current signal includes: generating an input current waveform based on the frequency of the input voltage and a regulating current signal; generating a capacitor current waveform based on the input voltage, the frequency of the input voltage, and the total capacitance of one or more electromagnetic interference (EMI) filter capacitors in the SMPS; comparing the capacitor current waveform with the input current waveform; and determining the time value based on the time when the input current waveform equals the capacitor current waveform. A scaling circuit, configured to scale the time value with a phase factor to generate a scaled time value; A phase-shifted signal generation circuit is configured to phase-shift the reference waveform according to the scaled time value to generate a phase-shifted reference waveform; and A PFC signal generation circuit is configured to generate the PFC current signal based on the phase-shifted reference waveform, comprising: multiplying the phase-shifted reference waveform by an adjustment current signal to generate a phase-shifted current signal, and rectifying the phase-shifted current signal to generate the PFC current signal.

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