A display panel and a display device

Abstract

An embodiment of the present application provides a display panel and a display device. The display panel includes a normal display area and a functional area. Along a first direction, the lengths of a third display area, a first display area, and a second display area in the normal display area decrease in sequence. Among them, one of the first display area and the third display area is a specific display area, and the specific display area includes a first semiconductor pattern layer, and any one first semiconductor pattern layer is connected to at least one adjacent first semiconductor pattern layer arranged along a third direction. The second display area includes a second semiconductor pattern layer, and any one second semiconductor pattern layer is connected to at least one adjacent second semiconductor pattern layer arranged along a fourth direction. Among them, the second semiconductor pattern layer arranged and connected along the fourth direction is connected to the first semiconductor pattern layer arranged and connected along the third direction. In the display panel of the present application, the reliability and uniformity of the performance of the semiconductor pattern layer are improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel and a display device.

Background Art

[0002] With the increasing demands of consumers, full-screen display has gradually become the mainstream display technology. In existing full-screen displays, a light-transmitting area is usually set in the display area, and optical devices are arranged at the position where the light-transmitting area is located. Since the light-transmitting area is not set in the non-display area, the border of the display screen becomes narrower, and thus full-screen display can be achieved. However, due to the existence of the light-transmitting area in the display area, the display effect of the display panel deteriorates.

[0003]

Application Content

[0004] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of this application provides a display panel, including a conventional display area and a functional area; the conventional display area includes a first display area, a second display area, and a third display area. Along a first direction, the length of the second display area is respectively less than the lengths of the first display area and the third display area, and the length of the first display area is less than the length of the third display area; the sub-pixel density of the functional area is less than the sub-pixel density of the conventional display area, and the second display area, the functional area, and the first display area are adjacent to each other in sequence along the first direction, and at least one of the first display area and the second display area and the functional display area are adjacent to the third display area along a second direction; the first direction intersects with the second direction; wherein: one of the first display area and the third display area is a specific display area, the specific display area includes a plurality of first pixel circuits, each first pixel circuit includes a first semiconductor pattern layer, and any one first semiconductor pattern layer is connected to at least one adjacent first semiconductor pattern layer arranged along a third direction, and the included angle between the third direction and the first direction is a first included angle α, 90° > α ≥ 0°; the second display area includes a plurality of second pixel circuits, each second pixel circuit includes a second semiconductor pattern layer, and any one second semiconductor pattern layer is connected to at least one adjacent second semiconductor pattern layer arranged along a fourth direction; the included angle between the fourth direction and the first direction is a second included angle β, 90° > β ≥ 0°; wherein, the second semiconductor pattern layer arranged and connected along the fourth direction is connected to the first semiconductor pattern layer arranged and connected along the third direction.

[0006] In a second aspect, based on the same concept, an embodiment of this application provides a display device, including the display panel provided in the first aspect, and an optical device; the optical device is arranged at the position corresponding to the functional area of the display device.

[0007] In the display panel and the display device provided by the embodiments of the present application, the second semiconductor pattern layer is connected to the first semiconductor pattern layer in the functional area, realizing the continuity of the semiconductor pattern layer in the functional area and reducing the risk of static electricity flowing into the semiconductor pattern layer from the functional area. At the same time, when the string of second semiconductor pattern layers is connected to the string of first semiconductor pattern layers, the relatively high-density static electricity on the second semiconductor pattern layer 121 can be dispersed. Furthermore, the reliability and uniformity of the performance of the semiconductor pattern layer in subsequent high-temperature processes can be improved, realizing the display uniformity of the display panel and the display device and enhancing the display effect.

Description of the Drawings

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0009] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present application;

[0010] Figure 2 Schematic diagram of another display panel provided by an embodiment of the present application;

[0011] Figure 3 For Figure 1 A partial enlarged view of the AA area in

[0012] Figure 4 For Figure 1 Another partial enlarged view of the AA area in

[0013] Figure 5 Equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application;

[0014] Figure 6 A cross-sectional view corresponding to a sub-pixel area in the present application;

[0015] Figure 7 Schematic diagram of a semiconductor pattern layer corresponding to a pixel circuit provided by an embodiment of the present application;

[0016] Figure 8 For Figure 3 A schematic diagram of the film layer where the corresponding semiconductor pattern layer is located;

[0017] Figure 9 For Figure 3 Another schematic diagram of the film layer where the corresponding semiconductor pattern layer is located;

[0018] Figure 10 ForFigure 4 A schematic diagram of the film layer where the corresponding semiconductor pattern layer is located;

[0019] Figure 11 A connection schematic diagram of the second semiconductor pattern layer provided by the embodiment of the present application;

[0020] Figure 12 A schematic diagram of the functional area of the display panel provided by the present application;

[0021] Figure 13 is Figure 12 A sectional view along the MN direction;

[0022] Figure 14 Another schematic diagram of the functional area of the display panel provided by the present application;

[0023] Figure 15 is Figure 14 A sectional view along the MN direction;

[0024] Figure 16 Another schematic diagram of the functional area of the display panel provided by the present application;

[0025] Figure 17 is Figure 16 A sectional view along the MN direction;

[0026] Figure 18 is Figure 12 Another sectional view along the MN direction;

[0027] Figure 19 Another schematic diagram of the functional area of the display panel provided by the present application;

[0028] Figure 20 is Figure 19 A sectional view along the MN direction;

[0029] Figure 21 A schematic diagram of the display device provided by the embodiment of the present application.

Detailed implementation manners

[0030] In order to better understand the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0032] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should be understood that the term "and / or" used herein is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally indicates that the associated objects before and after are in an "or" relationship.

[0034] In the description of this specification, it should be understood that the words "substantially", "approximately", "about", "around", "roughly", "generally" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0035] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe the display areas, these display areas should not be limited to these terms. These terms are only used to distinguish the display areas from each other. For example, without departing from the scope of the embodiments of the present application, the first display area may also be referred to as the second display area, and similarly, the second display area may also be referred to as the first display area.

[0036] Through careful and in-depth research, the applicant of this case provides a solution to the problems existing in the prior art.

[0037] The embodiments of the present application provide a display panel and a display device.

[0038] The applicant found in the research that for a display panel, since the light-transmitting area is set within the display area, in order to ensure the light transmittance of the light-transmitting area, there is no or little light-shielding structure provided in the light-transmitting area. For example, there is no or little metal wiring and semiconductor layer provided, which means that the metal wiring and the semiconductor layer are disconnected in the light-transmitting area. Among them, since the lengths of the semiconductor layers at the upper and lower positions of the light-transmitting area are inconsistent, the electrostatic distribution during the preparation process of the semiconductor layer is uneven. For example, the electrostatic density on the semiconductor layer with a shorter length is large, while the electrostatic density on the semiconductor layer with a longer length is small. The manufacturing process of the semiconductor layer includes high-temperature processes, such as annealing and activation processes, and the static electricity during the high-temperature process will have an irreversible impact on the performance of the semiconductor layer, thereby affecting the performance of the corresponding transistor, such as the magnitude of the threshold voltage. Since the semiconductor layer is disconnected at the position where the light-transmitting area is located, resulting in uneven electrostatic distribution on the semiconductor layer, the irreversible impacts of the unevenly distributed static electricity on the performance of the semiconductor layer during the high-temperature process are different, so the performances of the transistors in the display screen are inconsistent, and thus the display uniformity of the display screen is poor. Figure 1 Schematic diagram of a display panel provided by an embodiment of the present application, Figure 2 Schematic diagram of another display panel provided by an embodiment of the present application, Figure 3 For Figure 1 a partial enlarged view of the AA area in Figure 4 For Figure 1 another partial enlarged view of the AA area in. It should be noted that, Figure 3 and Figure 4 the specific structure of the AA area shown schematically is basically the same as the specific structure near the functional area in Figure 2 .

[0039] As Figure 1 and Figure 2 shown, the display panel provided by the embodiment of the present application includes a conventional display area 01 and a functional area 02, and the conventional display area 01 at least partially surrounds the functional area 02. As Figure 1 shown, the functional area 02 can be completely surrounded by the conventional display area 01; as Figure 2 shown, the functional area 02 can also be partially surrounded by the conventional display area 01. As Figure 3 and Figure 4 shown, the conventional display area 01 includes a plurality of sub-pixels PX that can emit light, which are used for main light-emitting display. The sub-pixel density in the functional area 02 is less than the sub-pixel density in the conventional display area 01, and at least other functions besides light-emitting display can be realized, such as at least one of functions such as photographing, biometric recognition, and lighting; in addition, in an optional embodiment, the functional area 02 can both realize these other functions and perform light-emitting display.

[0040] Please continue to refer to Figure 1 and Figure 2, the conventional display area 01 includes a first display area 11, a second display area 12, and a third display area 13. The first display area 11, the second display area 12, and the third display area 13 are different regions of the conventional display area 01 and may have the same sub-pixel PX design pattern. Along the first direction Y, the second display area 12, the functional area 02, and the first display area 11 are adjacent in sequence; that is, along the first direction Y, the functional area 02 is disposed between the first display area 11 and the second display area 12. Along the second direction X, at least one of the first display area 11 and the second display area 12 and the functional area 02 are adjacent to the third display area 13; that is, the first display area 11, the second display area 12, and the functional area 02 are aligned in the first direction Y and the three are adjacent to the third display area 13 as a whole in the second direction X. Among them, the first direction Y intersects the second direction X. In one implementation, the first direction Y may be perpendicular to the second direction X.

[0041] Along the first direction Y, the length of the second display area 12 is respectively less than the length of the first display area 11 and the length of the third display area 13, and the length of the first display area 11 is less than the length of the third display area 13. The functional area 02 is at least partially surrounded by the conventional display area 01, which is equivalent to disposing the functional area 02 within the conventional display area 01, thereby avoiding the non-display area outside the conventional display area 01 from increasing the border width of the display panel.

[0042] However, the functional area 02 is usually disposed at a position close to the edge in the display panel to avoid affecting the display effect of the conventional display area 01. As Figure 1 and Figure 2 shown, along the first direction Y, the functional area 02 is disposed at a position close to one side edge of the conventional display area 01, such that the lengths of the first display area 11 on both sides of the conventional display area 01 along the first direction Y are different from the length of the second display area 12. In addition, as Figure 1 shown, when the functional area 02 is disposed along the first direction Y at a position close to the edge of the conventional display area 01, then as Figure 1 shown, the functional area 02 can be disposed at the middle position of the conventional display area 01 along the second direction X; or as Figure 2 shown, the functional area 02 can be disposed at a position close to the edge of the conventional display area 01 along the second direction X.

[0043] Among them, along the first direction Y, the lengths of the first display area 11, the second display area 12, and the third display area 13 respectively refer to the length of the region where the first display area 11 is located along the first direction Y, the length of the region where the second display area 12 is located along the first direction Y, and the length of the third display area 13 along the first direction Y.

[0044] It should be noted that the functional area 02 can be a rectangular structure or other structures. When the functional area 02 is a non-rectangular structure, the corresponding first display area 11, second display area 12, and / or third display area 13 are also non-rectangular structures. Therefore, the lengths of the first display area 11, second display area 12, and third display area 13 referred to in this application can respectively refer to the average lengths of the first display area 11, second display area 12, and third display area 13.

[0045] Since the length of the second display area 12 is respectively smaller than the lengths of the first display area 11 and the third display area 13, and the length of the first display area 11 is smaller than the length of the third display area 13, correspondingly, the number of sub-pixels PX arranged along the first direction Y in the second display area 12 is respectively less than the number of sub-pixels PX arranged along the first direction Y in the first display area 11 and the number of sub-pixels PX arranged along the first direction Y in the third display area 13, and the number of sub-pixels PX arranged along the first direction Y in the first display area 11 is less than the number of sub-pixels PX arranged along the first direction Y in the third display area 13. In addition, the number of sub-pixels PX arranged along the first direction Y in the first display area 11 can be the average value of multiple columns of sub-pixels PX arranged along the first direction Y in the first display area 11, the number of sub-pixels PX arranged along the first direction Y in the second display area 12 can be the average value of multiple columns of sub-pixels PX arranged along the first direction Y in the second display area 12, and the number of sub-pixels PX arranged along the first direction Y in the third display area 13 can be the average value of multiple columns of sub-pixels PX arranged along the first direction Y in the third display area 13.

[0046] The sub-pixels PX in the display panel provided by the embodiments of the present application can be self-luminous devices, such as organic light-emitting diodes or micro diode emitters. Then, as Figure 3 shown, the display panel further includes a pixel circuit DI corresponding to each sub-pixel PX one by one, and the pixel circuit DI is used to provide the voltage required for the corresponding sub-pixel to emit light.

[0047] Figure 5 is an equivalent circuit diagram of a pixel circuit provided by an embodiment of the present application. As Figure 5 shown, the pixel circuit DI is electrically connected to the sub-pixel PX.

[0048] Please continue to refer to Figure 5, the pixel circuit DI may include a light-emitting driving transistor Td, a reset transistor T1, a data voltage writing transistor T2, a threshold grabbing transistor T3, a power supply voltage writing transistor T4, a light-emitting control transistor T5, and a first capacitor C0. Herein, the following light-emitting driving transistor Td, reset transistor T1, data voltage writing transistor T2, threshold grabbing transistor T3, power supply voltage writing transistor T4, and light-emitting control transistor T5 are all P-type transistors as an example for illustration. In other alternative embodiments, the light-emitting driving transistor Td, reset transistor T1, data voltage writing transistor T2, threshold grabbing transistor T3, power supply voltage writing transistor T4, and light-emitting control transistor T5 may also all be N-type transistors, or some may be P-type transistors and some may be N-type transistors.

[0049] Among them, the source of the reset transistor T1 is electrically connected to the reset signal line REF, and the drain of the reset transistor T1 is electrically connected to the gate of the light-emitting driving transistor Td. The source of the data voltage writing transistor T2 is electrically connected to the data signal line DATA, and the drain of the data voltage writing transistor T2 is electrically connected to the source of the light-emitting driving transistor Td. The source of the threshold grabbing transistor T3 is electrically connected to the drain of the light-emitting driving transistor Td, and the drain of the threshold grabbing transistor T3 is electrically connected to the gate of the light-emitting driving transistor Td. The source of the power supply voltage writing transistor T4 is electrically connected to the power supply voltage line PVDD, and the drain of the power supply voltage writing transistor T4 is electrically connected to the source of the light-emitting driving transistor Td. The source of the light-emitting control transistor T5 is electrically connected to the drain of the light-emitting driving transistor Td, and the drain of the light-emitting control transistor T5 is electrically connected to the light-emitting device EL. The first plate of the first capacitor C0 is electrically connected to the gate of the light-emitting driving transistor Td, and the second plate of the first capacitor C0 is electrically connected to the power supply voltage line PVDD.

[0050] The following Figure 5 illustrates the working process of the shown pixel circuit, and the working process of this pixel circuit may include a reset stage, a data voltage writing stage, and a light-emitting stage.

[0051] In the reset stage, the reset transistor T1 is turned on, and the reset signal line REF transmits a reset signal. Then, the reset signal is written into the gate of the light-emitting driving transistor Td, the gate of the light-emitting driving transistor Td is reset, and the first capacitor C0 stores the reset signal.

[0052] In the data voltage writing stage, the power supply voltage writing transistor T4 and the light-emitting control transistor T5 are turned off, the data voltage writing transistor T2 and the threshold grabbing transistor T3 are turned on, and the data signal line DATA transmits a data voltage. Since the potential of the data voltage is higher than the potential of the reset signal, the light-emitting driving transistor Td is turned on and the data voltage is written into the gate of the light-emitting driving transistor Td.

[0053] In the light-emitting stage, the threshold-grab transistor T3 is turned off, the power-supply voltage writing transistor T4 and the light-emitting control transistor T5 are turned on, the power-supply voltage line PVDD transmits the power-supply voltage, so the power-supply voltage is transmitted to the source of the light-emitting driving transistor Td. Since the potential of the power-supply voltage is greater than the potential of the data voltage, the light-emitting driving transistor Td generates a light-emitting driving current and transmits it to the sub-pixel PX.

[0054] It should be noted that Figure 5 only an equivalent circuit diagram of a pixel circuit is shown, and the specific structure of the pixel circuit in the present application may also be in other forms.

[0055] Figure 6 This is a cross-sectional view corresponding to a sub-pixel region in the present application. Please refer to Figure 5 and Figure 6 , the pixel circuit DI that provides a light-emitting signal for a sub-pixel PX includes a plurality of transistor structures, and one of the transistor structures, such as the light-emitting control transistor T5, is electrically connected to the sub-pixel PX. In order to achieve a high sub-pixel PX density in the light-emitting display panel, the plurality of transistor structures included in a pixel circuit DI are arranged as closely as possible.

[0056] Figure 7 This is a schematic diagram of a semiconductor pattern layer corresponding to a pixel circuit provided in an embodiment of the present application. Among the plurality of transistor structures included in a pixel circuit DI, each transistor structure includes an active layer PL, and due to process precision limitations, the active layers PL of the plurality of transistor structures in a pixel circuit DI are connected together to form a semiconductor pattern layer as shown in Figure 7 . It should be noted that Figure 7 only shows a semiconductor pattern layer corresponding to a pixel circuit DI, and the semiconductor pattern layer corresponding to the pixel circuit DI may also be in other shapes.

[0057] Figure 8 This is Figure 3 a schematic diagram of the film layer where the corresponding semiconductor pattern layer is located, Figure 9 This is Figure 3 another schematic diagram of the film layer where the corresponding semiconductor pattern layer is located, Figure 10 This is Figure 4 a schematic diagram of the film layer where the corresponding semiconductor pattern layer is located.

[0058] Please refer to Figure 3 and Figure 8 - Figure 9 , Figure 4 and Figure 10, one of the first display area 11 and the third display area 13 is a specific display area. A plurality of pixel circuits DI in the specific display area are first pixel circuits 110. The first pixel circuit 110 includes a first semiconductor pattern layer 111. Any one of the first semiconductor pattern layers 111 is connected to at least one adjacent first semiconductor pattern layer 111 arranged along the third direction. The included angle between the third direction and the first direction Y is a first included angle α, where 90° > α ≥ 0°;

[0059] A plurality of pixel circuits DI in the second display area 12 are second pixel circuits 120. The second pixel circuit 120 includes a second semiconductor pattern layer 121. Any one of the second semiconductor pattern layers 121 is connected to at least one adjacent second semiconductor pattern layer 121 arranged along the fourth direction. The included angle between the fourth direction and the first direction Y is a second included angle β, where 90° > β ≥ 0°;

[0060] Among them, the second semiconductor pattern layer 121 arranged and connected along the fourth direction Y2 is connected to the first semiconductor pattern layer 111 arranged and connected along the third direction Y1.

[0061] In this application, by connecting the second semiconductor pattern layer 121 and the first semiconductor pattern layer 111, the continuity of the semiconductor pattern layer in the functional area 02 is realized, and the risk of static electricity flowing into the semiconductor pattern layer in the functional area 02 is reduced. At the same time, by connecting the string of second semiconductor pattern layers 121 and the string of first semiconductor pattern layers 111 together, the relatively large static electricity on the second semiconductor pattern layer 121 is dispersed on the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121, making the distribution of static electricity in the semiconductor pattern layer uniform. Furthermore, the reliability and uniformity of the performance of the semiconductor pattern layer in subsequent high-temperature processes can be improved, making the driving capabilities of the pixel circuits basically the same, realizing the display uniformity of the display panel, and enhancing the display effect.

[0062] In this application, the ratio of the length of the second display area 12 in the first direction Y to the length of the specific display area in the first direction Y ranges from [12, 50]. If the number of pixel circuits is used to characterize the lengths of different display areas, the number of first pixel circuits 111 arranged in the first direction Y in the specific display area is N, and the number of second pixel circuits 121 arranged in the first direction Y in the second display area 12 is M. Here, both M and N are positive integers greater than or equal to 2, and 50 ≥ N / M ≥ 12. When the length of the second display area 12 satisfies the above relationship, the position where the functional area 02 is set has less influence on the display effect of the display panel. However, if the second semiconductor pattern 121 in the second display area 12 is not connected to the first semiconductor pattern layer to dissipate static electricity in the manufacturing process, the display effect of the second display area 12 is significantly different from that of other display areas. Therefore, when the technical solution in which the second semiconductor pattern 121 in the embodiment of this application is connected to the first semiconductor pattern layer is applied to the case where the ratio of the length of the second display area 12 in the first direction Y to the length of the specific display area in the first direction Y ranges from [12, 50], the problem that the display effect of the second display area 12 is significantly different from that of other display areas can be effectively solved.

[0063] Here, in this application, the semiconductor pattern layer is one of polysilicon and metal oxide semiconductor. The pixel circuit using polysilicon as the semiconductor pattern layer has a relatively fast response speed, and the pixel circuit using metal oxide semiconductor as the semiconductor pattern layer can generate a stable light-emitting current. Therefore, when the semiconductor pattern layer in the display panel is one of polysilicon and metal oxide semiconductor, the display panel has excellent light-emitting performance. At the same time, when the semiconductor pattern layer in the display panel is one of polysilicon and metal oxide semiconductor, the connection between the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121 can effectively solve the problem of excessive static electricity accumulation in the semiconductor pattern layer in the specific display area.

[0064] In one implementation manner of this application, the third direction Y1 is parallel to the fourth direction Y2. That is, in the same direction, adjacent first semiconductor pattern layers 111 are connected, and adjacent second semiconductor pattern layers 121 are connected; and the mutually connected first semiconductor pattern layer 111 and second semiconductor pattern layer 121 are also arranged substantially along the same direction.

[0065] In one embodiment of this application, both the third direction Y1 and the fourth direction Y2 are parallel to the first direction Y, that is, α = 0°, β = 0°. Then, as Figure 7 - Figure 9 shown, the first semiconductor pattern layers 111 in the same column are sequentially connected, and the second semiconductor pattern layers 121 in the same column are sequentially connected.

[0066] Figure 11A connection schematic diagram of the second semiconductor pattern layer provided by an embodiment of the present application is as follows. Figure 11 As shown, the second semiconductor pattern layers 121 arranged along the fourth direction Y2 are sequentially connected, and the fourth direction Y2 forms a non-0° angle with the first direction Y, that is, 90° > α > 0°. Correspondingly, the connection effect of the first semiconductor pattern layers 111 arranged along the third direction Y1 is basically the same as that of the Figure 11 second semiconductor pattern layers 121 shown, so 90° > β > 0°.

[0067] It should be noted that in the normal display area of the display panel, the connection methods of the semiconductor pattern layers in each area should be the same. On the one hand, it can reduce the design difficulty, and on the other hand, it can ensure the uniformity of the coupling capacitance of each semiconductor pattern layer.

[0068] In addition, the first semiconductor pattern layers 111 directly connected to one first semiconductor pattern layer 111 may not only include the first semiconductor pattern layers 111 located on both sides of it along the third direction Y1, but also include the first semiconductor pattern layers 111 located on at least one side of it along the direction intersecting with the third direction Y1. Similarly, the second semiconductor pattern layers 121 directly connected to one second semiconductor pattern layer 121 may not only include the second semiconductor pattern layers 121 located on both sides of it along the fourth direction Y2, but also include the second semiconductor pattern layers 121 located on at least one side of it along the direction intersecting with the fourth direction Y2.

[0069] However, it should be noted that when the first semiconductor pattern layers 111 arranged along the third direction Y1 are sequentially connected, the number of the first semiconductor pattern layers 111 connected in the direction intersecting with the third direction Y1 is one to three, for example, two. In this way, the coupling capacitance of the first semiconductor pattern layers 111 can be reduced. For the same reason, the number of the second semiconductor pattern layers 121 connected in the direction intersecting with the fourth direction Y2 is also one to three, for example, two.

[0070] In an embodiment of the present application, as shown in Figure 8 and Figure 9 the first display area 11 is a specific display area, then the multiple pixel circuits DI in the first display area 11 are the first pixel circuits 110, and the semiconductor pattern layers included in the first pixel circuits 110 in the first display area 11 are the first semiconductor pattern layers 111. And there is at least one connection semiconductor CL in the functional area 02. Then, the second semiconductor pattern layers 121 arranged and connected along the fourth direction Y2 and the first semiconductor pattern layers 111 arranged and connected along the third direction Y1 are electrically connected through the connection semiconductor CL.

[0071] In an implementation manner of this embodiment, as shown in Figure 8As shown, a connecting semiconductor CL is connected to a plurality of second semiconductor pattern layers 121 near the functional area 02 in the second display area 12 and is also connected to a plurality of first semiconductor pattern layers 111 near the functional area 02 in the first display area 11. Then, the static electricity in the second semiconductor pattern layers 121 can be dispersed into the first semiconductor pattern layers 111 through a smaller number of connecting semiconductors CL.

[0072] In one solution, as Figure 8 shown, the connecting semiconductor CL is connected to all the second semiconductor pattern layers 121 near the functional area 02 in the second display area 12 and is also connected to all the first semiconductor pattern layers 111 near the functional area 02 in the first display area 11. That is, all the second semiconductor pattern layers 121 in the second display area 12 are directly or indirectly connected to the same connecting semiconductor CL, and all the first semiconductor pattern layers 111 in the first display area 11 are directly or indirectly connected to the same connecting semiconductor CL, and one connecting semiconductor CL is directly or indirectly connected to all the second semiconductor pattern layers 121 and all the first semiconductor pattern layers 111.

[0073] That is, multiple columns of first semiconductor pattern layers 111 arranged perpendicular to the third direction Y1 are all electrically connected to the same connecting semiconductor CL, and multiple columns of second semiconductor pattern layers 121 arranged perpendicular to the fourth direction Y2 are also all electrically connected to the same connecting semiconductor CL. Then, the static electricity in all the second semiconductor pattern layers 121 can be balanced between the first display area 111 and the second display area 121 on both sides of the functional area 02. In particular, when the shape of the functional area 02 is irregular and the number of second semiconductor pattern layers 121 in different columns is different, a better effect of balancing the static electricity on both sides of the functional area 02 can be obtained through this design.

[0074] In addition, since one connecting semiconductor CL is directly or indirectly connected to all the second semiconductor pattern layers 121 and all the first semiconductor pattern layers 111, the number of connecting semiconductors CL in the functional area 02 can be one, which simplifies the process and reduces the influence of the connecting semiconductor CL on the inner layer preparation process in the functional area 02.

[0075] In order to increase the static electricity circulation path, the number of connecting semiconductors CL can also be multiple. When the number of connecting semiconductors CL is multiple, these multiple connecting semiconductors CL can be connected to each other.

[0076] Figure 12 This is a schematic diagram of the functional area of the display panel provided by the present application. Figure 13 For Figure 12 a sectional view along the MN direction. Figure 14 This is another schematic diagram of the functional area of the display panel provided by the present application. Figure 15 ForFigure 14 A cross-sectional view along the MN direction Figure 16 Another schematic diagram of the functional area of the display panel provided by this application Figure 17 is Figure 16 A cross-sectional view along the MN direction

[0077] As Figure 12 , Figure 14 and Figure 16 shown, the functional area 02 includes a light-transmitting area 21 and a transition area 22 surrounding the light-transmitting area 21. Among them, within the area where the light-transmitting area 21 is located, light can penetrate the display panel along the thickness direction of the display panel. The transition area 22 is arranged between the light-transmitting area 21 and the conventional display area 01. Metal windings can be arranged in the transition area 22 to avoid arranging metal windings in the light-transmitting area 21, thereby increasing the light transmittance of the light-transmitting area 21. When there is a light-transmitting area 21, the periphery of the conventional display area 01 close to the light-transmitting area 21 may also need to be encapsulated, and an encapsulation structure can be arranged in the transition area 22

[0078] As Figure 13 , Figure 15 and Figure 17 shown, in order to improve the light transmittance of the light-transmitting area 21, some film layers in the conventional display area 01 extend to the transition area 22 and then stop. For example, the planarization layer, pixel definition layer, and organic layer in the encapsulation layer prepared from organic materials stop in the transition area 22. In order to prevent water vapor, oxygen, etc. from invading the conventional display area 01 through the light-transmitting area 21, a barrier structure can be arranged in the transition area 22, such as arranging a first barrier structure SC1 and a second barrier structure SC2. The first barrier structure SC1 can be formed by stacking structures that are on the same layer as the planarization layer and the pixel definition layer and are separated, and an inorganic material layer in the encapsulation layer can be arranged on its surface. The film layer on the side of the first barrier structure SC1 close to the light-transmitting area 21 does not include a film layer prepared from organic materials, so the height of the first barrier structure SC1 is higher than the film layer on the side of its outer side close to the light-transmitting area 21, increasing the transmission path of water vapor and oxygen. Therefore, the first barrier structure SC1 can play a role in blocking water vapor and oxygen. The second barrier structure SC2 can be formed by stacking metals that are on the same layer as the signal lines in the conventional display area 01 and can effectively block water vapor and oxygen

[0079] Please continue to combine Figure 12 with Figure 13 , Figure 14 and Figure 15 , Figure 16 and Figure 17, since light needs to pass through the light-transmitting region 21, the light-transmitting region 21 should have good light transmittance, and metal traces should be avoided as much as possible in the light-transmitting region 21. If the signal lines on both sides of the functional region 02 in the conventional display region 01 need to be electrically connected, they can be electrically connected through the metal traces ML in the transition region 22. Therefore, the transition region 22 also includes a metal trace group, where the metal trace group includes multiple metal traces ML, for example Figure 12 - Figure 17 As shown, the transition region 22 on one side of the functional region 02 includes three metal traces ML. And, as Figure 12 - 17 shown, the metal trace ML and the connection semiconductor CL can be arranged in different layers.

[0080] Please refer to Figure 12 and Figure 13 , Figure 14 and Figure 15 , Figure 16 and Figure 17 . At least one connection semiconductor CL is arranged in the transition region 22. Although the connection semiconductor CL is connected to the semiconductor pattern layer in the conventional display region 01, arranging the connection semiconductor CL in the transition region 22 can prevent the connection semiconductor CL from affecting the setting of the pixel circuit DI in the conventional display region 01. In addition, arranging the connection semiconductor CL in the transition region 22 can also avoid affecting the light transmittance of the light-transmitting region 02.

[0081] In one implementation, please refer to Figure 12 and Figure 13 . In a plane perpendicular to the thickness direction of the display panel, the connection semiconductor CL is arranged on the side of the metal trace group away from the light-transmitting region 21. That is, the connection semiconductor CL is arranged on the side of the transition region 22 close to the conventional display region 01, so that the connection semiconductor CL is easy to connect to the semiconductor pattern layer. In addition, arranging the connection semiconductor CL at a position away from the metal trace group can ensure that the film layer under the metal trace group is a flat film layer, reducing the design difficulty of the metal trace ML and the risk of metal trace disconnection, and there is basically no parasitic capacitance and signal crosstalk between the metal trace ML and the connection semiconductor CL.

[0082] In another implementation, please refer to Figure 14 and Figure 15, in a plane perpendicular to the thickness direction of the display panel, the connecting semiconductor CL is disposed on one side of the metal trace group close to the light-transmitting region 21. And along the thickness direction of the display panel, the connecting semiconductor CL can be disposed below the first barrier structure SC1 and / or the second barrier structure SC2, further increasing the barrier path of the first barrier structure SC1 and / or the second barrier structure SC2 to moisture and oxygen. In addition, disposing the connecting semiconductor CL at a position far from the metal trace group can ensure that the film layer below the metal trace group is a flat film layer, so that the design difficulty of the metal trace ML is reduced and the risk of metal trace breakage is reduced, and there is basically no parasitic capacitance and signal crosstalk phenomenon between the metal trace ML and the connecting semiconductor CL.

[0083] In another implementation, please refer to Figure 16 and Figure 17 , along the thickness direction of the display panel, at least a part of the metal trace group covers the connecting semiconductor CL. That is, as Figure 17 shown, along the thickness direction of the display panel, the connecting semiconductor CL is disposed below the metal trace group and the metal trace group completely covers the connecting semiconductor CL. Since the lengths of the first display region 11 and the second display region 12 are both smaller than the length of the third display region 13, then along the first direction Y, the number of intersection positions between the interconnected semiconductor pattern layers and the signal lines in the first display region 11 and the second display region 12 is less than the number of intersection positions between the interconnected semiconductor pattern layers and the signal lines in the third display region 13. By disposing the connecting semiconductor CL below the metal trace group, the number of intersection positions between the interconnected semiconductor pattern layers and the signal lines in the first display region 11 and the second display region 12 can be increased, and the coupling capacitance between the semiconductor pattern layers and the signal lines in each region of the conventional display region 01 can be balanced.

[0084] As Figure 12 - 17 shown, the sub-pixel density in the light-transmitting region 21 is 0, that is, no sub-pixels PX are disposed in the region where the light-transmitting region 21 is located and it is not used for light-emitting display.

[0085] In one implementation, as Figure 13 , Figure 15 and Figure 17 shown, the light-transmitting region 21 is a non-hollowed-out region of the display panel. That is, the display panel includes a first substrate BC and a second substrate TC disposed opposite to each other, and both the first substrate BC and the second substrate TC are continuous structures in the light-transmitting region 21 and the conventional display region 01.

[0086] In another implementation, the light-transmitting region 21 is a hollowed-out region of the display panel. Figure 18 is Figure 12 Another cross-sectional view along the MN direction. As Figure 18As shown, the display panel includes a first substrate BC and a second substrate TC which are oppositely arranged, and both the first substrate BC and the second substrate TC are hollowed out in the area where the light-transmitting region 21 is located. It should be noted that Figure 18 Only the case where the connecting semiconductor CL is located on the side of the transition region 22 away from the light-transmitting region 21 is schematically shown. However, in this implementation, the structure of the transition region 22 can be the same as that of any of the above embodiments.

[0087] Figure 19 This is another schematic diagram of the functional area of the display panel provided by this application. Figure 20 For Figure 19 A sectional view along the MN direction. As Figure 19 And Figure 20 As shown, the sub-pixel density in the light-transmitting region 21 is greater than 0, that is, the light-transmitting region 21 can also perform light-emitting display, thereby increasing the display area of the display panel. In one implementation, sub-pixels PX are also provided in the transition region 22, so that the normal display area 01 and the functional area 02 of the display panel can display continuous pictures. Among them, a pixel circuit DI and metal wirings are provided in the transition region 22, and the pixel circuit DI and metal wirings are avoided in the light-transmitting region 21, thereby increasing the light transmittance of the light-transmitting region 21. It should be noted that the pixel circuit DI for providing signals to the sub-pixels PX in the light-transmitting region 21 can be provided in the transition region 21.

[0088] When sub-pixels PX are provided in the light-transmitting region 21, the setting manner of the connecting semiconductor CL connected to the metal wire group in the transition region 22 can be the same as that of any of the above embodiments, and will not be elaborated here.

[0089] It should be noted that, in this embodiment, as Figure 12 , Figure 14 , Figure 16 , Figure 19 As shown, the connecting semiconductor CL can be a ring structure and the ring structure surrounds the light-transmitting region 21, so that all the first semiconductor pattern layers 111 and the second semiconductor pattern layers 112 close to the light-transmitting region 21 can be connected by using the least amount of connecting semiconductor CL, and the influence of the connecting semiconductor CL on the signal lines in the transition region 22 or the influence on the barrier structure can be avoided. The minimum number of connecting semiconductor CL can be one.

[0090] In addition, it should be noted that, in this embodiment, the connecting semiconductor CL being a ring structure means that the connecting semiconductor CL is a continuous structure and its overall contour is a ring. The connecting semiconductor CL may further include a protrusion structure connected to the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121, but its overall contour is still a ring.

[0091] In another implementation of this embodiment, as Figure 9As shown, one end of a connecting semiconductor CL is connected to a second semiconductor pattern layer 121 near the functional area 02 in the second display area 12, and the other end is connected to a first semiconductor pattern layer 111 near the functional area 02 in the first display area. Then, the second semiconductor pattern layers 121 interconnected within the second display area 12 are connected to the first semiconductor pattern layers 111 interconnected within the first display area 11 through the connecting semiconductor CL. The first semiconductor pattern layer 111 and the second semiconductor pattern layer 121 in the same column are connected, and the semiconductor pattern layers in the same column within the third display area 13 are sequentially connected. That is, the connection mode of the semiconductor pattern layers in the display areas on both sides of the functional area 02 is basically the same as that of the semiconductor pattern layers in other display areas, so that the static electricity and capacitance coupling in the semiconductor pattern layers in the conventional display area 01 can be ensured to be basically the same, ensuring display uniformity.

[0092] It should be noted that only the shape of the connecting semiconductor CL and its connection mode with the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121 are different from those in the above embodiment, and other structural designs are the same as any of the above embodiments, so they will not be elaborated here.

[0093] In an embodiment of the present application, as Figure 10 shown, the third display area 13 is a specific display area, then the multiple pixel circuits DI within the third display area 13 are first pixel circuits 110, and the semiconductor pattern layer included in the first pixel circuit 110 within the third display area 13 is the first semiconductor pattern layer 111.

[0094] In this embodiment, the display panel further includes a semiconductor connection area provided on the side of the second display area 12 away from the functional area 02 along the first direction Y, and at least one connecting semiconductor CL is included in the connecting semiconductor area. Along the first direction Y, multiple second semiconductor pattern layers 121 near the semiconductor connection area in the second display area 12 are all connected to one connecting semiconductor CL, and multiple first semiconductor pattern layers 111 near the semiconductor connection area in the third display area 13 are all connected to one connecting semiconductor CL. And the number of the first semiconductor pattern layers 111 connected to the same connecting semiconductor CL is more than the number of the second semiconductor pattern layers 121 connected thereto.

[0095] Then, the static electricity in the second semiconductor pattern layer 121 during the manufacturing process can be dispersed to multiple first semiconductor pattern layers 111 through the connection semiconductor CL, avoiding abnormal display in the second display area 11. At the same time, the number of first semiconductor pattern layers 111 connected in sequence along the third direction Y1 in the third display area 13 is much larger than the number of second semiconductor pattern layers 121 connected in sequence along the fourth direction Y2, and the number of columns of first semiconductor pattern layers 111 arranged in the direction perpendicular to the third direction Y1 is also much larger than the number of columns of second semiconductor pattern layers 121 arranged in the direction perpendicular to the first direction Y1. Therefore, the static electricity in the second semiconductor pattern layer 121 can be fully dispersed.

[0096] In an implementation manner of this embodiment, as Figure 10 shown, along the first direction Y, all the second semiconductor pattern layers 121 in the second display area 12 close to the semiconductor connection area are connected to a connection semiconductor CL, and all the first semiconductor pattern layers 11 in the third display area 13 close to the semiconductor connection area are connected to a connection semiconductor CL.

[0097] Among them, the semiconductor connection area can be set in the edge area of the conventional display area 01 or in the non-display area outside the conventional display area 01, avoiding the connection semiconductor CL affecting the setting of the semiconductor pattern layer in the conventional display area 01.

[0098] In an alternative implementation manner, the pixel circuit semiconductor pattern layers in different columns in the first display area 11 are not connected to each other in the second direction.

[0099] In this application, the connection semiconductor CL can be provided on the same layer as the semiconductor pattern layer, and the two can be prepared simultaneously, reducing the process complexity.

[0100] It should be noted that the position of the connection semiconductor CL and its position relative to the first semiconductor pattern layer 111 in this implementation manner are different from those in the above embodiments, and other structural designs can be the same as any of the above embodiments, which will not be elaborated here.

[0101] In addition, along the thickness direction of the display panel, the connection semiconductor CL can also be provided below the semiconductor pattern layer, and a planarization layer can be included between the connection semiconductor and the semiconductor pattern layer, and vias are provided on the planarization layer. That is, the connection semiconductor is prepared before the semiconductor pattern layer is prepared, and when the semiconductor pattern layer is prepared, the semiconductor pattern layer and the connection semiconductor are connected through the vias. In addition, the conductivity of the connection semiconductor can be better than that of the semiconductor pattern layer, which is beneficial to the dispersion of static electricity.

[0102] Figure 21 is a schematic diagram of the display device provided by the embodiment of this application, as Figure 21As shown, the display device includes the display panel 001 provided in any of the above embodiments. The display device provided in the embodiments of the present application can be a mobile phone. In addition, the display device provided in the embodiments of the present application can also be a display device such as a computer or a television.

[0103] As Figure 21 shown, the display device provided in the embodiments of the present application further includes an optical device 002, and the optical device 002 is disposed at the position of the functional area 02 of the display device corresponding to the display panel 001. That is, along the thickness direction of the display panel 001, the optical device 002 is disposed below the functional area 02 of the display panel 001. Then, the optical device 002 can emit light to the light-emitting surface side of the display panel 001 through the functional area 02, or can receive light from the light-emitting surface side of the display panel 001 through the functional area 02. Among them, the optical device is at least one of an optical fingerprint sensor, an iris recognition sensor, a camera, and a flashlight.

[0104] In the present application, by connecting the second semiconductor pattern layer 121 to the first semiconductor pattern layer 111, the continuity of the semiconductor pattern layer in the functional area 02 is achieved, and the risk of static electricity flowing into the semiconductor pattern layer in the functional area 02 is reduced. At the same time, the second semiconductor pattern layer 121 in series is connected to the first semiconductor pattern layer 111 in series, so that the relatively high-density static electricity on the second semiconductor pattern layer 121 is dispersed in the first semiconductor pattern layer 111 and the second semiconductor pattern layer 121, making the distribution of static electricity in the semiconductor pattern layer uniform. Furthermore, the reliability and uniformity of the performance of the semiconductor pattern layer in subsequent high-temperature processes can be improved, so that the driving capabilities of the pixel circuits are basically the same, and the display uniformity of the display panel is achieved.

[0105] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that, Comprising: A conventional display area, the conventional display area including a first display area, a second display area, and a third display area; wherein, along a first direction, the length of the second display area is respectively less than the lengths of the first display area and the third display area, and the length of the first display area is less than the length of the third display area; A functional area, the sub-pixel density of the functional area being less than the sub-pixel density of the conventional display area; along the first direction, the second display area, the functional area, and the first display area are adjacent in sequence; along a second direction, at least one of the first display area and the second display area and the functional display area are adjacent to the third display area; the first direction intersects with the second direction; wherein: One of the first display area and the third display area is a specific display area, the specific display area including a plurality of first pixel circuits, the first pixel circuits including a first semiconductor pattern layer, and any one of the first semiconductor pattern layers is connected to at least one of the first semiconductor pattern layers arranged adjacent thereto along a third direction; the included angle between the third direction and the first direction is a first included angle α, 90° > α ≥ 0°; The second display area includes a plurality of second pixel circuits, the second pixel circuits including a second semiconductor pattern layer, and any one of the second semiconductor pattern layers is connected to at least one of the second semiconductor pattern layers arranged adjacent thereto along a fourth direction; the included angle between the fourth direction and the first direction is a second included angle β, 90° > β ≥ 0°; Wherein, the second semiconductor pattern layer arranged and connected along the fourth direction and the first semiconductor pattern layer arranged and connected along the third direction are connected, the functional area includes a light-transmitting area and the first semiconductor pattern layer and the second semiconductor pattern layer are disconnected in the light-transmitting area.

2. The display panel according to claim 1, characterized in that, The first display area is the specific display area.

3. The display panel according to claim 2, characterized in that, The functional area includes a light-transmitting area and a transition area surrounding the light-transmitting area; The transition area includes at least one connecting semiconductor, and the second semiconductor pattern layer arranged and connected along the fourth direction and the first semiconductor pattern layer arranged and connected along the third direction are connected through the connecting semiconductor.

4. The display panel according to claim 3, characterized in that, One connecting semiconductor is connected to one of the second semiconductor pattern layers in the second display area close to the functional area, and is connected to one of the first semiconductor pattern layers in the first display area close to the functional area.

5. The display panel according to claim 3, characterized in that, One connecting semiconductor is connected to a plurality of the second semiconductor pattern layers in the second display area close to the functional area, and is connected to a plurality of the first semiconductor pattern layers in the first display area close to the functional area.

6. The display panel according to claim 3, characterized in that, The transition area further includes a metal trace group, the metal trace group including a plurality of metal traces.

7. The display panel according to claim 6, characterized in that, In a plane perpendicular to the thickness direction of the display panel, the connecting semiconductor is arranged on a side of the metal trace group away from the light-transmitting area.

8. The display panel according to claim 6, characterized in that, In a plane perpendicular to the thickness direction of the display panel, the connecting semiconductor is arranged on a side of the metal trace group close to the light-transmitting area.

9. The display panel according to claim 6, characterized in that, Along the thickness direction of the display panel, the metal trace group covers the connecting semiconductor.

10. The display panel according to claim 3, characterized in that, The sub-pixel density of the light-transmitting region is 0.

11. The display panel according to claim 10, characterized in that, The light-transmitting region is the hollowed-out region of the display panel.

12. The display panel according to claim 10, characterized in that, The light-transmitting region is the non-hollowed-out region of the display panel.

13. The display panel according to claim 3, characterized in that, The sub-pixel density of the light-transmitting region is greater than 0.

14. The display panel according to claim 1, characterized in that, The third display region is the specific display region; The display panel further includes a semiconductor connection region; along the first direction, the semiconductor connection region is disposed on a side of the second display region away from the functional region; The semiconductor connection region includes at least one connecting semiconductor; one connecting semiconductor is connected to a plurality of the second semiconductor pattern layers in the second display region close to the semiconductor connection region, and one connecting semiconductor is connected to a plurality of the first semiconductor pattern layers in the third display region close to the semiconductor connection region; The number of the first semiconductor pattern layers connected to the same connecting semiconductor is more than the number of the second semiconductor pattern layers connected thereto.

15. The display panel according to claim 14, characterized in that, Along the first direction, all the second semiconductor pattern layers in the second display region close to the semiconductor connection region are connected to one connecting semiconductor, and all the first semiconductor pattern layers in the third display region close to the semiconductor connection region are connected to one connecting semiconductor.

16. The display panel according to claim 1, characterized in that, The third direction is parallel to the fourth direction, and 90° > α > 0°, 90° > β > 0°.

17. The display panel according to claim 1, wherein The third direction is parallel to the fourth direction, and α = 0°, β = 0°.

18. The display panel according to claim 1, wherein The number of the second pixel circuits arranged along the first direction in the second display region is M, and the number of the first pixel circuits arranged along the first direction in the specific display region is N, where both M and N are positive integers greater than or equal to 2, and 50 ≥ N / M ≥ 12.

19. The display panel according to claim 1, wherein Both the first semiconductor pattern layer and the second semiconductor pattern layer are one of polysilicon and metal oxide semiconductor.

20. A display device, wherein Comprising the display panel according to any one of claims 1-19 and an optical device, the optical device is disposed at a position of the display device corresponding to the functional region.

21. The display device according to claim 20, wherein The optical device is at least one of an optical fingerprint sensor, an iris recognition sensor, a camera, and a flashlight.

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