Display panel and display device including the same

Abstract

The present invention discloses a display panel and a display device including the display panel. The display panel includes: a substrate including a main display area and an auxiliary display area, the auxiliary display area including a first pixel area, a second pixel area, and a transmissive area; a first pixel located in the first pixel area and including a first pixel electrode, a first pair of electrodes, and a first intermediate layer located between the first pixel electrode and the first pair of electrodes; a second pixel located in the second pixel area and including a second pixel electrode, a second pair of electrodes, and a second intermediate layer located between the second pixel electrode and the second pair of electrodes; a pixel defining layer located on the first pixel electrode and the second pixel electrode and having a first opening and a second opening, the centers of the first pixel electrode and the second pixel electrode being respectively exposed through the first opening and the second opening; and a first barrier wall located on the pixel defining layer.

Description

Technical Field

[0001] Aspects of some example embodiments relate to a display panel and a display device including the display panel. Background Art

[0002] In recent years, various uses or applications of display devices have become diversified. In addition, as the thickness and weight of display devices have decreased, their range of use has increased.

[0003] Since display devices are utilized in various ways, there may be various methods of designing the shape of display devices. In addition, functions of combining / connecting a display device with another display device have been added.

[0004] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus, the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0005] Aspects of some example embodiments relate to a display panel and a display device including the display panel, and for example, relate to a display panel with improved quality and a display device including the display panel.

[0006] One or more example embodiments include a display device having an auxiliary display area in which sensors and the like can be placed within the display area, such that functions of combining / connecting the display device with another display device can be increased. However, this feature is only an example, and the scope of embodiments according to the present disclosure is not limited thereto.

[0007] Additional aspects will be set forth in part in the description that follows and, in part, will become apparent from the description, or may be learned by practice of the example embodiments provided herein.

[0008] According to one or more example embodiments, a display panel includes a substrate including a main display area and an auxiliary display area, the auxiliary display area including a first pixel area, a second pixel area, and a transmissive area; a first pixel located in the first pixel area and including a first pixel electrode, a first pair of electrodes, and a first intermediate layer located between the first pixel electrode and the first pair of electrodes; a second pixel located in the second pixel area and including a second pixel electrode, a second pair of electrodes, and a second intermediate layer located between the second pixel electrode and the second pair of electrodes; a pixel defining layer located on the first pixel electrode and the second pixel electrode and having a first opening and a second opening, with the centers of the first pixel electrode and the second pixel electrode being respectively exposed through the first opening and the second opening; and a first barrier wall located on the pixel defining layer between the first pixel and the second pixel and having a top surface on which the first pair of electrodes and the second pair of electrodes overlap each other.

[0009] According to some example embodiments, the display panel may further include a third pixel located in the first pixel region, where the third pixel includes a third pixel electrode, a third intermediate layer located on the third pixel electrode, and a first pair of electrodes corresponding to the third intermediate layer and located in the first pixel region.

[0010] According to some example embodiments, the display panel may further include a second barrier rib on a pixel defining layer located between the first pixel and the third pixel.

[0011] According to some example embodiments, the first pair of electrodes may be located on a top surface of the second barrier rib.

[0012] According to some example embodiments, the display panel may further include a fourth pixel located in the second pixel region, where the fourth pixel includes a fourth pixel electrode, a fourth intermediate layer located on the fourth pixel electrode, and a second pair of electrodes corresponding to the fourth intermediate layer and located in the second pixel region.

[0013] According to some example embodiments, the display panel may further include a third barrier rib on a pixel defining layer located between the second pixel and the fourth pixel.

[0014] According to some example embodiments, the second pair of electrodes may be located on a top surface of the third barrier rib.

[0015] According to some example embodiments, distal ends of the first pair of electrodes and distal ends of the second pair of electrodes that overlap each other on the first barrier rib may be located on the first barrier rib.

[0016] According to some example embodiments, the first pair of electrodes and the second pair of electrodes may have an overlapping region, at least a part of the first pair of electrodes and at least a part of the second pair of electrodes overlap each other in the overlapping region, and the overlapping region may have a first reflectivity, and the first pixel region and the second pixel region except the overlapping region may have a second reflectivity different from the first reflectivity.

[0017] According to some example embodiments, the first pair of electrodes may be located in at least one first pixel region.

[0018] According to some example embodiments, the second pair of electrodes may be located in at least one second pixel region.

[0019] According to some example embodiments, a top surface of the first pair of electrodes and a bottom surface of the second pair of electrodes may be in surface contact with each other on the first barrier rib and may be in electrical contact with each other.

[0020] According to some example embodiments, the first pixel region, the second pixel region, and the transmissive region may be alternately arranged and may be arranged in a grid.

[0021] According to some example embodiments, the first pair of electrodes may have a first rectangular shape having a first width in a first direction, and the second pair of electrodes may have a second rectangular shape having a second width in the first direction, and the dimension of the first width may be the same as the dimension of the second width.

[0022] According to some example embodiments, a plurality of first pixel regions, a plurality of second pixel regions, and a plurality of transmissive regions may be located in the auxiliary display region, and the plurality of first pixel regions and the plurality of second pixel regions may be alternately arranged in a third direction, and the plurality of transmissive regions may be arranged in the third direction.

[0023] According to one or more example embodiments, a display device includes: a display panel including a substrate including a main display region and an auxiliary display region, the auxiliary display region including a pixel region and a transmissive region, the pixel region including a first pixel region and a second pixel region; a first pixel located in the first pixel region and including a first pixel electrode, a first pair of electrodes, and a first intermediate layer located between the first pixel electrode and the first pair of electrodes; a second pixel located in the second pixel region and including a second pixel electrode, a second pair of electrodes, and a second intermediate layer located between the second pixel electrode and the second pair of electrodes; a pixel defining layer located on the first pixel electrode and the second pixel electrode and having a first opening and a second opening, a center of the first pixel electrode and the second pixel electrode being respectively exposed through the first opening and the second opening; and a first barrier rib located on the pixel defining layer between the first pixel and the second pixel and having a top surface, the first pair of electrodes and the second pair of electrodes overlapping each other on the top surface; and components located at or corresponding to the auxiliary display region under the substrate and including electronic elements configured to transmit or receive signals (e.g., light or sound).

[0024] According to some example embodiments, the resolution of an image provided from the auxiliary display region may be lower than the resolution of an image provided from the main display region.

[0025] According to some example embodiments, the first pair of electrodes and the second pair of electrodes may have an overlapping region in which at least a portion of the first pair of electrodes and at least a portion of the second pair of electrodes overlap each other, and the overlapping region may have a first reflectivity, and the first pixel region and the second pixel region except for the overlapping region may have a second reflectivity different from the first reflectivity.

[0026] According to some example embodiments, a top surface of the first pair of electrodes and a bottom surface of the second pair of electrodes may be in surface contact with each other and may be in electrical contact with each other on the first barrier rib.

[0027] According to some example embodiments, the first pixel region, the second pixel region, and the transmissive region may be alternately arranged and may be arranged in a grid. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features, and characteristics of certain example embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a perspective view schematically showing a display device according to some example embodiments;

[0030] Figure 2 is a cross-sectional view schematically showing a display device according to some example embodiments;

[0031] Figure 3 is a plan view schematically showing a display panel according to some example embodiments;

[0032] Figure 4 illustrates Figure 3 an enlarged plan view of an example of an auxiliary display area;

[0033] Figure 5 and Figure 6 are equivalent circuit diagrams of a main pixel and / or an auxiliary pixel that may be included in a display panel according to some example embodiments;

[0034] Figure 7 is a cross-sectional view schematically showing a stacked structure of a main pixel and / or an auxiliary pixel that may be included in a display panel according to some example embodiments;

[0035] Figure 8 and Figure 9 are plan views illustrating a part of an auxiliary display area according to some example embodiments;

[0036] Figure 10 are plan views illustrating a part of an auxiliary display area according to some example embodiments;

[0037] Figure 11 are plan views illustrating a part of an auxiliary display area according to some example embodiments;

[0038] Figure 12 and Figure 13 are cross-sectional views schematically showing a part of a process of manufacturing a display panel according to some example embodiments;

[0039] Figure 14 is schematically showing along Figure 11 a cross-sectional view of a cross-section of an auxiliary display area taken along line B-B';

[0040] Figure 15 is a sectional view schematically showing a cross-section of an auxiliary display area taken along line C-C' of Figure 11 ;

[0041] Figure 16 is a plan view showing a part of an auxiliary display area according to some example embodiments;

[0042] Figure 17 is a sectional view schematically showing a cross-section of an auxiliary display area taken along line D-D' of Figure 16 ; and

[0043] Figure 18 is a sectional view schematically showing a cross-section of an auxiliary display area taken along line E-E' of Figure 16 ; DETAILED DESCRIPTION

[0044] Reference will now be made in more detail to example embodiments illustrated in the accompanying drawings, in which like reference numerals always refer to like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below only by referring to the drawings to explain aspects of the present specification. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" modify the entire list of elements when following a list of elements, rather than individual elements in the list.

[0045] Since the present disclosure permits various changes and many embodiments, specific embodiments will be illustrated in the drawings and described in more detail in the written description. The characteristics and features of some example embodiments of the present disclosure and the manner of implementing them will become more apparent by referring to the example embodiments that will be described in more detail later with reference to the drawings. However, embodiments in accordance with the present disclosure are not limited to the following example embodiments, but may be embodied in various forms.

[0046] Hereinafter, example embodiments of the present disclosure will be described in more detail below with reference to the drawings. Those components that are the same or corresponding are given the same reference numerals regardless of the reference numerals in the drawings, and redundant descriptions thereof are omitted.

[0047] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] It will be further understood that the terms “comprises” and / or “comprising” used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components. It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, there can be intermediate layers, regions, or components.

[0049] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily illustrated for ease of explanation, the following embodiments are not limited thereto.

[0050] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0051] When a certain embodiment can be implemented differently, a specific process can be performed in an order different from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0052] Figure 1 is a perspective view schematically showing a display device 1 according to some example embodiments.

[0053] Reference Figure 1 , the display device 1 includes a display area (DA and SA) for implementing an image and a non-display area NDA that does not implement an image. That is, the display device 1 is configured to display an image in the display area (DA and SA), and the image is not displayed in the non-display area NDA. The display area includes a main display area DA and a secondary display area SA inside the main display area DA. The display device 1 can use light emitted from a plurality of main pixels PXm in the main display area DA to provide a main image.

[0054] The display device 1 further includes a secondary display area SA inside the main display area DA. As will be described in more detail later with reference to Figure 2 , the secondary display area SA can be an area in which a component such as a sensor using infrared light (IR), visible light, or sound is provided below it. The secondary display area SA can include a transmissive area TA through which light or / and sound output from the component or traveling from the outside toward the component can pass. According to some example embodiments, when IR passes through the secondary display area SA, the light transmittance can be about 10% or higher, more specifically, about 20% or higher, about 25% or higher, about 50% or higher, about 85% or higher, or about 90% or higher.

[0055] According to some example embodiments, a plurality of auxiliary pixels PXa may be located in the auxiliary display area SA, and light emitted from the plurality of auxiliary pixels PXa may be used to provide a specific image from the auxiliary display area SA. The image provided from the auxiliary display area SA may be an auxiliary image and may have a lower resolution than the image provided from the main display area DA. That is, since the auxiliary display area SA includes a transmissive area TA through which light and / or sound can pass, the number of auxiliary pixels PXa that can be provided per unit area may be less than the number of main pixels PXm provided per unit area in the main display area DA.

[0056] According to some example embodiments, the auxiliary display area SA may be on one side of the main display area DA. According to some example embodiments, Figure 1 The figure shows that the auxiliary display area SA is on the upper side of the main display area DA and between the non-display area NDA and the main display area DA.

[0057] Hereinafter, according to some example embodiments, the display device 1 is described as an organic light-emitting diode (OLED) display device. However, the display device according to the embodiments of the present disclosure is not limited thereto. According to some example embodiments, various types of display devices may be used, such as inorganic electroluminescent (EL) display devices, quantum dot light-emitting display devices, and the like.

[0058] In Figure 1 the auxiliary display area SA is on the upper side of the main display area DA having a rectangular shape. However, the embodiments are not limited thereto. The shape of the main display area DA may be circular, oval, or polygonal (e.g., triangular or pentagonal), and the position and number of the auxiliary display areas SA may be modified in various ways.

[0059] Therefore, as Figure 1 illustrated in, an embodiment according to the present invention includes a display device 1 having a display area (DA and SA) and a non-display area NDA surrounding the display area. The display area may include a main display area DA having a plurality of main pixels PXm and one or more auxiliary display areas SA having a plurality of auxiliary pixels PXa located within the main display area DA. One or more components (such as sensors, or sound or light emitters (e.g., speakers), which will be described in more detail below) may be additionally located at the auxiliary display area SA. The density of the auxiliary pixels PXa at the auxiliary display area SA may be less than the density of the main pixels PXm at the main display area DA in order to accommodate one or more transmissive areas TA to allow light or sound (emitted or received by one or more components) to pass through the transmissive area TA.

[0060] Figure 2 is a schematic cross-sectional view of a display device 1 according to some example embodiments.Figure 2 It can correspond to a cross-section taken along Figure 1 the line A-A'.

[0061] Referring to Figure 2 , the display device 1 may include a display panel 10 and a component 20. The display panel 10 includes display elements, and the component 20 is located below the display panel 10 and corresponds to the auxiliary display area SA. In Figure 2 , the component 20 corresponds to one pixel area PA and one transmissive area TA. However, the embodiments are not limited thereto, and the component 20 may correspond to a plurality of pixel areas PA and a plurality of transmissive areas TA.

[0062] The display panel 10 may include a substrate 100, a display element layer 200 located on the substrate 100, and a thin film encapsulation layer 300 as a sealing member for sealing the display element layer 200. Additionally, the display panel 10 may further include a lower protective film 175 below the substrate 100.

[0063] The substrate 100 may include glass or a polymer resin. The polymer resin may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing the above polymer resin and an inorganic layer.

[0064] The display element layer 200 may include a circuit layer including thin film transistors TFTs, organic light emitting diodes OLEDs as display elements, and an insulating layer IL therebetween.

[0065] Main pixels PXm including thin film transistors TFTs and organic light emitting diodes OLEDs connected to the thin film transistors TFTs may be located in the main display area DA, and auxiliary pixels PXa including thin film transistors TFTs and organic light emitting diodes OLEDs connected to the thin film transistors TFTs and wirings may be located in the auxiliary display area SA.

[0066] Additionally, transmissive areas TA where no display elements and thin film transistors TFTs are placed may be located in the auxiliary display area SA. The transmissive area TA may be an area through which light or signals emitted from the component 20 or incident on the component 20 can pass or penetrate.

[0067] The component 20 can be placed in the auxiliary display area SA. The component 20 can include electronic components that use light or sound. For example, the component 20 can include sensors that receive and use light (such as IR sensors), sensors that output and detect light or sound to measure distance or identify fingerprints, small lights that output light, speakers that output sound, or camera sensors. However, embodiments of the present disclosure are not limited to the components listed above and can include any other suitable components, for example, components configured to transmit or receive signals (such as light, radio waves, IR, sound, etc.). In the case of electronic components that use light, light with various wavelengths can be used, such as visible light, IR, and ultraviolet (UV) light. There can be multiple components 20 located in the auxiliary display area SA. For example, a light-emitting device and a light-receiving device can be provided as components 20 in one auxiliary display area SA. Alternatively, a light-emitting part and a light-receiving part can be provided in one component 20 at the same time.

[0068] The thin-film encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 2 The figure shows a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and the organic encapsulation layer 320 therebetween.

[0069] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include one or more inorganic insulating materials, such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 can include polymer-based materials. The polymer-based materials can include PET, PEN, PC, PI, polyethersulfonate, polyoxymethylene, polyacrylate, hexamethyldisiloxane (HMDSO), acrylic resins (such as polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0070] The lower protective film 175 can be attached to the lower part of the substrate 100 and can support and protect the substrate 100. The lower protective film 175 can include an opening 175OP corresponding to the auxiliary display area SA. The opening 175OP can be formed in the lower protective film 175, and thus, the light transmittance of the auxiliary display area SA can be improved. The lower protective film 175 can include PET or PI.

[0071] The area of the auxiliary display area SA can be larger than the area of the region where the component 20 is located. In Figure 2 this case, the area of the auxiliary display area SA is the same as the area of the opening 175OP of the lower protective film 175. However, the area of the opening 175OP formed in the lower protective film 175 can be different from the area of the auxiliary display area SA. For example, the area of the opening 175OP can be smaller than the area of the auxiliary display area SA.

[0072] In addition, a plurality of components 20 may be located in the auxiliary display area SA. The plurality of components 20 may have different functions.

[0073] According to some example embodiments, elements such as an input sensing member that senses a touch input, an antireflection member including a polarizer and a retarder or including a color filter and a black matrix, and a transparent window may be further located on the display panel 10.

[0074] According to some example embodiments, the thin film encapsulation layer 300 serves as an encapsulation member for sealing the display element layer 200. However, the embodiments are not limited thereto. For example, a sealing substrate bonded to the substrate 100 using a sealant or a frit may also be used as a member for sealing the display element layer 200.

[0075] Figure 3 is a schematic plan view showing the display panel 10 according to some example embodiments, and Figure 4 is a diagram showing Figure 3 an enlarged plan view of an example of the auxiliary display area SA.

[0076] Referring to Figure 3 , various elements constituting the display panel 10 are located on the substrate 100. The substrate 100 includes a display area and a non-display area NDA surrounding the display area. The display area includes a main display area DA for displaying a main image and an auxiliary display area SA including a transmissive area TA and displaying an auxiliary image.

[0077] Main pixels PXm are located in the main display area DA. Each of the main pixels PXm may include a display element, such as an organic light emitting diode OLED. Each of the main pixels PXm may emit red light, green light, blue light, or white light from the organic light emitting diode OLED. As described above, the main pixels PXm in this specification may be pixels that emit one of red light, green light, blue light, and white light. The main display area DA may be covered with the encapsulation member described with reference to Figure 2 and may be protected from external air or moisture.

[0078] The auxiliary display area SA can be on one side of the main display area DA, and the auxiliary pixels PXa are located in the auxiliary display area SA. Each of the auxiliary pixels PXa can include a display element, such as an organic light-emitting diode OLED. Each of the auxiliary pixels PXa can emit red light, green light, blue light, or white light from the organic light-emitting diode OLED. As described above, the auxiliary pixels PXa in this specification can be pixels that emit one of red light, green light, blue light, and white light. The transmissive area TA can be provided in the auxiliary display area SA and between the auxiliary pixels PXa. At least one component 20 can be arranged to correspond to the lower part of the auxiliary display area SA of the display panel 10.

[0079] Since the auxiliary display area SA includes the transmissive area TA, the resolution of the auxiliary display area SA can be lower than the resolution of the main display area DA. For example, the resolution of the auxiliary display area SA can be about 1 / 2 of the resolution of the main display area DA. According to some example embodiments, the resolution of the main display area DA can be 400 ppi or higher, and the resolution of the auxiliary display area SA can be about 200 ppi.

[0080] Reference will be made to Figure 4 describe more details of the auxiliary display area SA according to some example embodiments.

[0081] The auxiliary display area SA can include a pixel area PA and a transmissive area TA, and the pixel area PA includes at least one auxiliary pixel PXa. The pixel area PA and the transmissive area TA can be alternately provided in the fourth direction DR4 (see Figure 8 )), for example, in a grid form.

[0082] The pixel area PA can include auxiliary pixels Pr that emit red light, auxiliary pixels Pg that emit green light, and auxiliary pixels Pb that emit blue light. In Figure 4 , a Pentile-type auxiliary pixel PXa is shown. However, the auxiliary pixels PXa can be provided in a stripe form or various forms. Additionally, in Figure 4 , four auxiliary pixels PXa are provided in one pixel area PA. However, the number of auxiliary pixels PXa can be modified according to the resolution of the auxiliary display area SA.

[0083] According to some example embodiments, the pixel circuit of one main pixel PXm can be the same as the pixel circuit of one auxiliary pixel PXa. However, the embodiments are not limited thereto. The pixel circuit included in the main pixel PXm can be different from the pixel circuit included in the auxiliary pixel PXa.

[0084] The auxiliary pixel PXa may not be located in the transmissive region TA. The fact that the auxiliary pixel PXa is not located in the transmissive region TA may mean that display elements such as an organic light-emitting diode OLED of the auxiliary pixel PXa may not be included in the transmissive region TA. That is, a pixel electrode, an intermediate layer, and a counter electrode constituting the organic light-emitting diode OLED and a pixel circuit electrically connected to the organic light-emitting diode OLED may not be located in the transmissive region TA. A part of signal lines PL, DL, SL, and EL connected to supply signals to the auxiliary pixel PXa located in the pixel region PA may cross the transmissive region TA. However, even in such a case, in order to increase the transmittance of the transmissive region TA, the signal lines PL, DL, SL, and EL may bypass the center of the transmissive region TA.

[0085] According to some example embodiments, a conductive layer may also be located on the substrate 100 to correspond to the pixel region PA of the auxiliary display region SA. The conductive layer may be located under the auxiliary pixel PXa, for example, between the thin-film transistor of the auxiliary pixel PXa and the substrate 100. The conductive layer may block external light emitted from the component 20 from being incident on a pixel circuit (e.g., see PC in Figure 5 ), and may prevent or reduce its influence. A constant voltage or signal may be applied to the conductive layer so that damage to the pixel circuit PC due to electrostatic discharge can be prevented or reduced. A plurality of conductive layers may be provided in the auxiliary display region SA. Different voltages may be supplied to the plurality of conductive layers according to circumstances.

[0086] Return reference Figure 3 , each of the main pixel PXm and the auxiliary pixel PXa may be electrically connected to an external circuit located in the non-display region NDA. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power supply line 160, and the second power supply line 170 may be located in the non-display region NDA.

[0087] The first scan driving circuit 110 may provide a scan signal to each of the main pixel PXm and the auxiliary pixel PXa via the scan line SL. The first scan driving circuit 110 may provide an emission control signal to each pixel via the emission control line EL. The second scan driving circuit 120 may be disposed in parallel with the first scan driving circuit 110, with the main display region DA between the second scan driving circuit 120 and the first scan driving circuit 110. Some pixels of the main pixel PXm and the auxiliary pixel PXa may be electrically connected to the first scan driving circuit 110, and other pixels of the main pixel PXm and the auxiliary pixel PXa may be connected to the second scan driving circuit 120. According to some example embodiments, the second scan driving circuit 120 may be omitted.

[0088] Terminal 140 may be located on one side of substrate 100. Terminal 140 may not be covered by an insulating layer, but may be exposed and electrically connected to a printed circuit board (PCB). The PCB-P of the PCB may be electrically connected to terminal 140 of display panel 10. The PCB transmits signals or power of the controller to display panel 10. Control signals generated by the controller may be transmitted via the PCB to each of the first scan driving circuit 110 and the second scan driving circuit 120. The controller may supply a first power voltage and a second power voltage to the first power line 160 and the second power line 170 via the first connection wiring 161 and the second connection wiring 171 (see ELVDD and ELVSS of Figure 5 and Figure 6 described below). The first power voltage ELVDD may be supplied to each of the main pixel PXm and the auxiliary pixel PXa via a driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS may be supplied to counter electrodes of each of the main pixel PXm and the auxiliary pixel PXa connected to the second power line 170.

[0089] The data driving circuit 150 is electrically connected to the data line DL. Data signals of the data driving circuit 150 may be provided to each of the main pixel PXm and the auxiliary pixel PXa via a connection wiring 151 connected to terminal 140 and a data line DL connected to the connection wiring 151. Figure 3 The figure shows the data driving circuit 150 located on the PCB. However, according to some example embodiments, the data driving circuit 150 may be located on the substrate 100. For example, the data driving circuit 150 may be between the terminal 140 and the first power line 160.

[0090] The first power line 160 may include a first sub-line 162 and a second sub-line 163, which extend parallel to each other in the x direction, with the main display area DA between the first sub-line 162 and the second sub-line 163. The second power line 170 may have an annular shape with an open side and may partially surround the main display area DA.

[0091] Figure 5 and Figure 6 are equivalent circuit diagrams of the main pixel PXm and / or the auxiliary pixel PXa that may be included in the display panel 10 according to some example embodiments.

[0092] The pixel circuit PC includes a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 may be connected to the scan line SL and the data line DL, and may transmit the data signal Dm input through the data line DL to the driving TFT T1 according to a scan signal Sn input through the scan line SL.

[0093] The storage capacitor Cst is connected to the switching TFT T2 and the driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching TFT T2 and the first power supply voltage (or driving voltage) ELVDD supplied to the driving voltage line PL.

[0094] The driving TFT T1 can be connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL corresponding to the voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a certain brightness according to the driving current.

[0095] In Figure 5 , the pixel circuit PC includes two TFTs and one storage capacitor. However, the embodiment is not limited thereto. As Figure 6 shown, the pixel circuit PC may include seven TFTs and one storage capacitor. In Figure 6 , the pixel circuit PC includes one storage capacitor. However, the pixel circuit PC may include two or more storage capacitors.

[0096] Referring to Figure 6 , each of the main pixel PXm and the auxiliary pixel PXa includes a pixel circuit PC and an organic light-emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a storage capacitor and a plurality of TFTs. The storage capacitor and the plurality of TFTs may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0097] In Figure 6 , each of the main pixel PXm and the auxiliary pixel PXa is connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL. However, the embodiment is not limited thereto. According to some example embodiments, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared by adjacent pixels.

[0098] The signal lines may include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting a previous scan signal Sn-1 to a first initialization TFT T4 and a second initialization TFT T7, an emission control line EL for transmitting an emission control signal En to an operation control TFT T5 and an emission control TFT T6, and a data line DL intersecting the scan line SL and transmitting a data signal Dm. A driving voltage line PL transmits a driving voltage ELVDD to a driving TFT T1, and an initialization voltage line VL transmits an initialization voltage Vint for initializing the driving TFT T1 and the pixel electrode of the organic light emitting diode OLED.

[0099] The driving gate electrode G1 of the driving TFT T1 may be connected to the lower electrode Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving TFT T1 may be connected to the driving voltage line PL via the operation control TFT T5, and the driving drain electrode D1 of the driving TFT T1 may be electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6. The driving TFT T1 may receive the data signal Dm according to the switching operation of the switching TFT T2, and supply a driving current I OLED to the organic light emitting diode OLED.

[0100] The switching gate electrode G2 of the switching TFT T2 may be connected to the scan line SL, the switching source electrode S2 of the switching TFT T2 may be connected to the data line DL, the switching drain electrode D2 of the switching TFT T2 may be connected to the driving source electrode S1 of the driving TFT T1, and may be connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 may be turned on according to the scan signal Sn transmitted via the scan line SL, and may perform a switching operation of transmitting the data signal Dm transmitted via the data line DL to the driving source electrode S1 of the driving TFT T1.

[0101] The compensating gate electrode G3 of the compensating TFT T3 may be connected to the scan line SL, the compensating source electrode S3 of the compensating TFT T3 may be connected to the driving drain electrode D1 of the driving TFT T1, and may be connected to the pixel electrode of the organic light emitting diode OLED via the emission control TFT T6, and the compensating drain electrode D3 of the compensating TFT T3 may be connected to the lower electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensating TFT T3 may be turned on according to the scan signal Sn transmitted via the scan line SL, and may electrically connect the driving gate electrode G1 of the driving TFT T1 to the driving drain electrode D1, thereby diode-connecting the driving TFT T1.

[0102] The first initialization gate electrode G4 of the first initialization TFT T4 can be connected to the previous scan line SL-1, and the first initialization source electrode S4 of the first initialization TFT T4 can be connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization TFT T4 can be connected to the lower electrode Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the drive gate electrode G1 of the drive TFT T1. The first initialization TFT T4 can be turned on according to the previous scan signal Sn-1 transmitted via the previous scan line SL-1, and can perform an initialization operation of transmitting the initialization voltage Vint to the drive gate electrode G1 of the drive TFT T1, so as to initialize the voltage of the drive gate electrode G1 of the drive TFT T1.

[0103] The operation control gate electrode G5 of the operation control TFT T5 can be connected to the emission control line EL, the operation control source electrode S5 of the operation control TFT T5 can be connected to the drive voltage line PL, and the operation control drain electrode D5 of the operation control TFT T5 can be connected to the drive source electrode S1 of the drive TFT T1 and the switch drain electrode D2 of the switch TFT T2.

[0104] The emission control gate electrode G6 of the emission control TFT T6 can be connected to the emission control line EL, the emission control source electrode S6 of the emission control TFT T6 can be connected to the drive drain electrode D1 of the drive TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and the emission control drain electrode D6 of the emission control TFT T6 can be electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0105] The operation control TFT T5 and the emission control TFT T6 can be turned on simultaneously according to the emission control signal En transmitted via the emission control line EL, and thus, the drive voltage ELVDD can be transmitted to the organic light emitting diode OLED, and the drive current I OLED can flow through the organic light emitting diode OLED.

[0106] For the second initialization of the TFT T7, the second initialization gate electrode G7 of the second initialization TFT T7 may be connected to the previous scan line SL-1, and the second initialization source electrode S7 of the second initialization TFT T7 may be connected to the emission control drain electrode D6 of the emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED. Also, the second initialization drain electrode D7 of the second initialization TFT T7 may be connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 may be turned on according to the previous scan signal Sn-1 transmitted via the previous scan line SL-1, and may initialize the pixel electrode of the organic light emitting diode OLED.

[0107] In Figure 6 , the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SL-1. However, the embodiments are not limited thereto. According to some example embodiments, the first initialization TFT T4 may be connected to the previous scan line SL-1 and may be driven according to the previous scan signal Sn-1, while the second initialization TFT T7 may be connected to an additional signal line, such as a subsequent scan line, and may be driven according to the signal transmitted to the signal line.

[0108] The upper electrode Cst2 of the storage capacitor Cst may be connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED may be connected to the line to which the second power supply voltage ELVSS is provided. Thus, the organic light emitting diode OLED may receive the driving current I from the driving TFT T1 OLED and may emit light, thereby displaying an image.

[0109] In Figure 6 , the compensation TFT T3 and the first initialization TFT T4 have dual gate electrodes. However, the compensation TFT T3 and the first initialization TFT T4 may have one gate electrode.

[0110] Figure 7 is a cross-sectional view schematically showing a stacked structure of the main pixel PXm and / or the auxiliary pixel PXa that may be included in the display panel 10 according to some example embodiments.

[0111] Hereinafter, Figure 7 a stacked structure of one pixel according to some example embodiments will be described with reference to

[0112] The substrate 100 may include glass or a polymer resin. The polymer resin may include PES, polyacrylate, PEI, PEN, PET, PPS, polyarylate, PI, PC, or CAP. The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer containing the above polymer resin and an inorganic layer.

[0113] The buffer layer 111 may be located on the substrate 100, may reduce or prevent the penetration of foreign substances, moisture, and / or external air from below the substrate 100, and may provide a flat surface for the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic compound, and may have a single-layer or multilayer structure including an inorganic material and an organic material. A barrier layer for preventing or reducing the penetration of external air may be further included between the substrate 100 and the buffer layer 111.

[0114] The gate electrodes G1 and G6 are located on the semiconductor layers A1 and A6, and a first gate insulating layer 112 is located between the gate electrodes G1 and G6 and the semiconductor layers A1 and A6. The gate electrodes G1 and G6 may include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may have a single-layer or multilayer structure. In an example, the gate electrodes G1 and G6 may have a single-layer structure of Mo. The scan line SL, the previous scan line SL-1, and the emission control line EL may be formed on the same layer as the gate electrodes G1 and G6. That is, the gate electrodes G1 and G6, the scan line SL, the previous scan line SL-1, and the emission control line EL may be located on the first gate insulating layer 112.

[0115] The first gate insulating layer 112 may include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0116] A second gate insulating layer 113 may be provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 may include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2).

[0117] The lower electrode Cst1 of the storage capacitor Cst may be formed integrally with the gate electrode G1 of the driving TFT T1. For example, the gate electrode G1 of the driving TFT T1 may be used as the lower electrode Cst1 of the storage capacitor Cst.

[0118] The upper electrode Cst2 of the storage capacitor Cst overlaps with the lower electrode Cst1, and the second gate insulating layer 113 is between the upper electrode Cst2 and the lower electrode Cst1 of the storage capacitor Cst. In this case, the second gate insulating layer 113 can be used as the dielectric layer of the storage capacitor Cst. The upper electrode Cst2 can include a conductive material containing Mo, Al, Cu, and Ti, and can have a multi-layer or single-layer structure including the above materials. In an example, the upper electrode Cst2 can have a single-layer structure of Mo or a multi-layer structure of Mo / Al / Mo.

[0119] In Figure 7 , the storage capacitor Cst overlaps with the driving TFT T1. However, the embodiment is not limited thereto. The storage capacitor Cst can be modified in various ways in which the storage capacitor Cst may not overlap with the driving TFT T1.

[0120] The upper electrode Cst2 can be used as the electrode voltage line HL. For example, a part of the electrode voltage line HL can be the upper electrode Cst2 of the storage capacitor Cst.

[0121] An interlayer insulating layer 115 can be provided to cover the upper electrode Cst2. The interlayer insulating layer 115 can include silicon oxide (SiO2), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum pentoxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). In Figure 7 , the interlayer insulating layer 115 has a single-layer structure. According to some example embodiments, the interlayer insulating layer 115 can also have a multi-layer structure.

[0122] The data line DL, the driving voltage line PL, and the contact metal 1175 can be located on the interlayer insulating layer 115. The data line DL, the driving voltage line PL, and the contact metal 1175 can include a conductive material containing Mo, Al, Cu, and Ti, and can have a multi-layer or single-layer structure including the above materials. In an example, the data line DL, the driving voltage line PL, and the contact metal 1175 can have a multi-layer structure of Ti / Al / Ti.

[0123] The upper electrode Cst2 of the storage capacitor Cst can be in contact with the driving voltage line PL via a contact hole CNT defined in the interlayer insulating layer 115. This can mean that the electrode voltage line HL is in contact with the driving voltage line PL via the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the driving voltage line PL.

[0124] The contact metal 1175 is in contact with the semiconductor layer A6 of the emission control TFT T6 via a contact hole 1153 that passes through the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control TFT T6 can be electrically connected to the pixel electrode 210 of the organic light-emitting diode OLED via the contact metal 1175.

[0125] The planarization layer 117 is located on the data line DL, the driving voltage line PL, and the contact metal 1175. The organic light-emitting diode OLED can be located on the planarization layer 117.

[0126] The planarization layer 117 can have a flat top surface, and the pixel electrode 210 can be formed flatly on this flat top surface. The planarization layer 117 can have a single-layer or multi-layer structure formed of an organic material. The planarization layer 117 can include general polymers (such as benzocyclobutene (BCB), PI, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and / or their blends. The planarization layer 117 can include inorganic materials. The planarization layer 117 can include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When the planarization layer 117 includes inorganic materials, chemical mechanical polishing can be performed as appropriate. The planarization layer 117 can include both organic materials and inorganic materials.

[0127] The pixel electrode 210 can include a (semi)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 can include a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and / or their compounds, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide (IGO), and aluminum zinc oxide (AZO). According to some exemplary embodiments, the pixel electrode 210 can have a stacked structure of ITO / Ag / ITO.

[0128] The pixel defining layer 118 may be located on the planarization layer 117. The pixel defining layer 118 may have an opening 118OP exposing the center of the pixel electrode 210, thereby defining the emission region of the pixel. Additionally, the pixel defining layer 118 may increase the distance between the edge of the pixel electrode 210 and the counter electrode 230 located at the upper portion of the pixel electrode 210, thereby preventing or reducing the occurrence of arcing at the edge of the pixel electrode 210. The pixel defining layer 118 may be formed of an organic insulating material such as PI, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin by spin coating.

[0129] The barrier rib 119 may be located on the pixel defining layer 118. When forming the intermediate layer 220, the barrier rib 119 may reduce the distance between the mask and the pixel electrode 210, thereby preventing or reducing color mixing. Additionally, when forming the counter electrode 230, the barrier rib 119 may reduce the distance between the mask and the intermediate layer 220, thereby preventing the counter electrode 230 from being formed with a large thickness. The barrier rib 119 may include an organic insulating material such as PI, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and may be formed by a method such as spin coating.

[0130] The intermediate layer 220 of the organic light-emitting diode OLED may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic emission layer may include a small molecular weight organic material or a polymeric organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may optionally be further located under / above the organic emission layer. The intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210. However, the embodiments are not limited thereto. There may be various modifications, such as the intermediate layer 220 including an integral layer entirely located on the plurality of pixel electrodes 210.

[0131] The counter electrode 230 may include a transmissive electrode or a reflective electrode. According to some exemplary embodiments, the counter electrode 230 may include a transparent or semi-transparent electrode and may include a thin metal layer having a small work function, the thin metal layer including lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, Al, silver (Ag), magnesium (Mg), and / or a compound thereof. Additionally, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In2O3 may be further located on the thin metal layer.

[0132] When the pixel electrode 210 includes a reflective electrode and the counter electrode 230 includes a transmissive electrode, light emitted from the intermediate layer 220 can be emitted toward the counter electrode 230, and thus, the display device 1 can be a top (front)-emission type. When the pixel electrode 210 includes a transparent or semi-transparent electrode and the counter electrode 230 includes a reflective electrode, light emitted from the intermediate layer 220 can be emitted toward the substrate 100, and thus, the display device 1 can be a bottom (rear)-emission type. However, the embodiments are not limited thereto. The display device 1 according to some example embodiments can be a dual-emission type in which light is emitted in two directions such as the front direction and the rear direction.

[0133] According to some example embodiments, the counter electrode 230 can be entirely located on the entire surface of the main display area DA, and a part of the edge can be located in the non-display area NDA. The counter electrode 230 can be integrally formed in the main pixels PXm (i.e., a plurality of organic light-emitting diodes OLEDs) located in the main display area DA and can correspond to the plurality of pixel electrodes 210.

[0134] The counter electrode 230 is provided in the auxiliary pixels PXa located in the auxiliary display area SA. That is, Figure 7 the counter electrode 230 can correspond to the first counter electrode 230a or the second counter electrode 230b which will be described in more detail below. Figure 8

[0135] However, the auxiliary display area SA can include a transmissive area TA and a pixel area PA in which the auxiliary pixels PXa are placed. Therefore, a part of the counter electrode 230 may not be provided in the partial area corresponding to the transmissive area TA. In the case of a top (front)-emission type display device, light can be emitted toward the counter electrode 230. However, due to the counter electrode 230, the transmittance of the top (front)-emission type display device may be partially reduced. Therefore, the counter electrode 230 is not provided in the area corresponding to the transmissive area TA, and thus, the transmittance of the transmissive area TA can be increased.

[0136] To this end, the counter electrode 230 in the auxiliary display area SA can be patterned according to the pixel area PA. The counter electrode 230 in the auxiliary display area SA can be formed by removing the partial area corresponding to the transmissive area TA by using laser lift-off or by patterning with a fine metal mask (FMM).

[0137] According to some example embodiments, the counter electrode 230 is formed in the main display area DA and the auxiliary display area SA by FMM patterning.

[0138] Figure 8 and Figure 9 are a plan view illustrating a part of the auxiliary display area SA according to some example embodiments, andFigure 10 FIG. is a plan view showing a part of the auxiliary display area SA according to some example embodiments. Figure 8 may correspond to Figure 3 region B of

[0139] Referring to Figure 8 , the counter electrode 230 in the main display area DA and the auxiliary display area SA can be formed by FMM patterning, and the auxiliary display area SA can include a pixel area PA and a transmissive area TA, and the auxiliary pixel PXa can be located in the pixel area PA.

[0140] As Figure 9 shown in

[0141] , the pixel area PA can include a first pixel area PA1 and a second pixel area PA2, and the first pixel PXa1 and the fifth pixel PXa5 can be located in the first pixel area PA1, and the second pixel PXa2 and the sixth pixel PXa6 can be located in the second pixel area PA2. Figure 13 ), the second pixel PXa2 can include a second pixel electrode 210b, a second counter electrode 230b, and a second intermediate layer 220b between the second pixel electrode 210b and the second counter electrode 230b (see Figure 13 ).

[0142] According to some example embodiments, the first counter electrode 230a can be provided in the first pixel area PA1, and the second counter electrode 230b can be provided in the second pixel area PA2. The first counter electrode 230a can be arranged to correspond to the first pixel area PA1, and the second counter electrode 230b can be arranged to correspond to the second pixel area PA2, and the first counter electrode 230a and the second counter electrode 230b can have an overlapping area in which at least some of the first counter electrode 230a and the second counter electrode 230b overlap each other on the first barrier wall 119a placed on the pixel defining layer 118, and the first barrier wall 119a is between the first pixel PXa1 and the second pixel PXa2.

[0143] In this case, the distal ends of the first counter electrode 230a and the second counter electrode 230b that overlap each other on the first barrier wall 119a can be located on the first barrier wall 119a.

[0144] As Figure 9As illustrated, the barrier wall 119 according to some example embodiments may have a structure in which a first barrier wall 119a is located between a first pixel PXa1 and a second pixel PXa2 and a fourth barrier wall 119d is located between a fifth pixel PXa5 and a sixth pixel PXa6. Alternatively, as Figure 10 As illustrated, the barrier wall 119 according to some example embodiments may have a structure in which the first barrier wall 119a between the first pixel PXa1 and the second pixel PXa2 extends between the fifth pixel PXa5 and the sixth pixel PXa6.

[0145] Return reference Figure 8 The first pair of electrodes 230a located in the first pixel region PA1 may have a first width W1 in a first direction DR1 and may have a first rectangular shape, and the second pair of electrodes 230b may have a second rectangular shape having a second width W2 in the first direction DR1. In this case, the first width W1 of the first pair of electrodes 230a and the second width W2 of the second pair of electrodes 230b may be substantially the same, and the first rectangular shape of the first pair of electrodes 230a and the second rectangular shape of the second pair of electrodes 230b may be substantially the same.

[0146] An overlapping region in which at least a part of the first pair of electrodes 230a and at least a part of the second pair of electrodes 230b overlap each other may have a first reflectance, and the first pixel region PA1 and the second pixel region PA2 except for the overlapping region may have a second reflectance. In this case, since at least some of the first pair of electrodes 230a and the second pair of electrodes 230b overlap each other in the overlapping region, the first reflectance of the overlapping region and the second reflectance of the first pixel region PA1 and the second pixel region PA2 except for the overlapping region may be different from each other.

[0147] The auxiliary pixel PXa located in the first pixel region PA1 may include the first pair of electrodes 230a formed integrally throughout at least one first pixel region PA1. The first pair of electrodes 230a formed integrally throughout at least one first pixel region PA1 may mean that the first pair of electrodes 230a are formed by the same mask process. In Figure 9 In, the first pair of electrodes 230a are formed integrally throughout one first pixel region PA1. However, the first pair of electrodes 230a may be formed integrally throughout two or more first pixel regions PA1.

[0148] In addition, the auxiliary pixel PXa located in the second pixel region PA2 may include a second pair of electrodes 230b formed integrally throughout at least one second pixel region PA2. The second pair of electrodes 230b formed integrally throughout at least one second pixel region PA2 may mean that the second pair of electrodes 230b are formed through the same mask process. In Figure 9 , the second pair of electrodes 230b are formed integrally throughout one second pixel region PA2. However, the second pair of electrodes 230b may be formed integrally throughout two or more second pixel regions PA2.

[0149] Figure 11 is a plan view showing a part of the auxiliary display area SA according to some example embodiments.

[0150] Reference Figure 11 , a plurality of first pixel regions PA1, a plurality of second pixel regions PA2, and a plurality of transmissive regions TA may be provided in the auxiliary display area SA. The plurality of first pixel regions PA1 and the plurality of second pixel regions PA2 may be arranged in the third direction DR3, and the plurality of transmissive regions TA may be arranged in the third direction DR3. Accordingly, the first pixel regions PA1, the second pixel regions PA2, and the transmissive regions TA may be alternately arranged and may be arranged in a grid structure.

[0151] When the counter electrode 230 is patterned through an opening mask in the main display area DA and the counter electrode 230 is patterned through an FMM in the auxiliary display area SA, a shadow appears in the boundary portion between the main display area DA and the auxiliary display area SA, and the thickness of the counter electrode 230 changes, and thus, an abnormality of color coordinates occurs.

[0152] In addition, as the resolution increases, the size of the portion of the pixel defining layer 118 located between its adjacent openings may decrease. Accordingly, the overlapping portion where the counter electrodes 230 may be in electrical contact with each other is insufficient, and thus, dark wiring may occur. Due to the shadow, different types of counter electrodes 230 may be additionally formed in the emission region of the organic light emitting diode OLED, and ultimately, the thickness of the counter electrode 230 may change and an abnormality of color coordinates may occur.

[0153] Accordingly, according to some example embodiments, when the counter electrode 230 is formed in the main display area DA and the auxiliary display area SA through FMM patterning, the barrier wall 119 is located on the pixel defining layer 118, and thus, the counter electrode 230 may be formed to have a relatively uniform thickness in the emission region of the organic light emitting diode OLED.

[0154] Figure 12 and Figure 13is a cross-sectional view schematically showing a part of a process of manufacturing a display panel 10 according to some example embodiments, and Figure 14 is a cross-sectional view schematically showing a cross-section of an auxiliary display area SA taken along line Figure 11 B-B', and Figure 15 is a cross-sectional view schematically showing a cross-section of an auxiliary display area SA taken along line Figure 11 C-C'.

[0155] Referring to Figure 12 , an insulating layer IL in which a pixel circuit PC is placed is formed on a substrate 100, and a first pixel electrode 210a and a second pixel electrode 210b are formed to be electrically connected to the pixel circuit PC. The first pixel electrode 210a is located in a first pixel area PA1, and the second pixel electrode 210b is located in a second pixel area PA2.

[0156] A pixel defining layer 118 having an opening is formed on the first pixel electrode 210a and the second pixel electrode 210b, and a first barrier rib 119a is formed on the pixel defining layer 118. The opening is for exposing the centers of the first pixel electrode 210a and the second pixel electrode 210b. A first intermediate layer 220a is formed on the first pixel electrode 210a exposed through the opening of the pixel defining layer 118, and a second intermediate layer 220b is formed on the second pixel electrode 210b exposed through the opening of the pixel defining layer 118. The first intermediate layer 220a and the second intermediate layer 220b may include the same material as the intermediate layer 220 described above.

[0157] Subsequently, a first pair of electrodes 230a and a second pair of electrodes 230b may be formed on the first intermediate layer 220a and the second intermediate layer 220b. According to some example embodiments, the first pair of electrodes 230a and the second pair of electrodes 230b may be formed by an FMM process.

[0158] When the first pair of electrodes 230a is formed on the first intermediate layer 220a, a first mask M1 is in close contact with the first barrier rib 119a, as Figure 12 shown. Accordingly, a part of the first pair of electrodes 230a may be formed in the second pixel area PA2, and the first pair of electrodes 230a may be prevented from being formed on the second intermediate layer 220b.

[0159] After the first pair of electrodes 230a is formed, when the second pair of electrodes 230b is formed on the second intermediate layer 220b, a second mask M1' is in close contact with the first barrier rib 119a and the first pair of electrodes 230a, as Figure 13 shown. Accordingly, a part of the second pair of electrodes 230b may be formed in the first pixel area PA1, and the second pair of electrodes 230b may be prevented from being formed on the first intermediate layer 220a.

[0160] In this case, the first mask M1 and the second mask M1' are the same mask, and after forming the first pair of electrodes 230a using the first mask M1, the first mask M1 can be moved in the third direction DR3 to form the second pair of electrodes 230b.

[0161] Reference Figure 14 , an overlapping region ORA where at least a part of the first pair of electrodes 230a and the second pair of electrodes 230b overlap each other can be located on the first barrier wall 119a. The first pair of electrodes 230a and the second pair of electrodes 230b can be in surface contact with each other through the overlapping region ORA, and thus can be in electrical contact with each other. The first pair of electrodes 230a and the second pair of electrodes 230b being in surface contact with each other can mean that there is no layer between the first pair of electrodes 230a and the second pair of electrodes 230b, and the second pair of electrodes 230b is stacked on the first pair of electrodes 230a, and thus the top surface of the first pair of electrodes 230a and the bottom surface of the second pair of electrodes 230b are in contact with each other.

[0162] In the overlapping region ORA, the second pair of electrodes 230b can be located on the first pair of electrodes 230a. This may mean that the second pair of electrodes 230b is formed in a process later than the first pair of electrodes 230a. The first pair of electrodes 230a and the second pair of electrodes 230b are in surface contact with each other, and thus, the overlapping region ORA can be formed to have a thickness twice that of the region where only the first pair of electrodes 230a or the second pair of electrodes 230b is located. Therefore, the overlapping region ORA can be not placed in the emission regions of the first pixel PXa1 and the second pixel PXa2. In this case, the emission regions can be formed in the pixel defining layer 118 and can be respectively defined as a first opening OP1 and a second opening OP2, and the centers of the first pixel electrode 210a and the second pixel electrode 210b are respectively exposed through the first opening OP1 and the second opening OP2.

[0163] When performing a deposition process using the FMM, the first barrier wall 119a located on the pixel defining layer 118 can prevent the formation of the first pair of electrodes 230a on the second intermediate layer 220b and can prevent the formation of the second pair of electrodes 230b on the first intermediate layer 220a. The first pair of electrodes 230a and the second pair of electrodes 230b can overlap each other on the first barrier wall 119a, and the distal ends of the first pair of electrodes 230a and the distal ends of the second pair of electrodes 230b overlapping each other on the first barrier wall 119a can be placed on the first barrier wall 119a. That is, the overlapping region ORA can be provided or arranged so as not to overlap with the first opening OP1 and the second opening OP2 formed in the pixel defining layer 118.

[0164] Reference Figure 11 and Figure 15, compared with the first pixel region PA1, the transmissive region TA may not include display elements such as an organic light-emitting diode (OLED) and a pixel circuit PC electrically connected to the display element. In addition, the transmissive region TA may be defined as a region where a part of the layer disposed on the substrate 100 is removed. As Figure 15 shown, the transmissive region TA may be defined as an opening formed in the pixel defining layer 118. According to some example embodiments, a part of the insulating layer IL under the pixel defining layer 118 may be further removed according to the transmissive region TA.

[0165] Figure 16 is a plan view illustrating a part of the auxiliary display region SA according to some example embodiments, Figure 17 is a schematic cross-sectional view taken along the line Figure 16 D-D’ of the auxiliary display region SA, and Figure 18 is a schematic cross-sectional view taken along the line Figure 16 E-E’ of the auxiliary display region SA.

[0166] Referring to Figure 16 , according to some example embodiments, the barrier wall 119 may be between the auxiliary pixels PXa in the auxiliary display region SA. The barrier wall 119 between the auxiliary pixels PXa may prevent or reduce color mixing caused by the mixing of emission materials when the intermediate layer 220 is formed on the pixel electrode 210. Hereinafter, this will be described in more detail with reference to Figure 17 and Figure 18 .

[0167] The display panel 10 according to some example embodiments may further include a third pixel PXa3 placed in the first pixel region PA1. Referring to Figure 17 , the third pixel PXa3 may include a third pixel electrode 210c, a third intermediate layer 220c placed on the third pixel electrode 210c, and a first pair of electrodes 230a placed in the first pixel region PA1 to correspond to the third intermediate layer 220c, and may further include a second barrier wall 119b placed on the pixel defining layer 118 between the first pixel PXa1 and the third pixel PXa3.

[0168] When the third intermediate layer 220c is formed on the third pixel electrode 210c, the second barrier wall 119b makes the FMM in close contact with the second barrier wall 119b, thereby preventing or reducing color mixing due to the mixing of the organic material for forming the third intermediate layer 220c and the organic material for forming the first intermediate layer 220a.

[0169] The display panel 10 according to some example embodiments may further include a fourth pixel PXa4 placed in the second pixel region PA2. Refer to Figure 18 , the fourth pixel PXa4 may include a fourth pixel electrode 210d, a fourth intermediate layer 220d placed on the fourth pixel electrode 210d, and a second pair of electrodes 230b placed in the second pixel region PA2 to correspond to the fourth intermediate layer 220d, and may further include a third barrier wall 119c placed on the pixel defining layer 118 between the second pixel PXa2 and the fourth pixel PXa4.

[0170] When the fourth intermediate layer 220d is formed on the fourth pixel electrode 210d, the third barrier wall 119c makes the FMM in close contact with the third barrier wall 119c, thereby preventing or reducing color mixing caused by the mixing of the organic material for forming the fourth intermediate layer 220d and the organic material for forming the second intermediate layer 220b.

[0171] The pixel region PA and the transmissive region TA of the auxiliary display area SA may be formed in the second direction DR2. When the pixel region PA and the transmissive region TA of the auxiliary display area SA are formed in the second direction DR2, the pixel region PA and the transmissive region TA may be alternately placed in the first direction DR1.

[0172] Except for those in the above embodiments, the pixel region PA and the transmissive region TA of the auxiliary display area SA may be provided in various forms. In addition, except for those in the above embodiments, the first pair of electrodes 230a and the second pair of electrodes 230b may be provided in various forms.

[0173] According to one or more embodiments, in order to solve the problem of color coordinate abnormality occurring in the boundary portion between the auxiliary display area where components are placed and the main display area where a plurality of pixels are placed in the display panel and the display device including the display panel according to the prior art, in the auxiliary display area where components are arranged and the main display area where a plurality of main pixels are provided, by using a barrier wall to form a pair of electrodes, a display panel with improved quality and a display device including the display panel can be provided.

[0174] So far, only the display panel and the display device including the display panel have been mainly described. However, the embodiments are not limited thereto. For example, a method for manufacturing a display device also belongs to the scope of the present disclosure.

[0175] As described above, in one or more embodiments of the present disclosure, in an auxiliary display area in which components are arranged and in a main display area in which a plurality of main pixels are arranged, counter electrodes are formed using barrier ribs, so that a display panel with improved quality and a display device including the display panel can be achieved. The scope of the present disclosure is not limited by these effects.

[0176] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes may be made in form and detail without departing from the spirit and scope defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: A substrate, comprising a main display area and an auxiliary display area, wherein the auxiliary display area comprises a first pixel area, a second pixel area and a transmissive area; A first pixel, located in the first pixel area, and comprising a first pixel electrode, a first pair of electrodes and a first intermediate layer located between the first pixel electrode and the first pair of electrodes; A second pixel, located in the second pixel area, and comprising a second pixel electrode, a second pair of electrodes and a second intermediate layer located between the second pixel electrode and the second pair of electrodes; A pixel defining layer, located on the first pixel electrode and the second pixel electrode, and having a first opening and a second opening, wherein the centers of the first pixel electrode and the second pixel electrode are respectively exposed through the first opening and the second opening; A first barrier wall, located on the pixel defining layer between the first pixel and the second pixel, and having a top surface, wherein the first pair of electrodes and the second pair of electrodes overlap each other on the top surface; And An overlapping area, in which at least a part of the first pair of electrodes and at least a part of the second pair of electrodes overlap each other; Wherein the pixel defining layer, the first barrier wall and the overlapping area overlap each other.

2. The display panel according to claim 1, further comprising A third pixel, located in the first pixel region, wherein The third pixel includes a third pixel electrode, a third intermediate layer located on the third pixel electrode, and a first pair of electrodes corresponding to the third intermediate layer and located in the first pixel region.

3. The display panel according to claim 2, further comprising A second barrier wall, located on the pixel defining layer between the first pixel and the third pixel.

4. The display panel according to claim 3, wherein The first pair of electrodes is located on the top surface of the second barrier wall.

5. The display panel according to claim 1, further comprising A fourth pixel, located in the second pixel region, wherein The fourth pixel includes a fourth pixel electrode, a fourth intermediate layer located on the fourth pixel electrode, and a second pair of electrodes corresponding to the fourth intermediate layer and located in the second pixel region.

6. The display panel according to claim 5, further comprising A third barrier wall, located on the pixel defining layer between the second pixel and the fourth pixel.

7. The display panel according to claim 6, wherein The second pair of electrodes is located on the top surface of the third barrier wall.

8. The display panel according to claim 1, wherein The distal ends of the first pair of electrodes and the distal ends of the second pair of electrodes that overlap each other on the first barrier wall are located on the first barrier wall.

9. The display panel according to claim 1, wherein The overlapping region has a first reflectivity, and The first pixel region and the second pixel region, except for the overlapping region, have a second reflectivity different from the first reflectivity.

10. The display panel according to claim 1, wherein The first pair of electrodes is located in at least one first pixel region.

11. The display panel according to claim 1, wherein The second pair of electrodes is located in at least one second pixel region.

12. The display panel according to claim 1, wherein The top surface of the first pair of electrodes and the bottom surface of the second pair of electrodes are in surface contact with each other and are in electrical contact with each other on the first barrier wall.

13. The display panel according to claim 1, wherein The first pixel region, the second pixel region, and the transmissive region are alternately arranged and arranged in a grid.

14. The display panel according to claim 1, wherein The first pair of electrodes has a first rectangular shape with a first width in a first direction, and The second pair of electrodes has a second rectangular shape with a second width in the first direction, and The size of the first width is the same as the size of the second width.

15. The display panel according to claim 1, wherein A plurality of first pixel regions, a plurality of second pixel regions, and a plurality of transmissive regions are provided in the auxiliary display region, and The plurality of first pixel regions and the plurality of second pixel regions are alternately arranged in a third direction, and the plurality of transmissive regions are arranged in the third direction.

16. A display device, comprising: A display panel, comprising a substrate, wherein the substrate comprises a main display area and an auxiliary display area, the auxiliary display area comprises a pixel area and a transmissive area, and the pixel area comprises a first pixel area and a second pixel area; A first pixel, located in the first pixel area, and comprising a first pixel electrode, a first pair of electrodes and a first intermediate layer located between the first pixel electrode and the first pair of electrodes; A second pixel, located in the second pixel area, and comprising a second pixel electrode, a second pair of electrodes and a second intermediate layer located between the second pixel electrode and the second pair of electrodes; A pixel defining layer, located on the first pixel electrode and the second pixel electrode, and having a first opening and a second opening, wherein the centers of the first pixel electrode and the second pixel electrode are respectively exposed through the first opening and the second opening, and A first barrier wall, located on the pixel defining layer between the first pixel and the second pixel, and having a top surface, wherein the first pair of electrodes and the second pair of electrodes overlap each other on the top surface; An overlapping area, in which at least a part of the first pair of electrodes and at least a part of the second pair of electrodes overlap each other; And A component, located under the substrate at the auxiliary display area, and comprising electronic components configured to transmit or receive signals; Wherein the pixel defining layer, the first barrier wall and the overlapping area overlap each other.

17. The display device according to claim 16, wherein The resolution of the image provided from the auxiliary display region is lower than the resolution of the image provided from the main display region.

18. The display device according to claim 16, wherein the overlapping region has a first reflectivity, and the first pixel region and the second pixel region other than the overlapping region have a second reflectivity different from the first reflectivity.

19. The display device according to claim 16, wherein the top surface of the first pair of electrodes and the bottom surface of the second pair of electrodes are in surface contact with each other and in electrical contact with each other on the first barrier wall.

20. The display device according to claim 16, wherein the first pixel region, the second pixel region, and the transmissive region are alternately arranged and arranged in a grid.

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