Supports systems that use external I / O interfaces to pass test, debug, or trace information

Abstract

Techniques and mechanisms for exchanging test, debug, or trace (TDT) information via a general purpose input / output (I / O) interface. In an embodiment, an I / O interface of a device is coupled to an external TDT unit, wherein the I / O interface is compatible with an interconnect standard that supports the transfer of data other than any test information, debug information, or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I / O interface. The information exchanged via the I / O interface generates or causes the execution of one or more TDT operations by evaluating the execution of one or more TDT operations of the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I / O interface with a test access point that is coupled between the one or more circuit components and the I / O interface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 60 / 245,931, filed October 23, 2015, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments discussed herein relate generally to microelectronic circuit arrangements, and more particularly (but exclusively) to evaluating the operation of an integrated circuit using a universal interface. Background Art

[0004] Currently, a typical laptop, tablet, smartphone or other system includes a system on chip (SoC) and / or other integrated circuit (IC) that is debugged and tested via a JTAG (or cJTAG) interface. Typically, it is desirable to send debug traces from system circuits (e.g., SoC or other IC) via a high-speed interface present on the system. The JTAG test data output (TDO) pin can also be used to send output debug traces, albeit at a lower data rate. Typically, the IEEE-1149.1 JTAG interface runs at approximately 100 MHz. The IEEE Standards Committee has also developed a 2-pin JTAG interface (also known as compact JTAG or cJTAG) via the IEEE-1149.7 standard, which uses TMS and TCK signals for debugging and testing. Since the data rate of the JTAG interface is typically about 100 Mhz and most trace requirements are much higher than the JTAG data rate, the trace is conventionally sent from the system via a dedicated high-speed serial trace port. However, as devices trend toward "closed chassis" solutions with fewer external connectors, there is an increasing need to eliminate external ports specific to supporting testing, debugging, and / or tracing information. Summary of the invention

[0005] According to the first aspect of the present invention, a system for server computing includes: an integrated circuit, including: a functional interface compatible with a protocol based on Peripheral Component Interconnect Express (PCIe), wherein the functional interface is used to receive information associated with testing, debugging or tracing TDT operations; a component, including a circuit for performing the TDT operation based at least in part on the information associated with the TDT operation; a first interface logic coupled between the component and the functional interface, wherein the information associated with the TDT operation is received from the functional interface to the component via the first interface logic; and a second interface logic coupled to the first interface logic and to a memory or I / O space, wherein data associated with the TDT operation is accessed from the memory or the I / O space via the second interface logic based on memory-mapped input / output MMIO information.

[0006] According to the second aspect of the present invention, a system for server computing includes: an integrated circuit, including: a functional interface compatible with a protocol based on Peripheral Component Interconnect Express (PCIe), wherein the functional interface is used to receive information associated with testing, debugging or tracing TDT operations from an external system; a network, used to pass the information associated with the TDT operation to a component, wherein the component is used to perform the TDT operation based at least in part on the information associated with the TDT operation; a first interface logic, coupled between the network and the functional interface, wherein the information associated with the TDT operation is exchanged from the functional interface to the network via the first interface logic; and a second interface logic, coupled to the first interface logic and coupled to a memory or I / O space, wherein data associated with the TDT operation is accessed from the memory or I / O space via the second interface logic based on memory-mapped input / output MMIO information.

[0007] A system for server computing according to a third aspect of the present invention comprises: an integrated circuit, comprising: a functional interface compatible with a protocol based on Peripheral Component Interconnect Express (PCIe), wherein the functional interface is used to couple to an external system, and wherein information associated with testing, debugging or tracing TDT operations is transferred to or from the external system via the functional interface; a network, used to transfer the information associated with the TDT operation to or from a component, wherein the component is used to perform the TDT operation; a first interface logic coupled between the network and the functional interface, wherein the information associated with the TDT operation is exchanged between the functional interface and the network via the first interface logic; and

[0008] A second interface logic coupled to the first interface logic and to a memory or an I / O space, wherein data associated with the TDT operation is accessed from the memory or the I / O space via the second interface logic based on memory-mapped input / output MMIO information; and a central processing unit CPU, wherein the CPU is external to the integrated circuit, and wherein the CPU is used to be coupled to the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, and in which: Figure 1 is a functional block diagram illustrating elements of a system on chip that performs debug and trace operations according to conventional techniques.

[0010] Figure 2 is a functional block diagram illustrating elements of a system that provides perform testing, debugging, or tracing (TDT) functionality according to an embodiment.

[0011] Figure 3 is a flow chart illustrating elements of a method of evaluating a circuit assembly according to an embodiment.

[0012] Figure 4 is a functional block diagram illustrating elements of a system supporting trace and debug operations according to an embodiment.

[0013] Figure 5 is a functional block diagram illustrating elements of a system for evaluating circuits based on memory mapped input / output information according to an embodiment.

[0014] Figure 6 is a functional block diagram illustrating elements of a system for evaluating circuits based on memory mapped input / output information according to an embodiment.

[0015] Figure 7 is a functional block diagram illustrating elements of a system that performs TDT operations according to an embodiment.

[0016] Fig. 8A , Figure 8B are functional block diagrams each illustrating elements of a respective system for evaluating one or more circuit components according to a corresponding embodiment.

[0017] Fig.9A , Fig. 9B are functional block diagrams each illustrating elements of a respective system for evaluating one or more circuit components according to a corresponding embodiment.

[0018] Fig.10 is a functional block diagram illustrating elements of a system for performing TDT evaluation of daisy-chain devices according to an embodiment.

[0019] Fig.11 is a functional block diagram illustrating an exemplary computer device according to one embodiment. DETAILED DESCRIPTION

[0020] The embodiments discussed herein provide various methods for enabling a general purpose input / output (IO) interface (e.g., with Thunderbolt) to communicate with a computer. TM As used herein, "PCIe" refers to compatibility with the Peripheral Component Interconnect (PCI) Express (or PCIe) standard, such as the PCIe 3.1 specification released by the PCI Special Interest Group (PCI-SIG) in November 2014, the PCIe 4.0 specification announced by the PCI-SIG on November 29, 2011, or any of various other such standards. The term "Thunderbolt" refers to any interface that is compatible with the Peripheral Component Interconnect (PCI) Express (or PCIe) standard. TM” (or “TBT”) in this article refers to Thunderbolt TM 2 Requirements, Thunderbolt TM 3Requires or other types of Thunderbolt TM Interface compatible features. Certain features of various embodiments are discussed herein with reference to an external interface, wherein the external interface is "PCIe / TBT" (i.e., a PCIe interface or a Thunderbolt TM (TBT) interface) and which is used to exchange TBT information with a "test access port network" (i.e., a network of test access ports internal to the system). However, this discussion can be extended to any external interface including various other types of external interfaces and / or any internal system network of various other types of internal system networks. For example, some embodiments may instead exchange TDT with a "debug access port network" (i.e., a network of debug access ports of various components in the system). A serial wire debug (SWD) port is just one example of a port that may be interconnected to form a debug access port (DAP) network in order to participate in TDT exchanges with a PCIe, TBT, or other functional interface.

[0021] As used herein, "test / debug / trace" (or "TDT") refers to functionality that supports test, debug, and / or trace operations and / or functionality that supports the transfer of debug information, test information, and / or debug information based on (or otherwise supporting) such operations. "External interface" is used herein to refer to a wired or wireless interface of a system that provides a communicative coupling of the system to an external agent. An external interface can be general purpose, at least to the extent that it is configured to support one or more types of communications in addition to supporting TDT functionality. For example, an external I / O interface can be compatible with a peripheral interconnect standard (e.g., the PCIe standard or Thunderbolt 3). TM The peripheral interconnect standard supports the transfer of operational data in addition to any test information, debug information, or trace information.

[0022] The term "M.2" herein refers to compatibility with the M.2 standard (e.g., the PCI-SIG M.2 specification or the SATA Rev.3.2 specification). The M.2 connector, previously referred to as the NGFF (Next Generation Form Factor) connector, can be used for internally mounted expansion cards and connectors. These can provide an alternative to the mSATA standard connector and support PCI Express Mini Cards and connectors. "(c) JTAG" as used herein refers to compatibility with the Joint Test Action Group (JTAG) standard (e.g., the IEEE 1149.1 specification of the Institute of Electrical and Electronics Engineers (IEEE)) or the Compact JTAG (cJTAG) standard (e.g., the IEEE 1149.7 specification of the IEEE). The term "USB" herein refers to compatibility with the Universal Serial Bus (USB) standard (e.g., the USB 3.0 specification published by the USB Implementers Forum in November 2008, the USB 3.1 specification published on July 31, 2013, or other such standards). The term "WiFi" refers herein to compatibility with any wireless communication standard of various wireless communication standards, such as standards of the WiFi Alliance or the Bluetooth Special Interest Group, which are based on the IEEE 802.11 specifications of the IEEE.

[0023] Existing systems (e.g., platforms including tablets, laptops, desktops, smartphones, etc., SoCs, etc.) typically include several components (chips, packages, etc.) that are configured to be debugged individually, wherein for each component there is a corresponding connector for coupling the component to some debugging software unit. Debugging may include operations to analyze, optimize, and / or observe the operation of the component. Such components may include, for example, one or more of a modem, an application processor, a different chip, a wireless LAN, etc. These components are traditionally debugged individually. Historically, there have been dedicated interfaces (separate connectors) that connect each component to a test unit that includes debugging software / hardware logic. Such debugging may tune components—e.g., to provide improved bandwidth for a modem, improved response time for an application processor, etc.

[0024] Figure 1A typical system 100 is shown that supports debugging using conventional mechanisms. The system 100 includes a (c) JTAG port 120 (a 4-pin (or 5-pin) JTAG connector or a 2-pin cJTAG connector) that supports the exchange of test and / or debug information with a test access point (TAP) network 130 of the system 100. Components 140 (which are shown to include illustratively a central processing unit (CPU) core 142, a hardware (HW) accelerator 144, and an audio digital signal processor (DSP) 146) are connected to the TAP network 130, which in turn interfaces with the (c) JTAG port 120. An external debugger (not shown) accesses the components 140 via signaling between the (c) JTAG port 120 and the TAP network 130 to read one or more registers of a given component. An additional trace port 110 of the system 100 facilitates the streaming and / or other exchange of trace information 112, 114. Since the data rate of the JTAG interface is typically around 100 Mhz and most trace requirements are much higher than the JTAG data rate, trace is conventionally sent out of the system via a dedicated high speed serial trace port 110 .

[0025] Some embodiments are based on the realization that there are certain types of connectors that are capable of interfacing a system with external agents and / or networks, which can be used to access an internal network of such a system, where the internal network facilitates debugging, testing, and / or tracing of multiple system components. Such embodiments provide functionality to exchange debugging, testing, and / or tracing information via a common hardware interface that supports such external connections. An external connector can be "owned" by a particular component of the system, at least to the extent that access to one or more other system components can be made via the particular component. Such a connector can conform to a standard (e.g., such as the PCIe specification and / or Thunderbolt 3). TM The terms "general purpose I / O", "in-band", "functional" are used herein to describe characteristics of such interfaces that are not limited to the transfer of debug, trace and / or test information. Although certain embodiments are not limited in this respect, the standards to which the external connectors are compatible may provide a "push model" protocol - for example, where commands from a host / source / etc. agent are pushed to a storage or client / sink / etc. component. PCIe and Thunderbolt TM is an example of a push model interface type—for example, where USB is an example of a pull model interface type.

[0026] Alternatively or additionally, the system's internal network (a network accessible only via the system's external connectors) may include one or more buses and / or other interconnects that conform to an interconnect standard—e.g., a standard such as the PCIe specification. Certain components enable one or more external system interface connectors to be eliminated or at least more efficiently utilized in various ways. Instead of using dedicated access points, some embodiments utilize a network internal to the system to perform (e.g., debugging, testing, and / or tracing operations. PCIe is just one example of such a network mechanism. In some illustrative embodiments, externally accessible (e.g., Thunderbolt 3) TM ) connection is used to access the internal network between system components (such as hard drives, etc.). TM (or other) connections, some embodiments support the use of daisy chain configurations to interconnect different devices. Through networked debugging functionality, a single connection to an external component allows a debug host to debug through this connection to complete the device and potentially all devices that are linked.

[0027] Certain embodiments provide debug operations in various ways that rely on protocols that utilize push-type information exchange for external interfaces. For example, even though the USB protocol uses a pull model to communicate in various ways, PCIe / Thunderbolt TM Instead, a push model is implemented, where (for example) commands are pushed from an external agent to the system's memory. The external (functional) interface of the system / platform can be used to access multiple functional blocks of the system / platform. Some embodiments, access to such multiple functional blocks can be performed via one or more wireless interfaces and / or a daisy-chain configuration of some or all such functional blocks. The interconnection (e.g., a PCIe bus) between two such functional blocks can enable one system component to act as a medium for debugging and / or testing of one or more other components - for example, where one or more other components are in the same system or external to the system.

[0028] As used herein, the term "closed chassis" refers to the characteristic of a system that lacks, in its outermost housing or other enclosure, an external interface dedicated to supporting only one or more types of TBT functionality. In embodiments, components of a closed chassis system are coupled to an external (PCIe, TBT, M.2, or other) interface, where TBT-related communications and / or operations are to be supported via the interface. At least one advantage of some embodiments is that PCIe or Thunderbolt TM Supports adaptation of debug functionality (e.g., instead of using USB). It is expected that the next generation interface technology will move more towards PCIe / Thunderbolt due to support for high-speed (e.g., 20Gbps and 40Gbps) signaling. TM .

[0029] The techniques described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the techniques described herein include any type of mobile and / or fixed device, such as a camera, a cellular phone, a computer terminal, a desktop computer, an electronic reader, a fax machine, a public telephone booth, a netbook computer, a notebook computer, an Internet device, a payment terminal, a personal digital assistant, a media player and / or recorder, a server (e.g., a blade server, a rack-mounted server, a combination thereof, etc.), a set-top box, a smart phone, a tablet personal computer, an ultra-mobile personal computer, a wired telephone, a combination thereof, etc. In some embodiments, the techniques described herein may be used in a desktop computer, a laptop computer, a smart phone, a tablet computer, a netbook computer, a notebook computer, a personal digital assistant, a server, a combination thereof, etc. More generally, the techniques described herein may be used in any of a variety of electronic devices that include an external interface and a component configured to participate in TBT operations supported via the external interface.

[0030] To accelerate debugging and / or other TDT communications, PCIe and / or Thunderbolt TM For example, in embodiments may be used to interface with a network of test access points (or "TAP network"), and / or serve as a trace destination for traces sent by various system components. A multiplexing (multiplexing) mechanism to select between the various trace sources may be implemented in a central component or, alternatively, in some combination of components operating together to implement the multiplexing functionality.

[0031] Figure 2 A system 200 (e.g., a SoC, a laptop, a tablet, a smartphone, etc.) is shown that supports communications and / or other operations of TDT evaluation of a circuit according to an embodiment. The system 200 may be a closed chassis system in which the external interface (through which the system 200 accesses an external TDT agent) is not dedicated only to TDT communications. The system 200 includes a functional (e.g., general purpose) I / O interface 210 (e.g., a PCIe interface or a Thunderbolt 3 interface). TM The system 200 may include an I / O interface 210 to enable coupling of the system 200 to an external TDT unit. M.2 is another example of an external interface type that may be suitable for TDT. According to some embodiments, further examples include USB, Wifi, or other external interface mechanisms. In some embodiments, the system 200 also includes an external TDT-specific interface (not shown), wherein at least some TDT exchanges may still occur via the I / O interface 210.

[0032] System 200 is an example of an embodiment in which some or all of the functional I / O interface 210 and internal TAP network 230 coupled to component 235 are employed to facilitate TDT access—e.g., to allow ease of debugging. In the illustrated embodiment shown, component 235 includes an application processor 240, a modem baseband processor BBP 260, and a modem transceiver (Tx / Rx) 280. However, in other embodiments, system 200 may include more, fewer, and / or different components. In one illustrative embodiment, the modem Tx / Rx 280 or other circuitry of component 235 provides WiFi, Bluetooth, frequency modulation (FM) radio, and / or other wireless functionality.

[0033] Components 235 may be coupled to each other in various ways via one or more interconnects (e.g., the illustrated illustrative PCIe buses 250, 270). Interprocessor communication (IPC) links may be used between various processing cores and / or other components of system 200. For example, interconnect 250 may include or be coupled via an IPC-PCIe interface between AP 240 and modem BBP 260. One advantage of such an embodiment may be that the entire SoC may be evaluated via functional I / O interface 210 using (c) JTAG and / or trace exchanges. Conventional techniques instead rely on dedicated debuggers—each for a different respective component and / or each coupled via a respective debug port. In an illustrative embodiment, interconnect 270 supports communications compatible with the DigRF specification (e.g., specification DigRFSM v4 v1.10 published by the MIPI Alliance in December 2011). However, such communications may not support direct control over a PCIe network. In such a case, the debug protocol may be tunneled in such DigRF communications.

[0034] System production, testing, verification, debugging, etc. can be improved by using the functional I / O interface 210 to access the internal TAP network of the TDT. Through the functional I / O interface 210, an external debug tool or other such TDT agent can access different components 235 of the system 200—for example, to establish a trace flow, access registers in any of the various components, etc. The system 200 may also include glue logic 220, which includes circuits, firmware, software, and / or other logic to provide an interface between the TAP network 230 and the functional I / O interface 210. For example, the functional I / O interface 210 may include a PHY, a protocol stack, and / or a protocol stack based on PCIe, Thunderbolt, etc. TM or other such functional I / O standard. Glue logic 220 illustrates the functional I / O interface 210 (e.g., its PCIe protocol logic and / or its ThunderboltTM The glue logic 220 is an example of hardware and / or software running to interface with the TAP network 230 (protocol logic). Such interface logic may implement speed conversion to accommodate different signal communication rates. For example, the glue logic 220 may include or otherwise have access to one or more buffers 222. The glue logic 220 may control buffering and debuffering by the one or more buffers 222 to store information received from the functional I / O interface 210 at a first rate, where such data is subsequently debuffered for communication via the TAP network 230 at a second rate (e.g., 100 MHz) that is lower than the first rate. Alternatively or additionally, such buffer control may store (e.g., store to a different buffer) data received from the TAP network 230 at a relatively low rate, where such information is subsequently debuffered for communication via the functional I / O interface 210 at a much faster rate. Thus, the glue logic 220 may function as a PCIe to TAP (PCIe2TAP) interface and / or Thunderbolt 2. TM Go to the TAP (TBT2TAP) interface to operate.

[0035] Various traces (e.g., illustrative trace streams 244, 264, 284 from AP 240, modem baseband 260, and modem RF 280) may be brought to functional I / O interface 210 for communication to external debug tools. A multiplexing mechanism to select between the various trace sources may be implemented in a central component or in one of the components that may accommodate this logic. Although trace streams 244, 264, 284 are shown as bypassing TAP network 230 and glue logic 220, certain embodiments are not limited in this respect, and some or all such trace streams may require processing (e.g., at glue logic 220) to prepare for communication from system 200 according to the PCIe protocol or the TBT protocol.

[0036] In the illustrative embodiment shown, TDT access (e.g., including (c) JTAG (or other) debug access and / or trace access) to the AP 240, the modem BBP 260, and the modem Tx / Rx 280 may be supported in various ways by the corresponding TDT logic 242, 262, 282. Such TDT logic 242, 262, 282 may provide certain tracing, debugging, and / or testing functionality adapted from conventional techniques in various ways. In some embodiments, one or more of the TDT logic 242, 262, 282 provides functionality for a component to load and run a local TDT agent to perform, for example, a TDT evaluation of the same component or another component. Alternatively or additionally, one or more of the TDT logic 242, 262, 282 may provide functionality to represent the corresponding component as a device of a type that supports TDT functionality (e.g., a multi-function device so identified using a modified PCIe class convention).

[0037] Available via PCIe and Thunderbolt TM The supported data rates (e.g., including 5 Gigabits per second (Gps) and even rates up to 20 Gps and 40 Gps) greatly improve TDT access and switching. In contrast, TAP switching, such as those performed in system 100, has traditionally been at approximately 100 MHz. Some embodiments can be implemented through functions such as TransBolt. TM ) I / O interface 210 to access application processor (AP) 240 and run the agent process therein. The agent can exchange TDT commands / queries via the internal network of system 200 (e.g., such as a network including PCIe buses 250, 270). In response, one or more other components of system 200 can send information back to AP 240 for evaluation, forwarding and / or other processing.

[0038] System 200 may include one or more additional or alternative connectors (e.g., an M.2 connector for a storage module or a communication module) that support PCIe mechanisms. Such connectors may support connection of system 200 to a test or debug tool that accesses components within system 200—e.g., for boundary scan, built-in self-test (BIST), fusing, flashing, testing, and / or debugging).

[0039] Figure 3 Elements of a method 300 for performing TDT operations based on communication via a functional interface according to an embodiment are shown. The method 300 may be performed on an IC chip, a packaged device, a computer platform, or other hardware having some or all of the features of the system 200, for example.

[0040] Method 300 may include, at 310, coupling the device to an external agent via an input / output (I / O) interface of the device. In an embodiment, the device (e.g., which may be or otherwise include, for example, system 200) includes a plurality of circuit components, such as component 235. The device may also include a first network coupling the plurality of circuit components to each other, the first network including access points interconnected to exchange TDT information. Such a first network may include a network of test access points (TAP network) coupled between the plurality of circuit components and the I / O interface. In an embodiment, the I / O interface is coupled to a peripheral interconnect standard (e.g., the PCIe standard or Thunderbolt 3). TM The peripheral interconnect standard supports the transfer of operational data in addition to any test information, debug information, or trace information.

[0041] In an embodiment, the method 300 further includes exchanging information with the external agent via the I / O interface at 320, and exchanging information between the network of the test access point and the I / O interface via the glue logic of the device at 330. The exchanging at 330 may include the glue logic adjusting the transfer of information between a first rate of the I / O interface and a second rate of the network of the test access point. For example, the glue logic may include one or more buffers, wherein the glue logic adjusts the rate of transfer of information by using the one or more buffers to buffer and debuffer data in various ways at different corresponding rates.

[0042] In some embodiments, the exchange at 330 includes mapping I / O information identifying the configuration state and / or other information describing one or more of the circuit components. For example, the device may also include a second network that interfaces with the first network via logic (referred to herein as a bus access unit) coupled between the first network and the second network. The second network may support communications with different formats, data rates, and / or characteristics other than those supported by the first network. Alternatively or additionally, the second network may be coupled to exchange information other than any TDT information. The bus access unit may provide functionality to adjust between different corresponding communication rates of the first network and the second network. In such embodiments, the exchange at 330 may include glue logic exchanging memory mapping I / O information, wherein such memory mapping I / O is accessed via the second network. The exchange at 330 may also include the bus access unit adjusting the rate at which such memory mapping I / O information is transmitted.

[0043] The method may also include performing a TDT operation at 340 to evaluate one of the plurality of circuit components. In an embodiment, the TDT operation generates information, or is performed in response to information. For example, the information may include software code provided by an external agent, wherein performing the TDT operation includes a first circuit component of the plurality of circuit components running the software code. The execution of the software code may cause the first circuit component to provide a TDT process that evaluates the first circuit component and / or some other circuit component of the device. Alternatively or additionally, the information exchanged at 320 and 330 may include one or more commands to be serviced by the TDT agent, results of the TDT operation, and the like.

[0044] Figure 4 Elements of a system 400 that performs TDT operations according to an embodiment are shown. System 400 is an example of an embodiment in which one device of a platform hosts TDT glue logic functionality for other devices of the platform. System 400 may include, for example, some or all of the features of system 200. In one embodiment, method 300 is performed in system 400.

[0045] The system 400 includes a host 410 that includes or is coupled to a functional interface (I / F) 412 that provides coupling of the system 400 to a debug tool and / or other external TDT agent (not shown). For example, the functional I / F 412 may reside on a SoC or on a computer platform that includes the SoC and / or one or more other IC devices. The host 410 may facilitate TDT operations to evaluate one or more components of the system 400, such as an illustrative modem 450 and connectivity logic CNV 460 (e.g., including Bluetooth, wireless LAN, and / or other such circuits).

[0046] By way of illustration and not limitation, glue logic 420 of host 410 may enable the exchange of TDT information between function I / F 412 and a TAP network, which includes, for example, endpoints EP 422, EP 452, and EP 462 of host 410, modem 450, and CNV 460, respectively. As used herein, an "endpoint" (or "EP") refers to a logical terminus of a communication link. The TAP network may also include links (e.g., including illustrative links 444, 446) to couple EP 422, EP 452, and EP 462 to each other in various ways.

[0047] The trace backbone 424 of the glue logic 420 may include circuitry to control communications and / or other operations adapted, for example, from conventional trace techniques. To provide for the exchange of trace information, the interface logic (functionally represented as Trace2PCIe 422) may provide buffering, data rate conversion, and / or other functionality to facilitate communication between the TAP network (via the trace backbone 424) and the PCIe mechanisms contained in or operating with the functional I / F 420. Alternatively or in addition, the debug control 428 may include circuitry to control communications and / or other operations adapted, for example, from conventional (c) JTAG and / or other debug techniques. Additional interface logic (functionally represented as JTAG2PCIe 426) may similarly facilitate the transfer of debug information between the TAP network (via the debug control 428) and the PCIe mechanisms contained in or operating with the functional I / F 420.

[0048] In the illustrative embodiment shown, the host 410 includes local resources (e.g., including an illustrative processor 430) that are to be evaluated through a TBT operation and / or otherwise participate in a TBT operation. The processor 430 may include one or more cores 436 (e.g., of a central processing unit (CPU), an application processor, etc.) to implement software, firmware, and / or other logic (e.g., logic that provides a host operating system (OS), a user interface, etc.). An interconnect 438 of the processor 430 may facilitate the connection of the one or more cores 436 to other components (not shown) of the processor 430—e.g., some or all of such components are to be evaluated through a TBT process according to an embodiment. Alternatively or additionally, the interconnect 438 may provide access to an external communication path, such as to transmit trace information from the processor 430. In one embodiment, the processor 430 includes local interface logic (represented by a functional block PCIe2TAP 434) that includes circuitry to interface the PCIe mechanism of the processor 430 with a TAP network. By way of illustration and not limitation, the circuitry of PCIe2TAP 436 may provide buffering, speed conversion, and / or other glue logic functionality to support exchanges between an internal network (e.g., PCIe hardware including interconnect 438) and corresponding circuitry residing in various manners on components to generate trace data.

[0049] Endpoint EP 432 of processor 430 may be coupled to EP 422 via switch 440, which also facilitates debug and / or other TDT communications between EP 442 and glue logic 420, for example. Processor 430 may also be coupled to switch 440 via PCIe root 414—for example, where PCIe root 414 provides a generic (e.g., in addition to TDT) switch with any of function I / F 412 and / or various components (e.g., modem 450 and NCV 460). The specific architecture in host 410 through which processor 430 is coupled to function I / F 412, glue logic 420, and / or EP 442 is merely illustrative and not limiting of some embodiments.

[0050] One or more components coupled to the host 410 may include corresponding mechanisms (e.g., similar to those of the processor 430) to participate in TBT operations in various ways. For example, the modem 450 may include one or more processor cores 456 and logic (functionally represented by the PCIe2TAP 454) that provides an interface between the TAP network and the PCIe mechanisms internal to the modem 450. Such internal PCIe mechanisms may be used, for example, to enable the one or more cores 456 to access or otherwise manage other resources (not shown) of the modem 450, which are coupled via the interconnect 458. According to an embodiment, some or all of such other resources may be evaluated through TDT operations. Alternatively or additionally, the CNV 460 may include one or more cores 466, a PCIe2TAP 464, and an interconnect 468 that provide functionality similar to the corresponding functionality of the one or more cores 456, the PCIe2TAP 454, and the interconnect 458 (at least with respect to TDT operations).

[0051] The endpoint components of system 400 may be coupled to each other in various ways (e.g., via one or more PCIe buses). The PCIe network may include one or more paths that are suitable for facilitating streaming and / or other exchange of tracing information in accordance with an embodiment. Memory I / O-based mechanisms (e.g., those supported by PCIe) may be suitable for read and write access to registers for exchanging TBT data, commands, and / or other information. In the illustrative embodiment shown, access to exchange tracing information with modem 450 and / or CNV 460 is performed via processor 430 and function I / F 412. Function I / F 412 may additionally or alternatively include a Thunderbolt 3 interface that complies with, for example, Thunderbolt 3. TM Standard Circuits and / or Other Hardware. In some embodiments, the function I / F 412 includes circuits and / or other hardware that conform to the USB standard or the WiFi standard.

[0052] Certain embodiments adapt various PCIe and / or other external interface mechanisms (e.g., device classes) to support additional TBT functionality. Some embodiments introduce the use of debug device classes to implement debug operations via PCIe—e.g., where the debug device class is used to expose debug capabilities through PCIe endpoints. In embodiments, a system component to be debugged (a "debug slave") may not be identified as a separate device to a debug host agent. Instead, the debug slave may be represented as functionality through which the debug host accesses the PCIe endpoint of the debug slave. The representation may be implemented, for example, using PCIe multifunction device options (e.g., options such as indicated in a header type field of a PCIe header space). Thus, debug functionality may be selectively exposed (or alternatively hidden) based on device settings, thereby avoiding the need to allocate and manage dedicated endpoint configuration information for debug slave components.

[0053] Additionally or alternatively, the PCIe functionality may be adapted to use subclasses and programmatic interfaces in various ways—e.g., to implement one or more independent driver instances in the system 400 that each implement corresponding data manipulation and / or component configuration. In an embodiment, a trace driver running in one of the modem 460 and CNV 460 is thus able to operate as a standalone agent after booting. Alternatively or additionally, such one or more trace driver instances may be established in various ways by a central system driver (e.g., at the host 410) registering various system components with corresponding trace information to be manipulated by the corresponding driver.

[0054] In one illustrative embodiment, the configuration subclass may be exposed by any device of the debug device class. The configuration class may be used to expose an interface to the debug topology of the debug slave device - for example in the form of a hierarchical tree or linked list. Alternatively or additionally, the debug access class may be used to expose functionality such as built-in self-test (BIST), scanning, and software (SW) code debugging. These functionalities may support breakpoint mechanisms, run control, and / or other features.

[0055] In some embodiments, a trace class may be used to configure the output path of a trace source. Depending on the implementation, trace data may be read out through this interface or written by the device itself. Alternatively or additionally, a trace configuration subclass may expose the trace source configuration and, in some embodiments, the configuration required to store one or more traces external to the trace device. Such a trace configuration subclass may be used to communicate, for example, the selection of PULL or PUSH functionality, the base address for DMA writes, etc. For example, the current PCIe standard does not define any such debug device class or trace class.

[0056] Figure 5Features of a system 500 according to another embodiment are shown, the system 500 including an external (e.g., PCIe or Thunderbolt) processor configured to provide TDT access to memory and / or I / O space. TM ) interface. System 500 may include features of, for example, one of systems 200 and 400. In one embodiment, some or all of method 300 is performed in system 500.

[0057] System 500 includes a functional interface 510 (eg, including an external PCIe connector or a Thunderbolt TM The bus access unit 514 includes a bus access unit 514 that is coupled to a bus access unit 514. The bus access unit 514 includes circuitry that provides access to a trace network-on-chip (NoC) 520—e.g., where the trace NoC 520 is dedicated to exchanging trace information and is distinguished, e.g., from a general-purpose NoC of the system 500. The trace NoC 520, in turn, may provide, for example, access to memory 540, I / O space 542, and / or memory space in an application processor 550 of the system 500. Such access may support execution and / or trace control functionality.

[0058] The functionality of the bus access unit 514 may be similar to the speed conversion (glue logic) functionality discussed herein with respect to the PCIe2TAP or other such interface logic. Such glue logic may match the interface speed. For example, the trace NoC 520 may include a relatively slow 32-bit or 64-bit bus, while the PCIe interface provides serial communication—e.g., at a field rate of 8 gigahertz. In such an embodiment, the bus access unit 514 may include buffer circuits and serializer / deserializer circuits to accommodate exchanges between the two interface types. In another embodiment, the system 500 does not include a dedicated trace NoC, and the bus access unit 514 facilitates trace exchanges via the general NoC 530.

[0059] In an embodiment, other TDT exchanges are performed through interfaces other than functional interface 510. By way of illustration and not limitation, system 500 may include another external interface (functionally represented as illustrative JTAG2Bus 512) that is dedicated to communicating debug information (e.g., including debug commands, output, etc.). In addition to (c) JTAG connector hardware, for example, JTAG2Bus 512 may also include circuit logic to facilitate buffering, speed matching, and / or other glue logic functions to interface with bus access unit 514.

[0060] To support high throughput exchange of debug information and high speed access for trace operations, PCIe and / or other mechanisms may be provided at NoC 530 to support memory mapped input / output (MMIO) access to the corresponding resources of AP 550, memory 540, or I / O space 542. Thus, the trace source can be accessed through the trace NoC 520 via high speed PCIe / Thunderbolt TM The multiplexing mechanism for selecting between various trace sources can be implemented in a central module or across multiple components. Figure 5 Used in to indicate the tracing signal path.

[0061] Figure 6 Elements of a system 600 that performs TDT operations according to another embodiment are shown. System 600 may include, for example, features of one of systems 200, 400, and 500. In one embodiment, some or all of method 300 is performed in system 600. System 600 is an example of a system that includes multiple (e.g., nested) layers of interface logic including, for example, (1) a first interface logic and (2) a second interface logic, wherein the first interface logic is coupled between a TAP network and a functional interface, and the second interface logic is coupled between the TAP network and another internal network. A functional interface of system 600 may include PCIe / TBT circuits and / or other hardware. Such a functional interface may access the TAP network via interface logic that provides speed conversion, buffering, and / or other interface functionality, such as the functionality described herein. The TAP network may provide access to any of a variety of components (including, for example, a CPU core, a hardware accelerator, an audio digital signal processor, etc.). In an embodiment, the TAP network may also access a bus access module, which in turn provides access to the NoC and, in some embodiments, provides access to one or more components coupled via the NoC (e.g., memory and I / O space). The interface logic (e.g., PCIe2TAP circuitry or TBT2TAP circuitry) may also provide an arbitration state machine or other such logic to facilitate handshaking / coordination between components.

[0062] In the illustrative embodiment of system 600, one or more functional interfaces (e.g., including PCIe port 612 and / or USB port 614) may be configured to support TDT communications and / or other operations to evaluate components of system 600. In the illustrative embodiment shown, such components may include one or more CPU cores 650, HW accelerators 652, audio DSP 654. Debug operations to evaluate some or all of such components may be performed via one of PCIe port 612 and USB port 614. In other embodiments, a dedicated external debug interface (e.g., illustrative (c) JTAG port 610) may provide connectivity to an external debug agent.

[0063] TDT access to components of system 600 may be facilitated in various ways by TAP network 630 and, in some embodiments, by another internal network (e.g., illustrative NoC 660). The glue logic of system 600 may include a first interface (denoted as PCIe2TAP 620) between PCIe port 612 and TAP network 630. PCIe2TAP 620 may facilitate debugging capabilities of system 600—e.g., where PCIe2TAP 620 operates to generate (c) JTAG sequences based on PCIe commands received from an external debugger agent coupled to PCIe port 612. The glue logic of system 600 may additionally or alternatively include a second interface (denoted as USB2TAP 622) between USB port 614 and TAP network 630. PCIe2TAP 620 and USB2TAP 622 may provide buffering, data rate matching, and / or other interface functionality in various ways as described herein. TAP network 630 and NoC 660 may interface with each other via glue logic, such as that provided by illustrative bus access unit 640 .

[0064] Mechanisms based on memory I / O (e.g., those supported by PCIe) may be suitable for read and write access to registers for exchanging TBT data, commands, and / or other information. For example, PCIe functionality may use PCIe2TAP 620 to access TAP network 630, and in turn access components that might otherwise be debugged using (c) JTAG port 610. TAP network 630 may (e.g., independently of NoC 660) access some or all of one or more CPU cores 650, HW accelerators 652, audio DSP 654, etc. Such access may be based on memory mapped I / O information, which is available, for example, via memory 670 and / or I / O space 672 coupled to NoC 660. For example, TAP network 630 may access register space and I / O space 672 in memory 670 via bus access module 640 and on-chip network 640.

[0065] Figure 7Elements of a system 700 that performs TDT operations according to an embodiment are shown. System 700 may include, for example, features of system 600. In one embodiment, some or all of method 300 is performed in system 700. External ports of system 700 may include some or all of PCIe port 712, USB port 714, and (c) JTAG port 710, which provide functionality corresponding to the corresponding functionality of, for example, PCIe port 612, USB port 614, and (c) JTAG port 610. Components of system 700 to be evaluated by TDT operations may include one or more CPU cores 750, HW accelerators 752, and audio DSP 754 (corresponding to, for example, one or more CPU cores 650, HW accelerators 652, and audio DSP 654, respectively). Such TDT operations may exchange trace, debug, and / or test information in various ways via some or all of the TAP network 730, bus access unit 740, and NoC 760 (e.g., having functionality corresponding to the corresponding functionality of the TAP network 630, bus access unit 640, and NoC 660). Glue logic to facilitate these exchanges may include PCIe2TAP 720 and USB2TAP 722 (e.g., corresponding to PCIe2TAP 620 and USB2TAP 622, respectively). TDT accesses used to evaluate components of system 700 may include or otherwise be based on access to memory-mapped I / O information that enables access to such components or otherwise describes such components. Some or all of such memory-mapped I / O information may be stored, for example, by memory 770 and / or I / O space 772 (having functionality corresponding to the corresponding functionality of, for example, memory 670 and I / O space 672).

[0066] System 700 is an example of an embodiment including a mechanism for enabling a test mode (e.g., for scan test, memory test, etc.) instead of or in addition to other conventional debug functionality. In an embodiment, a serial-to-parallel (S2P) interface of system 700 receives a test stimulus provided via an external PCIe interface. The S2P interface can convert the stimulus into a parallel test protocol, which is then applied to a scan interface or a memory BIST interface (not shown), for example. The response from such a scan interface or memory BIST interface can be converted from parallel to a serial format via a parallel-to-serial (P2S) interface and sent from system 700 via an external PCIe port 712.

[0067] As an illustration and not limitation, the system 700 can use the PCIe port 712 (or a TBT port in another embodiment) to capture a serial test stream and, for example, convert it into parallel data communication—for example, using deserializer logic, such as an illustrative serial-to-parallel circuit S2P 780. The parallelized data can be output from the S2P 780 to a parallel register 782 (for example, including a test mode I / O register and / or a status register) for use in loading a scan chain. The loaded scan chain can then be locked for execution of the test. The test can generate an output of test data, which is captured and serialized—for example, via the serializer logic of the P2S782—and passed to an external tester unit (not shown) via the PCIe port 720, which is coupled to the system 700. This exchange can occur for debugging, testing, verification, etc. The PCIe port 720 (or a TBT interface in another embodiment) can thus be used to facilitate other testing of any of the components of scan chain testing, memory testing, I / O testing, evaluation, and / or various other components of the system 700. In some embodiments, other test mode commands and / or test responses may be exchanged between PCIe interfaces via the TAP network (independent of any such S2P and P2S functionality) to facilitate any of the various other test modes. Access to the PCIe infrastructure may be through Thunderbolt TM or M.2 interface (not shown), i.e., where a plug-in card can be removed to gain access to PCIe.

[0068] Some embodiments provide for loading debug and / or test (debug / test) commands into an agent running, for example, on one component to perform TDT operations that evaluate another component. Referring to the example embodiment of system 200, the TDT logic 242 of AP 240 may run a debug / test agent based on software code provided by an external TDT unit via I / O interface 210 and TAP network 230. The operation of such a debug / test agent may evaluate, for example, modem BBP 260. I / O interface 210 (e.g., PCIe interface) may be used to load test / debug agent code and / or commands to be serviced by the debug / test agent to AP 240. The debug / test agent may additionally or alternatively evaluate, for example, AP 240 and / or modem Tx / Rx 280. Responses from the evaluated component(s) may be sent back to the debug / test agent at AP 240 and may then be correlated with the external TDT unit via I / O interface 210.

[0069] Alternatively or additionally, the debug / test agent (or other TDT agent) may be loaded into any of a variety of other system components capable of or running and executing such firmware and / or software. Referring again to system 200, the debug / test agent may instead be loaded to be run by processor logic (e.g., TDT logic 262) resident in the controller circuitry of modem BBP 260. Commands may be loaded into such a debug / test agent of modem BBP 260 to debug / test, for example, AP 420. I / O interface 210 may be used to load such a debug / test agent of modem BBP 260 with debug / test commands to test modem BBP 260, AP 240 modem Tx / Rx 280, and / or any other appropriately configured component of system 200.

[0070] Fig. 8A , Figure 8B Elements of system 800 that perform various TDT operations are shown in various ways, each according to a corresponding embodiment. System 800 may include features of one of systems 200, 400, 500, 600, and 700, for example. In one embodiment, some or all of method 300 is performed in system 800. Fig. 8A As shown, system 800 may include an application processor AP 810 coupled via link 804 to receive commands from, for example, an external debug / test agent (not shown) coupled to system 800 via interface hardware 802. In one embodiment, interface hardware 802 includes an external (e.g., PCIe or Thunderbolt 3) processor. TM ) interface. Hardware 802 may also include a TAP network and glue logic to interface with external interfaces. In some embodiments, glue logic is additionally or alternatively provided in another component of system 800 (e.g., illustrative AP 810).

[0071] Using AP 810, one or more PCIe links (e.g., illustrative interconnects 812, 814) in system 800 can be accessed to load one or more agents—e.g., each on a corresponding one of any of modem 820, WiFi 830, and / or various other components. Telephone communications can be provided with 3G Tx / Rx 824, which is coupled to modem 820 via link 822. Some or all of such one or more agents can perform corresponding debugging and / or testing in various ways. For example, an agent loaded to run on one component can perform debugging and / or testing to evaluate that same component or some other component of system 800. As an illustration and not limitation, AP 810 can facilitate the exchange 816 of debugging information between an external interface of hardware 802 and a debugging process DB1 run by a processor of modem 820. Additionally or alternatively, AP 810 can facilitate the exchange 818 of debugging information between an external interface of hardware 802 and another debugging process DB2 run by a processor of WiFi 830. In some embodiments, WiFi 830 may instead be any of a variety of wireless mechanisms, such as Bluetooth, Bluetooth-LE, NFC, 3G, 4G-LTE, 5G, etc.

[0072] exist Figure 8B In the illustrative embodiment of the system 800, the external agent may exchange executable code, test / debug commands, and / or other TDT information via wireless communications 850. For example, debug commands may be wirelessly downloaded to WiFi 830 and then sent to modem 820 via AP 810 and interconnects 812, 814. Thus, WiFi 830 and AP 810 may facilitate the exchange 852 of debug information between the external agent and the debug process DB3 executed by modem 820. The use of the PCIe network fabric of system 800 may enable continuous high-speed delivery of debug and / or other DTD information.

[0073] Fig.9A , Fig. 9B The TDT operations are shown to be performed in various ways by the system 900, each according to a corresponding embodiment. The system 900 may include, for example, features of the system 800. In one embodiment, some or all of the method 300 is performed in the system 900.

[0074] like Fig.9AAs shown, system 900 may include platform 902, which includes, for example, features of system 800. External ports (e.g., illustrative M.2 connector 904) may couple platform 902 to one or more external devices of system 900. In one example, embodiment, such external devices include PCIe switch 934, wireless communication circuit WiFi 936, and PCIe card 932. However, in other embodiments, platform 902 may be coupled to fewer, more, and / or different external devices. In addition to platform 902, some or all of such external devices may be evaluated by DTD unit 930.

[0075] Components of the platform 902 may include an AP 910, a modem 920, and a 3G Tx / Rx 924, which, for example, provide functionality corresponding to the respective functionality of the AP 810, the modem 820, and the 3G Tx / Rx 824. The interconnection of such components to each other and to the M.2 connector 904 may be provided using interconnects 912, 942, and links 922 (e.g., having functionality corresponding to the respective functionality of the interconnects 812, 842, and links 822). TDT operations performed using the DTD unit 930 may exchange trace, debug, and / or test information in various ways via a networked arrangement of the platform 902, PCIe switches 934, Wifi 936, and PCIe cards 940. Glue logic (not shown) may be included in various ways in some or all of such components of the network—e.g., where such glue logic is to interface a common functional interface (e.g., the M.2 connector 904) with a TAP network.

[0076] like Fig.9A As shown in the illustrated embodiment, the PCIe switch 934 can be used to provide communication with a discrete PCIe card 932 or a discrete WiFi 936 from the M.2 connector 904. The TDT unit 930 can participate in wired communication with the PCIe card 932—e.g., supporting one or more exchanges, such as the illustrated illustrative exchanges 940, 944, 942. For example, an exchange 940 between the PCIe card 932 and the PCIe switch 934 can facilitate one or both of the downstream exchanges 942, 944. The exchange 942 can communicate corresponding TDT information between the M.2 connector 904 and one or both of the AP 910 and the modem 920 in various ways. Based on the exchange 942, one or more test / debug agents can each run in various ways on the corresponding components of the platform 902. By way of illustration and not limitation, the AP 910 can run the debug process DB4, and / or the modem 920 can run the debug process DB5. Alternatively or additionally, exchange 944 may result from or be based on operations performed by debug process DB6 running on PCIe card 932 .

[0077] In by Fig. 9BIn the illustrated embodiment, the TDT unit 930 may participate in wireless communications with Wi-Fi 936, for example, in addition to or in lieu of wired communications with the PCIe card 932. Such wireless communications may facilitate the exchange of TDT information, such as the illustrative exchanges 990, 992, 994 shown. The exchange 990 between the WiFi 936 and the PCIe switch 934 may facilitate one or both of the downstream exchanges 992, 994. Based on the exchange 992, one or more test / debugging agents may each operate in various ways on the corresponding components of the platform 902. As an illustration and not limitation, the AP 910 may run the debug process DB7, and / or the modem 920 may run the debug process DB8. Alternatively or additionally, the exchange 994 may result from or be based on operations performed by the debug process DB9 running on the PCIe card 932.

[0078] Fig.10 Elements of a system 1000 that performs TDT operations according to an embodiment are shown. System 1000 may include, for example, features of one of systems 200, 400. In one embodiment, some or all of method 300 are performed in system 1000. According to an embodiment, system 1000 includes a plurality of devices arranged in a daisy chain configuration for TDT operations and / or communications. The daisy chain devices may be coupled to each other via corresponding functional interfaces (e.g., including PCIe interfaces and / or TBT interfaces). A TDT host (e.g., one of TDT units 1002, 1004) included in or coupled to system 1000 may be located at the end of a daisy chain connection between consecutive devices. Each of such devices may include corresponding glue logic (e.g., including PCIe2TAP circuits, TBT2TAP circuits, bus access mechanisms, etc.) to assist in various ways TDT operations / communications between corresponding test access points of functional interface mechanisms and internal device components.

[0079] In the illustrative embodiment of the system 1000, the daisy chain device includes a host platform 1010, which has some or all of the features of the host 410, for example. The host platform 1010 and other devices 1020, 1030, 1040 can be coupled to each other in series via respective physical layers PHY 1016, 1022, 1032, 1042 and respective endpoints EP 1014, 1024, 1034, 1044. In one embodiment, the host interface 1012 of the host platform 1010 enables the connection of the TDT unit 1002 at one end of the daisy chain configuration. The controllers 1026, 1036, 1054 of the devices 1020, 1030, 1040 provide processor functionality that each performs respective TDT operations in various ways. For some or all of the devices 1020, 1030, 1040, corresponding glue logic (e.g., one of the various PCIe2TAP interface circuits P2T 1028, P2T 1038, P2T 1050 shown) may interface the device's local PCIe mechanism with the device's TAP network structure. One or more devices may include additional or alternative architectures to facilitate TDT operations. For example, the device 1040 may include a trace backbone TBB 1062 to support trace functionality, which is adapted from conventional techniques, for example). The glue logic Tr2P 1060 of the device 1040 may interface the TBB 1060 with the PCIe mechanism of the device 1040. In an embodiment, such a PCIe mechanism may include or be coupled to a switch 1046, through which the P2T 1050, the controller 1054, and the EP 1044 communicate with each other and, for example, with the CPU 1052.

[0080] In some embodiments, a device's PCIe / TBT interface may be coupled to an independent power rail of that device, such as a debug power rail. This may enable relatively early and / or low power state debug operations. PCIe / Thunderbolt TM The interface is typically turned on during system wakeup, after other components are powered up. This is because users typically do not need a high-speed interface when the modem (or other component) is initially awake. For example, a user listening to music would not want an unused Thunderbolt TM However, placing such functional (e.g., in-band) interfaces on a separate power rail can enable early power-up of the interface at least for TBT functionality—e.g., to debug audio logic, a power management controller (PMC), and / or any of a variety of other relatively low-power components.

[0081] Fig.11A diagrammatic representation of a machine in the exemplary form of a computer system 1100 is shown, in which an instruction set for causing the machine to perform any one or more of the methods described herein can be run. In an alternative embodiment, the machine can be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine operates in the capacity of a server or client machine in a client-server network environment, or operates as a peer machine in a peer-to-peer (or distributed) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a World Wide Web device, a server, a network router, a switch or a bridge, or any machine capable of running an instruction set (sequential or otherwise) specifying the actions to be taken by that machine. In addition, although only a single machine is shown, the term "machine" should also be understood to include any collection of machines (e.g., computers) that run one (or more) instruction sets to perform any one or more of the methods described herein, either individually or in combination.

[0082] The exemplary computer system 1100 includes a processor 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or memory bus DRAM (RDRAM)), etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM)), etc.), and an auxiliary memory 1118 (e.g., a data storage device), which communicate with each other via a bus 1130.

[0083] The processor 1102 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processor 1102 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processor 1102 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processor 1102 is configured to run the processing logic 1126 for performing the operations described herein.

[0084] The computer system 1100 may also include a network interface device 1108. The computer system 1100 may also include a video display unit 1110 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 1112 (e.g., a keyboard), a cursor control device 1114 (e.g., a mouse), and a signal generating device 1116 (e.g., a speaker).

[0085] The secondary memory 1118 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 1132 on which is stored one or more sets of instructions (e.g., software 1122) that implement any one or more of the methods or functions described herein. The software 1122 may also reside completely or at least partially in the main memory 1104 and / or in the processor 1102 during its execution by the computer system 1100, the main memory 1104 and the processor 1102 also constituting machine-readable storage media. The software 1122 may also be transmitted or received over the network 1120 via the network interface device 1108.

[0086] Although the machine-accessible storage medium 1132 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated cache memory and servers) that store one or more sets of instructions. The term "machine-readable storage medium" will also be considered to include any medium that is capable of storing or encoding a set of instructions to be executed by a machine and causes the machine to perform any embodiment of one or more embodiments. The term "machine-readable storage medium" will accordingly be understood to include, but is not limited to, solid-state memories and optical and magnetic media.

[0087] In one implementation, the apparatus includes an input / output (I / O) interface to couple the apparatus to an external agent and exchange information with the external agent, wherein the I / O interface is compatible with a peripheral interconnect standard that supports the transfer of operational data in addition to any test information, debug information, or trace information. The apparatus also includes a first network; a plurality of circuit components coupled to each other via the first network, wherein the first network includes a network of test access points coupled between the plurality of circuit components and the I / O interface; and glue logic to exchange information between the network of test access points and the I / O interface, wherein the plurality of circuit components include circuitry that performs a test, debug, or trace (TDT) operation to evaluate one of the plurality of circuit components, wherein the TDT operation generates or responds to the information.

[0088] In an embodiment, the glue logic for exchanging information between the network of the test access point and the I / O interface includes glue logic for adjusting the transfer of information between a first rate of the I / O interface and a second rate of the network of the test access point. In another embodiment, the glue logic includes one or more buffers, wherein the glue logic for adjusting the transfer of information between the first rate and the second rate includes glue logic for buffering and debuffering data at different corresponding rates. In another embodiment, the device also includes a bus access unit; and a second network coupled to the first network via the bus access unit, wherein the bus access unit includes circuitry for adjusting between different corresponding communication rates of the first network and the second network, wherein the glue logic for exchanging information between the network of the test access point and the I / O interface includes glue logic for exchanging memory mapped I / O information accessed via the second network. In another embodiment, the peripheral interconnect standard is the Peripheral Component Interconnect Express (PCIe) standard or Thunderbolt TM In another embodiment, the information includes software code provided by an external agent to a plurality of circuit components, wherein the plurality of circuit components that perform the TDT operation include a first circuit component that executes the software code. In another embodiment, the TDT operation is to evaluate a second circuit component of the plurality of circuit components, the second circuit component being different from the first circuit component.

[0089] In another implementation, a method includes coupling a device to an external agent via an input / output (I / O) interface of the device, the device including a plurality of circuit components and a first network coupling the plurality of circuit components to each other, the first network including a network of test access points coupled between the plurality of circuit components and the I / O interface, wherein the I / O interface is compatible with a peripheral interconnect standard that supports the transfer of operational data in addition to any test information, debug information, or trace information; exchanging information with the external agent via the I / O interface; exchanging information between the network of test access points and the I / O interface via glue logic of the device; and performing a test, debug, or trace (TDT) operation to evaluate one of the plurality of circuit components, wherein the TDT operation generates information or is responsive to information.

[0090] In an embodiment, exchanging information between the network of the test access point and the I / O interface includes glue logic adjusting the transfer of information between a first rate of the I / O interface and a second rate of the network of the test access point. In another embodiment, the glue logic includes one or more buffers, wherein the glue logic adjusting the transfer of information between the first rate and the second rate includes glue logic to buffer and debuffer data at different corresponding rates. In another embodiment, exchanging information between the network of the test access point and the I / O interface via the glue logic includes the glue logic exchanging memory mapped I / O information accessed via the second network of the device, and adjusting the transfer of memory mapped I / O information between different corresponding communication rates of the first network and the second network. In another embodiment, the peripheral interconnect standard is the Peripheral Component Interconnect Express (PCIe) standard or Thunderbolt. TM In another embodiment, the information includes software code provided by an external agent to the plurality of circuit components, wherein performing the TDT operation includes a first circuit component of the plurality of circuit components executing the software code. In another embodiment, the TDT operation evaluates a second circuit component of the plurality of circuit components, the second circuit component being different from the first circuit component.

[0091] In another implementation, a system includes a system on a chip (SoC) including an input / output (I / O) interface to couple the SoC to an external agent and exchange information with the external agent, wherein the I / O interface is compatible with a peripheral interconnect standard that supports the transfer of operational data in addition to any test information, debug information, or trace information. The SoC also includes a first network; a plurality of circuit components coupled to each other via the first network, wherein the first network includes a network of test access points coupled between the plurality of circuit components and the I / O interface; and glue logic that exchanges information between the network of test access points and the I / O interface, wherein the plurality of circuit components include circuits that perform a test, debug, or trace (TDT) operation to evaluate one of the plurality of circuit components, wherein the TDT operation generates or responds to the information. The system also includes a display coupled to the SoC, the display generating an image based on the operational data exchanged via the I / O interface.

[0092] In an embodiment, the glue logic for exchanging information between the network of the test access point and the I / O interface includes glue logic for adjusting the transfer of information between a first rate of the I / O interface and a second rate of the network of the test access point. In another embodiment, the glue logic includes one or more buffers, wherein the glue logic for adjusting the transfer of information between the first rate and the second rate includes glue logic for buffering and debuffering data at different corresponding rates. In another embodiment, the SoC also includes a bus access unit; and a second network coupled to the first network via the bus access unit, wherein the bus access unit includes a circuit for adjusting between different corresponding communication rates of the first network and the second network, wherein the glue logic for exchanging information between the network of the test access point and the I / O interface includes glue logic for exchanging memory mapped I / O information accessed via the second network. In another embodiment, the peripheral interconnect standard is the Peripheral Component Interconnect Express (PCIe) standard or Thunderbolt TM In another embodiment, the information includes software code provided by an external agent to a plurality of circuit components, wherein the plurality of circuit components that perform the TDT operation include a first circuit component that executes the software code. In another embodiment, the TDT operation is to evaluate a second circuit component of the plurality of circuit components, the second circuit component being different from the first circuit component.

[0093] This article describes techniques and architectures for supporting testing, debugging, and / or tracing functionality. For purposes of explanation, numerous specific details are set forth in the above description in order to provide a thorough understanding of certain embodiments. However, it will be apparent to those skilled in the art that certain embodiments can be practiced without these specific details. In other examples, structures and devices are shown in block diagram form to avoid obscuring the description.

[0094] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily refer to the same embodiment.

[0095] Some parts of the detailed description herein are presented in terms of algorithms and symbolic representations of the operations on data bits in a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of computing use to most effectively communicate the substance of their work to other skilled in the art. An algorithm is here and generally expected to be a self-consistent sequence of steps that produce a desired result. Steps are those steps that require physical manipulation of physical quantities. These quantities are typically but not necessarily in the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated. Mainly for reasons of general use, these signals are referred to as bits, values, elements, symbols, characters, items, numbers, etc., which have proven to be convenient sometimes.

[0096] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated, it will be apparent from the discussion herein that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" etc. refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the computer system's registers and memories and transforms it into other data similarly represented as physical quantities in the computer system's memories or registers or other such information storage, transmission or display devices.

[0097] Certain embodiments also relate to apparatus for performing the operations described herein. Such apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to: any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM), random access memory (RAM), such as dynamic RAM (DRAM), EPROM, EEPROM; magnetic or optical cards; or any type of medium suitable for storing electronic instructions and coupled to a computer system bus.

[0098] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems can be used together with the programs taught herein, or it may prove convenient to build more specialized equipment to perform the required method steps. The required structure of a variety of these systems will be apparent from the description herein. In addition, some embodiments are not described with reference to any specific programming language. It will be appreciated that a variety of programming languages ​​can be used to implement the teachings of such embodiments as described herein.

[0099] In addition to what is described herein, various modifications may be made to the disclosed embodiments and implementations thereof without departing from their scope. Therefore, the descriptions and examples herein should be interpreted as illustrative rather than restrictive. The scope of the present invention should be limited only with reference to the following claims.

Claims

1. A system for server computing, comprising: Integrated circuits, including: a functional interface compatible with a Peripheral Component Interconnect Express (PCIe) based protocol, wherein the functional interface is used to receive information associated with testing, debugging, or tracing TDT operations; an assembly comprising circuitry for performing said TDT operation based at least in part on said information associated with said TDT operation; a first interface logic coupled between the component and the functional interface, wherein the information associated with the TDT operation is received from the functional interface to the component via the first interface logic; and A second interface logic is coupled to the first interface logic and to a memory or an I / O space, wherein data associated with the TDT operation is accessed from the memory or the I / O space via the second interface logic based on memory-mapped input / output MMIO information. 2 . The system of claim 1 , wherein the information associated with the TDT operation is received from an external system.

3. The system according to claim 1, further comprising: A network coupled to the component and the first interface logic, wherein the network is used to communicate the information associated with the TDT operation between the first interface logic and the component. 4 . The system of claim 1 , wherein the component generates output data associated with the TDT operation, and wherein the output data associated with the TDT operation is passed from the component to the functional interface via the first interface logic.

5. The system of claim 1, wherein the functional interface is configured to provide a universal switch based on PCIe.

6. The system of claim 1, further comprising a server computing system.

7. The system of claim 6, wherein the server computing system comprises a blade server or a rack-mount server.

8. The system of claim 1, wherein the integrated circuit is on a system on a chip (SoC).

9. The system of claim 1, wherein the integrated circuit is on a field programmable gate array (FPGA).

10. The system of claim 1, further comprising: A second integrated circuit comprising: a second functional interface compatible with a Peripheral Component Interconnect Express (PCIe) based protocol, wherein the second functional interface is used to couple to an external system, and wherein information associated with a second test, debug, or trace (TDT) operation is received from the external system via the second functional interface; and a second component comprising circuitry for performing the second TDT operation based at least in part on the information associated with the second TDT operation; and a third interface logic coupled between the second component and the second functional interface, wherein the information associated with the second TDT operation is exchanged from the second functional interface to the component via the third interface logic; and The second functional interface is used to provide PCIe-based exchange with the functional interface.

11. The system according to claim 1, further comprising a central processing unit (CPU), wherein the CPU is external to the integrated circuit, and wherein the CPU is configured to be coupled to the integrated circuit.

12. A system for server computing, comprising: Integrated circuits, including: a functional interface compatible with a Peripheral Component Interconnect Express (PCIe) based protocol, wherein the functional interface is used to receive information associated with testing, debugging, or tracing TDT operations from an external system; a network for communicating the information associated with the TDT operation to a component, wherein the component is configured to perform the TDT operation based at least in part on the information associated with the TDT operation; a first interface logic coupled between the network and the functional interface, wherein the information associated with the TDT operation is exchanged from the functional interface to the network via the first interface logic; and A second interface logic is coupled to the first interface logic and to a memory or I / O space, wherein data associated with the TDT operation is accessed from the memory or I / O space via the second interface logic based on memory-mapped input / output MMIO information.

13. The system of claim 12, further comprising a server computing system.

14. The system of claim 12, wherein the integrated circuit is on a field programmable gate array (FPGA).

15. A system for server computing, comprising: Integrated circuits, including: a functional interface compatible with a Peripheral Component Interconnect Express (PCIe) based protocol, wherein the functional interface is used to couple to an external system, and wherein information associated with testing, debugging, or tracing TDT operations is passed to or from the external system through the functional interface; a network for communicating said information associated with said TDT operation to or from a component, wherein said component is configured to perform said TDT operation; a first interface logic coupled between the network and the functional interface, wherein the information associated with the TDT operation is exchanged between the functional interface and the network via the first interface logic; and a second interface logic coupled to the first interface logic and to a memory or an I / O space, wherein data associated with the TDT operation is accessed from the memory or the I / O space via the second interface logic based on memory-mapped input / output MMIO information; and A central processing unit (CPU), wherein the CPU is external to the integrated circuit, and wherein the CPU is adapted to be coupled to the integrated circuit.

16. The system of claim 15, wherein the functional interface is configured to provide a universal switch based on PCIe.

17. The system of claim 15, further comprising a blade server or a rack-mount server.

18. The system of claim 15, wherein the integrated circuit is on a field programmable gate array (FPGA).

19. The system of claim 15, further comprising: A second integrated circuit comprising: a second functional interface compatible with a Peripheral Component Interconnect Express (PCIe) based protocol, wherein the second functional interface is used to couple to the external system, and wherein information associated with a second test, debug or trace (TDT) operation is transferred to or from the external system via the second functional interface; and a second network for communicating the information associated with the second TDT operation to or from a second component, wherein the second component is configured to perform the second TDT operation; and and a third interface logic coupled between the second network and the second functional interface, wherein the information associated with the second TDT operation is exchanged between the second functional interface and the second network via the third interface logic, and wherein the second functional interface is used to provide PCIe-based exchanges with the functional interface.

20. The system of claim 15, wherein the first interface logic includes circuitry to accommodate data communications from the functional interface at a rate of 100 MHz.

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