Reference voltage generation for voltage sensing in resistive memory

Abstract

This disclosure relates to reference voltage generation for voltage sensing in resistive memory. A sensing amplifier circuit includes a reference path, a cell path, and a comparator circuit. The reference path includes a first current load device and a reference comparison node, wherein during read operations, the reference path is coupled to a cell reference circuit, wherein the first current load device includes a control input for controlling the current of the reference path. The cell path includes a second current load device and a cell comparison node, wherein during read operations, the cell path is coupled to a memory cell, wherein the second current load device includes a control input for controlling the current of the cell path. Based on a comparison of the voltage of the reference comparison node with the voltage of the cell comparison node, the comparator circuit indicates a data value stored in the memory cell. Different signals are provided to the control inputs of the first current load device and the second current load device.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to generating a reference voltage for resistive memory. Background Technology

[0002] Resistive memories, such as magnetoresistive random access memory (MRAM), are commonly used as non-volatile memories (NVM). The magnetic elements of an MRAM cell are magnetic tunnel junctions (MTJs). For example, when the magnetic moments of the interleaved magnetic layers of the MTJ are aligned, a low-resistance state (LRS) corresponding to "0" is stored; conversely, when the magnetic moments are misaligned, a high-resistance state (HRS) corresponding to "1" is stored. Data stored in such memories is read by sensing the resistance difference in the resistive elements of the memory cell between the LRS and HRS states. However, the resistance difference between the high-resistance and low-resistance states can be extremely small. This is further amplified at high temperatures, where the resistance difference becomes even smaller. Because the resistance increment that must be sensed is small, the generation of a suitable reference voltage is crucial for successful sensing. Various error sources need to be considered during sensing. Therefore, there is a need to improve sensing in resistive memories so that it is even unaffected by temperature variations. Summary of the Invention

[0003] According to one embodiment, a circuit includes:

[0004] The sensing amplifier circuit includes:

[0005] A reference path, comprising a first current load device and a reference comparator node, is coupled to a cell reference circuit during voltage readout by the sensing amplifier circuit, wherein the first current load device includes a control input for controlling the current of the reference path;

[0006] A cell path, comprising a second current load device and a cell comparator node, wherein the cell path is coupled to a memory cell of a memory cell array during voltage readout by the sensing amplifier circuit, wherein the second current load device includes a control input for controlling the current of the cell path;

[0007] A comparator circuit includes a first input coupled to the reference comparator node, a second input coupled to the cell comparator node, and an output that provides a data output signal based on a comparison of the voltage of the reference comparator node and the voltage of the cell comparator node, and the comparator circuit indicates the data value stored in the memory cell that is read during a memory read operation.

[0008] A first circuit, the first circuit including an output for providing a first signal to the control input of the first current load device;

[0009] The second circuit includes an output for providing a second signal to the control input of the second current load device, wherein the first signal and the second signal are different signals.

[0010] Optionally, the second signal is a voltage that generates a relatively constant current through the cell path, regardless of the resistance value of the memory cell being read, wherein the memory cell is a resistive memory cell.

[0011] Optionally, the second circuit includes a voltage-to-current converter, which includes an input generated by a node receiving a current with a relatively constant temperature.

[0012] Optionally, the voltage of the second signal depends on a current with a relatively constant temperature, wherein the voltage of the first signal does not depend on the current with the relatively constant temperature.

[0013] Optionally, the second circuit includes a current mirror to mirror the current with a relatively constant temperature passing through the cell path.

[0014] Optionally, the first circuit includes a voltage-to-current converter, wherein the voltage-to-current converter includes a first resistor of a first resistive material, and wherein the unit reference circuit includes a second resistor of the first resistive material.

[0015] Optionally, the voltage across the second resistor is relatively insensitive to the temperature coefficient of the second resistor.

[0016] Optionally, the first circuit includes a voltage-to-current converter, the voltage-to-current converter including an input that receives a voltage at a relatively constant temperature, wherein the first signal is based on the voltage at the relatively constant temperature, and wherein the second signal is not based on the voltage at the relatively constant temperature.

[0017] Optionally, the first signal is a voltage that generates a relatively constant voltage across the cell reference circuit during the readout operation of the sensing amplifier circuit, taking into account temperature and process variations, wherein the cell reference circuit is a resistive reference circuit.

[0018] Optionally, the circuit further includes:

[0019] A second sensing amplifier circuit, the second sensing amplifier circuit comprising:

[0020] A second reference path, comprising a third current load device and a second reference comparison node, is coupled to a second unit reference circuit during voltage readout by the second sensing amplifier circuit, wherein the third current load device includes a control input for controlling the current of the second reference path.

[0021] The second unit path includes a fourth current load device and a second unit comparison node, which is coupled to the memory cells of the memory cell array during the voltage readout of the second sensing amplifier circuit, wherein the fourth current load device includes a control input for controlling the current of the second unit path.

[0022] The second comparator circuit includes a first input coupled to the second reference comparator node, a second input coupled to the second unit comparator node, and an output that provides a second data output signal based on a comparison of the voltage of the second reference comparator node with the voltage of the second unit comparator node, and the second comparator circuit indicates the data value stored in the memory cell that is read during a memory read operation performed by the second sense amplifier circuit.

[0023] The first signal is provided to the control input of the third current load device, and the second signal is provided to the control input of the fourth current load device.

[0024] Optionally, the memory cell is a resistive memory cell.

[0025] Optionally, the memory unit is an MRAM memory unit.

[0026] Optionally, the unit reference circuit is a resistor element.

[0027] According to another embodiment, a method for performing a memory read operation using a sensing amplifier circuit includes:

[0028] During a memory read operation of a memory cell in a memory cell array, a first signal is generated to control the current of a reference path of a sense amplifier circuit, the reference path including a reference comparator node;

[0029] During the memory read operation, a second signal is generated that controls the current of a cell path in the sensing amplifier circuit, the cell path including a cell comparison node, wherein the first signal and the second signal are different signals;

[0030] The voltage of the reference comparator node when the cell reference circuit is coupled to the reference path is compared with the voltage of the cell comparator node when the memory cell of the memory array is coupled to the cell path, in order to generate an indication of the value stored in the memory cell during the memory read operation.

[0031] Optionally, the generation of the first signal is based on a voltage with a relatively constant temperature, wherein the generation of the second signal is not based on the voltage with the relatively constant temperature.

[0032] Optionally, the generation of the second signal is based on a current with a relatively constant temperature, wherein the generation of the first signal is not based on the current with the relatively constant temperature.

[0033] Optionally, the method further includes:

[0034] During a memory read operation of the second memory cell in the memory cell array, the first signal controls the current of the second reference path of the second sensing amplifier circuit.

[0035] The second reference path includes a second reference comparison node;

[0036] During the memory read operation of the second memory cell, the current of the second cell path of the second sensing amplifier circuit is controlled, the second cell path including the second cell comparison node;

[0037] The voltage of the second reference comparison node when the second cell reference circuit is coupled to the second reference path is compared with the voltage of the second cell comparison node when the second memory cell of the memory array is coupled to the second cell path to generate an indication of the value stored in the second memory cell during the memory read operation.

[0038] According to another embodiment, a circuit includes:

[0039] Multiple sensing amplifier circuits, each of the multiple sensing amplifier circuits comprising:

[0040] A reference path, comprising a first current load device and a reference comparator node, is coupled to a cell reference circuit during voltage readout by the sensing amplifier circuit, wherein the first current load device includes a control input for controlling the current of the reference path;

[0041] A cell path, comprising a second current load device and a cell comparator node, wherein the cell path is coupled to a memory cell of a memory cell array during voltage readout by the sensing amplifier circuit, wherein the second current load device includes a control input for controlling the current of the cell path;

[0042] A comparator circuit includes a first input coupled to the reference comparator node, a second input coupled to the cell comparator node, and an output that provides a data output signal based on a comparison of the voltage of the reference comparator node and the voltage of the cell comparator node, and the comparator circuit indicates the data value stored in the memory cell that is read during a memory read operation.

[0043] A first circuit, the first circuit including an output for providing a first signal to the control input of the first current load device of each of the first plurality of sense amplifier circuits;

[0044] The second circuit includes an output for providing a second signal to the control input of the second current load device of each of the plurality of sense amplifier circuits, wherein the first signal and the second signal are different signals.

[0045] Optionally, the voltage of the second signal depends on a current with a relatively constant temperature, wherein the voltage of the first signal does not depend on the current with the relatively constant temperature.

[0046] Optionally, the unit reference circuit includes a resistor, wherein the voltage across the resistor is relatively insensitive to the temperature coefficient of the resistor. Attached Figure Description

[0047] The invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0048] Figure 1 An MRAM according to an embodiment of the present invention is shown in the form of partial schematic diagrams and partial block diagrams.

[0049] Figure 2 It is shown in the form of partial block diagrams and partial schematic diagrams. Figure 1 This is a part of the MRAM according to an embodiment of the present invention.

[0050] Figure 3 It is shown in the form of partial block diagrams and partial schematic diagrams. Figure 1 This is a part of the MRAM according to an embodiment of the present invention. Detailed Implementation

[0051] Because the resistance increment between two resistive states in resistive memory such as MRAM becomes increasingly smaller, bias generation circuitry is used to improve sense tolerance. In MRAM, a reference polysilicon resistor with resistance between LRS and HRS is typically used to generate a voltage reference for comparison with data in the memory element (e.g., MTJ) of the memory cell. However, unlike the process variations and temperature coefficients of the memory element (e.g., MTJ) of the memory cell, this polysilicon exhibits significant process variations and temperature coefficients. Therefore, a sensing scheme is used in MRAM that reduces or eliminates the influence of the polysilicon resistor. On one hand, to sense an MRAM bit cell, regardless of the resistance state of the MTJ, a first bias voltage is generated to produce a constant current through the MTJ of the sensed bit cell; and a second bias voltage is generated to produce a constant voltage drop across the corresponding reference polysilicon resistor, which compensates for temperature and process variations of the reference polysilicon resistor. In this way, an improved reference voltage can be generated based on the reference polysilicon resistor for the sense amplifier to compare with the sensed voltage of the MTJ. This allows for improved sensing schemes even throughout the entire process and across temperature variations.

[0052] Figure 1 An MRAM 100 according to an embodiment of the present invention is shown in partial schematic diagram and partial block diagram. The MRAM 100 includes an MRAM array 102, a row decoder 104, a column decoder 106, a control circuit system 110, a sense amplifier circuit 108, a constant current bias voltage generator 112, and a constant voltage bias voltage generator 114. The MRAM array 102 includes M rows, each with a corresponding word line WL1 to WLM, and N×K columns, each with a corresponding bit line (BL). (Note that WLj refers only to the rows to be used in the MRAM array 102.) Figure 2 The selected word line is used in a more detailed view. The bit lines are divided into N groups of K bit lines, resulting in BL. 1,1 To BL 1,K To BL N,1 To BL N,KEach BL is followed by two indices; the first index indicates a group, and the second index indicates one of the K bit lines within the group. Bit cells of the MRAM array 102 are located at each intersection of the word lines and bit lines. A row decoder 104 is coupled to the word lines, and a column decoder 106 is coupled between the bit lines and the sense amplifier circuit 108. A control circuit system 110 receives the access address (ADDR) and the corresponding control signal (CNKL) and is coupled to the row decoder 104 and the column decoder 106. The sense amplifier circuit 108 is coupled to the N data lines DL1 to DLN of the column decoder 106 and includes N sense amplifiers (SAs) that output N data outputs DO1 to DON. A constant current bias voltage generator 112 provides a first global bias voltage VCI to the sense amplifier circuit 108. A constant voltage bias voltage generator 114 provides a second global bias voltage VCV to the sense amplifier circuit 108. It should be noted that... Figure 1 The MRAM 100 in this document is a simplified MRAM having elements necessary for describing embodiments of the invention, and therefore may include additional elements and aspects not shown and not related to the embodiments described herein. For example, the MRAM array 102 also includes source lines for each column (corresponding to each bit line), which may also be coupled to the column decoder 106. The source lines are coupled to the bit cells of the MRAM array 102 like bit lines.

[0053] In operation, in response to an access address used for a read or write operation, row decoder 104 enables a word line based on a first portion of the access address, and column decoder 106 selects a bit line from each of the N sets of bit lines based on a second portion of the access address to couple to the corresponding data lines DL1 to DLN. In this way, specific row bit cells of array 102 located at the intersection of the selected word line and the selected bit line are accessed for read / write operations. For a read operation, sense amplifier circuitry 108 senses the data lines to generate corresponding output data DO1 to DON. For a write operation, write circuitry (not shown) provides write data to DL1 to DLN for storage in the selected bit cell. Control circuitry 110 resolves the access address and provides the appropriate first portion to row decoder 104 and column decoder 106, and provides timing information and any other control signals as needed and in a manner known in the art to perform read and write operations on array 102.

[0054] The sense amplifier circuit 108 for sensing the selected bit line for a read operation includes N SAs. Each SA has a first input and a corresponding current load device coupled to a corresponding DL in DL1 to DLN, and a second input and a corresponding current load device coupled to a first terminal of a corresponding reference polysilicon resistor R2 in R21 to R2N. In the illustrated embodiment, each current load device is implemented as a p-type metal-oxide-semiconductor (PMOS) transistor having a first power supply electrode coupled to a first voltage supply terminal (e.g., VDD), a control electrode coupled to receive a global bias voltage (e.g., VCI or VCV), and a second power supply electrode coupled to the first or second input of the corresponding SA. In one embodiment, each SA is implemented as a comparator, and the first input of each SA corresponds to the inverting input of the comparator, and the second input corresponds to the non-inverting input of the comparator. However, alternatively, the inverting and non-inverting inputs can be interchanged.

[0055] Referring to SA1 214 in the sense amplifier circuit 108, DL (i.e., DL1) is coupled to the inverting input of SA1 214. The first power supply electrode (also referred to as a current load device or current source) of PMOS transistor 212 is coupled to VDD, the control electrode of PMOS transistor 212 is coupled to receive VCI, and the second power supply electrode of PMOS transistor 212 is also coupled to the inverting input of SA1 214. Referring to the first terminal of polysilicon resistor R21 222, it is coupled to the non-inverting input of SA1 214, and the second terminal of R21 222 is coupled to the second power supply voltage terminal (e.g., VSS). The first power supply electrode (also referred to as a current load device or current source) of PMOS transistor 210 is coupled to VDD, the control electrode of PMOS transistor 210 is coupled to receive VCV, and the second power supply electrode of PMOS transistor 210 is also coupled to the non-inverting input of SA1 214. SA1 outputs DO1 based on the input of SA1. It should be noted that similar connections apply to PMOS transistors 118 and 122, the reference polysilicon resistor R2N, and SAN, all of which correspond to DLN and DON. Similar components and connections will apply to each SA in the sense amplifier circuit 108.

[0056] It should be noted that, if referenced Figure 2 In more detail, the input coupled to the corresponding R2 of the sense amplifier can be referred to as the reference path of the sense amplifier, and the input coupled to the corresponding DL can be referred to as the cell path of the sense amplifier. Since VCI and VCV are each supplied to multiple current sources for use by each of SA1 to SAN, rather than for use by only one SA, VCI and VCV are considered as global bias voltages.

[0057] Figure 2Further details of bias generators 112 and 114, a sense amplifier circuit 108 corresponding to a portion of SA1 214, and an example bit cell 228 including a transfer transistor 226 and a memory element (e.g., MTJ) selected for sensing components coupled to the MRAM array 102, are shown in partial block diagram and partial schematic diagram. Bias voltage generator 114 includes a bandgap voltage generator 202 providing a bandgap voltage reference VBGREF, an amplifier 204, a PMOS transistor 206, and a polysilicon resistor R1 208. The inverting input of amplifier 204 is coupled to receive VBGREF, and the output of amplifier 204 provides VCV and is coupled to the control electrode of transistor 206. A first supply electrode of transistor 206 is coupled to VDD, and a second supply electrode of transistor 206 is coupled to circuit node 209. The non-inverting input of amplifier 204 is coupled to node 209. The first end of R1 208 is coupled to node 209, and the second end of R1 208 is coupled to VSS.

[0058] The bias voltage generator 112 includes a current source 232 coupled between VDD and circuit node 235 to generate a temperature-proportional current (IPTAT); a current source 234 coupled between VDD and node 235 to generate a temperature-complementary current (ICTAT); a polysilicon resistor R3 236; an amplifier 238; a PMOS transistor 240; and a polysilicon resistor R4 242. A first terminal of R3 236 is coupled to node 235, and a second terminal of R3 236 is coupled to VSS. The inverting input of amplifier 238 is coupled to node 235, and the non-inverting input of amplifier 238 is coupled to circuit node 241. The output of amplifier 238 provides VCI and is coupled to the control electrode of transistor 240. A first supply electrode of transistor 240 is coupled to VDD, and a second supply electrode of transistor 240 is coupled to node 241. A first terminal of R4 242 is coupled to node 241, and a second terminal of R4 242 is coupled to VSS.

[0059] The sense amplifier circuit 108 includes transistors 210 and 212, and resistors R21 and R222, and resistor SA1214. The sense amplifier circuit 108 includes a reference path 211 and a cell path 213. Reference path 211 includes a current load device 210, switches 216 and 220, an NMOS transistor 218, and resistor R21 and R222. In one embodiment, the resistance of R21 and R222 is set to approximately half the resistance between the HRS and LRS of the MTJ in the MRAM array 102. (It should be noted that each resistor R2, such as resistor R21 and R222, can be implemented as a variable resistor, wherein the resistance of each R2 in the sense amplifier circuit 108 can be fine-tuned to accommodate local variations, as known in the art.) The second power supply electrode of transistor 210 is coupled to a reference comparator node 215 at the non-inverting input of SA1 and R214. A closed switch 216 is coupled between node 215 and the first power supply electrode of transistor 218. Closed switch 220 is coupled between the second power supply electrode of transistor 218 and circuit node 221. Circuit node 221 is coupled to the first end of R21 222. Transistor 218 corresponds to the transfer transistor, which is turned on when the selected word line WLj in this example is enabled by row decoder 104. Note that transfer transistor 218 represents a reference bit cell excluding memory elements. Closed switches 216 and 220 represent the circuitry within column decoder 106 that connects the reference bit cell (i.e., transfer transistor 218) and R21 222 to reference comparator node 215 at the input of sense amplifier circuit 108.

[0060] Cell path 213 includes transistor 212 serving as a current load device, switches 224 and 230, NMOS transistor 226, and selected bit cell 228 of array 102. The second power supply electrode of transistor 212 is coupled to cell comparator node 223 at the inverting input of SA1 214. Closed switch 224 is coupled between node 223 and the first power supply electrode of transistor 226. The second power supply electrode of transistor 226 is coupled to the first terminal (MTJ) of the selected bit cell 228 of the memory element. j,1 This corresponds to the memory element at the intersection of row j and column 1, where column 1 refers to BL. 1,1 To BL 1,K (The selected bit line). Closed switch 230 is coupled between the second terminal of the selected bit cell 228 and VSS. Like transistor 218, transistor 226 corresponds to the transmission transistor, which is turned on when the selected word line WLj in this example is enabled by row decoder 104. Closed switches 224 and 230 represent the circuitry within column decoder 106 that connects the selected bit cell to DL1 (and thus to cell comparator node 223) at the input of sense amplifier circuit 108.

[0061] In operation, the current load device 210 is controlled by VCV to ensure a constant voltage drop across R21 (i.e., a constant voltage at node 221), regardless of process and temperature variations of R21. Therefore, VCV stands for "voltage controlled by voltage," where the voltage at the control electrode of transistor 210 controls the voltage across R21. Transistor 212, acting as a current load device, is controlled by VCI to ensure a constant current through the read-through selected MTJ (i.e., selected bit cell 228), regardless of the resistance value of the MTJ. Therefore, VCI stands for "voltage controlled current," where the voltage at the control electrode of transistor 212 controls the current through the selected MTJ. It should be noted that resistors R1, R21 through R2N, R3, and R4 are all polysilicon type resistors that vary with process and temperature. However, since they are all of the same polysilicon type, all resistors will globally track each other according to process and temperature variations.

[0062] To generate the global bias voltage VCV, bias generator 114 uses VBGREF, a bandgap voltage that is constant across the entire temperature and voltage range (and can be fixed to a specific value based on the design of bandgap voltage generator 202). It should be noted that any bandgap voltage generator can be used to generate VBGREF. Amplifier 204 and transistor 206 are configured to convert VBGREF into a current through R1 208 at node 209. This current is represented by VBGREF / R1. It should be noted that this current depends on the resistance of the polysilicon resistor R1 208. Amplifier 204 controls the bias voltage VCV based on VBGREF and the voltage at node 209, and transistors 206 and 210 act as current mirrors to provide a current through R21 proportional to VBGREF / R1. This results in a voltage (VBGREF·R21) / R1 at node 221. The voltage across R21 remains constant during process and temperature changes (e.g., this voltage is relatively insensitive to the temperature coefficient of R21). In other words, because R21 / R1 is a factor affecting the voltage of node 221, the changes in polysilicon resistors R21 and R1 due to process and temperature cancel each other out, thereby offsetting the effect of the polysilicon resistors on the reference comparison node 215. Similarly, as described below for reference bias generator 112, the changes in polysilicon resistors R3 and R4 due to process and temperature cancel each other out, thereby offsetting the effect of the polysilicon resistors on the cell comparison node 223.

[0063] Referring to bias voltage generator 112, IPTAT current source 232 coupled between VDD and node 235 and ICTAT current source 234 coupled between VDD and node 235 together generate a constant current, Isustant, through node 235 and resistor R3 236. That is, the IPTAT current plus the ICTAT current provides a constant current during temperature changes. At node 235 and the inverting input of amplifier 238, a current-to-voltage conversion circuit (implemented by R3) converts Isustant into a voltage at node 235 based on Isustant and R3. Based on the voltages at nodes 235 and 211, amplifier 238 controls the bias voltage VCI and generates an absolutely constant current through R4 242 relative to temperature, expressed as (Iconstant·R3) / R4. It should be noted that because R3 / R4 are present as factors affecting the current at node 211, the changes in polysilicon resistors R3 and R4 due to process and temperature cancel each other out, thus negating the effect of the polysilicon resistors on the cell comparison node 223. Since transistors 240 and 212 act as current mirrors, transistor 212 provides a current proportional to (Iconstant·R3) / R4 through the selected bit cell 228. Therefore, the bias voltage VCI generates a current through the MTJ of bit cell 228, which remains constant throughout the temperature range, regardless of the programmed resistance value of the MTJ. SA1 214, implemented as a comparator, then compares the voltage at reference comparison node 215 with the voltage at cell comparison node 223 to determine the logic state of D01 at the output of SA1 214, while being minimally affected by process and temperature changes in the polysilicon resistor R21.

[0064] In other words, by receiving different and independent bias voltages for each transistor 210 and 212 used as a current load device, process and temperature variations can be reduced. For example, when VCV is based on the ratio between R21 and R1, the effects of R21 and R1 cancel each other out, and when VCI is based on the ratio between R4 and R3, the effects of R4 and R3 cancel each other out. In this way, the sensing of nodes 215 and 223 can be improved by using corresponding sensing amplifiers (e.g., SA1 214 in the illustrated example).

[0065] Figure 3 Alternative embodiments for generating VCIs are shown. For example... Figure 3As shown, the bias generator 112 can be replaced by a PMOS transistor 302, an IPTAT current generator 304, and an ICTAT current generator 306, eliminating the need for polysilicon resistors R3 and R4. In this embodiment, the first supply electrode of transistor 302 is coupled to VDD, and the control electrode provides VCI. The control electrode of transistor 302 is also connected to a second supply electrode of transistor 302, which is connected to a first terminal of each of current sources 304 and 306. In this way, a constant current over a temperature range is provided through the second supply electrode of transistor 302, thereby generating the bias voltage VCI. Figure 2 Transistor 212 in the VCI will mirror this constant current and also generate a constant current over a temperature range via selected bit cell 228, regardless of the programmed resistance of the MTJ. However, due to the lack of a global signal (i.e., as...) for the VCI's drive strength... Figure 1 As shown, the signals provided to multiple sensing amplifiers in this embodiment may not be as good as... Figure 2 The embodiment of the bias generator 112 shown is ideal.

[0066] Therefore, it is now understood how to use multiple polysilicon resistors of the same type and resistive material (e.g., R1, R21 to R2N, R3, and R4) to generate independent bias voltages, which are used to drive the reference path and the cell path with current-loaded devices to produce voltages that can be accurately sensed by the corresponding sense amplifiers. In one embodiment, during a read operation of a selected bit cell in the MRAM array, a first bias voltage for controlling the current in the reference path is VCV depending on VBGREF / R1, while a second bias voltage for controlling the current in the control path is VCI depending on Isustant. These bias voltages, VCV, and VCI can be used as global bias voltages within the sense amplifier circuitry system, where these bias voltages are used to control the current in the reference path and cell path of each of the multiple sense amplifier circuits in the MRAM array, respectively.

[0067] Because the devices implementing this invention consist mostly of electronic components and circuits known to those skilled in the art, circuit details will not be explained to any extent greater than that deemed necessary as stated above, in order to understand and comprehend the basic concepts of this invention and to avoid obscuring or diverting the teachings of this invention.

[0068] Although the invention has been described with respect to a particular type of conductivity or potential polarity, those skilled in the art will understand that the type of conductivity or potential polarity can be reversed.

[0069] Furthermore, the terms “front,” “rear,” “top,” “bottom,” “upper,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that such terms are interchangeable where appropriate, such that embodiments of the invention described herein can operate, for example, in orientations other than those shown or otherwise described herein.

[0070] Where applicable, some of the above embodiments can be implemented using various different architectures in various information processing systems. For example, although Figure 1 The description herein illustrates an exemplary memory system architecture, but this exemplary architecture is presented merely to provide useful reference in discussing various aspects of the invention. Of course, for illustrative purposes, the description of the architecture has been simplified, and it is only one of many different suitable architectures that can be used according to the invention. Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative, and alternative embodiments may combine logic blocks or circuit elements, or impose functional alternative decompositions on various logic blocks or circuit elements.

[0071] Therefore, it should be understood that the architectures described herein are merely exemplary, and in reality, many other architectures can be implemented to achieve the same functionality. In an abstract but still explicit sense, any arrangement of components that achieve the same functionality is actually “related” to enable the desired functionality. Thus, any two components combined in this paper to achieve a particular function can be considered “related” to each other to enable the desired functionality, regardless of the architecture or intermediate components. Similarly, any two such related components can also be viewed as “operably connected” or “operably coupled” to each other to achieve the desired functionality.

[0072] Furthermore, for example, in one embodiment, the components of the illustrated system 100 are circuits located on a single integrated circuit or within the same device. Moreover, those skilled in the art will recognize that the boundaries between the functionalities of the above-described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed across other operations. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may be changed in different other embodiments.

[0073] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. For example, memory system 100 may include resistive memory other than MRAM. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0074] As used in this article, the term “coupling” is not intended to be limited to direct coupling or mechanical coupling.

[0075] Furthermore, as used herein, the term "a" is defined as one or more. And the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing such an introductory claim element to an invention containing only one such element, even when the same claim includes the introductory phrase "one or more" or "at least one" and an indefinite article such as "a". The same applies to the use of definite articles.

[0076] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority of such elements.

[0077] The following are various embodiments of the present invention.

[0078] In one embodiment, a circuit includes a sense amplifier circuit, a first circuit, and a second circuit. The sense amplifier circuit includes a reference path comprising a first current load device and a reference comparator node, the reference path being coupled to a cell reference circuit during a voltage readout operation, wherein the first current load device includes a control input for controlling a current in the reference path. The sense amplifier circuit also includes a cell path comprising a second current load device and a cell comparator node, the cell path being coupled to a memory cell of a memory cell array during a voltage readout operation, wherein the second current load device includes a control input for controlling a current in the control cell path. The sense amplifier circuit further includes a comparator circuit comprising a first input coupled to the reference comparator node, a second input coupled to the cell comparator node, and an output providing a data output signal based on a comparison of the voltage of the reference comparator node and the voltage of the cell comparator node, and the comparator circuit indicating a data value stored in a memory cell being read during a memory readout operation; the first circuit includes an output providing a first signal to the control input of the first current load device, and the second circuit includes an output providing a second signal to the control input of the second current load device, the first signal and the second signal being different signals. In one aspect of the above embodiments, the second signal is a voltage that generates a relatively constant current through the cell path regardless of the resistance value of the memory cell being read, wherein the memory cell is a resistive memory cell. In another aspect, the second circuit includes a voltage-to-current converter, the voltage-to-current converter including an input generated by a node receiving a relatively constant current over a temperature range. In another aspect, the voltage of the second signal depends on a relatively constant current over a temperature range, wherein the voltage of the first signal does not depend on a relatively constant current over a temperature range. In yet another aspect, the second circuit includes a current mirror to mirror the relatively constant current through the cell path over a temperature range. In yet another aspect of the above embodiments, the first circuit includes a voltage-to-current converter, wherein the voltage-to-current converter includes a first resistor of a first resistive material, wherein the cell reference circuit includes a second resistor of the first resistive material. In yet another aspect, the voltage across the second resistor is relatively insensitive to the temperature coefficient of the second resistor. In yet another aspect, the first circuit includes a voltage-to-current converter, the voltage-to-current converter including an input receiving a relatively constant voltage over a temperature range, wherein the first signal is based on a relatively constant voltage over a temperature range, and wherein the second signal is not based on a relatively constant voltage over a temperature range. On the other hand, the first signal is a voltage that generates a relatively constant voltage across a cell reference circuit, taking into account temperature and process variations during the readout operation of the sensing amplifier circuit, wherein the cell reference circuit is characterized as a resistive reference circuit. On the other hand, the circuit further includes a second sensing amplifier circuit.In another aspect, the second sense amplifier circuit includes a second reference path, which includes a third current load device and a second reference comparison node. During voltage readout by the second sense amplifier circuit, the second reference path is coupled to a second cell reference circuit, wherein the third current load device includes a control input for controlling the current of the second reference path; a second cell path, which includes a fourth current load device and a second cell comparison node. During voltage readout by the second sense amplifier circuit, the second cell path is coupled to a memory cell of the memory cell array, wherein the fourth current load device includes a control input for controlling the current of the second cell path; and a second comparator circuit, which includes a first input coupled to the second reference comparison node, a second input coupled to the second cell comparison node, and an output that provides a second data output signal based on a comparison of the voltage of the second reference comparison node with the voltage of the second cell comparison node, and the second comparator circuit indicates the data value stored in the memory cell being read during a memory readout operation performed by the second sense amplifier circuit; wherein a first signal is provided to the control input of the third current load device, and a second signal is provided to the control input of the fourth current load device. In another aspect of the above embodiments, the memory cell is characterized as a resistive memory cell. In another aspect, the memory cell is characterized as an MRAM memory cell. In yet another aspect of the above embodiments, the cell reference circuit is characterized as a resistor element.

[0079] In another embodiment, a method of performing a memory read operation using a sense amplifier circuit includes: generating a first signal controlling the current of a reference path of the sense amplifier circuit during a memory read operation of a memory cell of a memory cell array, the reference path including a reference comparator node; generating a second signal controlling the current of a cell path of the sense amplifier circuit during the memory read operation, the cell path including a cell comparator node, wherein the first signal and the second signal are different signals; and comparing the voltage of the reference comparator node when a cell reference circuit is coupled to the reference path with the voltage of the cell comparator node when a memory cell of the memory array is coupled to the cell path to generate an indication of a value stored in the memory cell during the memory read operation. In one aspect of this other embodiment, the first signal is generated based on a relatively constant voltage over a temperature range, while the second signal is not based on a relatively constant voltage over a temperature range. In another aspect, the second signal is generated based on a relatively constant current over a temperature range, while the first signal is not based on a relatively constant current over a temperature range. In another aspect, the method further includes controlling the current of a second reference path of a second sense amplifier circuit, the second reference path including a second reference comparison node, with a first signal during a memory read operation of a second memory cell of the memory cell array; controlling the current of a second cell path of the second sense amplifier circuit, the second cell path including a second cell comparison node, during a memory read operation of the second memory cell; and comparing the voltage of the second reference comparison node when the second cell reference circuit is coupled to the second reference path with the voltage of the second cell comparison node when the second memory cell of the memory array is coupled to the second cell path, to generate an indication of a value stored in the second memory cell during the memory read operation.

[0080] In another embodiment, a circuit includes a plurality of sense amplifier circuits, each of the plurality of sense amplifier circuits including: a reference path including a first current load device and a reference comparator node, the reference path being coupled to a cell reference circuit during a sense amplifier circuit read voltage, wherein the first current load device includes a control input for controlling the current of the reference path; a cell path including a second current load device and a cell comparator node, the cell path being coupled to a memory cell of a memory cell array during a sense amplifier circuit read voltage, wherein the second current load device includes a control input for controlling the current of the control path; and a comparator circuit including a first input coupled to the reference comparator node, a second input coupled to the cell comparator node, and an output providing a data output signal based on a comparison of the voltage of the reference comparator node and the voltage of the cell comparator node, and the comparator circuit indicating the data value stored in the memory cell being read during a memory read operation. In yet another embodiment, the circuit further includes a first circuit comprising an output for providing a first signal to a control input of a first current-loaded device of each of the plurality of sense amplifier circuits; and a second circuit comprising an output for providing a second signal to a control input of a second current-loaded device of each of the plurality of sense amplifier circuits, the first signal and the second signal being different signals. In yet another aspect of this embodiment, the voltage of the second signal depends on a relatively constant current over the entire temperature range, wherein the voltage of the first signal does not depend on a relatively constant current over the entire temperature range. In another aspect, the cell reference circuit includes a resistor, wherein the voltage across the resistor is relatively insensitive to the temperature coefficient of the resistor.

Claims

1. A circuit for a memory, characterized in that, include: The sensing amplifier circuit includes: A reference path, comprising a first current load device and a reference comparator node, is coupled to a cell reference circuit during voltage readout by the sensing amplifier circuit, wherein the first current load device includes a control input for controlling the current of the reference path; A cell path, comprising a second current load device and a cell comparator node, wherein the cell path is coupled to a memory cell of a memory cell array during voltage readout by the sensing amplifier circuit, wherein the second current load device includes a control input for controlling the current of the cell path; A comparator circuit includes a first input coupled to the reference comparator node, a second input coupled to the cell comparator node, and an output that provides a data output signal based on a comparison of the voltage of the reference comparator node and the voltage of the cell comparator node, and the comparator circuit indicates the data value stored in the memory cell that is read during a memory read operation. A first circuit, the first circuit including an output for providing a first signal to the control input of the first current load device; The second circuit includes an output for providing a second signal to the control input of the second current load device, wherein the first signal and the second signal are different signals.

2. The circuit according to claim 1, characterized in that, The second circuit includes a voltage-to-current converter, which includes an input generated by a node that receives a current with a relatively constant temperature.

3. The circuit according to claim 1, characterized in that, The voltage of the second signal depends on the current at a relatively constant temperature, while the voltage of the first signal does not depend on the current at the relatively constant temperature.

4. The circuit according to claim 1, characterized in that, The first circuit includes a voltage-to-current converter, the voltage-to-current converter including an input that receives a voltage that is relatively constant at a temperature, wherein a first signal is based on the voltage that is relatively constant at a temperature, and wherein a second signal is not based on the voltage that is relatively constant at a temperature.

5. The circuit according to claim 1, characterized in that, In addition, including: A second sensing amplifier circuit, the second sensing amplifier circuit comprising: A second reference path, comprising a third current load device and a second reference comparison node, is coupled to a second unit reference circuit during voltage readout by the second sensing amplifier circuit, wherein the third current load device includes a control input for controlling the current of the second reference path. The second unit path includes a fourth current load device and a second unit comparison node, which is coupled to the memory cells of the memory cell array during the voltage readout of the second sensing amplifier circuit, wherein the fourth current load device includes a control input for controlling the current of the second unit path. The second comparator circuit includes a first input coupled to the second reference comparator node, a second input coupled to the second unit comparator node, and an output that provides a second data output signal based on a comparison of the voltage of the second reference comparator node with the voltage of the second unit comparator node, and the second comparator circuit indicates the data value stored in the memory cell that is read during a memory read operation performed by the second sense amplifier circuit. The first signal is provided to the control input of the third current load device, and the second signal is provided to the control input of the fourth current load device.

6. A method for performing a memory read operation using a sensing amplifier circuit, characterized in that, The method includes: During a memory read operation of a memory cell in a memory cell array, a first signal is generated to control the current of a reference path of a sense amplifier circuit, the reference path including a reference comparator node; During the memory read operation, a second signal is generated that controls the current of a cell path in the sensing amplifier circuit, the cell path including a cell comparison node, wherein the first signal and the second signal are different signals; The voltage of the reference comparator node when the cell reference circuit is coupled to the reference path is compared with the voltage of the cell comparator node when the memory cell of the memory array is coupled to the cell path, in order to generate an indication of the value stored in the memory cell during the memory read operation.

7. The method according to claim 6, characterized in that, The generation of the first signal is based on a voltage with a relatively constant temperature, while the generation of the second signal is not based on the voltage with the relatively constant temperature.

8. The method according to claim 6, characterized in that, The generation of the second signal is based on a current with a relatively constant temperature, wherein the generation of the first signal is not based on the current with the relatively constant temperature.

9. A circuit for a memory, characterized in that, include: Multiple sensing amplifier circuits, each of the multiple sensing amplifier circuits comprising: A reference path, comprising a first current load device and a reference comparator node, is coupled to a cell reference circuit during voltage readout by the sensing amplifier circuit, wherein the first current load device includes a control input for controlling the current of the reference path; A cell path, comprising a second current load device and a cell comparator node, wherein the cell path is coupled to a memory cell of a memory cell array during voltage readout by the sensing amplifier circuit, wherein the second current load device includes a control input for controlling the current of the cell path; A comparator circuit includes a first input coupled to the reference comparator node, a second input coupled to the cell comparator node, and an output that provides a data output signal based on a comparison of the voltage of the reference comparator node and the voltage of the cell comparator node, and the comparator circuit indicates the data value stored in the memory cell that is read during a memory read operation. A first circuit, the first circuit including an output for providing a first signal to the control input of the first current load device of each of the first plurality of sense amplifier circuits; The second circuit includes an output for providing a second signal to the control input of the second current load device of each of the plurality of sense amplifier circuits, wherein the first signal and the second signal are different signals.

10. The circuit according to claim 9, characterized in that, The voltage of the second signal depends on the current at a relatively constant temperature, while the voltage of the first signal does not depend on the current at the relatively constant temperature.

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