Semiconductor memory device and method of operating the same

Abstract

A semiconductor memory device and a method for operating the semiconductor memory device are disclosed. The semiconductor memory device includes: a memory cell array, the memory cell array including: a plurality of segments arranged at corresponding intersections of a plurality of row blocks and a plurality of column blocks, each row block including a plurality of dynamic memory cells coupled to word lines and bit lines; a row decoder, responsive to a row address, activating a first word line of a first row block; determining whether the first row block is a master block based on first fuse information and determining whether a second row block is mapped as a slave of the master block; activating a second word line of a second row block and outputting a row block information signal; and a column decoder, accessing a portion of a plurality of first memory cells coupled to the first word line or a portion of a plurality of second memory cells coupled to the second word line based on the column address, the row block information signal and the second fuse information.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0082453 filed on Jul. 9, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to memories, and more particularly, to semiconductor memory devices and methods of operating semiconductor memory devices. Background Art

[0003] Semiconductor chips are manufactured by semiconductor manufacturing processes and then tested by test equipment in wafer, die or package state. Defective semiconductor chips are selected by testing, and some defective cells of defective chips are replaced with spare cells in the repair process to save defective semiconductor chips. At present, semiconductor chips (such as dynamic random access memory (DRAM)) have continued to reduce in size through fine processes, and therefore, the possibility of errors occurring during the manufacturing process increases. In addition, some errors (i.e., soft errors) may occur during chip operation, and such soft errors can be detected and replaced by built-in self-test (BIST) logic implemented in semiconductor chips. Some fuses in row decoders or column decoders of semiconductor chips can be programmed using lasers in the repair process or using electricity in the BIST logic. Summary of the invention

[0004] Example embodiments may provide a semiconductor memory device capable of improving flexibility of a column repair operation.

[0005] Example embodiments may provide a method of operating a semiconductor memory device capable of improving flexibility of a column repair operation.

[0006] According to an exemplary embodiment of the present invention, a semiconductor memory device includes: a memory cell array, a row decoder and a column decoder. The memory cell array includes: a plurality of row blocks arranged in a first direction; a plurality of column blocks arranged in a second direction different from the first direction; and a plurality of segments, each of the plurality of segments being arranged at a corresponding intersection of the plurality of row blocks and the plurality of column blocks, each of the plurality of row blocks including a plurality of dynamic memory cells coupled to word lines and bit lines. The row decoder is configured to: receive a row address; in response to the row address, activate a first word line of a first row block of the plurality of row blocks, wherein the first row block is identified using at least one block address bit of the row address; determine whether the first row block is a master block and determine whether a second row block of the plurality of row blocks is mapped as a slave of the master block based on first fuse information, the first fuse information indicating that the first row block is a master block; in response to determining whether the first row block is a master block, activate a second word line of a second row block of the plurality of row blocks, and in response to activating the second word line, output a row block information signal, the row block information signal indicating that the second word line is activated. The column decoder is configured to: receive a column address; and access a portion of a plurality of first memory cells coupled to a first word line or a portion of a second word line of a plurality of second memory cells coupled to a second row block based on the column address, a row block information signal, and second fuse information, the second fuse information indicating a first segment of the plurality of segments that is set at an intersection of a main block and a first column block associated with the column address.

[0007] According to an exemplary embodiment of the present invention, a semiconductor memory device includes: a memory cell array, a row decoder, a column decoder and a peripheral circuit. The memory cell array includes: a plurality of row blocks arranged in a first direction; a plurality of column blocks arranged in a second direction different from the first direction; and a plurality of segments, each of the plurality of segments being arranged at a corresponding intersection of the plurality of row blocks and the plurality of column blocks, each of the plurality of row blocks including a plurality of dynamic memory cells coupled to word lines and bit lines. The row decoder is configured to: receive a row address; in response to the row address, activate a first word line of a first row block of the plurality of row blocks, wherein the first row block is identified using at least one block address bit of the row address; determine whether the first row block is a master block and determine whether a second row block of the plurality of row blocks is mapped as a slave of the master block based on first fuse information, wherein the first fuse information indicates that the first row block is a master block; in response to determining whether the first row block is a master block, activate a second word line of a second row block of the plurality of row blocks; and in response to activating the second word line, output a row block information signal, the row block information signal indicating that the second word line is activated. The column decoder is configured to: receive a column address; access a portion of a plurality of first memory cells coupled to a first word line or a portion of a plurality of second memory cells coupled to a second word line based on the column address, a row block information signal, and second fuse information indicating a first segment of the plurality of segments disposed at an intersection of a main block and a first column block associated with the column address among the plurality of column blocks. The peripheral circuit is configured to control the row decoder and the column decoder based on a command and an address received from the outside, the address including a row address and a column address.

[0008] According to an exemplary embodiment of the present invention, a method for operating a semiconductor memory device, wherein the semiconductor memory device includes a memory cell array, the memory cell array including: a plurality of row blocks arranged in a first direction; a plurality of column blocks arranged in a second direction different from the first direction; and a plurality of segments, each of the plurality of segments being arranged at a corresponding intersection of the plurality of row blocks and the plurality of column blocks, each of the plurality of row blocks including a plurality of dynamic memory cells coupled to word lines and bit lines, the method comprising: activating, by a row decoder, a first word line of a first row block of the plurality of row blocks in response to a row address, wherein the first row block uses at least one block address bit of the row address to identification; determining by a row decoder whether the first row block is a main block based on first fuse information, the first fuse information indicating that the first row block is the main block; activating by the row decoder and in response to determining whether the first row block is the main block a second word line of a second row block among the plurality of row blocks; generating a row block information signal in response to activating the second word line, the row block information signal indicating that the second word line is activated; and accessing by a column decoder a portion of a plurality of first memory cells coupled to the first word line or a portion of a second memory cell coupled to the second word line based on a column address, the row block information signal and second fuse information, the second fuse information indicating a first segment of the plurality of segments set at an intersection of the main block and a first column block associated with the column address. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Exemplary embodiments will be described in more detail below with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0011] Figure 2A and Figure 2B The semiconductor memory device according to the exemplary embodiment is respectively shown to perform a column repair operation.

[0012] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of an example of a semiconductor memory device in FIG.

[0013] Figure 4 Show Figure 3 An example of a first memory bank array in a semiconductor memory device.

[0014] Figure 5 Show Figure 3 A memory cell array, a row decoder and a column decoder in a semiconductor memory device.

[0015] Figure 6 is a diagram showing a method according to an exemplary embodiment Figure 5 Block diagram of one of the row block fuse circuits in FIG.

[0016] Figure 7 Show Figure 6 An example of a row block information storage table in a row block fuse circuit.

[0017] Figure 8 Show Figure 6 Example of a row address in .

[0018] Fig. 9 is a diagram showing a method according to an exemplary embodiment Figure 5 Block diagram of one of the repair circuits in .

[0019] Fig.10 is a diagram showing a method according to an exemplary embodiment Figure 5 Block diagram of one of the sub-column decoders in .

[0020] Fig.11 Shown in Figure 5 A first selection signal and a second selection signal are transmitted in a semiconductor memory device.

[0021] Fig.12 According to an exemplary embodiment, Figure 5 A portion of a memory cell array.

[0022] Fig.13 According to an exemplary embodiment, Fig.12 The local sense amplifier circuit in.

[0023] Fig.14 The column decoder 271 is shown in Figure 2A A column repair operation is performed in a memory bank array in the embodiment of the present invention.

[0024] Fig.15 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of another example of a semiconductor memory device in FIG.

[0025] Fig.16 is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment.

[0026] Fig.17A and Fig. 17B A method of operating a semiconductor memory device according to an exemplary embodiment is illustrated.

[0027] Fig.18 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0028] Fig.19 is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown.

[0030] Figure 1 is a block diagram illustrating a memory system according to an exemplary embodiment.

[0031] Reference Figure 1 , the memory system 20 may include a memory controller 100 and a semiconductor memory device 200 .

[0032] The memory controller 100 may control the overall operation of the memory system 20. The memory controller 100 may control the entire data exchange between the external host and the semiconductor memory device 200. For example, the memory controller 100 may write data into the semiconductor memory device 200 or read data from the semiconductor memory device 200 in response to a request from the host. In addition, the memory controller 100 may issue an operation command to the semiconductor memory device 200 to control the semiconductor memory device 200.

[0033] In some embodiments, the semiconductor memory device 200 is a memory device including a dynamic memory cell, such as a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or a LPDDR5 SDRAM).

[0034] The memory controller 100 transmits a clock signal CLK, a command CMD, and an address (signal) ADDR to the semiconductor memory device 200 , and exchanges data DQ with the semiconductor memory device 200 .

[0035] The semiconductor memory device 200 includes a memory cell array (MCA) 300 storing data DQ and an address decoder ADEC. The address decoder ADEC may include a row decoder (RD) 261 and a column decoder (CD) 271.

[0036] The memory cell array 300 may include a plurality of row blocks arranged in a first direction, each of the plurality of row blocks including a plurality of dynamic memory cells coupled to a plurality of word lines and a plurality of bit lines, each of the plurality of row blocks being identified by a row block identification bit (i.e., at least one block address bit) corresponding to a portion of a plurality of bits of a row address, and each of the plurality of row blocks including a plurality of segments arranged in a second direction intersecting the first direction.

[0037] The row decoder 261 may activate a first word line in a first row block in response to a row address, may activate a second word line in a second row block that is different from the first row block and mapped as a slave of the first row block in response to first fuse information indicating that the first row block is a master, and may provide a row block information signal indicating that the second word line is activated to the column decoder 271. The column decoder 271 may access a portion of a plurality of first memory cells coupled to the first word line and a portion of a plurality of second memory cells coupled to the second word line based on the column address, the row block information signal, and the second fuse information. Therefore, the semiconductor memory device 200 may increase the flexibility of the column repair operation.

[0038] Figure 2A and Figure 2B The semiconductor memory device according to the exemplary embodiment is respectively shown to perform a column repair operation.

[0039] Figure 2A and Figure 2B The address decoder ADEC is shown in Figure 1. Figure 1 The bank array BNR in the memory cell array 300 in FIG. 1 performs a column repair operation.

[0040] Reference Figure 2A , the memory bank array BNR includes a plurality of row blocks RBLK1 to RBLK4 arranged in a first direction D1 and identified by a row block identification bit corresponding to a portion of a plurality of bits of a row address. Each of the row blocks RBLK1 to RBLK4 may include a plurality of normal segments SEG1 to SEG4 and at least one spare segment SSEG arranged in a second direction D2 intersecting the first direction D1.

[0041] For example, the first fuse circuit FC1 may include Figure 1 The first fuse circuit FC1 may store information associated with the first row block and the second row block as first fuse information. The first row block may be designated as a master, and the second row block may be mapped as a slave of the first row block. Figure 2A In the example, row block RBLK1 is the master block (ie, the master block), and row block RBLK3 is the slave block (ie, the slave block) of row block RBLK1.

[0042] For example, the second fuse circuit FC2 may include Figure 1 The second fuse circuit FC2 may store segment information as the second fuse information. The segment information of the second fuse circuit FC2 may indicate a segment (H) among the multiple segments in the first row block as the subject to be replaced by at least one segment among the multiple segments in the second row block as the slave.

[0043] Reference Figure 2A, the segment SEG2 including the defective cell of the row block RBLK1 is replaced / repaired using the segment SEG2 of the row block RBLK3. In addition, the segment SEG4 including the defective cell of the row block RBLK1 can be repaired using the spare segment SSEG.

[0044] Reference Figure 2B , based on the information stored in the first fuse circuit FC1, the row block RBLK1 is the main body relative to the row block RBLK2, the row block RBLK2 is the main body relative to the row block RBLK3, and the row block RBLK3 is the main body relative to the row block RBLK4. In addition, based on the information stored in the second fuse circuit FC2, the segments SEG1, SEG2, and SEG3 of the row block RBLK1, which all include defective cells, are replaced with the segments SEG1, SEG2, and SEG3 of the row block RBLK2, respectively, the segments SEG1 and SEG2 of the row block RBLK2 are replaced with the segments SEG1 and SEG2 of the row block RBLK3, respectively, and the segment SEG1 of the row block RBLK3 is replaced with the segment SEG1 of the row block RBLK4. In addition, the segment SEG4 of the row block RBLK1, which includes a defective cell, can be repaired using the spare segment SSEG.

[0045] exist Figure 2B In the example, row block RBLK2 is mapped as a subordinate of row block RBLK1, row block RBLK3 is mapped as a subordinate of row block RBLK2, and row block RBLK4 is mapped as a subordinate of row block RBLK3.

[0046] The first fuse information and the second fuse information may be stored in the first fuse circuit FC1 and the second fuse circuit FC2 in advance by testing the memory cell array 300 or the bank array BNR.

[0047] When the row decoder 261 activates the first word line in the row block RBLK1 and the second word line in the row block RBLK2, the column decoder 271 may repair each defective cell of the segment SEG2 in the row block RBLK1 using the normal memory cells of the segment SEG2 in the row block RBLK2, and when the row decoder 261 activates the second word line in the row block RBLK2 and the third word line in the row block RBLK3, the column decoder 271 may replace the segment SEG2 in the row block RBLK2 with the segment SEG2 in the row block RBLK3. In addition, when the row decoder 261 activates the third word line in the row block RBLK3 and the fourth word line in the row block RBLK4, the column decoder 271 may replace the segment SEG1 in the row block RBLK3 with the segment SEG1 in the row block RBLK4.

[0048] Figure 3 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of an example of a semiconductor memory device in FIG.

[0049] Reference Figure 3 , the semiconductor memory device 200 a includes a memory cell array 300 a , a row decoder 261 , a column decoder 271 , and a peripheral circuit 201 .

[0050] The memory cell array 300a may include a plurality of memory bank arrays 310 to 380. Each of the memory bank arrays 310 to 380 may include a plurality of memory bank arrays 310 to 380. Figure 2A and Figure 2B The plurality of row blocks.

[0051] The semiconductor memory device 200 a may receive an activate command before receiving a write command or a read command from the outside (eg, a memory controller or a test device).

[0052] All memory cells connected to the word line (WL) of the semiconductor memory device 200a may be selected based on the activation command. Thereafter, if the semiconductor memory device 200a receives a write command or a read command, a plurality of bit lines may be selected. In one embodiment, a bit line may be selected by a write command or a read command. Data input / output may be performed on the memory cell coupled to the selected bit line.

[0053] Parity data for correcting data stored in at least one of the memory arrays 310 to 380 may be stored in some of the memory arrays 310 to 380 .

[0054] The column decoder 271 may be connected to the memory cell array 300a through a column selection line CSL and a spare column selection line SCSL. The column decoder 271 may select the column selection line CSL or the spare column selection line SCSL based on a write command or a read command. If the column decoder 271 selects the column selection line CSL, the normal segment is selected. When the column decoder 271 selects the spare column selection line SCSL, the spare segment is selected. Each normal segment includes a normal memory cell coupled to a word line and a bit line, and the spare segment includes a spare memory cell coupled to a word line and a spare bit line.

[0055] The peripheral circuit 201 may include a command / address pad (pad, which may also be referred to as a "pad") (CMD / ADD) 203, an input / output pad 205, and an error correction code (ECC) engine 280. In one embodiment, the ECC engine 280 may not be included in the peripheral circuit 201. The peripheral circuit 201 may receive a command CMD and an address ADDR from the outside, and may exchange data DQ with the outside.

[0056] The peripheral circuit 201 may provide a column address CADDR to the column decoder 271 according to a command CMD received from the outside, and may provide a row address RADDR to the row decoder 261. The peripheral circuit 201 may provide input data DQ to the column decoder 271 in response to a write command, or may receive output data DQ from the column decoder 271 in response to a read command. Input data may be input to the peripheral circuit 201 through the input / output pad 205. Output data may be output to the memory controller 100 through the input / output pad 205.

[0057] The ECC engine 280 may perform ECC encoding on the input data to generate parity data. The ECC engine 280 may store the input data and the parity data in the memory bank arrays 310 to 380. The ECC engine 280 may perform ECC decoding on the data read from the memory bank arrays 310 to 380 to correct at least one error in the read data. The ECC engine 280 may send the corrected data to the memory controller 100 through the input / output pad 205.

[0058] The row decoder 261 may activate a first word line in a first row block specified by the row address RADDR in response to the row address RADDR, the row decoder 261 may activate a second word line in a second row block different from the first row block when the first row block is a main body, and the row decoder 261 may output a row block information signal RBIN indicating that the second word line is activated. The row decoder 261 may include a row block information circuit (RBIC) 400, wherein the row block information circuit 400 may store row block information of each row block and may output the row block information signal RBIN.

[0059] Figure 4 Show Figure 3 An example of a first memory bank array in a semiconductor memory device.

[0060] Reference Figure 4 , the first memory bank array 310 includes a normal cell region NCR and a spare cell region SCR. The normal cell region NCR includes a plurality of word lines WL1 to WLm (m is a natural number greater than 2), a plurality of bit lines BL1 to BLn (n is a natural number greater than 2), and a plurality of memory cells MC arranged at a plurality of intersections between the word lines WL1 to WLm and the bit lines BL1 to BLn. The spare cell region SCR includes a plurality of spare bit lines SBL1 to SBLy (y is a natural number greater than 2), a plurality of word lines WL1 to WLm, and a plurality of spare cells (or, spare memory cells) SMC arranged at a plurality of intersections between the word lines WL1 to WLm and the spare bit lines SBL1 to SBLy.

[0061] The word lines WL1 to WLm extend in the second direction D2, and the bit lines BL1 to BLn and the spare bit lines SBL1 to SBLy extend in the first direction D1 intersecting the second direction D2. The first memory array 310 can be divided into a plurality of row blocks by at least one row block identification bit of the row address RADDR, and each row block can be divided into at least two segments in the second direction D2 by at least one segment identification bit of the column address CADDR. Using at least one segment identification bit of the column address CADDR, the first memory array 310 can be divided into a plurality of column blocks. The first memory array 310 may include a plurality of segments arranged in the first direction D1 and the second direction D2. Each segment of the plurality of segments may be located at a plurality of corresponding intersections of the plurality of row blocks and the plurality of column blocks. That is, the segments in different row blocks form a plurality of column blocks in the second direction.

[0062] In an exemplary embodiment, the first memory bank array may be a representative memory bank array among the plurality of memory bank arrays 310 to 380. The present invention is not limited thereto. In an exemplary embodiment, the other memory bank arrays 320 to 380 may not include the spare cell array SCA.

[0063] Figure 5 Show Figure 3 A memory cell array, a row decoder and a column decoder in a semiconductor memory device.

[0064] Reference Figure 5 , in the memory cell array 300a, I sub-array blocks SCB may be arranged in the second direction D2, and J sub-array blocks SCB may be arranged in the first direction D1 substantially perpendicular to the second direction D2. I and J represent the number of sub-array blocks SCB in the second direction and the first direction, respectively, and I and J are natural numbers greater than 2. The sub-array blocks SCB may correspond to Figure 2A or Figure 2B The sub-array blocks SCB may be arranged in a row in the second direction D2 and may be referred to as a row block. The sub-array blocks SCB may be arranged in a column in the first direction D1 and may be referred to as a column block. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells may be arranged in each sub-array block SCB.

[0065] I+1 sub-word line driver regions SWB may be disposed between sub-array blocks SCB in the second direction D2. Sub-word line drivers may be disposed in the sub-word line driver region SWB. J+1 bit line sense amplifier regions BLSAB may be disposed, for example, between sub-array blocks SCB in the first direction D1. Bit line sense amplifiers for sensing data stored in memory cells may be disposed in the bit line sense amplifier region BLSAB.

[0066] A plurality of coupling regions CONJ may be disposed adjacent to the sub word line driver region SWB and the bit line sense amplifier region BLSAB. A voltage generator is disposed in each coupling region CONJ.

[0067] The row decoder 261 includes a row block information circuit 400, which may include a plurality of row block fuse circuits RBFC1 401 to RBFCJ 40J corresponding to a plurality of row blocks in a first direction D1. The row block fuse circuits 401 to 40J may output a row block information signal RBIN to the column decoder 271 in response to the row block identification bit of the row address RADDR.

[0068] The column decoder 271 may include a plurality of sub-column decoders SCD1 551 to SCDI 55I and a plurality of repair circuits 501 to 50I. Each of the sub-column decoders 551 to 55I may be connected to a corresponding column block of a plurality of column blocks, each of the plurality of column blocks including J sub-array blocks SCB in one column. Each of the plurality of repair circuits 501 to 50I may be connected to a corresponding sub-column decoder of the plurality of sub-column decoders 551 to 55I.

[0069] Each of the repair circuits 501 to 50I may selectively activate the first repair signal CREN1 and the second repair signal CREN2 in response to the column address CADDR and the row block information signal RBIN to provide the first repair signal CREN1 and the second repair signal CREN2 to the corresponding sub-column decoder of the sub-column decoders 551 to 55I. In response to the first repair signal CREN1 and the second repair signal CREN2, each of the sub-column decoders 551 to 55(I-1) may select the column selection line CSL, and the sub-column decoder 55I may select the spare column selection line SCSL. In addition, each of the sub-column decoders 551 to 55I may output a corresponding first selection signal of the first selection signals SELa1 to SELaY (Y is a natural number greater than 2) associated with selecting the corresponding segment and a corresponding second selection signal of the second selection signals SELb1 to SELbY.

[0070] Will be in Fig.12 3. Portion 390 of memory cell array 300a is depicted in FIG.

[0071] Figure 6 is a diagram showing a method according to an exemplary embodiment Figure 5 Block diagram of one of the row block fuse circuits in FIG.

[0072] The configuration of each of the row block fuse circuits 402 to 40J may be substantially the same as that of the row block fuse circuit 401 .

[0073] Reference Figure 6The row block fuse circuit 401 may include a defect (fault) address storage table 410 (i.e., a defect address table storage device), a row address comparator 405, a row block information storage table 420 (i.e., a row block information table storage device), a row block address comparator (or row block comparator) 425 and a signal generator 430.

[0074] The defect address storage table 410 stores defective row block address information FRAI associated with address information of defective cells of a segment included in a corresponding row block. The row address comparator 405 compares the row address RADDR with the defective row block address information FRAI to output a row match signal RMTH indicating whether the row address RADDR matches the defective row block address information FRAI.

[0075] The row block information storage table 420 may store a master bit MB indicating whether the corresponding row block is a master, (master) row block information MRB associated with address information of the corresponding row block, and slave row block information SRBI associated with address information of a slave row block including a second word line. The row block information storage table 420 may correspond to Figure 2A and Figure 2B The master row block information MRB and the slave row block information SRBI may correspond to the first fuse information.

[0076] The row block information storage table 420 may provide the main row block information MRB to the row block address comparator 425. The row block address comparator 425 may compare the row block identification bit BRB with the main row block information MRB to provide the row block information storage table 420 and the signal generator 430 with a row block match signal RBMTH indicating whether the row block identification bit BRB matches the main row block information MRB.

[0077] The row block identification bit BRB may include some high bits of the row address RADDR. When the row address RADDR includes the g bit, the high r bits of the row address RADDR may correspond to the row block identification bit BRB. The row block information storage table 420 may provide the slave row block information SRBI associated with the row block including the second word line to the signal generator 430 in response to the row block match signal RBMTH.

[0078] The signal generator 430 may output the row block information signal RBIN1 to the column decoder 271 in response to the row match signal RMTH, the row block match signal RBMTH, and the slave row block information SRBI.

[0079] Figure 7 Show Figure 6 An example of a defect address storage table in a row block fuse circuit.

[0080] Reference Figure 7The defect address storage table 410 includes an antifuse array 411 , a control unit 412 , a sensing unit 413 , and a register unit 414 .

[0081] The antifuse array 411 includes p×q antifuses (AF) respectively connected to intersections of p rows and q columns (p and q are natural numbers greater than 2). The antifuse array 411 includes p word lines AWL1 to AWLp for accessing the antifuses (AF) arranged in the p rows, and q bit lines ABL1 to ABLq arranged corresponding to the q columns so as to transfer information read from the antifuses (AF).

[0082] The control unit 412 programs the defective row block address information FRAI in the antifuse array 412, or reads the defective row block address information FRAI from the antifuse array 412. The sensing unit 413 may sense and amplify the defective row block address information FRAI received from the antifuse array 411, and output the amplified result. The register unit 414 may temporarily store the defective row block address information FRAI received from the sensing unit 413. The register unit 414 outputs the defective row block address information FRAI to the row address comparator 405.

[0083] Figure 8 Show Figure 6 Example of a row address in .

[0084] exist Figure 8 In the example, it is assumed that the row address RADDR includes 16 bits A0 to A15.

[0085] Reference Figure 8 , upper 3 bits A15 to A13 of the row address RADDR may be designated as row block identification bits BRB. In this case, each of the memory bank arrays 310 to 380 may be divided into eight row blocks arranged in the first direction D1.

[0086] Fig. 9 is a diagram showing a method according to an exemplary embodiment Figure 5 Block diagram of one of the repair circuits in .

[0087] The configuration of each of the repair circuits 502 to 50J may be substantially the same as that of the repair circuit 501 .

[0088] Reference Fig. 9 The repair circuit 501 includes a failure address storage table 510 , a column address comparator 515 , a fuse circuit 520 , a signal generator 530 and a repair signal generator 540 .

[0089] The fail address storage table 510 may store defective (fail) column address information FCAI in association with column address information of defective cells of a corresponding segment.

[0090] The column address comparator 515 may compare the column address CADDR with the failure column address information FCAI to output a column match signal CMTH indicating whether the column address CADDR matches the failure column address information FCAI to the fuse circuit 520 and the repair signal generator 540. The column match signal CMTH may indicate whether the column address CADDR matches the failure column address information FCAI. The failure address storage table 510 may have Figure 7 The fault address storage table 410 is similarly configured.

[0091] The fuse circuit 520 includes a plurality of fuse sets 521, 522, and 523. The fuse sets 521, 522, and 523 may correspond to segments in the first direction D1.

[0092] Each of the plurality of fuse sets 521, 522, and 523 may store segment information associated with selection of each of the plurality of segments, and include a first region 521a and a second region 521b. The first region 521a may store segment information SGI associated with whether each segment will be replaced by a segment in a different row block, and the second region 521b may store a fuse bit FB associated with whether the corresponding segment will be replaced by a spare segment. In response to the column match signal CMTH, the fuse sets 521, 522, and 523 may provide the segment information SGI and the fuse bit FB to the signal generator 530 and the repair signal generator 540.

[0093] The signal generator 530 may generate first and second internal selection signals ISELa1 and ISELb1 associated with selecting a corresponding segment based on the row block information signal RBIN, the segment information SGI, and the fuse bit FB. The signal generator 530 may provide the first and second internal selection signals ISELa1 and ISELb1 to the corresponding sub-column decoders.

[0094] The repair signal generator 540 may determine the logic levels of the first repair signal CREN1 and the second repair signal CREN2 based on the column match signal CMTH, the segment information SGI, and the fuse bit FB. For example, when the column match signal CMTH indicates that the column address CADDR does not match the defective column address information FCAI, the repair signal generator 540 deactivates the first repair signal CREN1 and the second repair signal CREN2 using a low level. When the first repair signal CREN1 and the second repair signal CREN2 are deactivated, Figure 5 The first sub-column decoder 551 in may activate a corresponding column selection signal in the column selection signals CSL.

[0095] For example, when the column match signal CMTH indicates that the column address CADDR matches the failure column address information FCAI, and the fuse bit FB has a high level indicating that the corresponding segment will be replaced by a spare segment, the repair signal generator 540 activates the first repair signal CREN1 with a high level and deactivates the second repair signal CREN2 with a low level. In this case, Figure 5 The sub-column decoders 551 connected to the corresponding segments in the do not select the corresponding column selection lines in the column selection lines CSL.

[0096] In this case, the repair circuit 50I connected to the spare segment deactivates the first repair signal CREN1 with a low level and activates the second repair signal CREN2 with a high level. Figure 5 The sub-column decoder 55I in selects the spare column selection line SCSL connected to the spare segment.

[0097] Fig.10 is a diagram showing a method according to an exemplary embodiment Figure 5 Block diagram of one of the sub-column decoders in .

[0098] The configuration of each of the sub-column decoders 552 to 55I may be substantially the same as that of the sub-column decoder 551 .

[0099] Reference Fig.10 , the sub-column decoder 551 may include a column selection line driver 560 corresponding to a normal column selection line driver.

[0100] The column selection line driver 560 can select one of the column selection lines CSL, and can determine the logic levels of the first selection signal SELa1 and the second selection signal SELb1 associated with the selection of the corresponding segment in response to the column address CADDR, the column match signal CMTH, the first repair signal CREN1, the second repair signal CREN2, and the internal selection signals ISELa1 and ISELb1.

[0101] For example, to select a segment of a first row block as a subject, the column selection line driver 560 activates a first selection signal SELa1. To select a segment of a second row block as a slave, the column selection line driver 560 activates a second selection signal SELb1.

[0102] Fig.11 shows that the first selection signal and the second selection signal are transmitted to Figure 5 A semiconductor memory device.

[0103] Reference Fig.11, the row decoder 261 provides the row block information signal RBIN to the column decoder 271, and the column decoder 271 transmits the first selection signals SELa1 to SELaY and the second selection signals SELb1 to SELbY in the first direction D1 relative to the memory bank array 310. The first selection signals SELa1 to SELaY and the second selection signals SELb1 to SELbY are transmitted to the bit line sense amplifier regions in the corresponding segments, and activation of the local sense amplifier circuits associated with the corresponding segments may be determined.

[0104] Fig.12 According to an exemplary embodiment, Figure 5 A portion of a memory cell array.

[0105] Reference Figure 5 and Fig.12 , in the portion 390 ( Figure 5 ), a sub-array block SCB, a bit line sense amplifier region BLSAB, a sub-word line driver region SWB and a coupling region CONJ are set.

[0106] The sub-array block SCB includes a plurality of word lines WL1 to WL4 extending in the row direction (second direction D2) and a plurality of bit line pairs BL1 and BLB1 to BL2 and BLB2 extending in the column direction (first direction D1). The sub-array block SCB includes a plurality of memory cells MC arranged at intersections between the word lines WL1 to WL4 and the bit line pairs BL1 and BLB1 to the bit line pairs BL2 and BLB2.

[0107] Reference Fig.12 , the sub word line driver area SWB includes a plurality of sub word line drivers (SWD) 571, 572, 573, and 574 that drive the word lines WL1 to WL4, respectively. The sub word line drivers 571 and 572 may be disposed in the sub word line driver area SWB on the left side (in this example) relative to the sub array block SCB. In addition, the sub word line drivers 573 and 574 may be disposed in the sub word line driver area SWB on the right side (in this example) relative to the sub array block SCB.

[0108] The bit line sense amplifier region BLSAB includes a bit line sense amplifier BLSA 650 coupled to the bit line pair BL1 and BLB1 and a bit line sense amplifier BLSA 650a coupled to the bit line pair BL2 and BLB2, local sense amplifier circuits (LSA circuits) 700 and 700a, and a logic gate 750. The bit line sense amplifier (BLSA) 650 may sense and amplify a voltage difference between the bit line pair BL1 and BLB1 to provide the amplified voltage difference to the local I / O line pair LIO1 and LIOB1.

[0109] The local sense amplifier circuit 700 controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1 in response to the local enable signal LEN and the local control signal LCTL, and the local sense amplifier circuit 700a controls the connection between the local I / O line pair LIO2 and LIOB2 and the global I / O line pair GIO2 and GIOB2 in response to the corresponding local enable signal and the corresponding local control signal. The logic gate 750 performs a logic operation on the first selection signal SELa1 and the second selection signal SELb1 to provide the local enable signal LEN to the local sense amplifier circuit 700. The first selection signal SELa1 and the second selection signal SELb1 may be received from the sub-column decoder 551. The logic gate 750 may include an exclusive OR gate, and the logic operation may correspond to an exclusive OR operation. Therefore, if the first segment in the first row block is to be replaced by the first segment in the second row block, the local sense amplifier circuit associated with the first segment in the first row block may be deactivated, and the local sense amplifier circuit associated with the first segment in the second row block may be activated.

[0110] like Fig.12 As shown in FIG. 1 , the bit line sense amplifiers 650 and 650a may be alternately disposed at the upper and lower portions of the sub-array block SCB. The junction region CONJ is disposed adjacent to the bit line sense amplifier region BLSAB, the sub-word line driver region SWB, and the sub-array block SCB. A plurality of voltage generators (VG) 610, 620, 630, and 640 may be disposed in the junction region CONJ.

[0111] Fig.13 According to an exemplary embodiment, Fig.12 The local sense amplifier circuit in.

[0112] Reference Fig.13 , the local sense amplifier circuit 700 includes a local sense amplifier 710 , a local I / O line controller 720 , and an activation control circuit 730 .

[0113] The activation control circuit 730 performs an exclusive OR (XOR) operation on the local enable signal LEN and each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1 and the second connection control signal PMUXON2, and outputs the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3 and the fourth connection control signal PMUXON4.

[0114] Therefore, the logic levels of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3 and the fourth connection control signal PMUXON4 may be the same as or opposite to the logic levels of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1 and the second connection control signal PMUXON2, respectively, according to the logic level of the local enable signal LEN. The activation control circuit 730 includes a first gate 731, a second gate 732 and a third gate 733.

[0115] The local sense amplifier 710 amplifies the voltage difference between the local I / O line pair LIO1 and LIOB1 in response to the second local sense enable signal PLSAEN2 to provide the amplified voltage difference to the global I / O line pair GIO1 and GIOB1. The local I / O line controller 720 includes a first NMOS transistor 721, a second NMOS transistor 722, a third NMOS transistor 723, and a fourth NMOS transistor 724, and the local I / O line controller 720 controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1 in response to the third connection control signal PMUXON3 and the fourth connection control signal PMUXON4.

[0116] For example, when each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 is at a high level and the local enable signal LEN is at a high level, each of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 becomes a low level. Therefore, the local sense amplifier 710 is disabled, and the local I / O line controller 720 cuts off the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1.

[0117] For example, when each of the first local sensing enable signal PLSAEN1, the first connection control signal PMUXON1, and the second connection control signal PMUXON2 is at a high level and the local enable signal LEN is at a low level, each of the second local sensing enable signal PLSAEN2, the third connection control signal PMUXON3, and the fourth connection control signal PMUXON4 becomes a high level. Therefore, the local sense amplifier 710 is enabled, and the local I / O line controller 720 provides connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1.

[0118] Fig.14 The column decoder 271 is shown in Figure 2A A column repair operation is performed in a memory bank array in the embodiment of the present invention.

[0119] exist Fig.14 , it is assumed that row block RBLK1 (first row block) is the master, and row block RBLK3 (second row block) is mapped as a slave of row block RBLK1.

[0120] Reference Fig.14 , segment SEG2 (first segment) in row block RBLK1 includes defective memory cells. If column select line CSL1 is enabled, column decoder 271 replaces defective memory cells of segment SEG2 in row block RBLK1 with normal memory cells of row block RBLK3 as indicated by reference numeral 511. By enabling spare column select line SCSL1 as indicated by reference numeral 513, defective memory cells of segment SEG4 (second segment) in row block RBLK1 are replaced with spare memory cells of spare segment SSEG in row block RBLK1.

[0121] Fig.15 is a diagram showing a method according to an exemplary embodiment Figure 1 A block diagram of another example of a semiconductor memory device in FIG.

[0122] Reference Fig.15 , the semiconductor memory device 200b includes a control logic circuit 210, an address register 220, a memory body control logic 230, a refresh counter 245, a row address multiplexer 240, a column address latch 250, a row decoder 260, a column decoder 270, a memory cell array 300b, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, an ECC engine 280 and a data I / O buffer 295.

[0123] The memory cell array 300b includes a first memory bank array 310 to an eighth memory bank array 380 (or referred to as a first memory bank memory array 310 to an eighth memory bank memory array 380). The row decoder 260 includes a first memory bank row decoder 260a to an eighth memory bank row decoder 260h respectively coupled to the first memory bank array 310 to the eighth memory bank array 380, the column decoder 270 includes a first memory bank column decoder 270a to an eighth memory bank column decoder 270h respectively coupled to the first memory bank array 310 to the eighth memory bank array 380, and the sense amplifier unit 285 includes a first memory bank sense amplifier 285a to an eighth memory bank sense amplifier 285h respectively coupled to the first memory bank array 310 to the eighth memory bank array 380. The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form the first to eighth banks. Each of the first to eighth bank arrays 310 to 380 includes a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BL.

[0124] The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address RADDR, and a column address CADDR from the memory controller 100. The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230, provides the received row address RADDR to the row address multiplexer 240, and provides the received column address CADDR to the column address latch 250.

[0125] The bank control logic 230 generates a bank control signal in response to the bank address BANK_ADDR. A bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 260a to 260h is activated in response to the bank control signal, and a bank column decoder corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders 270a to 270h is activated in response to the bank control signal.

[0126] The row address multiplexer 240 receives the row address RADDR from the address register 220 and receives the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 selectively outputs one of the row address RADDR and the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 is applied to the first to eighth bank row decoders 260a to 260h.

[0127] The bank row decoder activated by the bank control logic 230 among the first bank row decoder 260a to the eighth bank row decoder 260h decodes the row address RA output from the row address multiplexer 240 and activates the word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line driving voltage to the word line corresponding to the row address RA.

[0128] The column address latch 250 receives the column address CADDR from the address register 220 and temporarily stores the received column address CADDR. In some embodiments, in the burst mode, the column address latch 250 generates a column address by increasing the received column address CADDR. The column address latch 250 applies the temporarily stored or generated column address to the first memory bank column decoder 270a to the eighth memory bank column decoder 270h.

[0129] The activated bank column decoder among the first to eighth bank column decoders 270a to 270h activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address CADDR through the I / O gating circuit 290. The I / O gating circuit 290 includes a circuit for gating input / output data, and also includes a read data latch for storing data output from the first to eighth bank arrays 310 to 380, and a write driver for writing data to the first to eighth bank arrays 310 to 380.

[0130] The codeword CW read from one of the first to eighth bank arrays 310 to 380 is sensed by a sense amplifier coupled to the one bank array from which data is to be read, and is stored in a read data latch. The codeword CW stored in the read data latch may be provided to the memory controller 100 via the data I / O buffer 295 after performing ECC decoding on the codeword CW by the ECC engine 280. Data DQ to be written to one of the first to eighth bank arrays 310 to 380 may be provided from the memory controller 100 to the data I / O buffer 295, and written to the one bank array by a write driver after performing ECC encoding on the data DQ by the ECC engine 280.

[0131] The data I / O buffer 295 may provide data DQ from the memory controller 100 to the ECC engine 280 in a write operation of the semiconductor memory device 200b based on the clock signal CLK, and may provide data DQ from the ECC engine 280 to the memory controller 100 in a read operation of the semiconductor memory device 200b.

[0132] In a write operation, the ECC engine 280 may generate a parity bit based on the data DQ from the data I / O buffer 295, and may provide a codeword CW including the data DQ and the parity bit to the I / O gating circuit 290. The I / O gating circuit 290 may write the codeword CW into one bank array. In addition, in a read operation, the ECC engine 280 may receive a codeword CW read from one bank array from the I / O gating circuit 290. The ECC engine 280 may perform ECC decoding on the data DQ based on the parity bit in the codeword CW to correct at least one error bit in the data DQ, thereby providing the corrected data to the data I / O buffer 295.

[0133] The control logic circuit 210 may control the operation of the semiconductor memory device 200b. For example, the control logic circuit 210 may generate a control signal for the semiconductor memory device 200b so as to perform a write operation or a read operation. The control logic circuit 210 includes a command decoder 211 and a mode register 212, wherein the command decoder 211 decodes the command CMD received from the memory controller 100 and the mode register 212 sets the operation mode of the semiconductor memory device 200b.

[0134] Each of the first to eighth bank arrays 310 to 380 may include a plurality of row blocks identified by row identification bits of the row address RADDR. Each of the first to eighth bank row decoders 260a to 260h may use Figure 5 The row decoder 261 in the memory bank can provide the row block information signal to the corresponding memory bank column decoder in the first memory bank column decoder 270a to the eighth memory bank column decoder 270h.

[0135] Each of the first to eighth bank column decoders 270a to 270h may adopt Figure 5 The column decoder 271 in the memory cell is configured to perform column repair in segments by simultaneously activating a first word line of the first row block and a second word line of a second row block mapped as a slave of the first row block based on a column address CADDR and a row block information signal if a first row block designated as a main body is accessed.

[0136] Fig.16 is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment.

[0137] Reference Figures 2A to 16 , a method for operating a semiconductor memory device 200 including a memory cell array is provided. The memory cell array includes a plurality of row blocks arranged in a first direction, each of the plurality of row blocks includes a plurality of dynamic memory cells coupled to a plurality of word lines and a plurality of bit lines, each of the plurality of row blocks is identified by a row block identification bit corresponding to a portion of a plurality of bits of a row address, and each of the plurality of row blocks includes a plurality of segments arranged in a second direction intersecting the first direction. In the method, a row decoder 261 activates a first word line of a first row block among the plurality of row blocks and a second word line of a second row block among the plurality of row blocks mapped as a slave of the first row block in response to the row address and the first fuse information (S110).

[0138] The column decoder 271 accesses a portion of the plurality of first memory cells coupled to the first word line and a portion of the plurality of second memory cells coupled to the second word line based on the column address, the row block information signal and the second fuse information (S120). The row block information signal indicates that the second word line is activated.

[0139] Fig.17A and Fig. 17B A method of operating a semiconductor memory device according to an exemplary embodiment is illustrated.

[0140] Reference Figures 2A to 16 , Fig.17A and Fig. 17B , the semiconductor memory device 200 receives an activation command and a first row address specifying a word line included in a first row block among a plurality of word lines (S210). The row block information circuit 400 in the address decoder 261 determines whether the first row block is a main body by referring to the first fuse information (S220). When the first row block is not a main body ("No" in S220), the row decoder 261 activates the first word line (S240), and the column decoder 271 receives a column address using a write command or a read command (S260).

[0141] When the first row block is the master ("Yes" in S220), the row decoder 261 activates the first word line and the second word line in the second row block mapped as a slave of the first row block (S230), and the column decoder 271 receives the column address using a write command or a read command (S250). The corresponding repair circuit in the column decoder 271 determines whether the column address CADDR matches the defective column address of the bit line bound to at least one defective cell (S270).

[0142] When the column address CADDR matches the defective column address ("Yes" in S270), the corresponding repair circuit in the column decoder 271 determines whether to use the first segment in the second row block by referring to the second fuse circuit FC2. When the first segment in the second row block is determined to be used ("Yes" in S280), the corresponding repair circuit in the column decoder 271 activates the column selection line CSL and the second selection signal, and the data of the memory cell in the first segment of the second row block is input / output (S310). When the first segment in the second row block is not used ("No" in S280), the corresponding repair circuit in the column decoder 271 activates the spare column selection line SCSL, and performs a column repair operation by using a spare memory cell coupled to the first word line and the spare bit line. (S320).

[0143] When the column address CADDR does not match the defective column address (No in S270 ), the column decoder 271 accesses a memory cell designated by the row address RADDR and the column address CADDR ( S330 ).

[0144] Fig.18 is a block diagram illustrating a semiconductor memory device according to an exemplary embodiment.

[0145] Reference Fig.18 , the semiconductor memory device 800 may include a first die group 810 and a second die group 820 .

[0146] The first die group 810 may include at least one buffer die 811. The second die group 820 may include a plurality of memory dies 820-1 to 820-s, which are stacked on the first die group 810 (or, the buffer die 811) and transmit data through a plurality of through silicon via (TSV) lines extending from the memory die 820-s to the first die group 810 via the intermediate memory dies 820-s-1 to 820-1.

[0147] Each of the memory dies 820-1 to 820-s may include a cell core 822 including a memory cell array and an address decoder 824. The memory cell array may include a plurality of memory bank arrays, and each memory bank array may be divided into a plurality of row blocks. The row decoder 824 may use Figure 5 The row decoder 261 and the column decoder 271 in the embodiment of the present invention can perform column repair in units of segments.

[0148] The buffer die 811 may include an ECC engine 812 that corrects a transmission error using a transmission parity bit and generates error-corrected data when a transmission error is detected from transmission data received through the TSV line. The ECC engine 812 may be referred to as a "via ECC engine."

[0149] The semiconductor memory device 800 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines. The TSV lines may also be referred to as "through electrodes."

[0150] The TSV line group 832 formed at one memory die 820-s may include a plurality of TSV lines L1 to Ls, and the parity TSV line group 834 may include a plurality of TSV lines L10 to Lt. The TSV lines L1 to Ls of the data TSV line group 832 and the parity TSV lines L10 to Lt of the parity TSV line group 834 may be connected to micro bumps MCBs formed respectively between the memory dies 820-1 to 820-s.

[0151] Each of the memory dies 820 - 1 through 820 - s may include a DRAM cell, each DRAM cell including at least one access transistor and one storage capacitor.

[0152] The semiconductor memory device 800 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with a memory controller through a data bus B10. The buffer die 810 may be connected to the memory controller through the data bus B10.

[0153] The first type ECC engine 822, denoted as a unit core ECC engine, may output transmission parity bits and transmission data through the parity TSV line group 834 and the data TSV line group 832, respectively. The output transmission data may be data in which errors are corrected by the first type ECC engine 822.

[0154] The ECC engine 812, represented as a via ECC engine, may determine whether a transmission error occurs in the transmission data received through the data TSV line group 832 based on the transmission parity bit received through the parity TSV line group 834. When a transmission error is detected, the ECC engine 812 may use the transmission parity bit to correct the transmission error in the transmission data. When the transmission error is uncorrectable, the ECC engine 812 may output information indicating that an uncorrectable data error has occurred.

[0155] Fig.19 is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment.

[0156] Reference Fig.19 , the semiconductor package 900 may include one or more stacked memory devices 910 and a memory controller (CON) 920. The stacked memory device 910 and the memory controller 920 may be mounted on an intermediate layer 930, and the intermediate layer 930 on which the stacked memory device 910 and the memory controller 920 are mounted may be mounted on a package substrate 940. The memory controller 920 may be configured as Figure 1 The memory controller 100 in FIG.

[0157] Each stacked memory device 910 may be implemented in various forms, and may be a memory device in the form of a high bandwidth memory (HBM) in which a plurality of layers are stacked. Thus, each stacked memory device 910 may include a buffer die and a plurality of memory dies. Each stacked memory device 910 may be implemented in various forms, and may be a memory device in the form of a high bandwidth memory (HBM) in which a plurality of layers are stacked. Fig.18 Therefore, each stacked memory device 910 can perform column repair in units of segments.

[0158] As described above, the stacked memory device 910 may be mounted on the middle layer 930, and the memory controller 920 may communicate with the stacked memory device 910. For example, each of the stacked memory device 910 and the memory controller 920 may include a physical area, and communication may be performed between the stacked memory device 910 and the memory controller 920 through the physical area. Meanwhile, when each stacked memory device 910 includes a direct access area, a test signal may be provided to each stacked memory device 910 through a conductive device (e.g., solder ball 950) mounted under the package substrate 940 and the direct access area.

[0159] Aspects of the inventive concept may be applied to a system using a semiconductor memory device.

[0160] The foregoing is an illustration of exemplary embodiments and is not to be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are feasible in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A semiconductor memory device, comprising: A memory cell array comprising a plurality of row blocks arranged in a first direction, wherein each of the plurality of row blocks comprises a plurality of dynamic memory cells coupled to word lines and bit lines, each of the plurality of row blocks comprises a plurality of segments arranged in a second direction intersecting the first direction, the segments in different row blocks forming a plurality of column blocks in the second direction; The row decoder is configured as: Receiving row address; activating a first word line of a first row block of the plurality of row blocks in response to a row address, wherein the first row block is identified using at least one block address bit of the row address; determining whether the first row block is a primary block based on first fuse information, the first fuse information indicating that the first row block is a primary block; In response to determining that the first row block is a master block, determining whether a second row block of the plurality of row blocks is mapped as a slave of the master block; In response to determining that a second row block of the plurality of row blocks is mapped as a slave of the master block, activating a second word line of the second row block of the plurality of row blocks, and In response to activating the second word line, outputting a row block information signal, the row block information signal indicating that the second word line is activated; and The column decoder is configured as: receiving a column address; and A portion of the plurality of first memory cells coupled to a first word line of a first row block among the plurality of dynamic memory cells and / or a portion of the plurality of second memory cells coupled to a second word line of a second row block among the plurality of dynamic memory cells are accessed based on a column address, a row block information signal, and second fuse information indicating a first segment among the plurality of segments that is disposed at an intersection of a main block and a first column block associated with the column address.

2. The semiconductor memory device according to claim 1, in, The plurality of segments include a plurality of normal segments and at least one spare segment, each of the plurality of normal segments includes a plurality of normal memory cells, and the at least one spare segment includes a plurality of spare memory cells, wherein the row address is received using the activate command, and The column address is received using a write command or a read command.

3. The semiconductor memory device according to claim 2, in, The portion of the plurality of second memory cells coupled to the second word line corresponds to a portion of a plurality of normal memory cells coupled to the second word line in a second row block, and the portion of the plurality of normal memory cells is disposed in a second segment at an intersection of a second row block and a first column block among the plurality of segments.

4. The semiconductor memory device according to claim 2, in, The portion of the plurality of first memory cells coupled to the first word line corresponds to a portion of a plurality of spare memory cells of a first row block.

5. The semiconductor memory device according to claim 3, in, The column decoder is configured to: select a second segment in a second row block for replacing the first segment of the first row block based on the second fuse information, and The first segment of the first row of blocks includes at least one defective cell.

6. The semiconductor memory device according to claim 5, in, The column decoder is configured to replace the second segment in the second row block with a third segment disposed at an intersection of a third row block different from the second row block and the first column block, and Among them, the third row of blocks is mapped as a slave to the second row of blocks.

7. The semiconductor memory device according to claim 1, in, The row decoder includes a plurality of row block fuse circuits, each row block fuse circuit of the plurality of row block fuse circuits being associated with a corresponding row block of the plurality of row blocks, and Wherein, each row block fuse circuit of the plurality of row block fuse circuits comprises: a row block information table storage device configured to store first fuse information including a master bit, row block information of a corresponding row block, and slave row block information, wherein the master bit indicates whether the corresponding row block is a master row block, and the slave row block information is associated with information of the slave row block mapped to the master row block; and The signal generator is configured to output a row block information signal to the column decoder based at least on the row block information.

8. The semiconductor memory device according to claim 7, in, Each row block fuse circuit of the plurality of row block fuse circuits further comprises: a defect address table storage device configured to store a defective row address of at least one defective cell included in a corresponding row block; a row address comparator configured to compare the row address with the defective row address to output a row match signal indicating whether the defective row address matches a corresponding bit of the row address; and a row block comparator configured to compare at least one block address bit of the row address with row block address information associated with the corresponding row block to output a row block match signal indicating whether the at least one block address bit matches the row block address information, and The signal generator is configured to output a row block information signal in response to the row matching signal, the row block matching signal and the slave row block information.

9. The semiconductor memory device according to claim 1, in, The column decoder includes: a plurality of sub-column decoders respectively connected to the plurality of segments; and a plurality of repair circuits, respectively connected to the plurality of sub-column decoders, and Wherein, each of the plurality of repair circuits is configured to apply a first repair signal, a second repair signal, a first internal selection signal, and a second internal selection signal to a corresponding sub-column decoder among the plurality of sub-column decoders, the first internal selection signal and the second internal selection signal being associated with the selection of each segment among the plurality of segments.

10. The semiconductor memory device according to claim 9, in, Each of the plurality of repair circuits comprises: A fuse circuit, comprising a plurality of fuse groups, wherein each of the plurality of fuse sets stores segment information associated with a selection of each of the plurality of segments; and The signal generator is configured to generate a first internal selection signal and a second internal selection signal based on the row block information signal and the segment information.

11. The semiconductor memory device according to claim 10, in, Each of the plurality of repair circuits further comprises: a defect address table storage device configured to store defect column address information of at least one defective cell of a corresponding segment among the plurality of segments; a column address comparator configured to compare the column address with the defective column address information to output a column match signal indicating whether the column address matches the defective column address information; and The repair signal generator is configured to generate a first repair signal and a second repair signal based on the column matching signal and the segment information.

12. The semiconductor memory device according to claim 11, in, Each of the plurality of sub-column decoders comprises: a plurality of normal column selection line drivers respectively connected to the normal segment of each of the plurality of row blocks; and At least one spare column selection line driver is respectively connected to at least one spare segment in the plurality of row blocks.

13. The semiconductor memory device according to claim 12, in, Each of the multiple normal column selection line drivers is configured to select a column selection line based on a column address, a column matching signal, a first repair signal, a second repair signal, a first internal selection signal, and a second internal selection, and is configured to determine the logic levels of the first selection signal and the second selection signal associated with the selection of a corresponding segment among the multiple segments.

14. The semiconductor memory device according to claim 13, in, In response to a column match signal indicating that the column address matches the defective column address information and segment information indicating that the corresponding segment will be replaced by a second segment in a second row block, each of the plurality of normal column selection line drivers deactivates the first selection signal and activates the second selection signal.

15. The semiconductor memory device according to claim 13, in, The plurality of segments are arranged in a first direction and a second direction of the substrate, and Wherein, the memory cell array further comprises: a plurality of sub-word line driver regions disposed between the plurality of segments in a first direction; a plurality of bit line sense amplifier regions disposed between the plurality of segments in a second direction; a plurality of local sense amplifier circuits disposed in the plurality of bit line sense amplifier regions; and A logic gate is configured to perform a logic operation on a first selection signal and a second selection signal to provide a local enable signal to a corresponding local sense amplifier circuit among the plurality of local sense amplifier circuits, wherein activation of the first selection signal is associated with selection of a segment of a first row block and activation of the second selection signal is associated with selection of a segment of a second row block.

16. The semiconductor memory device according to claim 15, in, The memory cell array includes a plurality of memory bank arrays, and Each of the plurality of memory arrays includes the plurality of row blocks.

17. A semiconductor memory device comprising: A memory cell array comprising a plurality of row blocks arranged in a first direction, wherein each of the plurality of row blocks comprises a plurality of dynamic memory cells coupled to word lines and bit lines, each of the plurality of row blocks comprises a plurality of segments arranged in a second direction intersecting the first direction, the segments in different row blocks forming a plurality of column blocks in the second direction; The row decoder is configured as: Receiving row address; activating a first word line of a first row block of the plurality of row blocks in response to a row address, wherein the first row block is identified using at least one block address bit of the row address; determining whether the first row block is a primary block based on first fuse information, the first fuse information indicating that the first row block is a primary block; In response to determining that the first row block is a master block, determining whether a second row block of the plurality of row blocks is mapped as a slave of the master block; In response to determining that a second row block of the plurality of row blocks is mapped as a slave of the master block, activating a second word line of a second row block of the plurality of row blocks; and In response to activating the second word line, outputting a row block information signal, the row block information signal indicating that the second word line is activated; The column decoder is configured as: receiving a column address; and accessing a portion of a plurality of first memory cells coupled to a first word line among the plurality of dynamic memory cells and / or a portion of a plurality of second memory cells coupled to a second word line among the plurality of dynamic memory cells based on a column address, a row block information signal and second fuse information, wherein the second fuse information indicates a first segment among the plurality of segments disposed at an intersection of a main block and a first column block among the plurality of column blocks associated with the column address; and The peripheral circuit is configured to control the row decoder and the column decoder based on a command and an address received from the outside, the address including a row address and a column address.

18. The semiconductor memory device according to claim 17, in, Peripheral circuits include an error correction code engine, and The error correction code engine is configured to perform error correction code encoding on data to be stored in the memory cell array, and is configured to perform error correction code decoding on data read from the memory cell array.

19. A method of operating a semiconductor memory device, in, A semiconductor memory device includes a memory cell array, the memory cell array includes a plurality of row blocks arranged in a first direction, wherein each of the plurality of row blocks includes a plurality of dynamic memory cells coupled to word lines and bit lines, each of the plurality of row blocks includes a plurality of segments arranged in a second direction intersecting the first direction, the segments in different row blocks forming a plurality of column blocks in the second direction, The method comprises: activating, by a row decoder in response to a row address, a first word line of a first row block of the plurality of row blocks, wherein the first row block is identified using at least one block address bit of the row address; determining, by a row decoder, whether the first row block is a primary block based on first fuse information, wherein the first fuse information indicates that the first row block is a primary block; determining, by the row decoder, in response to determining that the first row block is a master block, whether a second row block of the plurality of row blocks is mapped as a slave of the master block; In response to determining that a second row block of the plurality of row blocks is mapped as a slave of the master block, activating a second word line of a second row block of the plurality of row blocks; In response to activating the second word line, generating a row block information signal, the row block information signal indicating that the second word line is activated; and A portion of the plurality of first memory cells coupled to a first word line among the plurality of dynamic memory cells and / or a portion of the plurality of second memory cells coupled to a second word line among the plurality of dynamic memory cells are accessed by a column decoder based on a column address, a row block information signal, and second fuse information indicating a first segment among the plurality of segments that is disposed at an intersection of a main block and a first column block associated with the column address.

20. The method according to claim 19, in, The plurality of segments include a plurality of normal segments and at least one spare segment, each of the plurality of normal segments includes a plurality of normal memory cells, and the at least one spare segment includes a plurality of spare memory cells, Among them, the row address is received using the activation command, Among them, a column address is received using a write command or a read command. wherein a first segment of a first word line coupled to a first row block includes at least one defective cell, wherein the portion of the plurality of second memory cells coupled to the second word line corresponds to a portion of the plurality of normal memory cells coupled to the second word line in the second row block, and The portion of the plurality of first memory cells coupled to the first word line corresponds to a portion of the plurality of spare memory cells of a spare segment among the at least one spare segment of the first row block.

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