Method for managing the startup of a phase-locked loop and corresponding integrated circuit

Abstract

Various embodiments of the present disclosure relate to a method for managing the startup of a phase-locked loop and a corresponding integrated circuit. The operation of the phase-locked loop includes a startup phase, during which a reference signal with a 50% duty cycle is applied to a phase comparator of the loop. A first frequency divider of the output signal of the loop's voltage-controlled oscillator is reset at each first-type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first frequency divider and generates a control pulse at each second-type signal edge of the reference signal, which causes the control voltage of the oscillator to increase.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French application No. 1907661, filed on July 9, 2019, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] The embodiments and examples relate to integrated circuits, and in particular to phase-locked loops, which are generally known to those skilled in the art, and more particularly to managing the startup of phase-locked loops. Background Art

[0004] Phase-locked loops are often used in digital systems, such as programmable cores or microprocessors, which require a high internal operating frequency, for example, of the order of several hundred megahertz.

[0005] The role of the phase-locked loop is therefore in particular to deliver an internal clock signal with a high operating frequency to these digital systems.

[0006] However, due to the presence of the feedback loop and the capacitive network required to stabilize the phase-locked loop, the startup time, i.e. the duration required for the loop to stabilize (i.e. where the reference signal and the oscillator output signal are close to being synchronized with each other), can be very long, typically greater than 100 μs.

[0007] Furthermore, during this startup phase, the output signal of the loop oscillator experiences a frequency overshoot relative to its final nominal value, which may also reach 25% of the final nominal value.

[0008] This frequency overshoot at startup means that the digital circuit of the PLL must be designed to withstand this higher frequency. Consequently, the speed of the circuit must be increased, which in particular results in an increase in leakage current and / or dynamic consumption.

[0009] Therefore, it is necessary to limit the startup time of the phase-locked loop and the amplitude of the frequency overshoot. Summary of the Invention

[0010] According to one aspect, a method for managing the operation of a phase-locked loop is presented.

[0011] Operation of the phase-locked loop includes a startup phase or step involving: delivering a reference signal having a 50% duty cycle to a phase comparator of the loop; resetting a first frequency divider of an output signal of a voltage-controlled oscillator of the loop at each signal edge of a first type of the reference signal (e.g., at each rising signal edge); and delivering a control pulse via the phase comparator receiving the reference signal and a feedback signal from the first frequency divider, during which control pulse a control voltage of the oscillator is increased at each signal edge of a second type of the reference signal (e.g., at each falling signal edge).

[0012] Combining these features, in particular providing a reference signal with a 50% duty cycle and resetting the frequency divider of the loop at (for example) each rising signal edge of the reference signal, allows a significant reduction of the startup time and frequency overshoot of the loop.

[0013] Thus, by way of indication, for a frequency of the reference signal equal to 2 MHz, 4 MHz, 8 MHz or 16 MHz and a nominal frequency of the output signal of the oscillator equal to 832 MHz, a start-up time of the order of thirty microseconds is achieved, compared to a start-up time of 70 microseconds to more than 100 microseconds for conventional phase-locked loops.

[0014] Similarly, a frequency overshoot of about a few percent (eg, about 2%) is achieved on the output signal of the oscillator, compared to a frequency overshoot of up to 25% for a conventional phase-locked loop.

[0015] In the presence of an initial reference signal that does not have a duty cycle of 50%, the delivery of the reference signal advantageously comprises dividing the initial reference signal by two so as to obtain a reference signal with a duty cycle of 50%, and in this case the feedback signal is not the output signal directly from the first frequency divider of the loop, but the output signal of the first frequency divider divided by two.

[0016] This allows any initial reference signal to be used, regardless of its duty cycle.

[0017] Although the control pulses delivered by the phase comparator can be used in the charge pump circuit, it is particularly advantageous to "short-circuit" this charge pump circuit during the start-up phase to apply the pre-charge current directly to the resistive-capacitive filter connected to the input of the oscillator.

[0018] In other words, according to this embodiment, during the start-up phase, increasing the control voltage of the oscillator comprises applying a pre-charge current to a resistive-capacitive filter connected to the input of the oscillator.

[0019] This further helps to reduce the startup time of the loop and makes it less dependent on the current constraint of the charge pump, which is linked to the stability of the loop.

[0020] According to one embodiment, the resistive-capacitive filter comprises: a first branch connected between the above-mentioned input of the oscillator and ground and comprising a resistive network connected in series with a first capacitor having a first capacitance, wherein the resistive network comprises: a first resistor connected between the above-mentioned input of the oscillator and an intermediate node and having a first resistance; and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between the above-mentioned input of the oscillator and ground and comprising a second capacitor having a second capacitance.

[0021] The first capacitance is then advantageously equal to A times the second capacitance, and the first resistance is equal to A times the second resistance.

[0022] A precharge current is then advantageously applied to the aforementioned intermediate node.

[0023] A uniform increase of the two capacitive voltages across the terminals of the two capacitors and thus a stable increase of the capacitive voltage delivered at the oscillator input is achieved.

[0024] According to one embodiment, the startup phase ends when the duration of the control pulse is less than a few percent (eg 2%) of the product of the period of the output signal of the oscillator and the frequency division ratio of the first frequency divider.

[0025] According to one embodiment, when the startup phase is over, the output of the phase comparator is connected to a charge pump circuit, and the output of the charge pump circuit is connected to the input of the voltage controlled oscillator.

[0026] In other words, during the startup phase, when the charge pump circuit has been disconnected and the pre-charge current has been applied to the resistive-capacitive filter, the charge pump circuit will be reconnected to the phase comparator at the end of the startup phase.

[0027] Of course, if the charge pump circuit remains connected to the phase comparator during the startup phase, this connection is not modified at the end of the startup phase.

[0028] According to one embodiment, when, during the startup phase, the initial reference signal and the output signal of the first frequency divider have already been divided by two, these divisions by two are not continued at the end of the startup phase.

[0029] In other words, when the start-up phase has ended, the initial reference signal is delivered to the phase comparator, and the feedback signal delivered to the phase comparator is the output signal of the first frequency divider.

[0030] Furthermore, when the startup phase has ended, a final reset of the first frequency divider can advantageously be performed after the end of the startup phase on a first signal edge of the first type (eg a first rising signal edge) of the reference signal.

[0031] This makes it possible to synchronize the reference signal and the feedback signal from the first frequency divider.

[0032] According to another aspect, an integrated circuit is provided, comprising a phase-locked loop comprising: a phase comparator; a voltage-controlled oscillator; a first frequency divider connected between the output of the oscillator and the first input of the phase comparator; a delivery circuit configured to deliver a reference signal having a 50% duty cycle at the second input of the phase comparator during a startup phase of the loop; a reset circuit configured to reset the first frequency divider at each signal edge of a first type of the reference signal during the above-mentioned startup phase, the phase comparator being configured to deliver a control pulse at each signal edge of a second type of the reference signal during the above-mentioned startup phase; and a control circuit configured to increase the control voltage of the oscillator during the above-mentioned control pulse.

[0033] According to one embodiment, the delivery circuit includes: an input for receiving an initial reference signal; a divide-by-two frequency divider connected to the input; and an output configured to deliver the divided-by-two initial reference signal as the reference signal, and wherein the integrated circuit further includes another divide-by-two frequency divider connected between the output of the first frequency divider and the first input of the phase comparator.

[0034] According to one embodiment, the control circuit comprises a current source which can be activated at the aforementioned pulse and is configured to apply, after being activated, a pre-charge current to the resistive-capacitive filter connected at the input of the oscillator.

[0035] According to one embodiment, a resistive-capacitive filter comprises: a first branch connected between the above-mentioned input of the oscillator and ground and comprising a resistive network connected in series with a first capacitor having a first capacitance, the resistive network comprising: a first resistor connected between the above-mentioned input of the oscillator and an intermediate node and having a first resistance; and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between the above-mentioned input of the oscillator and ground and comprising a second capacitor having a second capacitance, wherein the first capacitance is equal to A times the second capacitance and the first resistance is equal to A times the second resistance, and wherein a current source is connected to the above-mentioned intermediate node.

[0036] According to one embodiment, the integrated circuit further comprises a detection circuit configured to detect the end of the startup phase.

[0037] According to one embodiment, the detection circuit is configured to detect the duration of the control pulse and / or the type of the pulse signal delivered by the phase comparator.

[0038] Thus, the detection circuit may be configured to deliver a signal indicating the end of the start-up phase when the duration of the control pulse is less than a few percent of the product of the period of the output signal of the oscillator and the division ratio of the first frequency divider.

[0039] As a variant, the detection circuit can be configured to deliver a signal indicating the end of the start-up phase when detecting a first pulse of a pulse signal delivered by the phase comparator requesting a reduction in the control voltage of the voltage-controlled oscillator.

[0040] According to one embodiment, the integrated circuit is configured to connect the output of the phase comparator to a charge pump circuit having an output connected to an input of the voltage controlled oscillator when the startup phase is over.

[0041] According to one embodiment, when the startup phase has ended, the delivery circuit is configured to deliver the initial reference signal to the phase comparator, and the integrated circuit includes a control circuit configured to deactivate the aforementioned further divide-by-two frequency divider so that the feedback signal delivered to the phase comparator is the output signal of the first frequency divider.

[0042] According to one embodiment, the reset circuit is configured to perform a final reset of the first frequency divider on a first signal edge of the first type of the reference signal after the end of the startup phase when the startup phase has ended. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Other advantages and features of the present invention will become apparent upon examination of the detailed description of purely non-limiting examples and embodiments of the invention and the accompanying drawings, in which:

[0044] Figure 1 A diagram showing a phase locked loop circuit;

[0045] Figure 2 is a diagram of the filter circuit; and

[0046] Figure 3 is a timing diagram illustrating an embodiment of a method for managing the operation of a loop PLL. DETAILED DESCRIPTION

[0047] exist Figure 1 In the embodiment, reference symbol PLL denotes a phase-locked loop circuit, which includes an input terminal BE for receiving an initial reference signal CKin and includes a circuit for delivering an output signal CK generated by a voltage controlled oscillator VCO. VCO The output terminal BS.

[0048] As an example, the frequency of the initial reference signal CKin may be equal to 16 MHz, and the output signal CK VCO The frequency can be equal to 832MHz.

[0049] Furthermore, the output terminal BS of the phase-locked loop PLL is connected to the input of a first frequency divider DV1 (eg a fractional frequency divider) configured to divide the signal CK delivered by the local oscillator VCO by a fractional frequency divider. VCO Perform N frequency division.

[0050] The frequency division ratio N is equal to the signal CK VCO The ratio between the frequency of the initial reference signal CKin and the frequency of the initial reference signal CKin.

[0051] By way of example, in this case the division ratio is equal to 800 / 16, ie 52. The divide-by-N frequency divider has a conventional structure known per se and is usually formed by a counter which can be reset by receiving a reset signal or pulse IMPRST on its reset input RST.

[0052] The output signal of the first frequency divider is based on CKfb.

[0053] The phase-locked loop PLL involves a startup phase or step, at the end of which the reference signal delivered at the input of the phase comparator PFD (of a conventional and known structure) of the loop is almost synchronized with the signal CKfb. Of course, when the reference signal and the signal CKfb are almost synchronized, the reference signal and the output signal CK VCO Almost synchronized.

[0054] In this example, the end of the startup phase occurs when the logic signal ENST has, for example, the logic value “1”.

[0055] It is now assumed that, in this example, the initial reference signal CKin has any duty cycle, in particular, a duty cycle other than 50%.

[0056] To this end, the loop PLL comprises a delivery circuit MDV configured to deliver a reference signal CKin / 2 on a second input E2 of the phase comparator PFD, the reference signal CKin / 2 being a frequency division of the initial reference signal CKin by two.

[0057] To this end, the delivery circuit comprises, in this case, for example a divide-by-two frequency divider DV2A (which is actually a counter) which is connected to the input terminal BE and delivers the reference signal CKin / 2.

[0058] Furthermore, the delivery circuit MDV comprises a first multiplexer Mux1 which is controlled by the signal ENST and which receives on the one hand the reference signal CKin / 2 and the initial reference signal CKin.

[0059] During the start-up phase (ie when the logic signal ENST has the logic value “0”), the multiplexer Mux1 delivers an initial reference signal divided by two on the input E2 , which thereby forms the reference signal received on the second input E2 of the phase comparator PFD.

[0060] The feedback signal delivered on the first input E1 of the phase comparator PFD comes from a second multiplexer Mux2 which is also controlled by the signal ENST.

[0061] The output signal of the first frequency divider CKfb is delivered to a first input of the second multiplexer Mux2.

[0062] A second input of the second multiplexer Mux2 receives the signal CKfb / 2, which is delivered by a further divide-by-two frequency divider DV2B and thus results from the frequency division by two of the signal CKfb.

[0063] Thus, in this example, during the start-up phase of the loop PLL, the feedback signal delivered on the first input E1 of the phase comparator is the signal CKfb / 2, since the input E2 of the phase comparator receives the reference signal CKin / 2.

[0064] As is conventional, the phase comparator PFD, depending on the signals present at its two inputs, delivers a control pulse UP configured to increase the control voltage or command voltage at the input of the oscillator VCO or a control pulse DOWN configured to decrease this control voltage.

[0065] Furthermore, the loop PLL comprises a resistive-capacitive filter FLT having a node ND1 connected to the command or control input of the voltage-controlled oscillator VCO.

[0066] Furthermore, the phase-locked loop PLL comprises a charge pump circuit CHP of a conventional and per se known structure, configured to receive two control pulses UP and DOWN and to deliver a current to a resistive-capacitive filter FLT, thereby generating a control voltage Vcontrol that can be applied to the input of an oscillator.

[0067] That is, in this embodiment, the phase comparator PFD is connected to the input of the charge pump circuit CHP via a set of first switches SW1 which can be commanded by the logic signal ENST.

[0068] In another embodiment, the set of first switches SW1 may be replaced by a logic gate, one input of which is connected to a logic signal ENST, which enables the switches inside the charge pump circuit CHP to be opened.

[0069] Therefore, in this embodiment, when the phase-locked loop is in its startup phase (eg, ENST=0), the switch SW1 is open, thereby disconnecting the charge pump circuit CHP from the output of the phase comparator PFD.

[0070] like Figure 2 As illustrated in , in this case, the filter FLT comprises a first branch BR1 connected between the node ND1 and the ground GND, and comprises a second branch BR2 also connected between the node ND1 and the ground GND.

[0071] The first branch comprises a resistive network R connected in series with a first capacitor C1 .

[0072] The resistive network R includes a first resistor R1 connected between the node ND1 and the intermediate node ND2 , and includes a second resistor R2 connected between the intermediate node ND2 and the first capacitor C1 .

[0073] For simplicity, C1 , C2 , R1 , and R2 will also represent the capacitance of the first capacitor C1 , the capacitance of the second capacitor C2 , the resistance of the first resistor R1 , and the resistance of the second resistor R2 , respectively.

[0074] In this example, the capacitance C1 of the first capacitor C1 is equal to the capacitance C2 of the second capacitor C2 times a constant A. As an indication, the value of A is approximately 10.

[0075] The resistance R1 of the first resistor R1 is equal to a value A times the resistance R2 of the second resistor R2 for its part.

[0076] Therefore, the product R2C1 is equal to the product R1C2, that is, equal to A times the product R2C2.

[0077] Additionally, during the startup phase, a precharge current Ip will be applied to the intermediate node ND2.

[0078] Additionally, since C1 is equal to aC2, it will take the same time to precharge C1 and C2, so this time is equal to the filter constant divided by A.

[0079] like Figure 1 As illustrated in FIG, the pre-charge current Ip comes from a current source SC which can be activated by a second switch SW2 which is commanded by the output of a logic AND gate (reference PL).

[0080] This gate PL receives, at a first input, a control pulse IMP of a signal UP and, at a second input, a signal ENST inverted by an inverter INV.

[0081] The signal ENST is at "0" during the startup phase and at "1" after the startup phase.

[0082] Therefore, during the startup phase, the second switch SW2 is commanded by the pulse of the signal UP, whereas after the startup phase, the second switch SW2 is always opened.

[0083] More precisely, during the startup phase, if the signal UP is at a high level (representing a pulse IMP), the switch SW2 is closed and the current source delivers the pre-charge current Ip on the intermediate node ND2 .

[0084] And this situation lasts as long as the signal UP is at 1, ie as long as the control pulse IMP is present.

[0085] In contrast, once the pulse IMP disappears (signal UP is at zero), the switch SW2 is turned off and no precharge current is delivered to the node ND2.

[0086] The capacitive filter FLT is thus charged during the pulses IMP, and these charging operations make it possible to increase the control voltage at the input of the oscillator VCO and thus to increase the frequency of the output signal of this oscillator.

[0087] Thus, the current source SC and the filter FLT form part of a control circuit which is configured to increase the control voltage of the oscillator during the above-mentioned control pulse IMP.

[0088] As described above, the first frequency divider DV1 is reset by applying a reset pulse IMPRST to the reset input RST of the frequency divider.

[0089] In the startup phase, the reset pulse IMPRST is obtained by the reset circuit MRST in response to each rising signal edge FM of the reference signal (in this case the signal CKin / 2).

[0090] Of course, the reset can be performed at every falling signal edge of the signal CKin / 2.

[0091] Furthermore, as will be seen in more detail below, once the startup phase has ended, the reset circuit MRST will deliver a final reset pulse on the first rising signal edge of the reference signal, which will now be the signal CKin after the end of the startup phase.

[0092] The reset circuit MRST can be easily generated by a logic circuit.

[0093] Furthermore, the integrated circuit IC incorporating the phase-locked loop PLL also comprises a detection circuit MDT configured so as to detect the end of the startup phase and thus deliver a logic value 1 to the signal ENST.

[0094] When the duration T of the control pulse IMP corresponding to the high state of the "up" signal is less than the nominal period T of the output signal of the oscillator VCO CKVCO When the product of the frequency division ratio N reaches a certain percentage, the startup phase is considered to have ended.

[0095] As an example, the threshold may be taken equal to 2%.

[0096] Therefore, according to a first possibility, in order to detect the end-of-start-up phase condition, the detection circuit MDT can be configured to detect the signal CK during the duration of the pulse IMP. VCO The number of signal edges is counted.

[0097] According to another possible embodiment, the detection circuit MDT may include a low-pass filter for receiving the signal UP, the time constant of the low-pass filter being linked to the threshold value of a few percent.

[0098] Depending on whether the output of this filter delivers a high signal or not, the detection circuit MDT will deliver a signal ENST of logical value “0” or logical value “1”.

[0099] As a variant, the end of the startup phase can also be considered to be reached when the first control pulse corresponding to the high state of the signal "DOWN" is detected. Figure 3 , in order to illustrate one embodiment of a method for managing the operation of the loop PLL illustrated in the previous figures.

[0100] Should Figure 3 In the form of a timing diagram.

[0101] Figure 3 The first row shows the initial reference signal CKin, which, as can be seen, has a duty cycle other than 50%.

[0102] The second row shows the reference signal CKin / 2, which is generated by dividing the frequency of the initial reference signal by two and which at this time has a duty cycle equal to 50%.

[0103] As mentioned above, this signal CKin / 2 is the reference signal delivered on the second input E2 of the phase comparator PFD.

[0104] In addition, it can be seen that at each rising signal edge of the reference signal CKin / 2, the reset circuit MRST emits a reset pulse IMPRST, which resets the first frequency divider DV1, that is, resets the counter forming the first frequency divider to 0.

[0105] Furthermore, at each falling signal edge of the reference signal CKin / 2, the phase comparator PFD compares the phase of the reference signal CKin / 2 with the phase of the feedback signal CKFB / 2 and thereby delivers a control pulse IMP of the signal UP.

[0106] When the pulse IMP is present, it makes it possible to apply the precharge current Ip to the intermediate node ND2 of the filter FLT.

[0107] As the startup phase progresses, it can be noted that due to the signal CK VCO The output frequency of the signal UP increases and therefore the duration of the pulses IMP of the signal UP decreases.

[0108] In addition, as mentioned above, when the duration T of the pulse IMP is less than or equal to the frequency division ratio N and the period TCK of the oscillator signal VCO When the product of 0 and 1 becomes 2%, the control signal ENST becomes 1, which marks the end of the startup phase.

[0109] At this time, the first multiplexer Mux1 delivers the initial reference signal CKin to the second input E2 of the phase comparator, and the initial reference signal CKin becomes the reference signal.

[0110] Furthermore, the feedback signal delivered on the first input E1 of the phase comparator PFD becomes the signal CKfb directly coming from the frequency divider (ie without being divided by two beforehand).

[0111] At the same time, the switch SW1 is closed, connecting the two outputs of the phase comparator PFD (delivering two signals UP and DOWN respectively) to the input of the charge pump circuit in order to resume normal operation of the phase-locked loop.

[0112] The switch SW2 is turned off to interrupt the application of the precharge current Ip.

[0113] At this time, the current used to adjust the control voltage Vcontrol of the local oscillator VCO is the current Icp delivered by the charge pump circuit.

[0114] That is, to speed up the signal CK VCO In synchronization with the reference signal CKin, as described above, after the end of the startup phase, the reset circuit MRST performs a final reset of the first frequency divider DV1 at the first rising signal edge of the reference signal CKin.

[0115] The phase locked loop will then be ready to deliver its output signal after a few cycles.

[0116] This output signal can serve, for example, as a clock signal for a microprocessor.

Claims

1. A method for starting a phase-locked loop (PLL) circuit, comprising: delivering a reference signal to a phase comparator of the PLL circuit, the reference signal having a duty cycle equal to 50%; resetting a first frequency divider of an output signal of a voltage controlled oscillator of the PLL circuit at each first type signal edge of the reference signal; outputting a control pulse by the phase comparator at each second-type signal edge of the reference signal in response to the reference signal and a feedback signal obtained from the output of the first frequency divider; as well as In response to each control pulse, increasing a control voltage of the voltage controlled oscillator; wherein increasing the control voltage of the voltage controlled oscillator comprises: applying a precharge current to a resistive capacitive filter in response to the control pulse, the resistive capacitive filter being connected at an input of the voltage controlled oscillator; The resistive capacitive filter comprises: a first branch connected between the input of the voltage controlled oscillator and ground and comprising a resistive network connected in series with a first capacitor having a first capacitance, the resistive network comprising: a first resistor connected between the input of the voltage controlled oscillator and an intermediate node and having a first resistance; and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between the input of the voltage controlled oscillator and ground and comprising a second capacitor having a second capacitance; wherein the first capacitance is equal to A times the value of the second capacitance, and wherein the first resistance is equal to A times the value of the second resistance; and The precharge current is applied to the intermediate node. 2 . The startup method of claim 1 , wherein delivering the reference signal comprises dividing an initial reference signal by two, and wherein the feedback signal is the output of the first frequency divider divided by two.

3. The startup method according to claim 1, further comprising: When the duration of the control pulse is less than several percent of the product of the period of the output signal of the voltage controlled oscillator and the frequency division ratio of the first frequency divider, the startup is terminated.

4. The startup method according to claim 3, further comprising: In response to terminating startup, the output of the phase comparator is connected to a charge pump circuit configured to generate the control voltage of the voltage controlled oscillator. 5 . The startup method of claim 4 , further comprising performing a final reset of the first frequency divider on the first type signal edge of the reference signal after terminating startup.

6. The startup method of claim 3 , wherein delivering the reference signal comprises dividing an initial reference signal by two, and wherein the feedback signal is the output of the first frequency divider divided by two, and the method further comprises: In response to terminating startup, the initial reference signal is delivered to the phase comparator, and the output signal of the first frequency divider is delivered to the phase comparator as the feedback signal. 7 . The startup method of claim 6 , further comprising performing a final reset of the first frequency divider on the first type signal edge of the reference signal after terminating startup.

8. A phase-locked loop (PLL) circuit, comprising: Phase comparator; voltage controlled oscillator; a first frequency divider connected between the output of the voltage controlled oscillator and the first input of the phase comparator; a delivery circuit configured to: deliver a reference signal having a 50% duty cycle to a second input of the phase comparator during a startup phase of the PLL circuit; a reset circuit configured to: reset the first frequency divider at each first-type signal edge of the reference signal during the startup phase; wherein the phase comparator is configured to: deliver a control pulse at each second-type signal edge of the reference signal during the startup phase; as well as a control circuit configured to: increase a control voltage of the voltage controlled oscillator during the control pulse; The control circuit comprises: a current source configured to generate a precharge current that is selectively applied to a resistive capacitive filter connected at an input of the voltage controlled oscillator in response to the control pulse; The resistive capacitive filter comprises: a first branch connected between the input of the voltage controlled oscillator and ground and comprising a resistive network connected in series with a first capacitor having a first capacitance, the resistive network comprising: a first resistor connected between the input of the voltage controlled oscillator and an intermediate node and having a first resistance; and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between the input of the voltage controlled oscillator and ground and comprising a second capacitor having a second capacitance; wherein the first capacitance is equal to A times the value of the second capacitance, and wherein the first resistance is equal to A times the value of the second resistance; and The current source is connected to the intermediate node.

9. The PLL circuit of claim 8, wherein the delivery circuit comprises: an input configured to receive an initial reference signal; a divide-by-two frequency divider connected to the input; as well as output, configured to deliver the initial reference signal divided by two as a reference signal during the startup phase, and The PLL circuit further comprises a further divide-by-two frequency divider which is active during the start-up phase and is connected between the output of the first frequency divider and the first input of the phase comparator. 10 . The PLL circuit of claim 8 , further comprising a detection circuit configured to detect an end of the startup phase.

11. The PLL circuit of claim 10, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator to detect the end of the startup phase.

12. The PLL circuit according to claim 11 , wherein the detection circuit is further configured to generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a certain percentage of the product of the period of the output signal of the voltage controlled oscillator and the division ratio of the first frequency divider.

13. The PLL circuit of claim 10, further comprising a switching circuit configured to connect the output of the phase comparator to a charge pump circuit that generates the control voltage of the voltage controlled oscillator when the startup phase has ended.

14. The PLL circuit of claim 13, wherein the reset circuit is configured to perform a final reset of the first frequency divider on a signal edge of the first type of the reference signal after the end of the startup phase when the startup phase has ended.

15. The PLL circuit of claim 10 , wherein the delivery circuit comprises: an input configured to receive an initial reference signal; a divide-by-two frequency divider connected to the input; as well as output, configured to deliver the initial reference signal divided by two as a reference signal during the startup phase, and The PLL circuit further includes another divide-by-two frequency divider, the another divide-by-two frequency divider being active during the startup phase and connected between an output of the first frequency divider and the first input of the phase comparator; wherein the delivery circuit is configured to: deliver the initial reference signal to the phase comparator when the startup phase has ended; A control circuit is configured to deactivate the further divide-by-two frequency divider so that the feedback signal delivered to the phase comparator is the output signal of the first frequency divider.

16. The PLL circuit of claim 15, wherein the reset circuit is configured to perform a final reset of the first frequency divider on a signal edge of the first type of the reference signal after the end of the startup phase when the startup phase has ended.

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