OTDR sampling system and method for real-time dynamic segmented adjustment of amplification factor

Abstract

The invention relates to the field of optical fiber sensing technology, and more specifically to an OTDR sampling system and method capable of real-time dynamic segmented adjustment of amplification factor, which is proposed to solve the problem that the intensity of reflected light signals in existing OTDR systems is weakened as the length of optical fibers increases, thereby improving the sampling accuracy. The system is characterized in that a photosensitive element, more than two operational amplifiers, an ADC group including more than two analog-to-digital conversion circuits ADC, and an FPGA controller are provided, wherein the photosensitive element receives an optical signal output by an optical path system to be measured and outputs an electrical signal to the more than two operational amplifiers; the output ends of the more than two operational amplifiers are respectively connected to the input ends of the more than two analog-to-digital conversion circuits ADC in a one-to-one correspondence, the output ends of the analog-to-digital conversion circuits ADC output digital signals to the FPGA controller, the FPGA controller provides a sampling clock signal for the analog-to-digital conversion circuit ADC group, and the FPGA controller also provides a trigger pulse signal for a laser in the optical path system to be measured.

Description

Technical Field

[0001] The present invention relates to the field of optical fiber sensing technology, and more specifically to an OTDR sampling system and method capable of real-time dynamic segmented adjustment of amplification factor to improve sampling accuracy, which is proposed to solve the problem that the intensity of reflected light signals in existing OTDR systems is weakened as the optical fiber length increases. Technical Background

[0002] The OTDR (Optical Time Domain Reflectometry) system uses optical fiber as a sensing component. Compared with traditional sensors, it has the advantages of intrinsic passivity, anti-electromagnetic interference, long monitoring distance, and high sensitivity. It has a wide range of applications and can be used to measure parameters such as optical fiber temperature and stress. While having the advantages of optical fiber sensors, the OTDR system can also locate vibration events, and is particularly suitable for safety monitoring of oil and gas pipelines, national defense borders, railway borders, and national defense optical cables.

[0003] The basic principle of OTDR is to measure the optical fiber transmission loss caused by scattering, absorption and other reasons and the structural loss caused by various structural defects by analyzing the backscattered light or forward scattered light of the pulse light in the optical fiber. When the light pulse is transmitted in the optical fiber and a certain point of the optical fiber is subjected to temperature or stress, the scattering characteristics of the point will change. Therefore, by measuring the useful information returned by the detector, it is possible to determine the disturbance information of the external signal distributed on the sensing optical fiber, and the time taken from the transmitted signal to the returned signal can be used to determine the distance the light propagates in the optical fiber. However, as the propagation distance of the pulse light in the optical fiber increases, the amplitude of the backscattered light received by the detector will decay accordingly. When the detection distance is long, the reflected light signal of the short-distance optical fiber is strong, requiring the detector to have a larger range, while the reflected light of the long-distance optical fiber is weak, requiring higher detection accuracy. This creates a contradiction, which requires both a large measurement range and high detection accuracy. Summary of the invention

[0004] In view of the situation that the intensity of the reflected light signal in the above-mentioned OTDR system weakens as the optical fiber length increases, and the sampling range and sampling accuracy of the sampling system cannot be taken into account at the same time, the present invention proposes a sampling system that selects the amplification factor of the operational amplifier module according to the analysis results of the data collected by the OTDR sampling system, and adjusts the amplification factor of the OTDR sampling system in real time and dynamically to take into account the range and sampling accuracy of the sampling system.

[0005] The present invention is achieved by the following measures:

[0006] An OTDR sampling system with real-time dynamic segmented adjustment of amplification factor, characterized in that it is provided with a photosensitive element, more than two operational amplifiers, an ADC group including more than two analog-to-digital conversion circuits ADC, and an FPGA controller, wherein the photosensitive element receives an optical signal output by an optical path system to be measured and outputs an electrical signal to the more than two operational amplifiers; the output ends of the more than two operational amplifiers are respectively connected with the input ends of the more than two analog-to-digital conversion circuits ADC in a one-to-one correspondence, the output ends of the analog-to-digital conversion circuits ADC output digital signals to the FPGA controller, the FPGA controller provides a sampling clock signal for the analog-to-digital conversion circuit ADC group, and the FPGA controller also provides a trigger pulse signal for the laser in the optical path system to be measured; The sampling clock signal is synchronized with the trigger pulse signal; the FPGA controller is provided with a reference signal determination module for calculating the over-range percentage of the n groups of ADC data collected and then determining the best reference signal; the FPGA controller is provided with a segmented average calculation module for segmentally processing the determined reference signal; the FPGA controller is also provided with an amplification factor selection module for selecting different amplification factors according to the calculation results of the segmented average calculation module; the FPGA controller is also provided with an operational amplification module for amplifying different amplification factors according to different amplification factors; the FPGA controller is also provided with a data splicing module for splicing multiple segments of data amplified by the operational amplification module.

[0007] The present invention is also provided with a host computer connected with the FPGA controller.

[0008] The FPGA controller of the present invention is provided with n operational amplifier modules corresponding one-to-one to the n analog-to-digital conversion circuits in the ADC group, so as to meet the requirement of multiple groups of optional amplification factors.

[0009] The present invention also proposes an OTDR sampling method with real-time dynamic segmented adjustment of amplification factor, which is characterized by comprising the following steps:

[0010] Step 1: The FPGA controller outputs a trigger pulse signal to the light source of the OTDR system, and simultaneously outputs a sampling clock signal to an ADC group including more than two analog-to-digital conversion circuits;

[0011] Step 2: The photosensitive element collects n data from the optical path of the OTDR system, where n≥…. The backscattered light of the optical path of the OTDR system is converted into an electrical signal by the photosensitive element, amplified by the operational amplifier module, and then input into the ADC for analog-to-digital conversion. Finally, the digital signal output by the ADC is collected by the FPGA, and the analog signal is analyzed and calculated.

[0012] Step 3: Select a reference signal, and then compare the segmented average value of the reference signal with the set value, select the amplification factor of the operational amplifier module according to the comparison result, and perform segmented amplification sampling on the OTDR signal, so as to select an operational amplifier module with a low amplification factor at a location where the scattered light signal is strong, and select an operational amplifier module with a high amplification factor at a location where the scattered light signal is weak;

[0013] Step 4: Through the data splicing module inside the FPGA controller, the signal segments with different amplification factors are selected based on the calculation results of the step to be spliced ​​into complete OTDR data, and finally the collected and spliced ​​signals are uploaded to the host computer for further processing.

[0014] When the operational amplifier module in the FPGA controller in step 3 of the present invention is working, when the laser receives the trigger signal provided by the FPGA controller, it will emit pulse light and inject it into the optical path of the OTDR system. Then, its backscattered light signal is converted into an electrical signal by the photosensitive device, and is amplified by the operational amplifier module 1 and the multi-channel operational amplifier module n pairs (n=1.2.3...), and the amplification factor of these n operational amplifier modules is from Q to 2 n-1 ×Q is set in n stages, where the value of Q is determined by the hardware circuit, and its amplification factor is arranged in ascending order according to the serial number of the operational amplifier module. More than two operational amplifier modules amplify the electrical signal emitted by the photosensitive device at the same time, and send the amplified signal to the ADC for analog-to-digital conversion, and at the same time send it to the FPGA, which analyzes and processes the collected n groups of OTDR data.

[0015] The sampling rate of the ADC described in the present invention is adjustable from 10M to 100MSPS, which is convenient for meeting different spatial resolution requirements. Such ADCs have the same number n as the operational amplifier modules and have the same specifications and models. They together constitute an ADC group, and simultaneously perform analog-to-digital conversion on the n-way operational amplifier modules and transmit the data to the FPGA.

[0016] The synchronous processing method of the sampling clock signal and the laser trigger clock signal in step 1 of the present invention is to generate a high-frequency clock by using the PLL module in the FPGA controller, whose frequency is the common multiple of the ADC sampling clock frequency and the laser trigger clock frequency, and use the clock to perform counting operations. When the count value reaches half of the ratio of the high-frequency clock frequency and the ADC sampling clock frequency, the FPGA sends a differential anti-jump signal to the ADC; similarly, according to the value reaching half of the ratio of the high-frequency clock frequency and the laser trigger clock frequency as the count value, an anti-jump signal is sent to the laser. In addition, the laser has requirements for the pulse width of the received trigger clock, so timing is performed at the rising edge of this jump signal, and the timing pulse also comes from the high-frequency clock generated by the PLL module, and the timing number is the required pulse width time multiplied by the high-frequency clock frequency. In this way, a synchronized ADC sampling clock and laser trigger pulse clock can be obtained.

[0017] The reference signal selection method in step 3 of the present invention is as follows: the data collected by the OTDR system is analyzed and processed. First, it is ensured that the strong signal will not be amplified beyond the system sampling range. The LPM_COMPARE IP core in the FPGA controller is used to set the "datab[]" parameter in the n groups of LPM_COMPARE IP cores to the ADC range value, and the "dataa[]" parameter is the n groups of collected data. The comparison method is selected as "dataa[]>datab[]". Whenever this condition is met, the count is increased by 1. Finally, the ratio of the count value to the number of data in this data is calculated. If this ratio is smaller than the over-range percentage set by the host computer to the FPGA controller, this group of data is selected. Finally, the OTDR signal collected by a group of operational amplifier modules with the largest amplification factor that meets the percentage condition, that is, the largest operational amplifier module number, is selected as the reference signal. It is assumed that the serial number of this group of operational amplifier modules is m.

[0018] The method for averaging the reference signal by segment in step 3 of the present invention is as follows: first, the reference signal is segmented by average, and the number of segments is n-m+1. The method for averaging is to accumulate the segment data and divide the accumulated result by the number of accumulations. In this way, the noise signal caused by various reasons of the reference signal can be filtered out, so that the system can select the amplification factor of each segment data more accurately.

[0019] The method for selecting the amplification factor of the reference signal segment in step 3 of the present invention is as follows: the FPGA compares the average value of the above n-m+1 segment signals with the ADC full-scale value, and also uses the nm group LPM_COMPARE IP core, and its "datab[]" parameter is set to 1 / 4 to 1 / 2 of the ADC maximum range in sequence. n-m+1, the "dataa[]" parameter is set to the average value data of the segmented data, and the comparison method is selected as "dataa[]>datab[]". When the condition is met, the output is 0, and when it is not met, the output is 1. In this way, starting from the first segment of the average value segment of the reference signal, the comparison calculation is carried out in this nm group of LPM_COMPARE IP cores, and the comparison results are listed as a two-dimensional matrix. This matrix has a total of n-m+1 rows, and each row is the result of comparing the average value of a segment of the reference signal with the set value of the nm group. There are a total of nm non-0 or 1 elements. Next, determine the first element number of 1 in each row of the matrix. Assume that the number is p. If there is no 1, it means that the average value of this segment is greater than 1 / 4 of the maximum range of the ADC, so p is 0; if p is not 0, it means that the signal has weakened to a value less than 1 / 4 of the ADC range. Finally, select the digital signal output by the m+p operational amplifier modules as the upload data of this segment of data. By analogy, the entire matrix is ​​judged once, and the output data of the operational amplifier module is selected as the upload data according to the p value of each row.

[0020] The uploaded data splicing described in the present invention is performed inside the FPGA. The specific implementation method is that when uploading data, an LPM_MUX IP core is used inside the FPGA as an n-to-1 selector to select the collected n-channel data. The selection signal value and the sending time are determined according to the m+p value and its change time. Finally, the entire spliced ​​data is uploaded to the host computer.

[0021] Compared with the prior art, the present invention averages the data collected by the OTDR sampling system in segments, selects the amplification factor of the operational amplifier module according to the calculation result to collect multiple segments of data, and splices these data in sequence, thereby taking into account the data of the sampling system range and accuracy, and realizing real-time dynamic adjustment of the amplification factor of the OTDR sampling system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Attached Figure 1 It is a system structure diagram of the present invention.

[0023] Attached Figure 2 It is the FPGA workflow diagram of the present invention.

[0024] Attached Figure 3 It is a logic block diagram of the sampling splicing algorithm of the present invention. DETAILED DESCRIPTION

[0025] As attached Figure 1 As shown, the OTDR system of the sampling method mainly includes: 1 laser; 2 optical path system; 3 photosensitive element; 4 operational amplifier module 1... operational amplifier module n (n=1.2.3...); 5 ADC sampling circuit; 6 FPGA digital control circuit; 7 host computer.

[0026] The 1 laser mentioned in the present invention receives the trigger signal sent by the FPGA and sends a pulsed laser. 2 The system optical path is the optical device and sensor fiber of the OTDR system. 3 The photosensitive element is a photosensitive semiconductor, which mainly realizes the conversion of optical signals into electrical signals. 4 The main function of operational amplifier module 1...operational amplifier module n is to amplify the electrical signal emitted by the 3 photosensitive elements by n different multiples, and the amplification multiples are arranged in increasing order of the operational amplifier module number. 5 The ADC sampling circuit is composed of multiple groups of ADCs, and the number of ADCs is the same as the number of operational amplifier modules. It is responsible for converting the analog signals output by multiple groups of operational amplifier modules into digital signals and sending them to the FPGA digital control circuit. 6 The FPGA digital control circuit is the control and acquisition function center of the OTDR system and is responsible for the operation of the entire system. 7 The host computer calculates the received data.

[0027] The FPGA analysis and processing flow of OTDR data is shown in the attached figure. Figure 2 As shown in the figure, the host computer first configures the FPGA to collect relevant parameters, such as ADC sampling frequency, sampling length, laser trigger frequency pulse width, and over-range percentage. Next, the FPGA provides a synchronous clock to the ADC and laser to start working. The photosensitive element converts the backscattered light of the optical path system into an electrical signal. Next, n operational amplifier modules with different amplification factors are used to amplify the electrical signal at the same time, and the amplified data is sent to n ADC circuits, which perform analog-to-digital conversion and output digital signals to the FPGA. In this way, the FPGA will receive digital signals with different amplification factors of the n backscattered light signals of the same OTDR system.

[0028] Next, as attached Figure 3 The algorithm shown in the figure calculates the over-range percentage of the n digital signals inside the FPGA to determine the reference signal. After the reference signal is determined, the reference signal is segmented and averaged, and the average is compared with the range value. Data segments with different amplification factors are selected according to the comparison results. Since the amplification factors of the operational amplifier modules are arranged in increasing order with the module numbers, and the signal strength gradually decays with the number of segments, it is possible to use operational amplifier modules with small amplification factors when the signal strength is large, and use operational amplifier modules with large amplification factors when the signal attenuation is weak. The FPGA splices these selected data into a set of data, which can take into account the sampling range and sampling accuracy of the sampling module.

[0029] Finally, upload the spliced ​​data to the host computer for the next step of data analysis and calculation.

Claims

1. An OTDR sampling system with real-time dynamic segmented adjustment of magnification, characterized in that A photosensitive element, two or more operational amplifiers, an ADC group including two or more analog-to-digital conversion circuits ADC, and an FPGA controller are provided, wherein the photosensitive element receives the optical signal output by the optical path system to be measured and outputs an electrical signal to the two or more operational amplifiers; the output ends of the two or more operational amplifiers are respectively connected to the input ends of the two or more analog-to-digital conversion circuits ADC in a one-to-one correspondence, the output end of the analog-to-digital conversion circuit ADC outputs a digital signal to the FPGA controller, the FPGA controller provides a sampling clock signal for the analog-to-digital conversion circuit ADC group, and the FPGA controller also provides a trigger pulse signal for the laser in the optical path system to be measured; The sampling clock signal is synchronized with the trigger pulse signal; the FPGA controller is provided with a reference signal determination module for calculating the over-range percentage of the n groups of ADC data collected and thereby determining the best reference signal; the FPGA controller is provided with a segmented average calculation module for segmentally processing the determined reference signal; the FPGA controller is also provided with an amplification factor selection module for selecting different amplification factors according to the calculation results of the segmented average calculation module; the FPGA controller is also provided with a data splicing module for splicing multiple segments of data with different selected amplification factors.

2. The OTDR sampling system with real-time dynamic segmented adjustment of amplification factor according to claim 1 is characterized in that A host computer connected to the FPGA controller is also provided.

3. The OTDR sampling system with real-time dynamic segmented adjustment of amplification factor according to claim 1 is characterized in that The FPGA controller is provided with n operational amplifiers corresponding one-to-one to the n analog-to-digital conversion circuits in the ADC group to meet the requirement of multiple groups of optional amplification factors.

4. An OTDR sampling method with real-time dynamic segmented adjustment of amplification factor, characterized in that The following steps are involved: Step 1: The FPGA controller outputs a trigger pulse signal to the light source of the OTDR system, and simultaneously outputs a sampling clock signal to an ADC group including more than two analog-to-digital conversion circuits; Step 2: The photosensitive element collects n data from the optical path of the OTDR system, where n=2, 3, ..., and the backscattered light of the optical path of the OTDR system is converted into an electrical signal by the photosensitive element, amplified by an operational amplifier, and input into the ADC for analog-to-digital conversion. Then, the digital signal output by the ADC is collected by the FPGA, and the digital signal is analyzed and calculated; Step 3: Select the reference signal, and then compare the segmented average value of the reference signal with the set value, select the amplification factor of the operational amplifier according to the comparison result, and perform segmented amplification sampling on the OTDR signal, so as to select an operational amplifier with a low amplification factor at the location where the scattered light signal is strong, and select an operational amplifier with a high amplification factor at the location where the scattered light signal is weak; Step 4: Through the data splicing module inside the FPGA controller, according to the calculation results of step 3, select signal segments with different amplification factors to splice into complete OTDR data, and finally upload the collected and spliced ​​signals to the host computer for further processing.

5. The OTDR sampling method with real-time dynamic segmented adjustment of amplification factor according to claim 4 is characterized in that In step 3, when the laser receives the laser trigger clock signal provided by the FPGA controller, it will emit pulsed light and inject it into the optical path of the OTDR system. Then, its backscattered light signal is converted into an electrical signal by the photosensitive device and amplified by n operational amplifiers. The amplification factor of these n operational amplifiers is from Q to 2. n-1 ×Q is set in n stages, where the value of Q is determined by the hardware circuit, and its amplification factor is arranged in ascending order according to the serial number of the operational amplifier. More than two operational amplifiers amplify the electrical signal emitted by the photosensitive element at the same time, and send the amplified signal to the ADC for analog-to-digital conversion, and at the same time send it to the FPGA, which analyzes and processes the collected n groups of OTDR data.

6. The OTDR sampling method with real-time dynamic segmented adjustment of amplification factor according to claim 4 is characterized in that The ADC group sampling rate is adjustable from 10M to 100MSPS, which is convenient for meeting different spatial resolution requirements. Such an ADC group has the same number n as the operational amplifiers, which together constitute the ADC group, and simultaneously perform analog-to-digital conversion on the n-channel operational amplifiers and transmit the data to the FPGA.

7. The OTDR sampling method with real-time dynamic segmented adjustment of amplification factor according to claim 4 is characterized in that The synchronous processing method of the sampling clock signal and the laser trigger clock signal in step 1 is to generate a high-frequency clock by using the PLL module in the FPGA controller, whose frequency is a common multiple of the ADC sampling clock frequency and the laser trigger clock signal frequency. The clock is used for counting operations. When the count value reaches half of the ratio of the high-frequency clock frequency and the ADC sampling clock frequency, the FPGA sends a differential inversion jump signal to the ADC; similarly, according to the value reaching half of the ratio of the high-frequency clock frequency and the laser trigger clock signal frequency as the count value, an inversion jump signal is sent to the laser. In addition, the laser has pulse width requirements for the received trigger clock, so timing is performed at the rising edge of this jump signal. The timing pulse also comes from the high-frequency clock generated by the PLL module. The timing number is the required pulse width time multiplied by the high-frequency clock frequency. In this way, synchronized ADC sampling clock and laser trigger clock signals can be obtained.

8. The OTDR sampling method with real-time dynamic segmented adjustment of amplification factor according to claim 4 is characterized in that The reference signal selection method in step 3 is as follows: Analyze and process the data collected by the OTDR system. First, ensure that the strong signal will not be amplified beyond the system sampling range. Use the LPM_COMPARE IP core in the FPGA controller, set the "datab[]" parameter in these n groups of LPM_COMPARE IP cores to the ADC range value, and the "dataa[]" parameter to the n groups of collected data. Select the comparison method as "dataa[]>datab[]". Whenever this condition is met, add 1 to the count. Finally, calculate the ratio of the count value to the number of data in this data. If this ratio is smaller than the over-range percentage set by the host computer to the FPGA controller, select this group of data. Finally, select the OTDR signal collected by a group of operational amplifiers with the largest amplification factor that meets the percentage condition, that is, the largest operational amplifier number, as the reference signal. Assume that the serial number of this group of operational amplifiers is m.

9. The OTDR sampling method with real-time dynamic segmented adjustment of amplification factor according to claim 8, characterized in that The method for averaging the reference signal segments in step 3 is as follows: first, the reference signal is segmented and averaged, and the number of segments is n-m+1. The method for averaging is to accumulate the segment data and divide the accumulated result by the number of accumulations. In this way, the noise signal caused by various reasons of the reference signal can be filtered out, so that the system can more accurately select the amplification factor of each segment data.

10. The OTDR sampling method with real-time dynamic segmented adjustment of amplification factor according to claim 9, characterized in that The method for selecting the amplification factor of the reference signal segment in step 3 is as follows: the FPGA compares the average value of the above n-m+1 segment signals with the ADC full-scale value. The nm group LPM_COMPARE IP core is also used, and its "datab[]" parameter is set to 1 / 4 to 1 / 2 of the ADC maximum range. n-m+1 , the "dataa[]" parameter is set to the average value data of the segmented data, and the comparison method is selected as "dataa[]>datab[]". When the condition is met, the output is 0, and when it is not met, the output is 1. In this way, starting from the first segment of the average value segment of the reference signal, the comparison calculation is performed in this nm group of LPM_COMPARE IP cores in turn, and the comparison results are listed as a two-dimensional matrix. This matrix has a total of n-m+1 rows, and each row is the result of comparing a segment average value of the reference signal with the nm group set value. There are a total of nm non-0 or 1 elements. Next, determine the first element number that is 1 in each row of the matrix. Assume that the number is p. If there is no 1, it means that the average value of this segment is greater than 1 / 4 of the maximum range of the ADC, so p is 0; if p is not 0, it means that the signal has weakened to a value less than 1 / 4 of the ADC range.

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