Chip package and method for manufacturing chip package

Abstract

A method for manufacturing a chip package is provided. The method may include: patterning at least one chip pad of a chip to form a patterned structure in the at least one chip pad, the patterned structure including at least one predetermined recess; and encapsulating the chip with an encapsulation material to fill the at least one predetermined recess.

Description

Technical Field

[0001] Various embodiments generally relate to a chip package and a method of manufacturing a chip package. Background Art

[0002] In a bare die package, especially in a laminated bare die package, such as a double-sided chip embedded product (CE), an example of which is Figure 2 As shown in FIG, the adhesion between the metallization 104, 106, 108 of the semiconductor die / chip 112 and the encapsulation material 124 (e.g., printed circuit board (PCB) laminate) may be weaker than desired. Therefore, in current CE products, one of the biggest challenges may be delamination between the relatively smooth, possibly large, die Cu surface 104, 106, 108 and the PCB laminate 124. The larger the copper area, the higher the risk of delamination.

[0003] Attempts to solve this problem include, for example, adding an additional polyimide layer on the metallization. However, this necessitates subsequent drilling through the polyimide passivation and removal of residues by a desmear process prior to a subsequent plating process, which may be complicated or even impossible. Furthermore, polyimide can only be applied to the front side of the die and may therefore not provide a solution for a die package comprising two or more dies mounted in different orientations, i.e. one die with its front side facing the carrier and another die with its back side facing the carrier.

[0004] Another attempt includes so-called Cu roughening, which means roughening the copper surface, which is possible because the bare die is first diffusion soldered to a copper (Cu) lead frame, and the lead frame with the chip can be subjected to, for example, a wet chemical treatment for roughening before the lamination process without damaging the lead frame. However, other chip embedding processes may be more complicated. For example, the front side of the chip (or more generally, the side facing down during the bonding process) can be roughened only after the first lamination process, but this may be risky because the laminating material may only be partially cured after the first lamination and may therefore be damaged during the roughening process. Similarly, the back side of the chip (or more generally, the side facing down during the bonding process) may not be roughened.

[0005] For current CE chip embedding process flows, there is no practical solution for increasing adhesion of both die surfaces, ie, the front side and the back side. Summary of the invention

[0006] A method for manufacturing a chip package is provided. The method may include: patterning at least one chip pad of a chip to form a patterned structure in the at least one chip pad, the patterned structure including at least one predetermined recess; and encapsulating the chip with an encapsulation material to fill the at least one predetermined recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the drawings, like reference numerals generally refer to like parts throughout the different views. Some reference numerals that could otherwise be repeated may be omitted to avoid congestion. The drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0008] Figure 1 shows a cross-sectional view of a chip package device according to the prior art;

[0009] Figure 2 Top views of a chip package according to the prior art and a chip package according to various embodiments are respectively shown;

[0010] Figure 3 The bottom views of a chip package according to the prior art and a chip package according to various embodiments are respectively shown;

[0011] Figure 4 The bottom views of a chip package according to the prior art and a chip package according to various embodiments are respectively shown;

[0012] Figure 5 shows a cross-sectional view of a chip package according to the prior art, and a cross-sectional view of a chip package according to various embodiments (each view having an enlarged view);

[0013] Figure 6 shows a cross-sectional view of a chip package according to various embodiments;

[0014] Figure 7 A process of forming a chip package according to various embodiments is shown in a sequence of cross-sectional views;

[0015] Figure 8 A process of forming a chip package according to various embodiments is shown in a sequence of cross-sectional views;

[0016] Fig. 9 A process flow of a method for manufacturing a chip package according to various embodiments is shown. DETAILED DESCRIPTION

[0017] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0018] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0019] The term "above" used in relation to forming a deposition material "above" a side or surface may be used herein to indicate that the deposition material may be formed "directly" on the side and surface, such as in direct contact with the side and surface. The term "above" used in relation to forming a deposition material "above" a side or surface may also be used herein to indicate that the deposition material may be formed "indirectly" on the side or surface such that one or more additional layers are disposed between the side or surface and the deposition material.

[0020] A number of different aspects of the present disclosure are provided for an apparatus, and a number of different aspects of the present disclosure are provided for a method. It will be appreciated that the basic features of the apparatus also hold true for the method, and vice versa. Therefore, for the sake of brevity, a repeated description of these features may have been omitted.

[0021] In various embodiments, a locking structure between a chip pad and a molding or laminate material in a CE type chip package is provided.

[0022] In various embodiments, the (large) copper pads (e.g. front side and / or back side) of a chip (e.g. a transistor, e.g. a SiC transistor or a GaN transistor, e.g. a MOSFET or an IGBT or different devices) in a chip package may be structured to improve adhesion between the copper pads and the molding and reduce the risk of delamination.

[0023] In other words, the (e.g. copper) chip pad metallization area can be at least partially divided into smaller areas to form a locking structure for the molding / laminate encapsulation, such as a recess that can be filled by the molding / laminate, so that the molding / (PCB-)laminate and the chip (e.g. copper) metallization have a reduced surface area due to the openings in the metallization to reduce the risk of delamination. The openings can reduce the area of ​​the (e.g. copper) metallization that is in direct contact with the laminate. This can reduce the stress at the metallization-encapsulation interface and thus reduce the risk of delamination.

[0024] The locking structure for the molding / laminate may be used on both sides of the chip. In various embodiments, the locking structure may extend completely through the (eg, Cu) metallization. This may have the advantage of being easier to handle, as no additional processing may be required.

[0025] In other embodiments, the locking structure may only partially extend through the Cu metallization, which may require additional photolithography and etching processes. In various embodiments, an etching process may be used to create the locking structure (e.g., opening) after the power metal is plated. In the case of a patterned plating process to form the structured metallization, the plating mask may have been patterned before plating.

[0026] Figure 2 1 and 2 respectively show top views of a chip package 102 according to the prior art and a chip package 202 according to various embodiments.

[0027] Figure 3 and Figure 4 1 and 2 show a bottom view of a chip package 102 according to the prior art and a chip package 202 according to various embodiments, respectively. Figure 5 A cross-sectional view of a chip package 102 according to the prior art and a cross-sectional view of a chip package 202 according to various embodiments are shown (each view having an enlarged view). Figure 6 A cross-sectional view of a chip package 202 according to various embodiments is shown. Figure 7 and Figure 8 Each of the figures shows a process of forming a chip package according to various embodiments in a sequence of cross-sectional views.

[0028] like Figure 5 As shown, (for ease of comparison, a chip package 102 according to the prior art is shown at the top), the chip package 202 may include a chip 112, the chip 112 including at least one chip pad 104, 108 and an encapsulation material 124 encapsulating the chip 112. The at least one chip pad 104, 108 may, for example, have a first chip pad 104 located on a first side of the chip 112 and a second chip pad 108 located on a second side 108 of the chip. A third chip pad 106 may be additionally arranged on the first side of the chip (together with the first chip pad 104), or arranged on the second side of the chip (together with the second chip pad 108).

[0029] Chip 112 may include or consist of an electronic circuit device, such as a transistor or a diode. Chip 112 may include or consist of a power device, such as a power transistor or a power diode. Chip pads 104, 106, 108 may be configured as contacts for electronic circuit devices, such as a control pad (e.g., a gate) and two current-carrying pads (e.g., a source and a drain) of a transistor. Chip pad 108 may be a chip backside metallization. Therefore, chip pad 108 may have a large area, which may be particularly useful for current-carrying chip pads, and thereby may, for example, form a source or drain contact of a transistor.

[0030] In various embodiments, the surface of the chip pad 104 , 106 , 108 may include a patterned structure including at least one predetermined recess 222 . Figures 2 to 7 Various exemplary embodiments of such a patterned structure including the at least one predetermined recess 222 are shown. Although in an embodiment, a predetermined recess 222 of a specific pattern, arrangement, etc. may be shown for only one or a certain pad (e.g., only for the backside metallization, such as the drain, or only for the gate), it should be understood that in various embodiments, any arrangement of recesses 222 may be applied to any one of the chip pads 104, 106, 108 according to the physical limitations of the chip pads 104, 106, 108.

[0031] A "predetermined recess" may be understood as having a predetermined shape and position. In various embodiments, a mask may be used to structure the chip pads 104, 106, 108, thereby forming the at least one predetermined recess 222. For example, the mask may be used to post-process the chip pads 104, 106, 108, for example, by wet or dry etching. The mask may be formed, for example, by a photolithography process. The at least one predetermined recess 222 may be formed in the mask, or more precisely, a mask counterpart of the predetermined recess 222 may be formed. In various embodiments, the at least one predetermined recess 222 may be formed, for example, by laser structuring without using a mask. Generally, any suitable structuring process may be used to form the at least one predetermined recess 222, preferably, a structuring process that can be used in current CE manufacturing processes.

[0032] The at least one predetermined recess 222 may be filled with the encapsulation material 124 .

[0033] Even though all illustrated embodiments have more than one predetermined recess 222 , in various embodiments, a single predetermined recess 222 may be sufficient to increase adhesion between the chip pads 104 , 106 , 108 and the encapsulation material 124 .

[0034] Even though the at least one predetermined recess 222 only partially extends through the (e.g. copper) chip pad 104, 106, 108, the at least one predetermined recess 222 is completely formed in the low-adhesion material, and thus the structured surface can provide one or more anchoring areas, thereby already increasing the “mechanical” adhesion between the structured surface and the encapsulation material 124. Assuming that the material of the chip pad 104, 106, 108 forming the sidewalls and the bottom of the at least one predetermined recess 222 is the low-adhesion material, Figure 5 (middle) and Figure 8 can be considered as illustrative examples of such embodiments.

[0035] In its illustrative example Figure 5 (bottom), Figure 6 and Figure 7 In various embodiments shown in FIG. 1 , adhesion can be further increased by forming the at least one predetermined recess 222 as a through hole, i.e., the depth of the predetermined recess is deep enough to extend all the way through the chip pads 104, 106, 108. Under the chip pads 104, 106, 108, a material 110 having higher adhesion to the encapsulation material 124 than to the material of the chip pads 104, 106, 108 (which can, for example, include or consist of copper or a copper alloy, such as AlCu, or, for example, Ni, NiV, Au, NiVAg, and / or NiVPd, all of which may have lower adhesion to the encapsulation material 124) can be exposed. The material 110 that can be exposed at the bottom of the at least one predetermined recess 222 can, for example, include or consist of a semiconductor material, such as silicon, silicon carbide, or other known semiconductor materials, and / or a dielectric material, such as an oxide, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or an organic material, such as polyimide (PI).

[0036] In various embodiments, at least one chip pad 104, 106, 108 may include or consist of a metal layer stack having a first layer at the surface of the chip pad and at least one second layer below the first layer, the first layer including or consisting of a first type of metal (e.g., copper or copper-containing), and the second layer including or consisting of a second type of metal, e.g., a metal that may have a higher adhesion to the encapsulation material 124 (than the first type of metal). The at least one predetermined recess 222 may extend through the first layer, but not through the second layer. The second type of metal may, for example, include or consist of aluminum, nickel and / or tungsten. Assuming that the material of the chip pad 104, 106, 108 forming at least the bottom of the at least one predetermined recess 222, and possibly also partially forming its sidewalls, is the second type of metal, Figure 5 (middle) and Figure 8 can be considered as illustrative examples of such embodiments.

[0037] The depth d of the at least one predetermined recess may be at least 2 μm and at most the thickness of the chip pads 104 , 106 , 108 , for example, a depth between about 2 μm and 8 μm, for example, a depth between 3 μm and 7 μm. Figure 5 For the corresponding illustration.

[0038] The thickness of the chip attach pads 104 , 106 , 108 in the recess 222 may be reduced compared to the thickness of the chip attach pads 104 , 106 , 108 outside the recess 222 .

[0039] The shape of the at least one predetermined recess 222 may not be limited. The shape (e.g., the shape of the periphery of the recess 222 in the plane of the chip pads 104, 106, 108) may be, for example, rounded, for example, circular (e.g., Figure 2 As shown in the third embodiment), a polygon, such as a rectangle (for example, as Figure 2 As shown, the second embodiment; Figure 3 As shown, the first, second and fourth embodiments; and Figure 4 As shown in the first and fourth embodiments), for example, a square (for example, as Figure 2 As shown, the first embodiment; Figure 3 As shown, the third embodiment; and Figure 4 shown, second embodiment), or substantially any shape.

[0040] The width w of the at least one predetermined recess 222 (see the corresponding diagram) Figure 5 ) may be in the range of about 10 μm to about 100 μm, for example, in the range of about 20 μm to about 80 μm, for example, about 30 μm to about 60 μm. The maximum size and number of recesses 222 may be limited by the design (e.g., shape) of chip pads 104, 106, 108 and the number of micro vias (e.g., μ vias) that may need to be formed in chip package 202 and that may be physically and electrically connected to chip pads 104, 106, 108.

[0041] The at least one predetermined recess 222 may include a plurality of predetermined recesses 222. Figures 2 to 8 The plurality of predetermined recesses 222 may, for example, form an array of predetermined recesses 222, such as recesses 222 arranged in a matrix form, such as Figure 3 The second, third and fourth exemplary embodiments and Figure 4 As shown in the first and second exemplary embodiments; or a grid of recesses 222, wherein the recesses 222 form the lines of the grid, such as Figure 3 As shown in the first embodiment and as Figure 4 In various embodiments, the arrangement of the plurality of predetermined recesses 222 may be irregular, for example, Figure 2 As shown in the embodiment.

[0042] In various embodiments, the array of predetermined recesses 222 may be distributed over the entire surface of the chip pads 104, 106, 108. In other words, for a grid of lines forming recesses 222, the lines may extend to the edge of the chip pads 104, 106, 108, for example Figure 3 As shown in the first embodiment and as Figure 4For the array pattern of the respective recesses 222, the recesses 222 may be arranged on the surface of the chip pads 104, 106, 108 such that for each recess 222 closest to the edge of the chip pads 104, 106, 108, the adjacent array arranged according to the array pattern will fall outside the surface of the chip pads 104, 106, 108. Figure 3 The second, third and fourth embodiments and Figure 4 The first and second embodiments are shown.

[0043] In various embodiments, the array of predetermined recesses 222 may extend over only a portion of the surface of the chip pads 104, 106, 108. In other words, with respect to the array pattern, at least for one of the recesses 222, adjacent recesses 222 may in principle be arranged according to the array pattern, but no recess 222 is arranged at this position, or with respect to the grid, the grid lines may not extend all the way to the edge of the chip pads 104, 106, 108.

[0044] In various embodiments, for example, Figure 2 The second embodiment shown and Figure 3 As shown in the second and fourth embodiments, the at least one predetermined recess 222 may include at least one groove, for example, a plurality of grooves. In various embodiments, at least one groove of the plurality of grooves may have a long axis along a first direction, and at least one other groove of the plurality of grooves may have a long axis along a second direction different from the first direction. Figure 2 In the second embodiment of the present invention, the die pads 104, 108 are shown and Figure 3 In various embodiments, all grooves may be parallel, for example, Figure 2 As shown in the second embodiment of the present invention with respect to the chip pad 106, Figure 3 The second embodiment shown and Figure 4 The first embodiment is shown. Figure 3 The first embodiment and Figure 4 The grid lines of the third embodiment can be thought of as intersecting grooves.

[0045] In various embodiments, the distance S between adjacent recesses 222 (see Figure 3 ) may be in the range of about 100 μm to about 150 μm. Therefore, the density of the plurality of predetermined recesses 222 on the surface of the chip pads 104, 106, 108 may be smaller or greater. Figure 3 It can be seen in FIG. 1 that the distance S between adjacent recesses decreases from the left column to the right column, and correspondingly, the density of the recesses 222 increases from left to right.

[0046] In various embodiments, the surface of the chip pads 104 , 106 , 108 (excluding the at least one recess 222 ) may have a surface roughness R of at most 3 μm, for example between about 0.5 μm and 2 μm. z .

[0047] In various embodiments, for example, Figure 6 As shown, the chip package 202 may include at least one via 224 (eg, μ-via) contacting a predetermined area on the pads 104, 106, 108. The position of the at least one predetermined recess 222 may not overlap with the predetermined area of ​​the at least one via 224. Figure 2 The right column and Figure 4 A top view of an embodiment of the right column is shown.

[0048] like Figure 7 As shown in a sequence of cross-sectional views, the process of forming a chip package according to various embodiments may include panel plating followed by structuring of the plated metal layer, the chip pads 104 , 106 , 108 .

[0049] like Figure 7 As shown, chip pads 104, 106, 108 (second panel) may be arranged on semiconductor chip 112. Chip pad 104 may be a source pad of a transistor, chip pad 106 may be a gate pad, and chip pad 108 may be a drain pad. Chip pads 104, 106, 108 may be formed, for example, by sputtering and subsequent copper plating.

[0050] like Figure 7 As shown in the first panel of , the source pad 104 and the gate pad 106 can be formed on the first metal layer 118, which can be formed of a metal with relatively low adhesion to the encapsulation material 124, such as AlCu. In various embodiments, the first metal layer 118 can be disposed on both sides of the chip 112 or not on any side. At least at certain predetermined locations, the material 110 can be arranged as a passivation layer between the first metal layer 118 and the chip pads 104, 106, 108. The material 110 can protect the first metal layer 118 from the etching chemicals used to form the recess 222. It can be a dielectric material. Between the source pad 104 and the gate pad 106, the material 110 can be arranged in a layer of material 110 to separate the source pad 104 from the gate pad 106. In the case where the metal material 110 is used as a passivation layer, the dielectric material can be used to separate the source pad 104 from the gate pad 106. In various embodiments, a barrier layer may be provided as (eg, a portion of) or in addition to the first metal layer 118 .

[0051] Examples of a stack formed by the chip pads 104 , 106 , 108 and the optional first metal layer, the material 110 and the barrier layer may include AlCu and / or Cu in combination with a passivation layer and / or a barrier layer, or without a passivation layer and a barrier layer.

[0052] As shown in the third panel, the front side and the back side can then be structured, for example using photolithography and etching. On the front side, the source pad 104 and the gate pad 106 can be separated from each other by forming pad spacers 120 , and on the back side, copper can be removed from scribe streets 122 .

[0053] In various embodiments, the at least one predetermined recess 222 may be formed simultaneously with the slitting street 122 or the pad spacing 120. For example, the predetermined recess 222 on the back side may be formed simultaneously with the slitting street 122, and / or the predetermined recess 222 on the front side may be formed simultaneously with the pad spacing 120 and the slitting street 122 on the front side. In various embodiments, only the mask used for the etching process may be configured differently from the mask in the standard process.

[0054] As shown in the fourth panel, encapsulation material 124 may be arranged on both sides of chip 112, for example by molding or lamination. Encapsulation material 124 may be arranged as a layer and may intrude into predetermined recesses 222 where it may be cured. For example, as described above, solid encapsulation material 124 may be "locked" to chip pads 104, 106, 108 in predetermined recesses 222.

[0055] Figure 8 A process of forming a chip package according to various embodiments is shown in a sequence of cross-sectional views.

[0056] Figure 8 The process shown can be different from Figure 7 The process shown differs in that the structuring of the front-side metallizations 104 , 106 and of the back-side metallization 108 can be performed at least partially by structured deposition, for example plating using a mask.

[0057] In various embodiments, at least some of the structuring forms, for example, pad spaces 122 and scribe streets 120. This process may allow for the formation of recesses 222 that do not extend all the way through the chip pads 104, 106, 108.

[0058] This means that, in case the recesses 222 are formed only partially through the metallization 104, 106, 108 (eg copper), an additional etching process may be required.The number and shape of the recesses 222 may not be limited.

[0059] exist Figure 7 and Figure 8In order to easily identify the recess 222 and distinguish it from the pad space 120 and the kerf street 122, the recess 222 is shown in gray shading in the third panel.

[0060] Fig. 9 A process flow 900 of a method of manufacturing a chip package according to various embodiments is shown.

[0061] The method may include: patterning at least one chip pad of the chip to form a patterned structure in the at least one chip pad, the patterned structure including at least one predetermined recess (in step 910); and encapsulating the chip using an encapsulation material to fill the at least one predetermined recess (in step 920).

[0062] Various examples are described below:

[0063] Example 1 is a method for manufacturing a chip package. The method may include: patterning at least one chip pad of a chip to form a patterned structure in the at least one chip pad, the patterned structure including at least one predetermined recess; and encapsulating the chip with an encapsulation material to fill the at least one predetermined recess.

[0064] In Example 2, the subject matter of Example 1 can optionally include that the at least one chip pad is patterned using a mask.

[0065] In Example 3, the subject matter of Example 1 may optionally include that the at least one predetermined recess is formed by processing the chip pad using a mask.

[0066] In Example 4, the subject matter of any one of Examples 1 to 3 may optionally include that forming the at least one predetermined recess includes or consists of etching.

[0067] In Example 5, the subject matter of Example 1 can optionally include that forming the at least one predetermined recess includes or consists of laser processing.

[0068] In Example 6, the subject matter of Example 1 can optionally include that forming the at least one predetermined recess includes forming the at least one predetermined recess during a pattern plating process.

[0069] In Example 7, the subject matter of any one of Examples 1 to 6 may optionally include that forming the at least one predetermined recess includes reducing a thickness of the chip pad in at least one predetermined region of the chip pad.

[0070] In Example 8, the subject matter of any one of Examples 1 to 7 may optionally include performing the patterning of the at least one chip pad at a wafer level.

[0071] In Example 9, the subject matter of Example 8 can optionally include performing encapsulation at a wafer level.

[0072] In Example 10, the subject matter of any one of Examples 1 to 9 can optionally include that encapsulating includes laminating the chip using a laminating material.

[0073] In Example 11, the subject matter of any one of Examples 1 to 9 can optionally include that encapsulating includes molding.

[0074] In Example 12, the subject matter of any one of Examples 1 to 11 can optionally include that patterning the at least one chip pad includes forming a plurality of predetermined recesses.

[0075] In Example 13, the subject matter of any one of Examples 1 to 12 can optionally include that forming the plurality of predetermined recesses includes forming the plurality of predetermined recesses into an array of recesses.

[0076] Example 14 is a chip package. The chip package may include: a chip including at least one chip pad and an encapsulation material encapsulating the chip, wherein a surface of the chip pad includes a patterned structure, the patterned structure includes at least one predetermined recess, and the at least one predetermined recess is filled with the encapsulation material.

[0077] In Example 15, the subject matter of Example 14 can optionally include that the at least one predetermined recess has a depth of at least 2 μm.

[0078] In Example 16, the subject matter of Example 14 or 15 can optionally include that the patterned structure comprises a mask-patterned structure.

[0079] In Example 17, the subject matter of any one of Examples 14 to 16 can optionally include that the at least one predetermined recess comprises at least one through hole extending through an entire thickness of the at least one chip pad.

[0080] In Example 18, the subject matter of any one of Examples 14 to 17 can optionally include: at a bottom of the at least one predetermined recess, exposing the semiconductor material and / or the dielectric material.

[0081] In Example 19, the subject matter of any one of Examples 14 to 18 can optionally include that the material at the chip pad surface includes or consists of copper.

[0082] In Example 20, the subject matter of any one of Examples 14 to 19 may optionally include: the at least one chip pad includes or consists of a metal layer stack, the metal layer stack having a first layer at the surface of the chip pad and at least one second layer below the first layer, the first layer includes or consists of a first type of metal, and the second layer includes or consists of a second type of metal.

[0083] In Example 21, the subject matter of Example 20 can optionally include that the at least one predetermined recess extends through the first layer but not through the second layer.

[0084] In Example 22, the subject matter of Example 20 or 21 can optionally include that the first type of metal is copper.

[0085] In Example 23, the subject matter of any one of Examples 20 to 22 can optionally include that the second type of metal is from a group of metals consisting of aluminum, nickel, and tungsten.

[0086] In Example 24, the subject matter of any one of Examples 14 to 23 can optionally include a thickness of the chip pad in the recess being reduced compared to a thickness of the chip pad outside of the recess.

[0087] In Example 25, the subject matter of any one of Examples 14 to 24 can optionally include that the at least one predetermined recess includes a plurality of predetermined recesses.

[0088] In Example 26, the subject matter of Example 25 can optionally include: the plurality of predetermined recesses forming an array of predetermined recesses.

[0089] In Example 27, the subject matter of Example 26 can optionally include: the array of predetermined recesses is distributed over the entire surface of the chip pad.

[0090] In Example 28, the subject matter of any one of Examples 14 to 27 can optionally include that the at least one predetermined recess comprises at least one groove.

[0091] In Example 29, the subject matter of Example 28 can optionally include that the at least one groove comprises a plurality of grooves.

[0092] In Example 30, the subject matter of Example 29 can optionally include: at least one groove of the plurality of grooves having a major axis along a first direction, and at least one other groove of the plurality of grooves having a major axis along a second direction different from the first direction.

[0093] In Example 31, the subject matter of Example 29 or 30 can optionally include: the plurality of grooves intersecting.

[0094] In Example 32, the subject matter of Example 31 can optionally include that the plurality of intersecting grooves comprises or consists of a grid of grooves.

[0095] In Example 33, the subject matter of any one of Examples 14 to 32 can optionally include the at least one recess having a width in a range from about 10 μm to about 100 μm.

[0096] In Example 34, the subject matter of any one of Examples 14 to 33 can optionally include that a distance between adjacent recesses is in a range from about 100 μm to about 150 μm.

[0097] In Example 35, the subject matter of any one of Examples 14 to 34 may optionally include that the chip includes or consists of a power device.

[0098] In Example 36, the subject matter of Example 35 can optionally include that the power device includes or consists of a power transistor.

[0099] In Example 37, the subject matter of any one of Examples 14 to 36 may optionally include: the chip includes or consists of a transistor.

[0100] In Example 38, the subject matter of any one of Examples 14 to 18 can optionally include that the at least one chip pad includes a chip backside metallization.

[0101] In Example 39, the subject matter of any one of Examples 14 to 38 can optionally include that the at least one chip pad comprises a current carrying pad.

[0102] In Example 40, the subject matter of any one of Examples 14 to 39 may optionally include that the at least one chip pad comprises a source or drain pad.

[0103] In Example 41, the subject matter of any one of Examples 14 to 40 may optionally include that the at least one chip pad comprises a control pad.

[0104] In Example 42, the subject matter of any one of Examples 14 to 41 may optionally include that the at least one chip pad comprises a gate pad.

[0105] In Example 43, the subject matter of any one of Examples 14 to 42 may optionally further include: at least one via contacting a predetermined area on the pad, wherein a position of the at least one predetermined recess does not overlap with the predetermined area of ​​the at least one via.

[0106] Although the present invention has been particularly shown and described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention as defined in the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and it is therefore intended to include all changes within the meaning and scope of equivalent substitutions of the claims.

Claims

1. A method for manufacturing a chip package, the method comprising: ● patterning at least one chip pad of the chip to form a patterned structure in the at least one chip pad, the patterned structure comprising at least one predetermined recess; and encapsulating the chip with an encapsulation material so as to fill the at least one predetermined recess, ●Wherein, the at least one predetermined recess is formed by processing the at least one chip pad using a mask.

2. The method according to claim 1, further comprising: The at least one predetermined recess is formed by etching.

3. The method according to claim 1, further comprising: ●Another predetermined recess is formed by laser processing.

4. The method according to claim 1, further comprising: The at least one predetermined recess is formed by reducing the thickness of the at least one chip pad in at least one predetermined region of the at least one chip pad.

5. The method according to claim 1, further comprising: ● encapsulating the chip using an encapsulation material includes laminating the chip using a laminating material; or ● Forming at least one via hole in contact with a predetermined area on the at least one pad, wherein a position of the at least one predetermined recess does not overlap with the predetermined area of ​​the at least one via hole.

6. The method according to claim 1, wherein: The at least one predetermined recess has a depth of at least 2 μm.

7. The method according to claim 1, wherein: The at least one predetermined recess includes at least one through hole extending through the entire thickness of the at least one chip pad.

8. The method according to claim 1, wherein: The at least one chip pad includes a metal layer stack having a first layer at a surface of the at least one chip pad and at least one second layer below the first layer, the first layer including a first type of metal, the second layer including a second type of metal.

9. The method according to claim 1, wherein: The at least one predetermined recess includes at least one groove.

10. A method for manufacturing a chip package, the method comprising: ● patterning at least one chip pad of the chip to form a patterned structure in the at least one chip pad, the patterned structure comprising at least one predetermined recess; and encapsulating the chip with an encapsulation material so as to fill the at least one predetermined recess, ●Wherein, the at least one predetermined recess is formed by laser processing.

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