Method for manufacturing bit line contact
By forming a composite layer and an oxide layer in the bit line contact of the DRAM, the dopant diffusion is prevented, and the problems of conductivity and resistance value increase caused by dopant diffusion are solved, and the performance of DRAM is improved.
Patent Information
- Application Number
- CN201980036491.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2018-08-02
- Filing Date
- 2019-07-30
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2039-07-30
AI Technical Summary
In the bit line contacts of the DRAM cell transistor, dopant diffusion leads to an increase in conductivity and an increase in resistance of the undoped polysilicon, affecting the bit line capacitance and overall performance.
By forming a composite layer, including a first insulating material, a second insulating material and a first polysilicon layer, and converting it to a third insulating material at an edge portion of the polysilicon layer, or oxidizing on the side surface of the non-doped polysilicon layer and forming The oxide layer, the opening is filled with a doped polysilicon layer to prevent the dopant from diffusion.
It effectively prevents the diffusion of dopants, maintains the electrical properties of the undoped polycrystalline silicon, reduces the resistance value of bit-line contacts, and improves the performance of DRAM.
Smart Images
Figure CN112262472B_ABST
Abstract
Description
Background Art
[0001] The bit line contact that connects the cell transistor and the bit line of DRAM (dynamic random access memory) to each other is made of doped polysilicon filled in the bit contact hole. The bit contact hole is an opening formed in the multilayer structure. When non-doped polysilicon is used as a dielectric film containing the multilayer structure, dopants can diffuse from the doped polysilicon constituting the bit line contact to the non-doped polysilicon constituting the dielectric film containing the multilayer structure. In this case, part of the non-doped polysilicon is changed to doped polysilicon with a certain conductivity, which causes the problem of increased bit line capacitance. In addition, if the dopant diffuses, the dopant concentration in the doped polysilicon constituting the bit line contact is reduced and another problem arises, that is, the resistance value of the bit line contact increases. Summary of the invention
[0002] Apparatus and methods for forming semiconductor devices are described. In aspects of the present disclosure, a method includes forming a composite layer, and forming a hole in the composite layer, and converting an edge portion. The composite layer includes a first insulating material and a second insulating material and a first polysilicon layer located between the first insulating material and the second insulating material. The hole penetrates the composite layer to define the first insulating material and the second insulating material and a corresponding edge portion of the first polysilicon layer. The edge portion of the first polysilicon layer is converted to a third insulating material such that the third insulating material is located between the corresponding edges of the first insulating material and the second insulating material.
[0003] In another aspect of the present disclosure, a method includes forming a composite layer, patterning the composite layer, oxidizing a side surface, forming an additional layer, and filling an opening with a doped polysilicon layer. The composite layer includes a first dielectric layer and a second dielectric layer and a non-doped polysilicon layer positioned between the first and second dielectric layers. An opening exposing a side surface of the non-doped polysilicon layer is formed by patterning. The side surface of the non-doped polysilicon layer is oxidized to form an oxide layer. The additional layer is formed on the oxide layer.
[0004] In another aspect of the present disclosure, a device includes a first insulating material, a first polysilicon material, a second insulating material, and an additional material. The first insulating material has a first upper surface and a first side surface extending downward from an edge of the first upper surface. The first polysilicon material is above the first insulating material. The first polysilicon material has a second upper surface and a second side surface extending downward from an edge of the second upper surface. The second side surface is recessed from the edge of the first upper surface of the first insulating material to expose a portion of the first upper surface. The second insulating material is above the portion of the first upper surface of the first insulating material to cover the second side surface of the first polysilicon material. The second insulating material has a third side surface on a side opposite to the second side surface of the first polysilicon material. The additional material covers the first side of the first insulating material and the third side surface of the second insulating material. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 is a schematic cross-sectional view showing the configuration of a semiconductor device according to some embodiments of the present disclosure.
[0006] Figures 2 to 12 It is used to explain some embodiments of the present disclosure. Figure 1 Flowchart of a method for manufacturing a semiconductor device shown in FIG. DETAILED DESCRIPTION
[0007] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show specific aspects and embodiments of the present disclosure that can be practiced in an illustrative manner. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessarily mutually exclusive, because some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.
[0008] The semiconductor device according to the present embodiment is a DRAM and has a unit transistor T such as Figure 1 However, the subject matter of the present disclosure is not limited to DRAM. The cell transistor T is formed in an active region 4 provided in a semiconductor substrate 2. The active region 4 is defined by an STI region 6. The cell transistor T is connected between a bit line 10 and a cell capacitor C. A word line WL is connected to a gate electrode of the cell transistor T.
[0009] The bit line 10 is connected to the cell transistor T via the bit line contact 12 and the barrier metal layer 14. The bit line contact 12 is provided in the bit contact hole 18. The inner wall of the bit contact hole 18 is covered by a silicon nitride film 32. It does not matter whether part or all of the silicon nitride film 32 is lost during the manufacturing process. The bit line 10 is made of, for example, tungsten (W), the bit line contact 12 is made of, for example, doped polysilicon, and the barrier metal 14 is made of, for example, tungsten nitride (WN) or titanium nitride (TiN). A hard mask 16 made of silicon nitride is provided on the bit line 10. The hard mask 16 is a mask layer for patterning the bit line 10, the barrier metal layer 14, and the bit line contact 12.
[0010] by Figure 1 The cross section illustrated in FIG. 1 illustrates a bit line 10 positioned on a bit line contact 12 (on the left) and a bit line 10 not positioned on a bit line contact 12 (on the right). Figure 1 1 , the portion of the bit line 10 that is not positioned on the bit line contact 12 is placed over the silicon dioxide film 20 and the non-doped polysilicon film 22.
[0011] Next, the manufacturing process of the bit line contact 12 and the bit line 10 is explained. First, after forming the cell transistor T in the active region 4 of the semiconductor substrate 2, a composite layer including a first silicon dioxide film 20 as a first insulating material, a non-doped polysilicon film 22 as a polysilicon layer, and a second silicon dioxide film 24 as a second insulating material is stacked upward in this order, as shown in FIG. Figure 2 Next, a resist film 26 is formed on the surface of the second silicon dioxide film 24, and the resist film 26 in the region where the bit contact hole 18 is to be formed is removed by a photolithography method. In this state, a multilayer structure including the second silicon dioxide film 24, the non-doped polysilicon film 22, and the first silicon dioxide film 20 as a composite layer is patterned, thereby forming Figure 3 The bit contact hole 18 illustrated in FIG. 1 is formed. The active region 4 in which the cell transistor T is formed is exposed on the bottom of the bit contact hole 18. The side surface 22s of the non-doped polysilicon film 22 is exposed on the inner wall of the bit contact hole 18. Thereafter, the resist film 26 is removed.
[0012] Subsequently, the side surface 22s of the non-doped polysilicon film 22 exposed on the inner wall of the bit contact hole 18 is converted (eg, oxidized by ashing) to form a silicon dioxide film 30 as a third insulating material. Figure 4 As described in , the side surface 22s of the non-doped polysilicon film 22 is completely covered by the silicon dioxide film 30. The surface of the active region 4 is also oxidized by the ashing process.
[0013] Then, if Figure 5 2, after the silicon nitride film 32 as the additional material is completely formed, the silicon nitride film 32 is etched back. Therefore, the silicon nitride film 32 remains on the inner wall portion of the bit contact hole 18, as shown in FIG. Figure 6 As described in the foregoing. As a result, the side surface 22s of the non-doped polysilicon film 22 is covered by a double protective film including the silicon dioxide film 30 and the silicon nitride film 32. Thereafter, a pretreatment using hydrofluoric acid is performed to remove the silicon dioxide film formed on the surface of the active region 4. This pretreatment is a pretreatment for forming the doped polysilicon film 12A performed later. The silicon nitride film 32 has a sufficient film thickness to protect the silicon dioxide film 30 in the pretreatment described above, and the film thickness of the silicon nitride film 32 may be smaller than the film thickness of the silicon dioxide film 30.
[0014] Subsequently, a doped polysilicon film 12A is formed as a second additional material using a CVD (Chemical Vapor Deposition) method to fill the bit contact hole 18 therewith. Figure 7 The double protective film including the silicon dioxide film 30 and the silicon nitride film 32 is positioned between the doped polysilicon film 12A and the non-doped polysilicon film 22 filled in the bit contact hole 18. Therefore, the dopant (e.g., phosphorus (P)) included in the doped polysilicon film 12A is not diffused into the non-doped polysilicon film 22. In addition, even if the pre-treatment described above depletes part of the silicon nitride film 32, migration of the dopant does not occur because the side surface 22s of the non-doped polysilicon film 22 is covered by the silicon dioxide film 30.
[0015] Next, the doped polysilicon film 12A is etched back. Figure 8 The etch-back amount needs to be an amount that at least etches back the doped polysilicon film 12A until the top surface of the second silicon dioxide film 24 is exposed, and preferably etches back the doped polysilicon film 12A until the top surface of the doped polysilicon film 12A becomes substantially flush with the top surface of the non-doped polysilicon film 22.
[0016] Later, in Fig. 9 After the second silicon dioxide film 24 is removed as described in the above, the barrier metal layer 14, the metal layer 10A, the silicon nitride film 16A and the resist film 40 are stacked upward in this order, and the portion of the resist film 40 other than the region where the hard mask 16 is to be formed is removed by a photolithography method, as shown in FIG. Fig.10 In this state, the silicon nitride film 16A is patterned to form a hard mask 16, such as Fig.11 The metal layer 10A, the barrier metal layer 14, and the doped polysilicon film 12A / non-doped polysilicon film 22 are patterned using the hard mask 16 as a mask to form Figure 1 The bit line 10 and the bit line contact 12 described in the above can be patterned by overetching using the first silicon dioxide film 20 as a stopper. Therefore, the silicon dioxide film 30 formed on the side surface 22s of the non-doped polysilicon film 22 can be consumed at this stage. Next, an interlayer insulating film and a cell capacitor C ( Fig.11) and the like, thereby completing the DRAM according to this embodiment.
[0017] As described above, in the present embodiment, the side surface 22s of the non-doped polysilicon film 22 exposed on the inner wall of the bit contact hole 18 is covered by the double protective film including the silicon dioxide film 30 and the silicon nitride film 32. Therefore, the dopant (e.g., phosphorus (P)) contained in the doped polysilicon film 12A is not diffused into the non-doped polysilicon film 22. In addition, since it is sufficient that the silicon nitride film 32 has a minimum film thickness, a sufficient opening area of the doped polysilicon film 12A is ensured when etching the doped polysilicon film 12A, as shown in FIG. Fig.12 In the description, Fig.12 It is a plan view. Fig.12 The cross-sectional view of line A-A' corresponds to Fig.11 18 is a cross-sectional view of a region including the hole 18 in FIG. That is, if the film thickness of the silicon nitride film 32 is large, the opening area of the doped polysilicon film 12A is correspondingly reduced, and there is a risk of etching failure of the doped polysilicon film 12A due to the micro-loading effect. However, since the side surface 22s of the polysilicon film 22 is oxidized in the present embodiment, it is sufficient for the silicon nitride film 32 to have a minimum film thickness, and therefore etching failure of the doped polysilicon film 12A due to the micro-loading effect can also be prevented. The hard mask 16 is patterned along Fig.12 The B-B' line in is extended. Therefore, Figure 1 In the embodiment, the bit line 10 is patterned to extend along the line BB′ and is formed inside the bit contact hole 18 and on the first silicon dioxide film 20 .
[0018] As a second exemplary embodiment, Figure 1 The silicon nitride film 32 in the embodiment can be replaced by a polysilicon liner. Figure 5 In the embodiment, a doped or undoped polysilicon liner 32 is deposited. Then, the polysilicon liner 32 is etched back. Figure 6 Next, after cleaning, a doped polysilicon film 12A is formed on the polysilicon liner 32, as shown in FIG. Figure 7 In this case, because the silicon oxide film 30 is covered by the polysilicon liner 32, the silicon oxide film 30 is not removed by cleaning. Next, the doped polysilicon film is etched back to form a bit line contact (plug) as part of the doped polysilicon film 12A, as shown in FIG. Figure 8 In this case, the size (horizontal diameter) of the bit line contact of the second embodiment is larger than that of the bit line contact of the first embodiment having a dual material structure including the doped polysilicon film 12A and the silicon nitride film 32. Therefore, the second embodiment can more preferably prevent the micro loading problem.
[0019] Although various embodiments of the present disclosure have been disclosed in the context of specific preferred embodiments and examples, it will be appreciated by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and / or embodiments uses and obvious modifications and equivalents thereof. In addition, it will be readily apparent to those skilled in the art that other modifications within the scope of the present disclosure are possible. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and still fall within the scope of the present disclosure. It should be appreciated that the various features and aspects of the disclosed embodiments may be combined or replaced with one another to form a variation of the embodiments of the present disclosure. Therefore, it is desirable that the scope of at least some of the present disclosure should not be limited by the specific disclosed embodiments described above.
Claims
1. A method for forming a semiconductor device, wherein include: forming a composite layer, the composite layer comprising a first insulating material, a second insulating material, and a first polysilicon layer located between the first insulating material and the second insulating material; forming a hole in the composite layer, the hole penetrating the composite layer to define the first insulating material and the second insulating material and corresponding edge portions of the first polysilicon layer; converting the edge portion of the first polysilicon layer into a third insulating material such that the third insulating material is located between the corresponding edges of the first insulating material and the second insulating material; and After converting the edge portion of the first polysilicon layer into the third insulating material, an additional layer covering the sidewalls of the hole is formed.
2. The method according to claim 1, further comprising: include: After forming the additional layer, the hole is filled with a second polysilicon layer. 3 . The method of claim 2 , wherein a dopant concentration of the second polysilicon layer is greater than a dopant concentration of the first polysilicon layer. The method of claim 3 , wherein the first polysilicon layer comprises undoped polysilicon. The method of claim 3 , wherein the third insulating material is converted by oxidizing the edge portion of the first polysilicon layer. The method according to claim 5 , wherein the oxidizing is performed by an ashing process. The method of claim 3 , wherein the third insulating material is thicker than the additional layer. The method of claim 3 , wherein the additional layer is a silicon nitride layer.
9. The method of claim 3, wherein the additional layer is a polysilicon layer.
10. The method of claim 2, further comprising forming a metal layer on the second polysilicon layer.
11. The method of claim 1, wherein the first insulating material and the second insulating material comprise silicon oxide.
12. A method of forming a semiconductor device, wherein include: forming a composite layer comprising a first dielectric layer and a second dielectric layer and a first undoped polysilicon layer positioned between the first and second dielectric layers; patterning the composite layer to form an opening exposing a side surface of the undoped polysilicon layer; oxidizing the side surface of the non-doped polysilicon layer to form an oxide layer; forming an additional layer on the oxide layer; and The opening is filled with a doped polysilicon layer.
13. The method of claim 12, wherein the first dielectric layer and the second dielectric layer comprise silicon oxide. The method according to claim 12 , wherein the oxidizing is performed by an ashing process. The method of claim 12 , wherein the oxide layer is thicker than the additional layer.
16. The method according to claim 12, further comprising: include: Etching back the doped polysilicon layer until the second dielectric layer is exposed; removing the second dielectric layer to expose the undoped polysilicon layer; and The doped polysilicon layer and the undoped polysilicon layer are patterned simultaneously. 17 . The method of claim 16 , further comprising forming a metal layer on the doped polysilicon layer and the undoped polysilicon layer after the removing and before the patterning. The method of claim 17 , wherein the metal layer is a bit line.
19. A semiconductor device, include: A first insulating material having a first upper surface and a first side surface extending downward from an edge of the first upper surface; a first polysilicon material above the first insulating material, the first polysilicon material having a second upper surface and a second side surface extending downward from an edge of the second upper surface, the second side surface being recessed from the edge of the first upper surface of the first insulating material to expose a portion of the first upper surface; a second insulating material over the portion of the first upper surface of the first insulating material to cover the second side surface of the first polysilicon material, the second insulating material having a third side surface on a side opposite to the second side surface of the first polysilicon material; and An additional material covers the first side of the first insulating material and the third side surface of the second insulating material.
20. The semiconductor device of claim 19, wherein the additional material comprises a second polysilicon material.
21. The semiconductor device of claim 19, wherein the additional material comprises a third insulating material.
22. The semiconductor device according to claim 21, further comprising: include: A second additional material contacts the third insulating material and has a different composition than the third insulating material.
23. The semiconductor device of claim 22, wherein the third insulating material comprises silicon nitride.
24. The semiconductor device of claim 23, wherein the second additional material comprises polysilicon. 25 . The semiconductor device of claim 23 , further comprising a semiconductor substrate, wherein the semiconductor substrate comprises an active region, and wherein the second additional material is in contact with the active region.
26. The semiconductor device of claim 25, wherein a dopant concentration of the second additional material is greater than a dopant concentration of the first polysilicon material.
27. The semiconductor device of claim 26, wherein the first polysilicon material comprises undoped polysilicon.