A wireless communication circuit for reducing interference

Abstract

The present invention discloses a wireless communication circuit for reducing interference. The wireless communication circuit includes: a chip, a crystal, and an impedance element; the chip is provided with a crystal oscillator and a first ground port; the crystal is provided with a second ground port; the crystal oscillator is connected to the crystal; the impedance element is disposed between the crystal and the second ground port to block the disturbance of the second ground port from entering the crystal oscillator and at the same time reduce the influence of the disturbance of the first ground port on the crystal oscillator. The wireless communication circuit for reducing interference proposed by the present invention can reduce or even eliminate the influence of external interference signals on the crystal oscillator and improve the communication quality of the entire communication system.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and relates to a wireless communication circuit, and particularly to a wireless communication circuit for reducing interference. Background Art

[0002] With the progress of the times, science and technology have developed rapidly and gradually integrated into people's lives. Among them, the pursuit of miniaturization or even micro-miniaturization of devices has become increasingly urgent.

[0003] The miniaturization or even micro-miniaturization of electronic devices has brought unprecedented difficulties and challenges to the design of radio frequency systems. As the area of the circuit board becomes smaller, the lack of wiring resources and the complexity of the layout of electronic components increase sharply. Usually, electronic components that originally have electromagnetic interference have to be placed together to improve the integration degree. Typical miniaturized devices such as wireless Bluetooth earphones have to place components such as Bluetooth chips, power management chips, and even audio chips in an extremely narrow space, not to mention various passive components such as resistors, capacitors, and inductors that exist to cooperate with these chips. More challenging is that in order to obtain more functions and better performance, the number of pins of the chip increases instead of decreasing, which leads to more electronic components to be accommodated in a narrow space.

[0004] As the size of the printed circuit board (PCB) decreases, the ground layout of the entire circuit board will become less robust, which will lead to larger jitters on the ground wire, making the chip more vulnerable to interference. In addition, in order to save costs, more and more products use two-layer boards, making the ground layout even more difficult.

[0005] In a wireless communication system, in addition to chips, the two most important and essential components, crystals or crystal oscillators and antennas or antenna arrays, the mutual perturbation between them becomes stronger as the size of the PCB decreases and the number of layers decreases. At the lightest, it affects radio frequency performance, such as the sensitivity of the receiver and the error vector magnitude (EVM) of the transmitter, and at the heaviest, the entire communication system cannot work properly. Of course, digital systems, such as the communication between flash memory devices (FLASH) and chips, traditional serial communication (UART), etc. can also interfere with the radio frequency communication system. Therefore, how to effectively reduce the mutual interference between them becomes particularly important.

[0006] Since the signal voltage swing output by the power amplifier is very large, usually a part of the energy will be transmitted to the ground wire of the entire PCB. The magnitudes and phases of the perturbations received by the ground wires at different positions are different. As Figure 1 shown, the area ① shows the crystal oscillator circuit inside the chip, and the area ② shows the simplified model of the external crystal. Among them, R fbis the feedback resistor of the inverter, which provides a suitable DC bias voltage for the inverter. C L1 and C L2 are the on-chip load capacitors of the crystal oscillator. L0, L1, and L2 are the inductors for the connection lines from the internal pads PAD of the chip to the corresponding PINs of the chip package. The inductance values of these inductors may be different. R1 and R2 are the series resistors added to the two PINs of the crystal oscillator on the PCB board. These two resistor values can be different, or there can be only one resistor or no resistor at all. C p1 , C p2 are all the capacitors on the two pins of the external crystal oscillator of the chip, including but not limited to the parasitic capacitance of the traces of these two pins on the PCB board, the external load capacitance, and the internal parasitic capacitance of the crystal, etc. Interference usually deteriorates the quality of the output signal of the final power amplifier through the following several situations.

[0007] (1) The interference enters the crystal oscillator through the ground wire GND_0 inside the chip and generates a spurious frequency related to the frequency of the power amplifier and the frequency of the local oscillator at the output of the crystal oscillator. This spurious will affect the quality of the output signal of the local oscillator, thus affecting the final EVM

[0008] (2) The interference enters the crystal oscillator inside the chip through the ground wire GND_1 of the crystal and generates a spurious frequency related to the frequency of the power amplifier and the frequency of the local oscillator at the output of the crystal oscillator, thus affecting the final EVM

[0009] To reduce the influence of the external environment on the crystal oscillator, the crystal is usually placed as close to the chip as possible. Based on this consideration, the ground wire of the crystal and the ground wire of the chip are usually directly connected together. Then, the interference to the entire system through these two ground wires is random. For example, different parasitic capacitances, different board sizes, and different thicknesses and lengths of the connection lines between the chip ground wire and the crystal ground wire may all cause the deterioration of the quality of the final output RF signal.

[0010] Traditional solutions are generally divided into the following several methods:

[0011] (1) Adopt multi-layer PCB board layout and wiring to make the ground wire of the entire chip stable enough, so as to reduce the crosstalk of the output signal of the power amplifier to the ground wire to reduce its interference to the crystal oscillator. This method significantly increases the hardware cost compared with two-layer PCB.

[0012] (2) Increase the size of the PCB board to make the feed point of the antenna far away from the chip and the crystal, so as to reduce the crosstalk of the power amplifier to the ground wires of the above two points. This method is limited by the size of the PCB board and will increasingly not adapt to the overall trend of miniaturized design.

[0013] (3) By adding resistors R1 and R2, the interference from the outside is blocked from entering the crystal oscillator. At the same time, the impedance seen by the internal nodes of the crystal oscillator chip from the outside of the chip is increased, so that the input and output of the illustrated inverter swing with GND_0, turning the interference into common-mode noise and eliminating its influence. Adding a resistor to the crystal pin will, at best, increase the circuit power consumption, and at worst, cause the crystal oscillator not to oscillate, resulting in a fatal functional defect.

[0014] (4) By adding an external capacitor (as part of C p1 , C p2 ), GND_0 and GND_1 are forced to share the same ground. Similarly, the interference on the ground wire can be made to appear as common-mode noise to the crystal oscillator, thereby eliminating its influence on the output signal. However, adding an external load capacitor will increase the area of the PCB board and the cost of the entire hardware design.

[0015] In view of this, there is an urgent need to design a new wireless communication circuit for reducing interference in order to overcome at least some of the above-mentioned defects existing in the existing wireless communication circuits for reducing interference. Summary of the Invention

[0016] The present invention provides a wireless communication circuit for reducing interference, which can reduce or even eliminate the influence of external interference signals on the crystal oscillator and improve the communication quality of the entire communication system.

[0017] To solve the above technical problems, according to one aspect of the present invention, the following technical solution is adopted:

[0018] A wireless communication circuit for reducing interference, the wireless communication circuit comprising:

[0019] A chip provided with a crystal oscillator and a first grounding port;

[0020] A crystal provided with a second grounding port; the crystal oscillator is connected to the crystal;

[0021] An impedance element disposed between the crystal and the second grounding port for blocking the disturbance of the second grounding port from entering the crystal oscillator and at the same time reducing the influence of the disturbance of the first grounding port on the crystal oscillator.

[0022] As an embodiment of the present invention, the impedance element includes at least one of a resistor, an inductor, and a magnetic bead.

[0023] As an embodiment of the present invention, the impedance element is a resistor with a resistance value higher than a set threshold.

[0024] As an embodiment of the present invention, the second grounding port of the crystal is floating.

[0025] As an implementation manner of the present invention, the wireless communication circuit includes a circuit board.

[0026] As an implementation manner of the present invention, the crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with on-chip load capacitors, including a first capacitor and a second capacitor; the inductors of the connection lines from the pads inside the chip to the corresponding pins of the chip package include a first inductor, a second inductor, and a third inductor;

[0027] The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor;

[0028] The second ends of the first capacitor and the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded.

[0029] As an implementation manner of the present invention, all the capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor;

[0030] The second end of the third capacitor is respectively connected to the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.

[0031] As an implementation manner of the present invention, the third capacitor and the fourth capacitor are parasitic capacitors on the PCB board or load capacitors provided on the PCB board.

[0032] As an implementation manner of the present invention, the crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with on-chip load capacitors, including a first capacitor and a second capacitor; the inductors of the connection lines from the pads inside the chip to the corresponding pins of the chip package include a first inductor, a second inductor, and a third inductor;

[0033] All the capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor;

[0034] The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor;

[0035] The second ends of the first capacitor and the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded;

[0036] The second end of the first inductor is respectively connected to the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected to the second end of the crystal and the first end of the fourth capacitor;

[0037] The first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor;

[0038] The second end of the third capacitor is respectively connected to the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.

[0039] As an embodiment of the present invention, the chip further includes a power amplifier.

[0040] The beneficial effects of the present invention are as follows: The wireless communication circuit for reducing interference proposed by the present invention can reduce or even eliminate the influence of external signals on the crystal oscillator, and improve the communication quality of the entire communication system.

[0041] The structure of the present invention can be applied to any scenario using a crystal oscillator, and it does not change with the type, number of layers, and size of the PCB board. The resistor R0 does not affect the oscillation startup of the crystal oscillator and does not increase the power consumption of the crystal oscillator.

[0042] At the same time, the material cost of the resistor is lower than that of the capacitor, and compared with an external load capacitor, adding a resistor only requires one resistor position. In addition, if further cost savings are desired, the ground of the crystal can be floated (i.e., R0 is infinite), and this can also achieve the results expected by the present invention. Description of the Drawings

[0043] Figure 1 It is a schematic diagram of a simplified model of a traditional crystal oscillator circuit.

[0044] Figure 2 It is a schematic diagram of a simplified model of the wireless communication circuit in an embodiment of the present invention. Detailed Embodiments

[0045] The preferred embodiments of the present invention will be described in detail below with reference to the drawings.

[0046] In order to further understand the present invention, the preferred implementation schemes of the present invention will be described below in conjunction with embodiments. However, it should be understood that these descriptions are only for further explaining the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0047] The description of this part only focuses on several typical embodiments, and the present invention is not limited to the scope described in the embodiments. The mutual replacement of the same or similar prior art means and some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0048] "Connection" in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or conduction media; it may also include connection through other active devices or passive devices based on the same or similar functional purposes known to those skilled in the art, such as connection through circuits or components such as switches and follower circuits.

[0049] The present invention discloses a wireless communication circuit for reducing interference. Figure 2 It is a simplified model schematic diagram of the wireless communication circuit in an embodiment of the present invention; please refer to Figure 2 , the wireless communication circuit includes a chip, a crystal 2 and an impedance element. The chip is provided with a crystal oscillator 1 and a first ground port GND_0; the crystal 2 is provided with a second ground port GND_1; the crystal oscillator 1 is connected to the crystal 2; the impedance element 3 is arranged between the crystal 1 and the second ground port GND_1 to block the disturbance of the second ground port GND_1 from entering the crystal oscillator 1, and at the same time reduce the influence of the disturbance of the first ground port on the crystal oscillator. In an embodiment of the present invention, the impedance element includes at least one of a resistor, an inductor, and a magnetic bead.

[0050] As Figure 2 shown, in an embodiment, the impedance element is a resistor R0; the resistance value of the resistor R0 can be higher than a set threshold. In an embodiment of the present invention, the second ground port of the crystal 2 can be floated (i.e., the resistor R0 is infinite), and the desired effect of the present invention can also be achieved. In an embodiment of the present invention, the wireless communication circuit may include a circuit board and may also include an antenna; the chip may include a power amplifier.

[0051] Please continue to refer to Figure 2 , in an embodiment of the present invention, the crystal oscillator 1 includes an inverter 11 and a feedback resistor R fb ; the crystal oscillator 1 is provided with on-chip load capacitors, including a first capacitor C L1 , a second capacitor C L2 ; the inductances of the connections from the internal pads of the chip to the corresponding pins of the chip package include a first inductor L1, a second inductor L0, and a third inductor L2. The input end of the inverter 11 is respectively connected to the first end of the feedback resistor R fb , the first end of the first capacitor C L1 , and the first end of the first inductor L1; the output end of the inverter 11 is respectively connected to the second end of the feedback resistor R fb , the first end of the second capacitor C L2 , and the first end of the third inductor L2; the second end of the first capacitor C L1 , the second end of the second capacitor C L2The second ends are respectively connected to the first end of the second inductor L0; the second end of the second inductor L0 is grounded.

[0052] Please continue to refer to Figure 2 , in an embodiment, all the capacitances of the two pins of the crystal 2 are respectively the third capacitor C p1 and the fourth capacitor C p2 ; the second end of the first inductor L1 is respectively connected to the first end of the crystal 2 and the first end of the third capacitor C p1 , the second end of the third inductor L2 is respectively connected to the second end of the crystal 2 and the first end of the fourth capacitor C p2 . The second end of the third capacitor C p1 is respectively connected to the second end of the fourth capacitor C p2 and the first end of the resistor R0; the second end of the resistor R0 is grounded. In an embodiment, the third capacitor C p1 and the fourth capacitor C p2 are parasitic capacitances on the PCB board or load capacitances provided on the PCB board.

[0053] In addition, a resistor can be provided between the first inductor L1 and the third capacitor C p1 , and a resistor can be provided between the third inductor L2 and the fourth capacitor C p2 .

[0054] In the present invention, a resistor R0 is connected in series between the crystal 2 and the ground GND_1. While blocking the disturbance of the ground GND_1 from entering the crystal oscillator, the impedance seen from the inside of the chip to the outside of the chip is increased, so that the input and output ends of the inverter 11 swing following the ground GND_0 to eliminate its influence on the output signal quality. The resistance value of the resistor R0 can be adjusted according to actual applications. In extreme cases, the resistor R0 can even be designed to be infinite (the crystal is floating). In addition, theoretically, the function of the resistor R0 is to block the radio frequency signal from entering the chip. Therefore, an inductor or a magnetic bead can also provide a certain impedance at the radio frequency signal frequency, so as to achieve the same effect as adding a resistor.

[0055] The present invention is not limited to specific applications. Its core content is to connect an impedance R0 in series between the crystal and GND_1. The impedance R0 can be realized in the form of a resistor, an inductor or a magnetic bead. The purpose is to block the disturbance of GND_1 from entering the crystal oscillator while increasing the impedance seen from the inside of the chip to the outside of the chip, so that the input and output ends of the illustrated inverter swing following GND_0 to eliminate its influence on the output signal quality. Therefore, regardless of the frequency of the crystal oscillator, whether an external load capacitor is applied, and whether a resistor is connected in series on xtal_in or xtal_out, the scheme of connecting an impedance in series between the crystal and the ground is beneficial to reducing the magnitude of interference entering the signal path through the ground wire.

[0056] In summary, the wireless communication circuit for reducing interference proposed by the present invention can reduce or even eliminate the influence of external signals on the crystal oscillator, and improve the communication quality of the entire communication system.

[0057] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0058] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above embodiments. The effects or advantages involved in the embodiments may not be reflected in the embodiments due to various factors. The description of the effects or advantages is not used to limit the embodiments. The modifications and changes of the embodiments disclosed here are possible, and the substitutions and equivalent components of the embodiments are well known to those of ordinary skill in the art. Those skilled in the art should clearly understand that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the present invention. Other modifications and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A wireless communication circuit for reducing interference, characterized in that, The wireless communication circuit includes: a chip provided with a crystal oscillator and a first ground port; a crystal provided with a second ground port; the crystal oscillator is connected to the crystal; an impedance element disposed between the crystal and the second ground port for blocking the disturbance of the second ground port from entering the crystal oscillator and reducing the influence of the disturbance of the first ground port on the crystal oscillator; the crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with on-chip load capacitors including a first capacitor and a second capacitor; inductors for connecting the internal pads of the chip to the corresponding pins of the chip package, including a first inductor, a second inductor, and a third inductor; the input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor; the second ends of the first capacitor and the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded; all the capacitors of the two pins of the crystal are a third capacitor and a fourth capacitor respectively; the first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor; the second end of the third capacitor is respectively connected to the second end of the fourth capacitor and the first end of the impedance element; the second end of the impedance element is grounded.

2. The interference-reducing wireless communication circuit according to claim 1, wherein: the impedance element includes at least one of a resistor, an inductor, and a magnetic bead.

3. The interference-reducing wireless communication circuit according to claim 1, wherein: the impedance element is a resistor with a resistance value higher than a set threshold.

4. The interference-reducing wireless communication circuit according to claim 1, wherein: the second ground port of the crystal is floating.

5. The interference-reducing wireless communication circuit according to claim 1, wherein: the wireless communication circuit includes a circuit board.

6. The interference-reducing wireless communication circuit according to claim 1, wherein: the third capacitor and the fourth capacitor are parasitic capacitors on the PCB board or load capacitors provided on the PCB board.

7. The interference-reducing wireless communication circuit according to claim 1, wherein: the crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with on-chip load capacitors including a first capacitor and a second capacitor; inductors for connecting the internal pads of the chip to the corresponding pins of the chip package, including a first inductor, a second inductor, and a third inductor; all the capacitors of the two pins of the crystal are a third capacitor and a fourth capacitor respectively; the first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor; the input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor, and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor, and the first end of the third inductor; The second terminal of the first capacitor and the second terminal of the second capacitor are respectively connected to the first terminal of the second inductor; the second terminal of the second inductor is grounded; The second terminal of the first inductor is respectively connected to the first terminal of the crystal and the first terminal of the third capacitor, and the second terminal of the third inductor is respectively connected to the second terminal of the crystal and the first terminal of the fourth capacitor; The first terminal of the crystal is connected to the first terminal of the third capacitor, and the second terminal of the crystal is connected to the first terminal of the fourth capacitor; The second terminal of the third capacitor is respectively connected to the second terminal of the fourth capacitor and the first terminal of the impedance element; the second terminal of the impedance element is grounded.

8. The interference-reducing wireless communication circuit according to claim 1, wherein: The chip further includes a power amplifier.

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