Layout of a Fault-Tolerant Quantum Computer

Abstract

Examples of layouts and layout generation techniques for fault-tolerant quantum computers are disclosed herein. Example embodiments include methods for performing layout simplification techniques for fault-tolerant quantum computing. In certain embodiments, the layout of any quantum circuit is simplified to a layout of an exponent of multi-qubit Pauli matrices and measurements of multi-qubit Pauli matrices. In certain embodiments, qubits are labeled as one of data qubits, interface qubits, or ancilla qubits for a 2D nearest-neighbor qubit connectivity graph, and ancillary paths are provided from corresponding data qubits to corresponding interface qubits.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 681,540, filed on Jun. 6, 2018, entitled “Layout of Fault-Tolerant Quantum Computers”, the entire content of which is incorporated herein by reference. SUMMARY OF THE INVENTION

[0003] Example layouts and layout generation techniques for fault-tolerant quantum computers are disclosed herein. The particular embodiments described should not be construed as limiting because the disclosed method acts can be performed separately, in a different order, or at least partially simultaneously with each other. Further, any one of the disclosed method or method acts can be performed using any other method or method act disclosed herein. Similarly, the disclosed combinations of features can include rearrangements of any novel or non-obvious combination or sub-combination of features.

[0004] One example embodiment includes a method for performing layout simplification techniques for fault-tolerant quantum computing. In a particular embodiment, the method is performed by one or more classical computing devices, where at least some of the one or more classical computing devices are in a configuration that can operate a quantum computer. In certain embodiments, the layout of any quantum circuit is simplified to a layout of an exponential of multi-qubit Pauli matrices and measurements of multi-qubit Pauli matrices; and the quantum computer is configured to implement the simplified layout. In a particular implementation, the qubits of the quantum computer include data qubits, interface qubits, and ancilla qubits. In other implementations, the qubit connectivity graph satisfies a condition of providing an auxiliary path from one or more data qubits to an interface qubit.

[0005] Another example embodiment includes another method for performing layout techniques for fault-tolerant quantum computing. In a particular embodiment, the method is performed by one or more classical computing devices, where at least some of the one or more classical computing devices are in a configuration that can operate a quantum computer. In certain embodiments, the qubits are labeled as one of data qubits, interface qubits, or ancilla qubits for a 2D nearest neighbor qubit connectivity graph; an auxiliary path is provided from a corresponding data qubit to a corresponding interface qubit; and the quantum computer is configured to implement the auxiliary path from the corresponding data qubit to the corresponding interface qubit. In certain implementations, the method takes into account and avoids any broken qubits and satisfies the condition of providing an auxiliary path from the data qubit to the interface qubit.

[0006] Any of the methods described above can be performed in a system that includes a quantum computing device; and one or more classical computing devices, where at least some of the classical computing devices are programmed to perform any of the disclosed methods.

[0007] Additionally, any of the methods described above can be implemented as one or more classical computer-readable media storing classical computer-executable instructions that, when executed by a classical computer, cause the classical computer to perform any of the disclosed methods.

[0008] Other embodiments include a quantum circuit configured to apply an exponentiation of a multi-qubit Pauli matrix and measure the multi-qubit Pauli matrix. In some implementations, an auxiliary path is provided from data qubits to interface qubits. In other implementations, the depth of the quantum circuit does not depend on the number of vertices. In some implementations, the quantum circuit uses a single-depth multi-target CNOT gate or a low-depth multi-target CNOT gate as a sub-circuit.

[0009] Some embodiments include a quantum circuit configured to: (a) provide a multi-target CNOT gate using single-qubit Pauli measurements, two-qubit Pauli measurements, and single-qubit Clifford gates; or (b) provide a multi-target CNOT gate using single-qubit, Pauli measurements, single-qubit Clifford gates, and controlled-Z gates. In some implementations, the quantum circuit provides a multi-target CNOT gate using single-qubit Pauli measurements, two-qubit Pauli measurements, and single-qubit Clifford gates, where the quantum circuit acts on qubits for which the qubit connectivity graph satisfies the condition of providing an auxiliary path from the target qubit to the control qubit. In other implementations, the quantum circuit provides a multi-target CNOT gate using single-qubit Pauli measurements, two-qubit Pauli measurements, and single-qubit Clifford gates, where the depth of the quantum circuit does not depend on the number of vertices. In some implementations, the quantum circuit is configured to use single-qubit, Pauli measurements, single-qubit Clifford gates, and controlled-Z gates to provide a multi-target CNOT gate, and where the quantum circuit acts on qubits for which the qubit connectivity graph satisfies the condition of providing an auxiliary path from the target qubit to the control qubit. In other implementations, the quantum circuit is configured to use single-qubit, Pauli measurements, single-qubit Clifford gates, and controlled-Z gates to provide a multi-target CNOT gate, where the depth of the quantum circuit does not depend on the number of vertices.

[0010] The foregoing and other objects, features, and advantages of the disclosed technology become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic block diagram of a circuit representing a CNOT gate between a top qubit and a bottom qubit.

[0012] Figure 2 is a schematic block diagram showing an example of providing a multi-target CNOT gate through measurement.

[0013] Figure 3 is a diagram showing that after moving the purple measurement to the left to parallelize the last red block between the ancilla and the target, Figure 2 a schematic block diagram of a modified version of

[0014] Figure 4 is a schematic block diagram showing further modification of the initial measurement to parallelize the purple block between the control qubit and the ancilla (the effect of this parallelization only appears when there are more than two targets).

[0015] Figure 5 is a schematic block diagram of another general circuit according to an embodiment of the disclosed technology.

[0016] Figure 6 is a schematic block diagram of an example circuit for propagating the Pauli operator X C

[0017] Figure 7 represents Figure 6 a block diagram of the planar layout of a multi-target CNOT gate of

[0018] Figure 8 is a flowchart showing a general method for implementing an embodiment of the disclosed technology.

[0019] Figure 9 is a flowchart showing another general method for implementing an embodiment of the disclosed technology.

[0020] Figure 10 illustrates a general example of a suitable classical computing environment in which various aspects of the described embodiments can be implemented.

[0021] Figure 11 shows an example of a possible network topology (e.g., a client-server network) for implementing a system according to the disclosed technology.

[0022] Figure 12 shows another example of a possible network topology (e.g., a distributed computing environment) for implementing a system according to the disclosed technology.

[0023] Figure 13 ​An exemplary system for implementing the disclosed quantum computing techniques is shown. Detailed Description

[0024] 1. General Considerations

[0025] As used in this application, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" include plural forms. Additionally, the term "includes" means "comprises". Further, the term "coupled" does not exclude the existence of intermediate elements between the coupled items. Further, as used herein, the term "and / or" means any one or any combination of the items in the phrase.

[0026] Although the operations of some of the disclosed methods are described in a particular order for convenience of presentation, it should be understood that this description style covers rearrangements unless the specific language set forth below requires a particular order. For example, in some cases, the operations described in sequence may be rearranged or performed simultaneously. Also, for simplicity, the figures may not show the various ways in which the disclosed systems, methods, and devices can be used in conjunction with other systems, methods, and devices. Additionally, the description sometimes uses terms such as "generate" and "provide" to describe the disclosed methods. These terms are high-level abstractions of the actual operations being performed. The actual operations corresponding to these terms vary depending on the particular implementation, and one of ordinary skill in the art can readily discern these actual operations.

[0027] 2. Quantum Computing Preliminaries and Notation

[0028] Let I, X, Y, and Z denote the single-qubit Pauli matrices. All single-qubit Pauli matrices are Hermitian matrices. The square of each Pauli matrix is equal to I. Multi-qubit Pauli matrices are tensor products of single-qubit Pauli matrices (which is denoted as ). The notation X k , Y k , Z k refers to the multi-qubit Pauli matrix where X, Y, and Z are on qubit k and I is on all other qubits. For example, X2 as a 3-qubit Pauli matrix refers to the following matrix:

[0029]

[0030] Multi-qubit Pauli matrices are also Hermitian matrices, and their squares are the identity matrix. Multi-qubit Pauli matrices are hereinafter simply referred to as Pauli matrices. I is the identity matrix on any number of qubits. The dimension of I can be clearly seen from the context.

[0031] Notation \(P^{[k]}\) k The \(k\)-th component of the Pauli matrix for multi-qubits. For example, for \(P = X\) a \(Y\) b \(Z\) c , \(P^{[1]}\) a \(= X\), \(P^{[2]}\) b \(= Y\), and \(P^{[3]}\) c \(= Z\).

[0032] For any square matrix \(A\), \(Tr(A)\) is the sum of the diagonal elements of \(A\). For any square matrices \(A\) and \(B\), it holds that \(Tr(AB)=Tr(BA)\). Additionally,[[]]

[0033] An orthogonal projector is a Hermitian matrix \(C\) with the property \(C^{2}=C\). \(Tr(C)\) is equal to the dimension of the subspace onto which \(C\) projects.[[]]

[0034] If \(AB = BA\), then matrices \(A\) and \(B\) commute. If \(AB=-BA\), matrices \(A\) and \(B\) anti-commute. Any two Pauli matrices either commute or anti-commute.[[]]

[0035] The positive state \(|+\rangle\) is

[0036] \(H\) k is the Hadamard gate on qubit \(k\). This \(H\) k is equal to

[0037] A single-qubit Clifford gate is the product \(HP\), \(SP\), \(HSP\), \(SHP\), \(HSHP\), where \(P\) is \(I\), \(X\), \(Y\), \(Z\). A single-qubit Clifford gate also includes the Pauli matrices \(X\), \(Y\), \(Z\).[[]]

[0038] \(CZ\) ij is the controlled-Z gate on qubits \(i\) and \(j\). This \(CZ\) ij is equal to \((I + Z^{[i]}Z^{[j]})\) i \(+ Z^{[i]}-Z^{[j]}\) j \(-Z^{[i]}Z^{[j]}\) i \(Z^{[i]}Z^{[j]}\) j ).

[0039] If the state \(|\psi\rangle\) is the +1 eigenvector of \(M\), then the Hermitian matrix \(M\) stabilizes the state \(|\psi\rangle\). In other words, \(M|\psi\rangle = |\psi\rangle\).[[]]

[0040] The \(n\)-qubit cat state is the state also known as the GHZ state

[0041] Let \(U\) be some unitary and let It can be said that \(U\) maps \(P\) to \(Q\).

[0042] 3. Quantum Circuit Layout Problem

[0043] In this section, example embodiments of algorithms for solving special cases of the following problems are disclosed:

[0044] Problem 3.1 (Layout Problem of a Graph). Let (V, E) be a graph, and V rot be a subset of V. The vertices are qubits. Consider a quantum computation that uses single-qubit Clifford operations, two-qubit Clifford operations, single-qubit rotations exp(iφZ), and single-qubit measurements. The quantum computation that produces the same measurement result is performed using the following:

[0045] · A single-qubit measurement and a single-qubit Clifford unitary,[[]]

[0046] · (A) A controlled-Z gate or (B) a two-qubit measurement on qubits connected by an edge

[0047] · Single-qubit rotations exp(iφZ) can only be performed on the subset Vro t

[0048] Using two (e.g., only two) qubit measurements on each edge is more restrictive. Any two-qubit measurement can always be performed using two controlled-Z gates, one measurement, and single-qubit Clifford gates. However, it is not possible to perform a controlled-Z gate on these two qubits by only measuring these two qubits. The constraint on the qubits (on which single-qubit rotations can be performed) reflects the fact that performing these rotations on a fault-tolerant quantum computer typically uses resource states that are often generated in a dedicated part of the computer. The subset V rot represents qubits as follows, where the resource state required to implement the rotation can be easily delivered to the qubit.

[0049] The above problem can also be reduced to the case where V rot contains one element r and (V, E) is a tree rooted at r. In fact, for any graph (V, E), we can compute a spanning tree rooted at r. First, the solution to this case is described.

[0050] The first part of the example solution is to transform the quantum computation into a canonical solution. In this article, the notation M(a, P) = (I + aP) / 2 is used for measuring any multi-qubit Pauli operator P with the result a = ±1. Suppose we have an n-qubit quantum computation, which is described as follows:

[0051] (1) ​

[0052] C k are Clifford operators. Recall that for any Clifford operator C and Pauli matrix P, the product is a Pauli matrix. Also recall that exponentiation and measurement both have the following properties:

[0053] (2)

[0054] We can rewrite the quantum computation (1) as follows:

[0055]

[0056] Using the properties (2) of measurement and exponentiation, we can also rewrite the computation as follows:

[0057] where C′ = C2C1C0.

[0058] Finally, we can transform any quantum computation into a sequence of measurements and exponentiations of multi-qubit Clifford operations and Clifford gates. Finally, since this information is not extracted from the quantum computer after execution, there is no need to perform Clifford gates.

[0059] To perform an arbitrary computation under the constraints described in Problem 3.1, it is sufficient to be able to perform measurements M(a, P) and exp(iφP) on any Pauli matrix supported on some qubits The size of the subset V data determines the maximum number of qubits we can use for computation. Under the constraints of the two-qubit operations described in Problem 3.1, it is sufficient to be able to perform Clifford C and such that As described in Section 4, such Clifford operations can be constructed using multi-target controlled-Z gates. Tables 1 and 2 show the programs for such Clifford C operations using multi-target controlled-Z gates. The program in Table 1 applies controlled-Z gates on the edges of the tree, while the program in Table 2 applies two-qubit measurements. When this construction is used for Clifford C, the set V data corresponds to all the leaves of the tree except the root.

[0060] In Section 5, a description is provided on how to construct a tree with a high ratio of the number of leaves to the number of vertices in a 2D nearest-neighbor architecture. Additionally, this is the case when a portion of the qubits in the 2D nearest-neighbor architecture are broken. It has been found that when the breakage ratio exceeds 90%, we can still utilize a large number of qubits for computation.

[0061]

[0062] Table 1: Program of Pauli mapper using controlled-Z gates

[0063] 4. Low-depth multi-target controlled-Z gates

[0064] This section describes two ways to perform low-depth multi-target controlled-Z gates. One way is applicable to architectures with native controlled-Z gates. Another way is for architectures with two-qubit operations that are constrained to only measurements of two-qubit Pauli matrices. Both are notable for low-depth circuits for cat state preparation and for fan-out gates. Hereinafter, qubits are regarded as vertices of a tree, and only two-qubit operations are allowed.

[0065]

[0066] Table 2: Example programs of Pauli mapper using two-qubit Pauli measurements

[0067]

[0068] Table 3: Program for preparing low-depth cat states between qubits connected by edges. Recall that when we need to perform measurements of qubits a and b, it is equivalent to the following:[[]] preparation. Recall that when we need to perform measurements of qubits a and b, it is equivalent to the following:[[]] measurement, it is equivalent to the following:[[]]

[0069]

[0070] The next proposition shows that the circuit depth required to prepare a cat state on a tree does not depend on the number of tree vertices.

[0071] Proposition 4.1 (Low-depth cat state preparation). Let (V, E) be a tree. The vertices of the tree correspond to qubits. All qubits are in the plus state. Only the following operations can be applied:[[]]

[0072] · Measure observables on qubits connected by edges

[0073] · Apply Pauli X to any one of the qubits other than a pre-selected qubit w.

[0074] Then, a cat state on the qubits corresponding to the vertices can be prepared with a depth equal to the maximum vertex degree, using measurements. Additionally, we need to perform at most |V| - 1 Pauli X operations all in parallel. Table 3 gives the pseudocode for cat state preparation.

[0075] Proof. First, it is shown that the process on Table 3 does indeed prepare a cat state. Recall that the cat state on n = |V| qubits The only one can be described by the following constraints (until the global stage):

[0076]

[0077] In fact, the above implies that |ψ> is stabilized by the following projection operators:

[0078]

[0079] Next, expand the above product into a sum of Pauli matrices. Use |E| = |V| - 1, and the trace of all non-identity Pauli matrices is zero, to check Tr(P) = 1. It is concluded that P fixes a one-dimensional subspace.

[0080] Initializing all qubits to the |+> state ensures that their joint state is stabilized by Π v∈V X v . Measuring Z u Z v for (u, v) ∈ E ensures that the state is in the +1 or -1 eigenstate of Z u Z v . It should be noted that since all constraints commute, adding new constraints via measurement preserves all previous constraints. When all measurements are performed and the edges are flagged, the state of the qubit |φ> satisfies the following constraints:

[0081]

[0082] It still needs to fix the -1 sign. This can be done by applying the single-qubit Pauli X operator to the vertex. If we do not apply X to the vertex, we can flag the vertex with 0, and if we apply X to the vertex, we can flag the vertex with 1. This changes the sign in the following way:

[0083]

[0084] The label assignment can be found by a one tree traversal (e.g., using depth-first search). The label of the root of the tree can be chosen to be zero. Based on the label of the parent and the label of the edge connecting the vertex and its parent, the label of each vertex is calculated.

[0085] Finally, it should be noted that the edges of each color do not share vertices. Therefore, the measurements on the corresponding qubits can be performed in parallel. This implies that the depth of the measurement part of the cat state preparation is equal to the chromatic number of the tree, which is the maximum vertex degree plus one.

[0086] Given an n-qubit cat state, it is sufficient to perform a two-qubit measurement once to obtain a fan-out gate from one qubit to n + 1 qubits.

[0087]

[0088] The next proposition intuitively explains how a one - two - qubit measurement helps to perform a partially - specified unitary acting on \(n + 1\) qubits.

[0089] Proposition 4.2 (Unitary Operations via Measurements). Let \(|\psi\rangle\) be a multi - qubit state and \(P\) be a multi - qubit Pauli matrix that stabilizes \(|\psi\rangle\) (e.g., \(P|\psi\rangle=|\psi\rangle\)). Let \(Q\) be another multi - qubit Pauli matrix that anti - commutes with \(P\). Then, the probability of measuring \(+ 1\) for the observable \(Q\) of \(|\psi\rangle\) is \(1 / 2\). Moreover, if the measurement result is \(-1\), then applying \(P\) conditioned on the result \(-1\) is equivalent to measuring \(+1\). Under the above conditions, we can always deterministically apply the following transformation to \(|\psi\rangle\) via measurement:

[0090] (3)

[0091] Proof. First, it is shown that the probability of measuring \(+1\) is \(1 / 2\). This can be shown by showing that the probabilities of measuring \(+1\) and measuring \(-1\) are equal. Recall that the probability of measuring \(\pm1\) is Next, use the fact that \(P\) stabilizes \(|\psi\rangle\) and the anti - commutation of \(P\) and \(Q\) to check the following equality:

[0092]

[0093] We can see that when the measurement result is \(+1\), the state is transformed according to (3).

[0094] Next, check that this is also the case when the measurement result is \(-1\), and apply the correction \(P\).

[0095]

[0096] Table 4: Program for MeasurePlusOne

[0097] If the measurement result is \(-1\), then we can apply the correction \(P\), and the state becomes:

[0098]

[0099] Above, use the anti - commutation of \(P\) and \(Q\), and the fact that \(P\) stabilizes \(|\psi\rangle\). Finally, we can note that \((I + Q)|\psi\rangle=(I + QP)|\psi\rangle\), and use the fact that for any matrix \(A\), \(\exp(\varphi A)=I\cos(\varphi)+A\sin(\varphi)\) by squaring it to subtract the identity.

[0100] It has been shown that under the conditions of Proposition 4.2, measurement with classical feedback is equivalent to a unitary transformation. This is because QP is an anti-Hermitian matrix, and is a unitary matrix. It should be noted that the unitary operation performed includes the Pauli P. Even if Q acts only on a pair of qubits, the operation result can be equivalent to a unitary element on a large number of qubits. This occurs when the constraint P involves a large number of qubits.

[0101] The above discussion motivates the introduction of the operation MeasurePlusOne(Q / P) (see Table 4). The operation MeasurePlusOne(Q / P) performs the operation given by Equation (3), assuming that the state to which Equation (3) is applied is stabilized by P. In other words, the operation MeasurePlusOne always projects the state onto the +1 eigenspace of Q. We can call P the constraint on the state.

[0102] Now, it is shown how MeasurePlusOne can be used to perform a fanout gate.

[0103] Proposition 4.3 (Low-depth fanout). Let (V, E) be a tree. The vertices of the tree correspond to qubits. Except for the root of the tree, all qubits are in the |+> state. We can only apply the following operations:

[0104] · Measure the observable on the qubits connected by the edge

[0105] · Apply the Pauli X to any one of the qubits.

[0106]

[0107] Table 5: Fanout gate procedure

[0108] With a depth equal to the maximum vertex degree, using measurement, a fanout gate from the root to all qubits can be performed. Additionally, we need to perform at most |V| - 1 Pauli X operations all in parallel. Table 5 gives the pseudocode for the fanout gate.

[0109] Proof. First, the correctness of the operation Fanout1 in Table 5 is shown. Next, it is shown that the operation Fanout1 is equivalent to the operation Fanout described on the same table. The claim about the depth of the measurement in the proposition stems from the fact that the number of colors in the edge coloring of the tree is equal to the maximum vertex degree plus 1.

[0110] Let the state of the root vertex be α|0> + β|1>. According to Proposition 4.2, the last three rows of operations Fanout1 in Table 4 deterministically project onto Z r Zr′ on the +1 eigenspace. This is because the cat state is stabilized by the product of X over all non-root vertices of the tree, and this product anti-commutes with Z r Z r′ anti-commutes. Thus, after the last three lines of Fanout1, the state of all qubits becomes:

[0111]

[0112] This is because the projection operator (I + Z1Z2) / 2 selects the computational basis states where the first two bits are equal:

[0113]

[0114] Next, check whether the operations Fanout and Fanout1 on Table 5 are equivalent. First, we can inline CatStatePrep. Next, we can observe that no X correction is performed on vertex r' before measuring Z r Z r′ before the measurement of Z r Z r′ can be performed together with all other measurements. Finally, the X correction applied at the end of CatStatePrep is combined with the X correction applied at the end of the operation Fanout1.

[0115] Next, provide a description of how to perform multi-target controlled-Z using the fanout gate. We can start with the case that is more suitable for an architecture with native controlled-Z gates.

[0116] Proposition 4.4 (Low-depth multi-target controlled-Z). Let (V, E) be a tree. The vertices of the tree correspond to qubits. The qubits that are not leaves are in the plus state. The measurements of observables and controlled-Z gates can only be applied to qubits connected by edges. The program given in Table 6 performs a multi-target controlled-Z gate, where the root of the tree is the control and the remaining leaves are the targets. The remaining tree vertices return to the plus state.

[0117] The depth of the joint measurement is at most the maximum vertex degree. The depth of the controlled-Z gates is at most the maximum vertex degree. The total number of joint measurements and controlled-Z operations applied is equal to the total number of edges. The depth of the X measurement is one.

[0118]

[0119] Table 5: Program for the multi-target controlled-Z gate.

[0120] Evidence. First, the program MultipleTargetControlledZ1 on Table 6 is shown to perform the multi-target controlled-Z gate and satisfy the required post-condition. Next, it is shown that this program is equivalent to MultipleTargetControlledZ. Finally, the depth of the operations performed in MultipleTargetControlledZ is counted.

[0121] Recall that in the computational basis state, the multi-target controlled-Z gate is as follows:

[0122]

[0123] Above the first qubit are the controls, and the rest are the targets. In this case, the controls and targets are the leaves of the tree. We also have other (e.g., m) qubits that are not leaves of the tree. Using the fan-out operation, the state is transformed to:

[0124]

[0125] After the first foreach loop, the state becomes:

[0126] (4)

[0127] This is because a controlled-Z gate is performed between each target qubit in the target qubits and some qubit that is not a leaf of the tree and is in the |c> state. It should be noted that the above state (4) is the +1 eigenstate of all Z r Z v operators, where r is the root and control qubit, and v is a non-leaf ancilla qubit. For this, we can use the MeasurePlusOne operation to set all non-leaf ancilla qubits back to the positive state. It is important to note that setting one of the non-leaf ancilla qubits to the positive state does not violate the Z r Z v constraints on the other qubits, so this can be done in parallel.

[0128] To obtain the MultipleTargetControlledZ program, we can inline all calls to MeasurePlusOne. Next, we can observe that all measurements can be performed first, and then the corrections can be performed. As shown below, we can also aggregate all the corrections applied to the root vertex so that the corrections can be applied once.

[0129] To count the measurement depth, we can observe that these The measurements are all performed within the fan-out operation, and the maximum vertex degree (V', E') is at most the maximum vertex degree (V, E). The depth of the controlled-Z operation performed is at most the number of edges that share a vertex of maximum vertex degree.

[0130] The rest of this section is dedicated only to the architecture with two-qubit measurements. First, let's review how to perform a Controlled-Z gate with one extra qubit in this architecture. It is convenient to express this result in a concise way using MeasurePlusOne(Q / P). This result will also help us gain an understanding of multi-target Controlled-Z.

[0131] Proposition 4.5. Consider three qubits a, b, and c, where qubit a is in the |+> state. Then, the following operation performs a controlled-Z gate between qubits t and c and returns qubit a to the +> state:

[0132]

[0133] Proof. First, we check that all MeasurePlusOne can be applied. The qubit a is in |+>, so the input state is determined by X a Stable. After the first step, as a result of the measurement, the overall state is consistent with Z b Z a After applying Hadamard to the second qubit, the state is Exchange, the It happens to be Z t X a After the third step, according to the requirements of step 4, the state is the same as Z a Z c exchange.

[0134] Now, we can show that a controlled +Z gate is indeed executed. It is sufficient to consider the case when all three qubits are in the tensor product state. Suppose qubit t is in the state α t |0>+β t |1> state. After step 1, the state of qubit t, a becomes:

[0135] α t |00>+β t |11>

[0136] After step 2, the state of the qubit t, a is (through Until standardization):

[0137] α t |00>+α t |01>+β t |10>-β t|11>

[0138] Assume that qubit c is in the state α c |0> + β c |1>. Then, after step 3, the state of all three qubits becomes:

[0139] α t α c |000> + α t β c |011> + β t α c |100> - β t β c |111>.

[0140] Finally, measuring X a transforms the state to:

[0141] α t α c |0+0> + α t β c |0+1> + β t α c |1+0> - β t β c |1+1>.

[0142] We can see that the state of the second qubit is |+>, and the joint state of the first and third qubits is as follows:

[0143]

[0144] Let us compare the above program for controlled-Z with the version of the MultipleTargetControlledZ operation applied to a tree with three vertices c, t, a and edges (c, a) and (a, t) via measurement:

[0145]

[0146] The difference is that Hadamard followed by MeasurePlusOne(Z a Z t / Z r X a ) replaces the call to controlled-Z. The result shows that they perform a unitary similar to controlled-Z.

[0147] Proposition 4.6. The following two operations H2; for a, b zero or one, MeasurePlusOne(Z2Z3 / Z1X2) map the computational basis state |aab| to (-1) ab |abb>.

[0148] Evidence. Applying the Hadamard gate transforms the input state to:

[0149]

[0150] The result of MeasurePlusOne(Z2Z3 / Z1X2) is as follows:

[0151]

[0152] This is because (I + Z2Z3) / 2 projects onto the span of |00> and |11>.

[0153] Using this operation, we can construct a multi-target controlled-Z gate using only joint measurements and single-qubit operations.

[0154]

[0155] Table 7: Program for the multi-target controlled-Z gate via measurement

[0156] Proposition 4.7 (Low-depth multi-target controlled-Z via measurement). Let (V, E) be a tree where all leaves except the root are connected to vertices of degree 2. In other words, none of these leaves are connected to the same vertex. The vertices correspond to qubits. All non-leaf auxiliary qubits are in the plus state. The program MultipleTargetControlledZMeasure in Table 7 implements a multi-target controlled-Z gate where the root is the control and the remaining leaves are the targets. The measurement depth is at most the maximum vertex degree plus two.

[0157] Evidence. Consider how the MultipleTargetControlledZMeasure operation acts on an input from the computational basis. For each non-root leaf, in other words, the target of the control operation is the unique vertex connected to that non-root leaf in the plus state. At the start of the computation, the state of such a pair is |t1>|+>. We can order the qubits as follows. First is the control qubit, followed by the new pairs corresponding to each target qubit and the qubit connected to that target qubit, and then the remaining qubits. The state of all qubits at the start of the computation is as follows:

[0158]

[0159] After applying the fan-out operation, the state becomes:

[0160]

[0161] After the first foreach loop, according to Proposition 4.6, the state of the qubits becomes:

[0162]

[0163] Now, we can see that the above state satisfies all the constraints in the MeasurePlusOne operation in the last two foreach loops. The state |t k ||t k > satisfies the Z v Z v' constraint that appears in the second foreach loop, while the state |c>|c> satisfies the Z v Z r constraint that appears in the third foreach loop. After applying the last two foreach loops, the state of the qubits becomes, as required:

[0164]

[0165] The last two foreach loops can be executed in parallel because they involve different qubits. The measurement depth of each foreach loop in the foreach loop is one. Therefore, the overall measurement depth is the measurement depth of the fan-out operation plus two.

[0166] 5. Embedding the tree into a 2D grid of qubits

[0167] All data qubits should be connected to the interface qubits through auxiliary paths. Therefore, only a portion of all qubits can be data qubits, with the remaining qubits used as connection aids. Given a rectangular qubit field with a nearest-neighbor (each internal qubit has 4 neighbors) architecture, the maximum number of data qubits we can obtain is 2 / 3 of the total number of qubits. This is because an auxiliary (without edges) can attach at most 2 data qubits, and use the other two connections until attached to two other auxiliaries.

[0168] An ideal field configuration might be a 3×N grid of qubits, where the center row consists of auxiliaries, and the top and bottom rows are data qubits. This could achieve an ideal ratio of data qubits to total qubits of 2 / 3.

[0169] Assuming an N×N grid of qubits, the best configuration to achieve the highest ratio of data qubits is a comb, where the second column and every third row starting from row #2 are auxiliaries among the qubits from qubit 2 to N. The first row is reserved for interface qubits, and the rest are data qubits. For the calculations in this article, interface qubits that are to be data qubits are counted. In this configuration, the ratio of data qubits to total qubits is (2N - 1) / 3N or 2 / 3 - 1 / 3N, which is very close to 2 / 3.

[0170] Physical qubits have a certain probability of failure. Some of the qubits in a perfect rectangular grid may be dead (not suitable for use). This not only reduces the number of available qubits, but also breaks the connections between the remaining qubits. For example, there may be dead qubits in the auxiliary path, which are used as part of the circuit and damage the connections between the corresponding data qubits and interface qubits.

[0171] Given an irregular qubit map, an algorithm is needed to create an optimal qubit layout. However, such an algorithm would require non-polynomial execution time, making it impractical. According to the disclosed technology, a near-optimal heuristic-based algorithm is provided.

[0172] Given the starting layout of the comb described above, the algorithm determines the segments of the graph that are disconnected from the interface qubits and attempts to reconnect them to enable as many data qubits as possible. Starting from the interface qubits, if consecutive horizontal auxiliary line segments are connected to the interface, we can mark them as powered. For each powered segment, we can queue all possible vertical routes extending from that powered segment. Routes starting from the end of the segment enter the high-priority queue, while the remaining routes enter the normal-priority queue.

[0173] Then, for each queued route (starting with the high-priority routes), we can determine whether the route connects a previously unpowered auxiliary segment. If so, we accept the route, mark the auxiliary segment as powered, and add more possible routes to the queue starting from the newly powered segment. Each accepted route converts two data qubits to auxiliary. This continues until the queue is empty. Routes at the end of the segment are preferred because they supply power to one or two additional data qubits (next to the dead auxiliary), while routes emanating from the middle segment do not supply power to one or two additional data qubits.

[0174] Each dead data qubit causes us to lose one data qubit in proportion. Each dead auxiliary causes two data qubits not to be powered and separates the auxiliary segment. Reattaching the auxiliary segment requires using two data qubits and is likely to power one of the disconnected qubits again. Therefore, each dead auxiliary is likely to result in the loss of 3 data qubits.

[0175] 6. Other embodiments of exemplary multi-target CNOT gates

[0176] As may be used in embodiments of the disclosed technology, this section discloses more details for implementing multi-target CNOT gates in a Majorana architecture.

[0177] 6.1. Introduction. In a measurement-based architecture such as a Majorana qubit lattice, an auxiliary qubit can be used to implement a CNOT gate through four measurement sequences. By applying this circuit sequentially, we can implement a multi-target CNOT gate with m targets where the depth is 4m and the time is linear in m. In this section, a constant-depth implementation of a multi-target CNOT gate based on single-qubit measurements and two-qubit measurements is disclosed. In terms of the number of measurement levels, the depth of this circuit is five (three two-qubit measurements and two single-qubit measurements). Each target requires one auxiliary. This implementation is well-suited for a Majorana qubit grid.

[0178] The following circuit consists of single-qubit Pauli measurements and two-qubit Pauli measurements. Each measurement M is followed by a Clifford update U(P), where the Clifford update U(P) means that the Clifford operation P is a classical controlled gate that is applied only if the result of the measurement M is 1. The update U(P) is represented in the circuit as the same box as the previous measurement box of M, but does not necessarily act only on the support of M. We are particularly interested in the background of Majorana qubits. Then, by changing the frame, single-qubit Clifford operations can be implemented without any physical action on the qubits. In particular, all updates of Clifford are free. This is why the depth is regarded as the number of measurement levels.

[0179] 6.2. CNOT Gate via Measurement. In this subsection, recall the implementation of a CNOT gate using single-qubit measurements, two-qubit measurements, and an auxiliary qubit. Figure 1 FIG. 100 is a schematic block diagram showing a circuit that implements a CNOT gate between the top qubit and the bottom qubit. The middle qubit is the auxiliary required for the CNOT gate. More specifically, the blue gate prepares the auxiliary qubit, the purple gate entangles the blue gate with the control qubit, and the red gate acts on the auxiliary and target qubits.

[0180] Let the control qubit (qubit 1) be represented by |ψ> = α|0> + β|1>, and let be the target qubit (qubit 3). We can check that Figure 1 the circuit implements a CNOT gate. To simplify the calculation, we can show that the circuit implements a CZ gate in the case where there is no H conjugate on the last qubit. Adding two H gates provides a CNOT gate.

[0181] · The first measurement M X (followed by the update U(Z2) in the case of the result being 1) prepares the auxiliary qubit in the |+> state. Then, the combined state of qubits 1 and 2 is as follows:

[0182] |\psi_0\rangle=\alpha|00\rangle+\alpha|01\rangle+\beta|10\rangle+\beta|11\rangle.

[0183] Measuring Z1Z2 with the result 0 projects the states of qubits 1 and 2 onto the following states:

[0184] |\psi_1\rangle=\alpha|00\rangle+\beta|11\rangle.

[0185] If the result 1 is obtained, then we obtain the state \alpha|01\rangle+\beta|10\rangle, which is mapped to |\psi_1\rangle by updating U(X2).

[0186] · The gate H2 on the first two qubits results in |\psi_2\rangle=\alpha|00\rangle+\alpha|01\rangle+\beta|10\rangle+( + 1)\beta|11\rangle, and then, (without considering H3) the three - qubit state is as follows:

[0187] |\psi_2\rangle=\alpha\alpha'|000\rangle+\alpha\alpha'|010\rangle+\beta\alpha'|100\rangle+( - 1)\beta\alpha'|110\rangle+\alpha\beta'|001\rangle+\alpha\beta'|011\rangle+\beta\beta'|101\rangle+( - )\beta\beta'|111\rangle

[0188] · If the result of

[0189] |\psi_3\rangle=\alpha\alpha'|000\rangle+\beta\alpha'|100\rangle+\alpha\beta'|011\rangle+( - 1)\beta\beta'|111\rangle.

[0190] If the measurement result is 1, then the state after measurement is as follows:

[0191] \alpha\alpha'|010\rangle+( - 1)\beta\alpha'|110\rangle+\alpha\beta'|001\rangle+\beta\beta'|101\rangle,

[0192] which we can map to |\psi_3\rangle by updating U(Z1X2).

[0193] · Finally, the ancilla is removed by measuring X. Assuming the result is 0, then we obtain the following states on qubits 1 and 3 after M X :

[0194] |\psi_4\rangle=\alpha\alpha'|00\rangle+\beta\alpha'|10\rangle+\alpha\beta'|01\rangle+( - 1)\beta\beta'|11\rangle.

[0195] We recognize the controlled - Z gate applied to |\psi\rangle and |\varphi\rangle. If the result of MX is 1, then we obtain the following state:

[0196] αα′|00> + βα′|10> + (-1)αβ′|01> + ββ′|11>.

[0197] It is necessary to correct U(Z3) to map it to |ψ4>. In the CNOT gate, this correction is done by H conjugation and becomes U(X3).

[0198] This proves that Figure 1 the circuit implements a CNOT gate.

[0199] 6.3. Multi-target CNOT gate. The multi-target CNOT gate applies an X gate to a set of m qubits q1,..., q m , which is controlled in the state of the unique control qubit q θ . It can be easily implemented by a sequence of m CNOT gates CNOT(q θ , q i ), where i = 1,..., m. Thus, the depth of the multi-target CNOT gate is at most linear in the number of targets. In this section, it is shown how to implement a multi-target gate with constant depth using one ancilla qubit per target. Although the same ancilla qubit can be reused for the sequential implementation of m CNOT gates, m ancillas are consumed for the constant-depth implementation.

[0200] In the case of a two-target CNOT gate, Figures 2 to 4 a transformation of the sequential implementation for reducing the circuit depth to a constant value is shown.

[0201] Figure 2 is a schematic block diagram 200 showing an example of providing a multi-target CNOT gate by measurement. In particular, block diagram 200 illustrates an example sequential application of a CNOT circuit. Figure 3 is a schematic block diagram 300 illustrating a modification of block diagram 200, which is an example sequential order after moving the purple measurement to the left to parallelize the last red block between the ancilla and the target. Figure 4 is a schematic block diagram 400 that also illustrates modifying the initial measurement to parallelize the purple block between the control qubit and the ancilla (the effect of this parallelization only occurs when there are more than two targets).

[0202] As illustrated, this transformation can be performed in two steps. First, we move the joint measurement M ZZ between the control qubit and the ancilla to the past. This allows us to parallelize the last block of the circuit acting on the ancilla and the target. In the second step, we can replace m measurements with a single measurement (which involves the control qubit q0) and m - 1 measurements (which are on the ancilla qubits that can be implemented at depth 2). (It relates to controlling qubits).

[0203] Figure 5 The working principle of the general circuit represented for four targets in the schematic block diagram 500 is as follows:

[0204] · (i) [Auxiliary preparation (blue)] Prepare m auxiliary qubits a1,..., a by measuring m in the m-qubit cat state |0...0> + |1...1> on. This can be done in two measurement layers (followed by updates).

[0205] · (ii) [Control block (purple)] Entangle the auxiliary qubits with the control qubit q0 by measuring Update is applied in the case of non-zero results.

[0206] · (iii) [Target block (red)] Apply the target block of the standard CNOT through measurements parallel to all targets.

[0207] To check that the circuit implements the multi-target CNOT as claimed, it suffices to check that the circuit maps any Pauli operator to the same Pauli operator as the multi-target CNOT gate. Given the Pauli matrix P C represented by, the Pauli operator acts as P on the control qubit and acts trivially on all other qubits. Similarly, P ai acts on the i-th auxiliary, while P Ti acts on the i-th target. The multi-target CNOT gate is characterized by its operation on Pauli operators as follows:

[0208]

[0209] Propagating these Pauli operators through the circuit, we can easily check that the circuit satisfies these identities. For example, we can propagate the operation X Figure 6 through the circuit in C . In particular, Figure 6 is the schematic block diagram 600 of the circuit for propagating the Pauli operator X C through the circuit. We can check that the circuit maps X C to as expected.

[0210] This proves that it implements the desired multi-target CNOT operation.

[0211] 6.4. Two-dimensional layout. Such a multi-target CNOT gate can be implemented in a Majorana qubit grid, in which all single-qubit M X 、MZ are available, as well as two-qubit measurements of the Pauli operator P1P2 between adjacent qubits are also available.

[0212] For example, we can consider preparing a string of m ancilla qubits in a cat state, which is connected to a control qubit through one of its endpoints. Each ancilla can reach a target qubit directly below it. This allows for the local implementation of the multi-target CNOT gates described in this note. Figure 7 represents Figure 6 The block diagram 700 of the planar layout of the multi-target CNOT gate.

[0213] 7. Example embodiments

[0214] In this section, example methods for performing various aspects of the disclosed embodiments are disclosed. Since the disclosed method actions can be performed individually, in a different order, or at least partially simultaneously with each other, the specific embodiments described should not be construed as restrictive. Further, any of the disclosed methods or method actions can be performed using any other method or method action disclosed herein.

[0215] Figure 8 is an example method for performing layout simplification techniques for fault-tolerant quantum computing according to an embodiment of the disclosed technology. In a particular embodiment, the method is performed by one or more classical computing devices, where at least some of the classical computing devices are in a configuration that can operate a quantum computer.

[0216] At 810, the layout of any quantum circuit is simplified to a layout of an exponential of multi-qubit Pauli matrices and measurements of multi-qubit Pauli matrices.

[0217] At 812, the quantum computer is configured to implement the simplified layout.

[0218] In a particular implementation, the qubits of the quantum computer include data qubits, interface qubits, and ancilla qubits. In other implementations, the graph of qubit connectivity satisfies the condition of providing an auxiliary path from one or more data qubits to the interface qubits.

[0219] Figure 9 is an example method for performing layout techniques for fault-tolerant quantum computing according to an embodiment of the disclosed technology. In a particular embodiment, the method is performed by one or more classical computing devices, where at least some of the classical computing devices are in a configuration that can operate a quantum computer.

[0220] At 910, qubits are labeled as one of data qubits, interface qubits, or auxiliary qubits for a 2D nearest neighbor qubit connectivity graph.

[0221] At 912, an auxiliary path is provided from a corresponding data qubit to a corresponding interface qubit.

[0222] At 914, the quantum computer is configured to implement an auxiliary path from a corresponding data qubit to a corresponding interface qubit.

[0223] In some implementations, the method accounts for and avoids any broken qubits and meets the condition of providing an auxiliary path from data qubits to interface qubits.

[0224] Any of the methods described above can be performed in a system that includes a quantum computing device; and one or more classical computing devices, where at least some of the one or more classical computing devices are programmed to perform any of the disclosed methods.

[0225] Additionally, any of the methods described above can be implemented as one or more classical computer-readable media storing classical computer-executable instructions that, when executed by a classical computer, cause the classical computer to perform any of the disclosed methods.

[0226] Other embodiments include a quantum circuit that is configured to apply an exponentiation of a multi-qubit Pauli matrix and measure the multi-qubit Pauli matrix. In some implementations, an auxiliary path is provided from data qubits to interface qubits. In other implementations, the depth of the quantum circuit does not depend on the number of vertices. In some implementations, the quantum circuit uses single-depth multi-target CNOT gates or low-depth multi-target CNOT gates as subcircuits.

[0227] Some embodiments include a quantum circuit configured to: (a) provide a multi-target CNOT gate using single-qubit Pauli measurements, two-qubit Pauli measurements, and single-qubit Clifford gates; or (b) provide a multi-target CNOT gate using single-qubits, Pauli measurements, single-qubit Clifford gates, and controlled-Z gates. In some implementations, the quantum circuit provides a multi-target CNOT gate using single-qubit Pauli measurements, two-qubit Pauli measurements, and single-qubit Clifford gates, where the quantum circuit acts on qubits for which the qubit connectivity graph satisfies the condition of providing an auxiliary path from a target qubit to a control qubit. In other implementations, the quantum circuit provides a multi-target CNOT gate using single-qubit Pauli measurements, two-qubit Pauli measurements, and single-qubit Clifford gates, where the depth of the quantum circuit does not depend on the number of vertices. In some implementations, the quantum circuit is configured to use single-qubits, Pauli measurements, single-qubit Clifford gates, and controlled-Z gates to provide a multi-target CNOT gate, and where the quantum circuit acts on qubits for which the qubit connectivity graph satisfies the condition of providing an auxiliary path from a target qubit to a control qubit. In other implementations, the quantum circuit is configured to use single-qubits, Pauli measurements, single-qubit Clifford gates, and controlled-Z gates to provide a multi-target CNOT gate, where the depth of the quantum circuit does not depend on the number of vertices.

[0228] Another embodiment is a method that includes: implementing a product of exponents of swapped multi-qubit Pauli matrices at low depth, where non-Clifford gates can be executed in parallel.

[0229] An additional embodiment is a quantum circuit for providing a multi-target CNOT gate using single-qubit Pauli measurements and two-qubit Pauli measurements. In some implementations, the quantum circuit further includes a 2d nearest-neighbor architecture. In certain implementations, the quantum circuit includes a 3N grid of qubits having a central row or central column of data qubits, each corresponding data qubit also directly connected to two auxiliary qubits. In some implementations, the quantum circuit includes a comb architecture having a central row or central column of data qubits, each corresponding data qubit also directly connected to one auxiliary qubit, thereby forming a comb architecture. In certain implementations, the quantum circuit is a low-constant-depth quantum circuit. In some implementations, the depth of the quantum circuit is equal to the maximum vertex degree of the tree describing the quantum circuit.

[0230] Another embodiment includes a quantum circuit for calculating the exponent of a multi-qubit Pauli matrix. In some implementations, the multi-qubit Pauli matrix is a two-qubit Pauli matrix. In certain implementations, the quantum circuit is a low-constant-depth quantum circuit. In other implementations, the depth of the quantum circuit is equal to the maximum vertex degree of the tree describing the quantum circuit.

[0231] Another embodiment is a method that includes reducing the layout of an arbitrary quantum circuit to the layout of the exponent of a multi-qubit Pauli matrix.

[0232] Another embodiment is a method that includes implementing the product of the exponents of swapped multi-qubit Pauli matrices at low depth, where non-Clifford gates can be executed in parallel.

[0233] Another embodiment is a computer-implemented method that constructs a data qubit / ancilla qubit layout for a given qubit connectivity graph and satisfies the condition of providing an ancillary path from each data qubit to an interface qubit. In some implementations, the method takes into account and avoids any broken qubits.

[0234] Likewise, any of the methods described above can be implemented as one or more classical computer-readable media storing classical computer-executable instructions that, when executed by a classical computer, cause the classical computer to perform any of the disclosed methods.

[0235] 8. Example Computing Environments

[0236] Figure 10 A general example of a suitable classical computing environment 1000 in which several of the described embodiments can be implemented is illustrated. Since the techniques and tools described herein can be implemented in a variety of general-purpose or special-purpose environments having computing hardware, computing environment 1000 is not intended to pose any limitation on the scope of use or functionality of the disclosed technology.

[0237] Reference Figure 10 to, computing environment 1000 includes at least one processing device 1010 and a memory 1020. In Figure 10In this case, this most basic configuration 1030 is included within the dashed lines. A processing device 1010 (e.g., a CPU or microprocessor) executes computer-executable instructions. In a multiprocessing system, multiple processing devices execute computer-executable instructions to enhance processing capabilities. Memory 1020 can be volatile memory (e.g., registers, caches, RAM, DRAM, SRAM), non-volatile memory (e.g., ROM, EEPROM, flash memory), or some combination of both. Memory 1020 stores software 1080 that is used to implement, using a classical computer and / or a quantum computer, tools for performing any of the layout techniques for a fault-tolerant quantum computer disclosed herein. For example, memory 1020 can store software for controlling a quantum circuit to implement an embodiment of the disclosed approximation techniques. Memory 1020 can also store software 1080 for synthesizing, generating (or compiling), and / or controlling a quantum circuit as described herein.

[0238] The computing environment can have additional features. For example, computing environment 1000 includes a memory 1040, one or more input devices 1050, one or more output devices 1060, and one or more communication connections 1070. An interconnection mechanism, such as a bus, controller, or network (not shown), interconnects the components of computing environment 1000. Generally, an operating system software (not shown) provides an operating environment for other software executing in computing environment 1000 and coordinates the activities of the components of computing environment 1000.

[0239] Storage device 1040 can be removable or non-removable and includes one or more disks (e.g., hard disk drives), solid state drives (e.g., flash drives), magnetic tapes or cartridges, CD-ROMs, DVDs, or any other tangible non-volatile storage medium that can be used to store information and can be accessed in computing environment 1000. Memory 1040 can also store instructions for software 1080 that is used to implement, using a classical computer and / or a quantum computer, tools for performing any of the layout techniques for a fault-tolerant quantum computer disclosed herein. For example, memory 1020 can store software for controlling a quantum circuit to implement an embodiment of the disclosed layout techniques. Memory 1040 can also store instructions for software 1080 that is used to synthesize, generate (or compile), and / or control a quantum circuit as described herein.

[0240] One or more input devices 1050 can be touch input devices, such as a keyboard, touch screen, mouse, pen, trackball, voice input device, scanning device, or another device that provides input to the computing environment 1000. One or more output devices 1060 can be a display device (e.g., a computer monitor, laptop computer display, smart phone display, tablet display, netbook display, or touch screen), printer, speaker, or another device that provides output from the computing environment 1000.

[0241] One or more communication connections 1070 enable communication with another computing entity via a communication medium. The communication medium conveys information such as computer-executable instructions or other data in a modulated data signal. A modulated data signal is a signal in which one or more of the characteristics of the signal are set or changed in a manner that encodes information in the signal. By way of example, and not limitation, the communication medium includes wired or wireless technologies implemented using electrical, optical, RF, infrared, acoustic, or other carriers.

[0242] As noted, the various methods, quantum circuit control techniques, or compilation / synthesis techniques may be described in the general context of computer-readable instructions stored on one or more computer-readable media. A computer-readable medium is any available medium that can be accessed within or by a computing environment (e.g., a memory or storage device). A computer-readable medium includes tangible computer-readable memory or storage devices, such as memory 1020 and / or storage device 1040, which do not themselves include a propagated carrier wave or signal (a tangible computer-readable memory or storage device does not itself include a propagated carrier wave or signal).

[0243] In the general context of computer-executable instructions, such as those included in program modules, executed by a processor in a computing environment, various embodiments of the methods disclosed herein may also be described. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of program modules may be combined or split as needed. The computer-executable instructions for program modules may be executed within a local computing environment or a distributed computing environment.

[0244] In Figure 11 an example of a possible network topology 1100 (e.g., a client-server network) for implementing a system according to the disclosed technology is depicted. The networked computing device 1120 can be, for example, a computer running a browser or other software connected to the network 1112. The computing device 1120 can have as Figure 10The computer architecture shown and discussed above. The computing device 1120 is not limited to a traditional personal computer, but can also include other computing hardware configured to connect to and communicate with the network 1112 (e.g., a smart phone, a laptop computer, a tablet computer, or other mobile computing device, a server, a network device, a dedicated device, etc.). Further, the computing device 1120 can include an FPGA or other programmable logic device. In the illustrated embodiment, the computing device 1120 is configured to communicate with a computing device 1130 (e.g., a remote server, such as a server in a cloud computing environment) via the network 1112. In the illustrated embodiment, the computing device 1120 is configured to transmit input data to the computing device 1130, and the computing device 1130 is configured to: implement a quantum circuit control technique according to any one of the disclosed embodiments, and / or implement a circuit generation or compilation / synthesis method for generating a quantum circuit for use with any one of the techniques disclosed herein. The computing device 1130 can output the result to the computing device 1120. Any of the data received from the computing device 1130 can be stored or displayed on the computing device 1120 (e.g., at the computing device 1120, displayed as data on a graphical user interface or a web page). In the illustrated embodiment, the illustrated network 1112 can be implemented as a local area network (LAN) using wired networking (e.g., Ethernet IEEE standard 802.3 or other suitable standard) or wireless networking (e.g., one of the IEEE standards 802.11a, 802.11b, 802.11g, or 802.11n or other suitable standard). Alternatively, at least a portion of the network 1112 can be the Internet or a similar public network and operate using a suitable protocol (e.g., the HTTP protocol).

[0245] In Figure 12 it, another example of a possible network topology 1200 (e.g., a distributed computing environment) for implementing a system according to the disclosed technology is depicted. The networked computing device 1220 can be, for example, a computer running a browser or other software connected to the network 1212. The computing device 1220 can have as Figure 10The computer architectures shown and discussed above. In the illustrated embodiment, computing device 1220 is configured to communicate with a plurality of computing devices 1230, 1231, 1232 (e.g., remote servers or other distributed computing devices such as one or more servers in a cloud computing environment) via network 1212. In the illustrated embodiment, each of the computing devices 1230, 1231, 1232 in computing environment 1200 is used to: execute at least a portion of the quantum circuit control techniques according to any of the disclosed embodiments, and / or execute a circuit generation or compilation / synthesis method for generating a quantum circuit for use with any of the techniques disclosed herein. In other words, computing devices 1230, 1231, 1232 form a distributed computing environment in which the quantum circuit control and / or generation / compilation / synthesis processes are shared among the plurality of computing devices. Computing device 1220 is configured to transmit input data to computing devices 1230, 1231, 1232, which are configured to include a distributed implementation (such as processing) including executing any of the disclosed methods or creating any of the disclosed circuits, and provide results to computing device 1220. Any of the data received from computing devices 1230, 1231, 1232 can be stored or displayed on computing device 1220 (e.g., at computing device 1220, displayed as data on a graphical user interface or web page). The illustrated network 1212 can be any of the networks discussed above with respect to Figure 11 any of the networks discussed.

[0246] Referring Figure 13 , an exemplary system for implementing the disclosed techniques includes computing environment 1300. In computing environment 1300, a compiled quantum computer circuit description (including quantum circuits generated by any of the disclosed layout techniques) can be used to program (or configure) one or more quantum processing units such that the one or more quantum processing units implement the circuit described by the quantum computer circuit description.

[0247] The environment 1300 includes one or more quantum processing units 1302 and one or more readout devices 1308. The one or more quantum processing units execute quantum circuits pre-compiled and described by a quantum computer circuit description. The quantum processing unit can be, but is not limited to, one or more of the following: (a) a superconducting quantum computer; (b) an ion trap quantum computer; (c) a fault-tolerant architecture for quantum computing; and / or (d) a topological quantum architecture (e.g., a topological quantum computing device using Majorana zero modes). Under the control of the quantum processor controller 1320, a pre-compiled quantum circuit, including any of the circuits disclosed herein, can be sent (or otherwise applied) to the one or more quantum processing units via the control lines 1306. The quantum processor controller (QP controller) 1320 can operate with a classical processor 1310 (e.g., having an architecture as described above with respect to Figure 10 ) to implement a desired quantum computing process. In the illustrated example, the QP controller 1320 also implements the desired quantum computing process via one or more QP sub-controllers 1304, which are particularly adapted to control a corresponding quantum processor among the one or more quantum processors 1302. For example, in one example, the quantum controller 1320 facilitates implementing the compiled quantum circuit by sending instructions to one or more memories (e.g., cryogenic memories), which then pass the instructions to one or more cryogenic control units (e.g., one or more QP sub-controllers 1304), and, for example, the one or more cryogenic control units transmit a pulse sequence representing gates to the one or more quantum processing units 1302 for implementation. In other examples, the one or more QP controllers 1320 and the one or more QP sub-controllers 1304 operate to provide an appropriate magnetic field, encoded operations, or other such control signals to the one or more quantum processors to implement the operations described by the compiled quantum computer circuit description. The one or more quantum controllers can also interact with the readout device 1308 to assist in controlling and implementing the desired quantum computing process (e.g., by reading or measuring data results from the quantum processing unit once available).

[0248] Reference Figure 13 , compilation is the process of converting a high-level description of a quantum algorithm into a quantum computer circuit description including a sequence of quantum operations or gates, which can include the circuits disclosed herein. Compilation can be performed by a compiler 1322 using the classical processor 1310 of the environment 1300 (e.g., as Figure 10 shown), which loads the high-level description from a memory or storage device 1312 and stores the resulting quantum computer circuit description in the memory or storage device 1312.

[0249] In other embodiments, compilation and / or verification may be performed remotely by a remote computer 1360 (e.g., a computer having a computing environment as described above with respect to Figure 10 ), which stores the resulting quantum computer circuit description in one or more memories or storage devices 1362 and transmits the quantum computer circuit description to the computing environment 1300 for implementation in one or more quantum processing units 1302. Further still, the remote computer 1300 may store a high-level description in a memory or storage device 1362 and transmit the high-level description to the computing environment 1300 for compilation and use with one or more quantum processors. In any of these scenarios, the results of the computations performed by one or more quantum processors may be communicated to the remote computer after and / or during the computational process. Still further, the remote computer may communicate with one or more QP controllers 1320 such that the quantum computing process (including any compilation, verification, and QP control processes) may be remotely controlled by the remote computer 1360. Generally, the remote computer 1360 communicates with the QP controller 1320, compiler / synthesizer 1322, and / or verification tool 1323 via a communication link 1350.

[0250] In a particular embodiment, the environment 1300 may be a cloud computing environment that provides the quantum processing resources of the environment 1300 to one or more remote computers (such as the remote computer 1360) via a suitable network, which may include the Internet.

[0251] 9. Conclusion

[0252] The principles of the disclosed technology have been described and illustrated with reference to the illustrated embodiments. It should be recognized that the illustrated embodiments may be arranged and details modified without departing from such principles. For example, elements of the illustrated embodiments shown in software may be implemented in hardware and vice versa. Additionally, techniques from any example may be combined with techniques described in one or more other examples. It should be appreciated that processes and functions such as those described with reference to the illustrated examples may be implemented in a single hardware or software module or separate modules may be provided. The above specific arrangements are provided for convenience of illustration and other arrangements may be used.

Claims

1. A method performed by one or more classical computers, comprising: Converting a quantum computation of the following form Into a sequence of measurements and exponents of the following form where P1 and P2 are multi-qubit Pauli operators, denoted as a measurement of the multi-qubit Pauli operator P2 that results in a = ±I, where I is the identity matrix, where and Constructing a tree (V, E) with a root node r ∈ V, the tree describing a 2D grid of qubits, where each vertex V describes a qubit in the 2D grid, and vertices describing nearest neighbor qubits in the 2D grid are connected by edges in E; and Configuring a quantum computer including the 2D grid of qubits to implement the sequence of measurements and exponents using: A single qubit measurement and a single qubit Clifford unitary, (A) Controlled-Z gate or (B) two-qubit measurement on nearest-neighbor qubits described by vertices connected by edges in E, where (A) or (B) is used to perform a multi-target controlled-Z gate and Clifford C and such that is constructed to use a multi-target controlled-Z gate, and Single qubit rotations that can only be performed on the qubit described by the root node r.

2. The method according to claim 1, wherein the qubits of the quantum computer include data qubits, interface qubits, and auxiliary qubits.

3. The method according to claim 2, wherein the qubit connectivity graph satisfies the condition of providing an auxiliary path from one or more data qubits to the interface qubits.

4. The method according to claim 2, wherein each data qubit is connected to an interface qubit via a path of auxiliary qubits.

5. A system for quantum computing, comprising: A quantum computer; And One or more classical computing devices, at least some of the one or more classical computing devices being programmed to perform the method according to claim 1.

6. A system for quantum computing, comprising: A quantum computer; And One or more classical computing devices, at least some of the one or more classical computing devices being programmed to perform the method according to claim 3.

7. One or more classical computer-readable media storing classical computer-executable instructions that, when executed by a classical computer, cause the classical computer to perform the method according to claim 1.

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